From 563872aba3b0443567be09c01fb49b6618fb13b4 Mon Sep 17 00:00:00 2001 From: Scott Beamer Date: Mon, 11 Oct 2021 23:01:49 -0700 Subject: [PATCH] bump rockets to firrtl 1.4.3 including updates to .fir files --- essent | 2 +- firrtl-sig | 2 +- rocket16/TestHarness.DefaultConfig.1609.fir | 66706 ++++++++-------- ...echips.rocketchip.system.DefaultConfig.fir | 4 +- 4 files changed, 33244 insertions(+), 33470 deletions(-) diff --git a/essent b/essent index 4547f40..dad3130 160000 --- a/essent +++ b/essent @@ -1 +1 @@ -Subproject commit 4547f40121072dcc3af68806c0c4abd31a7e10c5 +Subproject commit dad3130f214d5f5dbeec1e4c18ad97e8758f286c diff --git a/firrtl-sig b/firrtl-sig index ec84c8a..62392f8 160000 --- a/firrtl-sig +++ b/firrtl-sig @@ -1 +1 @@ -Subproject commit ec84c8a6fd786d196fbfdcf292a2126218706208 +Subproject commit 62392f8501a996c398f59319e758d4048fe2d9ae diff --git a/rocket16/TestHarness.DefaultConfig.1609.fir b/rocket16/TestHarness.DefaultConfig.1609.fir index ee47fb4..06b986e 100644 --- a/rocket16/TestHarness.DefaultConfig.1609.fir +++ b/rocket16/TestHarness.DefaultConfig.1609.fir @@ -1,34707 +1,34479 @@ -circuit TestHarness : - module RVCExpander : +circuit TestHarness : + module RVCExpander : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>} - + output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>} + io is invalid - node T_8 = bits(io.in, 1, 0) @[rvc.scala 160:20] - node T_10 = neq(T_8, UInt<2>("h03")) @[rvc.scala 160:26] - io.rvc <= T_10 @[rvc.scala 160:12] - node T_11 = bits(io.in, 12, 5) @[rvc.scala 51:22] - node T_13 = neq(T_11, UInt<1>("h00")) @[rvc.scala 51:29] - node T_16 = mux(T_13, UInt<7>("h013"), UInt<7>("h01f")) @[rvc.scala 51:20] - node T_17 = bits(io.in, 10, 7) @[rvc.scala 32:26] - node T_18 = bits(io.in, 12, 11) @[rvc.scala 32:35] - node T_19 = bits(io.in, 5, 5) @[rvc.scala 32:45] - node T_20 = bits(io.in, 6, 6) @[rvc.scala 32:51] - node T_22 = cat(T_20, UInt<2>("h00")) @[Cat.scala 20:58] - node T_23 = cat(T_17, T_18) @[Cat.scala 20:58] - node T_24 = cat(T_23, T_19) @[Cat.scala 20:58] - node T_25 = cat(T_24, T_22) @[Cat.scala 20:58] - node T_29 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_30 = cat(UInt<2>("h01"), T_29) @[Cat.scala 20:58] - node T_31 = cat(T_30, T_16) @[Cat.scala 20:58] - node T_32 = cat(T_25, UInt<5>("h02")) @[Cat.scala 20:58] - node T_33 = cat(T_32, UInt<3>("h00")) @[Cat.scala 20:58] - node T_34 = cat(T_33, T_31) @[Cat.scala 20:58] - node T_36 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_37 = cat(UInt<2>("h01"), T_36) @[Cat.scala 20:58] - node T_40 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_41 = cat(UInt<2>("h01"), T_40) @[Cat.scala 20:58] - node T_42 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_49 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_49 is invalid @[rvc.scala 19:19] - T_49.bits <= T_34 @[rvc.scala 20:14] - T_49.rd <= T_37 @[rvc.scala 21:12] - T_49.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_49.rs2 <= T_41 @[rvc.scala 23:13] - T_49.rs3 <= T_42 @[rvc.scala 24:13] - node T_55 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_56 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_58 = cat(T_55, T_56) @[Cat.scala 20:58] - node T_59 = cat(T_58, UInt<3>("h00")) @[Cat.scala 20:58] - node T_61 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_62 = cat(UInt<2>("h01"), T_61) @[Cat.scala 20:58] - node T_65 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_66 = cat(UInt<2>("h01"), T_65) @[Cat.scala 20:58] - node T_68 = cat(T_66, UInt<7>("h07")) @[Cat.scala 20:58] - node T_69 = cat(T_59, T_62) @[Cat.scala 20:58] - node T_70 = cat(T_69, UInt<3>("h03")) @[Cat.scala 20:58] - node T_71 = cat(T_70, T_68) @[Cat.scala 20:58] - node T_73 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_74 = cat(UInt<2>("h01"), T_73) @[Cat.scala 20:58] - node T_76 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_77 = cat(UInt<2>("h01"), T_76) @[Cat.scala 20:58] - node T_79 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_80 = cat(UInt<2>("h01"), T_79) @[Cat.scala 20:58] - node T_81 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_88 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_88 is invalid @[rvc.scala 19:19] - T_88.bits <= T_71 @[rvc.scala 20:14] - T_88.rd <= T_74 @[rvc.scala 21:12] - T_88.rs1 <= T_77 @[rvc.scala 22:13] - T_88.rs2 <= T_80 @[rvc.scala 23:13] - T_88.rs3 <= T_81 @[rvc.scala 24:13] - node T_94 = bits(io.in, 5, 5) @[rvc.scala 33:20] - node T_95 = bits(io.in, 12, 10) @[rvc.scala 33:26] - node T_96 = bits(io.in, 6, 6) @[rvc.scala 33:36] - node T_98 = cat(T_96, UInt<2>("h00")) @[Cat.scala 20:58] - node T_99 = cat(T_94, T_95) @[Cat.scala 20:58] - node T_100 = cat(T_99, T_98) @[Cat.scala 20:58] - node T_102 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_103 = cat(UInt<2>("h01"), T_102) @[Cat.scala 20:58] - node T_106 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_107 = cat(UInt<2>("h01"), T_106) @[Cat.scala 20:58] - node T_109 = cat(T_107, UInt<7>("h03")) @[Cat.scala 20:58] - node T_110 = cat(T_100, T_103) @[Cat.scala 20:58] - node T_111 = cat(T_110, UInt<3>("h02")) @[Cat.scala 20:58] - node T_112 = cat(T_111, T_109) @[Cat.scala 20:58] - node T_114 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_115 = cat(UInt<2>("h01"), T_114) @[Cat.scala 20:58] - node T_117 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_118 = cat(UInt<2>("h01"), T_117) @[Cat.scala 20:58] - node T_120 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_121 = cat(UInt<2>("h01"), T_120) @[Cat.scala 20:58] - node T_122 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_129 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_129 is invalid @[rvc.scala 19:19] - T_129.bits <= T_112 @[rvc.scala 20:14] - T_129.rd <= T_115 @[rvc.scala 21:12] - T_129.rs1 <= T_118 @[rvc.scala 22:13] - T_129.rs2 <= T_121 @[rvc.scala 23:13] - T_129.rs3 <= T_122 @[rvc.scala 24:13] - node T_135 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_136 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_138 = cat(T_135, T_136) @[Cat.scala 20:58] - node T_139 = cat(T_138, UInt<3>("h00")) @[Cat.scala 20:58] - node T_141 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_142 = cat(UInt<2>("h01"), T_141) @[Cat.scala 20:58] - node T_145 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_146 = cat(UInt<2>("h01"), T_145) @[Cat.scala 20:58] - node T_148 = cat(T_146, UInt<7>("h03")) @[Cat.scala 20:58] - node T_149 = cat(T_139, T_142) @[Cat.scala 20:58] - node T_150 = cat(T_149, UInt<3>("h03")) @[Cat.scala 20:58] - node T_151 = cat(T_150, T_148) @[Cat.scala 20:58] - node T_153 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_154 = cat(UInt<2>("h01"), T_153) @[Cat.scala 20:58] - node T_156 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_157 = cat(UInt<2>("h01"), T_156) @[Cat.scala 20:58] - node T_159 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_160 = cat(UInt<2>("h01"), T_159) @[Cat.scala 20:58] - node T_161 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_168 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_168 is invalid @[rvc.scala 19:19] - T_168.bits <= T_151 @[rvc.scala 20:14] - T_168.rd <= T_154 @[rvc.scala 21:12] - T_168.rs1 <= T_157 @[rvc.scala 22:13] - T_168.rs2 <= T_160 @[rvc.scala 23:13] - T_168.rs3 <= T_161 @[rvc.scala 24:13] - node T_174 = bits(io.in, 5, 5) @[rvc.scala 33:20] - node T_175 = bits(io.in, 12, 10) @[rvc.scala 33:26] - node T_176 = bits(io.in, 6, 6) @[rvc.scala 33:36] - node T_178 = cat(T_176, UInt<2>("h00")) @[Cat.scala 20:58] - node T_179 = cat(T_174, T_175) @[Cat.scala 20:58] - node T_180 = cat(T_179, T_178) @[Cat.scala 20:58] - node T_181 = shr(T_180, 5) @[rvc.scala 61:32] - node T_183 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_184 = cat(UInt<2>("h01"), T_183) @[Cat.scala 20:58] - node T_186 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_187 = cat(UInt<2>("h01"), T_186) @[Cat.scala 20:58] - node T_189 = bits(io.in, 5, 5) @[rvc.scala 33:20] - node T_190 = bits(io.in, 12, 10) @[rvc.scala 33:26] - node T_191 = bits(io.in, 6, 6) @[rvc.scala 33:36] - node T_193 = cat(T_191, UInt<2>("h00")) @[Cat.scala 20:58] - node T_194 = cat(T_189, T_190) @[Cat.scala 20:58] - node T_195 = cat(T_194, T_193) @[Cat.scala 20:58] - node T_196 = bits(T_195, 4, 0) @[rvc.scala 61:66] - node T_198 = cat(UInt<3>("h02"), T_196) @[Cat.scala 20:58] - node T_199 = cat(T_198, UInt<7>("h02f")) @[Cat.scala 20:58] - node T_200 = cat(T_181, T_184) @[Cat.scala 20:58] - node T_201 = cat(T_200, T_187) @[Cat.scala 20:58] - node T_202 = cat(T_201, T_199) @[Cat.scala 20:58] - node T_204 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_205 = cat(UInt<2>("h01"), T_204) @[Cat.scala 20:58] - node T_207 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_208 = cat(UInt<2>("h01"), T_207) @[Cat.scala 20:58] - node T_210 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_211 = cat(UInt<2>("h01"), T_210) @[Cat.scala 20:58] - node T_212 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_219 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_219 is invalid @[rvc.scala 19:19] - T_219.bits <= T_202 @[rvc.scala 20:14] - T_219.rd <= T_205 @[rvc.scala 21:12] - T_219.rs1 <= T_208 @[rvc.scala 22:13] - T_219.rs2 <= T_211 @[rvc.scala 23:13] - T_219.rs3 <= T_212 @[rvc.scala 24:13] - node T_225 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_226 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_228 = cat(T_225, T_226) @[Cat.scala 20:58] - node T_229 = cat(T_228, UInt<3>("h00")) @[Cat.scala 20:58] - node T_230 = shr(T_229, 5) @[rvc.scala 64:30] - node T_232 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_233 = cat(UInt<2>("h01"), T_232) @[Cat.scala 20:58] - node T_235 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_236 = cat(UInt<2>("h01"), T_235) @[Cat.scala 20:58] - node T_238 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_239 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_241 = cat(T_238, T_239) @[Cat.scala 20:58] - node T_242 = cat(T_241, UInt<3>("h00")) @[Cat.scala 20:58] - node T_243 = bits(T_242, 4, 0) @[rvc.scala 64:64] - node T_245 = cat(UInt<3>("h03"), T_243) @[Cat.scala 20:58] - node T_246 = cat(T_245, UInt<7>("h027")) @[Cat.scala 20:58] - node T_247 = cat(T_230, T_233) @[Cat.scala 20:58] - node T_248 = cat(T_247, T_236) @[Cat.scala 20:58] - node T_249 = cat(T_248, T_246) @[Cat.scala 20:58] - node T_251 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_252 = cat(UInt<2>("h01"), T_251) @[Cat.scala 20:58] - node T_254 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_255 = cat(UInt<2>("h01"), T_254) @[Cat.scala 20:58] - node T_257 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_258 = cat(UInt<2>("h01"), T_257) @[Cat.scala 20:58] - node T_259 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_266 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_266 is invalid @[rvc.scala 19:19] - T_266.bits <= T_249 @[rvc.scala 20:14] - T_266.rd <= T_252 @[rvc.scala 21:12] - T_266.rs1 <= T_255 @[rvc.scala 22:13] - T_266.rs2 <= T_258 @[rvc.scala 23:13] - T_266.rs3 <= T_259 @[rvc.scala 24:13] - node T_272 = bits(io.in, 5, 5) @[rvc.scala 33:20] - node T_273 = bits(io.in, 12, 10) @[rvc.scala 33:26] - node T_274 = bits(io.in, 6, 6) @[rvc.scala 33:36] - node T_276 = cat(T_274, UInt<2>("h00")) @[Cat.scala 20:58] - node T_277 = cat(T_272, T_273) @[Cat.scala 20:58] - node T_278 = cat(T_277, T_276) @[Cat.scala 20:58] - node T_279 = shr(T_278, 5) @[rvc.scala 63:29] - node T_281 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_282 = cat(UInt<2>("h01"), T_281) @[Cat.scala 20:58] - node T_284 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_285 = cat(UInt<2>("h01"), T_284) @[Cat.scala 20:58] - node T_287 = bits(io.in, 5, 5) @[rvc.scala 33:20] - node T_288 = bits(io.in, 12, 10) @[rvc.scala 33:26] - node T_289 = bits(io.in, 6, 6) @[rvc.scala 33:36] - node T_291 = cat(T_289, UInt<2>("h00")) @[Cat.scala 20:58] - node T_292 = cat(T_287, T_288) @[Cat.scala 20:58] - node T_293 = cat(T_292, T_291) @[Cat.scala 20:58] - node T_294 = bits(T_293, 4, 0) @[rvc.scala 63:63] - node T_296 = cat(UInt<3>("h02"), T_294) @[Cat.scala 20:58] - node T_297 = cat(T_296, UInt<7>("h023")) @[Cat.scala 20:58] - node T_298 = cat(T_279, T_282) @[Cat.scala 20:58] - node T_299 = cat(T_298, T_285) @[Cat.scala 20:58] - node T_300 = cat(T_299, T_297) @[Cat.scala 20:58] - node T_302 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_303 = cat(UInt<2>("h01"), T_302) @[Cat.scala 20:58] - node T_305 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_306 = cat(UInt<2>("h01"), T_305) @[Cat.scala 20:58] - node T_308 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_309 = cat(UInt<2>("h01"), T_308) @[Cat.scala 20:58] - node T_310 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_317 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_317 is invalid @[rvc.scala 19:19] - T_317.bits <= T_300 @[rvc.scala 20:14] - T_317.rd <= T_303 @[rvc.scala 21:12] - T_317.rs1 <= T_306 @[rvc.scala 22:13] - T_317.rs2 <= T_309 @[rvc.scala 23:13] - T_317.rs3 <= T_310 @[rvc.scala 24:13] - node T_323 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_324 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_326 = cat(T_323, T_324) @[Cat.scala 20:58] - node T_327 = cat(T_326, UInt<3>("h00")) @[Cat.scala 20:58] - node T_328 = shr(T_327, 5) @[rvc.scala 62:29] - node T_330 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_331 = cat(UInt<2>("h01"), T_330) @[Cat.scala 20:58] - node T_333 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_334 = cat(UInt<2>("h01"), T_333) @[Cat.scala 20:58] - node T_336 = bits(io.in, 6, 5) @[rvc.scala 34:20] - node T_337 = bits(io.in, 12, 10) @[rvc.scala 34:28] - node T_339 = cat(T_336, T_337) @[Cat.scala 20:58] - node T_340 = cat(T_339, UInt<3>("h00")) @[Cat.scala 20:58] - node T_341 = bits(T_340, 4, 0) @[rvc.scala 62:63] - node T_343 = cat(UInt<3>("h03"), T_341) @[Cat.scala 20:58] - node T_344 = cat(T_343, UInt<7>("h023")) @[Cat.scala 20:58] - node T_345 = cat(T_328, T_331) @[Cat.scala 20:58] - node T_346 = cat(T_345, T_334) @[Cat.scala 20:58] - node T_347 = cat(T_346, T_344) @[Cat.scala 20:58] - node T_349 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_350 = cat(UInt<2>("h01"), T_349) @[Cat.scala 20:58] - node T_352 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_353 = cat(UInt<2>("h01"), T_352) @[Cat.scala 20:58] - node T_355 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_356 = cat(UInt<2>("h01"), T_355) @[Cat.scala 20:58] - node T_357 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_364 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_364 is invalid @[rvc.scala 19:19] - T_364.bits <= T_347 @[rvc.scala 20:14] - T_364.rd <= T_350 @[rvc.scala 21:12] - T_364.rs1 <= T_353 @[rvc.scala 22:13] - T_364.rs2 <= T_356 @[rvc.scala 23:13] - T_364.rs3 <= T_357 @[rvc.scala 24:13] - node T_370 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_371 = bits(T_370, 0, 0) @[Bitwise.scala 33:15] - node T_374 = mux(T_371, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_375 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_376 = cat(T_374, T_375) @[Cat.scala 20:58] - node T_377 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_379 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_381 = cat(T_379, UInt<7>("h013")) @[Cat.scala 20:58] - node T_382 = cat(T_376, T_377) @[Cat.scala 20:58] - node T_383 = cat(T_382, UInt<3>("h00")) @[Cat.scala 20:58] - node T_384 = cat(T_383, T_381) @[Cat.scala 20:58] - node T_385 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_386 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_388 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_389 = cat(UInt<2>("h01"), T_388) @[Cat.scala 20:58] - node T_390 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_397 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_397 is invalid @[rvc.scala 19:19] - T_397.bits <= T_384 @[rvc.scala 20:14] - T_397.rd <= T_385 @[rvc.scala 21:12] - T_397.rs1 <= T_386 @[rvc.scala 22:13] - T_397.rs2 <= T_389 @[rvc.scala 23:13] - T_397.rs3 <= T_390 @[rvc.scala 24:13] - node T_403 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_405 = neq(T_403, UInt<1>("h00")) @[rvc.scala 75:24] - node T_408 = mux(T_405, UInt<7>("h01b"), UInt<7>("h01f")) @[rvc.scala 75:20] - node T_409 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_410 = bits(T_409, 0, 0) @[Bitwise.scala 33:15] - node T_413 = mux(T_410, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_414 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_415 = cat(T_413, T_414) @[Cat.scala 20:58] - node T_416 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_418 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_419 = cat(T_418, T_408) @[Cat.scala 20:58] - node T_420 = cat(T_415, T_416) @[Cat.scala 20:58] - node T_421 = cat(T_420, UInt<3>("h00")) @[Cat.scala 20:58] - node T_422 = cat(T_421, T_419) @[Cat.scala 20:58] - node T_423 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_424 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_426 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_427 = cat(UInt<2>("h01"), T_426) @[Cat.scala 20:58] - node T_428 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_435 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_435 is invalid @[rvc.scala 19:19] - T_435.bits <= T_422 @[rvc.scala 20:14] - T_435.rd <= T_423 @[rvc.scala 21:12] - T_435.rs1 <= T_424 @[rvc.scala 22:13] - T_435.rs2 <= T_427 @[rvc.scala 23:13] - T_435.rs3 <= T_428 @[rvc.scala 24:13] - node T_441 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_442 = bits(T_441, 0, 0) @[Bitwise.scala 33:15] - node T_445 = mux(T_442, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_446 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_447 = cat(T_445, T_446) @[Cat.scala 20:58] - node T_450 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_452 = cat(T_450, UInt<7>("h013")) @[Cat.scala 20:58] - node T_453 = cat(T_447, UInt<5>("h00")) @[Cat.scala 20:58] - node T_454 = cat(T_453, UInt<3>("h00")) @[Cat.scala 20:58] - node T_455 = cat(T_454, T_452) @[Cat.scala 20:58] - node T_456 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_459 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_460 = cat(UInt<2>("h01"), T_459) @[Cat.scala 20:58] - node T_461 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_468 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_468 is invalid @[rvc.scala 19:19] - T_468.bits <= T_455 @[rvc.scala 20:14] - T_468.rd <= T_456 @[rvc.scala 21:12] - T_468.rs1 <= UInt<5>("h00") @[rvc.scala 22:13] - T_468.rs2 <= T_460 @[rvc.scala 23:13] - T_468.rs3 <= T_461 @[rvc.scala 24:13] - node T_474 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_475 = bits(T_474, 0, 0) @[Bitwise.scala 33:15] - node T_478 = mux(T_475, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_479 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_480 = cat(T_478, T_479) @[Cat.scala 20:58] - node T_482 = neq(T_480, UInt<1>("h00")) @[rvc.scala 88:29] - node T_485 = mux(T_482, UInt<7>("h037"), UInt<7>("h03f")) @[rvc.scala 88:20] - node T_486 = bits(io.in, 12, 12) @[rvc.scala 39:30] - node T_487 = bits(T_486, 0, 0) @[Bitwise.scala 33:15] - node T_490 = mux(T_487, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 33:12] - node T_491 = bits(io.in, 6, 2) @[rvc.scala 39:38] - node T_493 = cat(T_490, T_491) @[Cat.scala 20:58] - node T_494 = cat(T_493, UInt<12>("h00")) @[Cat.scala 20:58] - node T_495 = bits(T_494, 31, 12) @[rvc.scala 89:31] - node T_496 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_497 = cat(T_495, T_496) @[Cat.scala 20:58] - node T_498 = cat(T_497, T_485) @[Cat.scala 20:58] - node T_499 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_500 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_502 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_503 = cat(UInt<2>("h01"), T_502) @[Cat.scala 20:58] - node T_504 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_511 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_511 is invalid @[rvc.scala 19:19] - T_511.bits <= T_498 @[rvc.scala 20:14] - T_511.rd <= T_499 @[rvc.scala 21:12] - T_511.rs1 <= T_500 @[rvc.scala 22:13] - T_511.rs2 <= T_503 @[rvc.scala 23:13] - T_511.rs3 <= T_504 @[rvc.scala 24:13] - node T_517 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_519 = eq(T_517, UInt<5>("h00")) @[rvc.scala 90:14] - node T_520 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_522 = eq(T_520, UInt<5>("h02")) @[rvc.scala 90:27] - node T_523 = or(T_519, T_522) @[rvc.scala 90:21] - node T_524 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_525 = bits(T_524, 0, 0) @[Bitwise.scala 33:15] - node T_528 = mux(T_525, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_529 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_530 = cat(T_528, T_529) @[Cat.scala 20:58] - node T_532 = neq(T_530, UInt<1>("h00")) @[rvc.scala 84:29] - node T_535 = mux(T_532, UInt<7>("h013"), UInt<7>("h01f")) @[rvc.scala 84:20] - node T_536 = bits(io.in, 12, 12) @[rvc.scala 40:34] - node T_537 = bits(T_536, 0, 0) @[Bitwise.scala 33:15] - node T_540 = mux(T_537, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_541 = bits(io.in, 4, 3) @[rvc.scala 40:42] - node T_542 = bits(io.in, 5, 5) @[rvc.scala 40:50] - node T_543 = bits(io.in, 2, 2) @[rvc.scala 40:56] - node T_544 = bits(io.in, 6, 6) @[rvc.scala 40:62] - node T_546 = cat(T_543, T_544) @[Cat.scala 20:58] - node T_547 = cat(T_546, UInt<4>("h00")) @[Cat.scala 20:58] - node T_548 = cat(T_540, T_541) @[Cat.scala 20:58] - node T_549 = cat(T_548, T_542) @[Cat.scala 20:58] - node T_550 = cat(T_549, T_547) @[Cat.scala 20:58] - node T_551 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_553 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_554 = cat(T_553, T_535) @[Cat.scala 20:58] - node T_555 = cat(T_550, T_551) @[Cat.scala 20:58] - node T_556 = cat(T_555, UInt<3>("h00")) @[Cat.scala 20:58] - node T_557 = cat(T_556, T_554) @[Cat.scala 20:58] - node T_558 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_559 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_561 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_562 = cat(UInt<2>("h01"), T_561) @[Cat.scala 20:58] - node T_563 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_570 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_570 is invalid @[rvc.scala 19:19] - T_570.bits <= T_557 @[rvc.scala 20:14] - T_570.rd <= T_558 @[rvc.scala 21:12] - T_570.rs1 <= T_559 @[rvc.scala 22:13] - T_570.rs2 <= T_562 @[rvc.scala 23:13] - T_570.rs3 <= T_563 @[rvc.scala 24:13] - node T_576 = mux(T_523, T_570, T_511) @[rvc.scala 90:10] - node T_582 = bits(io.in, 12, 12) @[rvc.scala 44:20] - node T_583 = bits(io.in, 6, 2) @[rvc.scala 44:27] - node T_584 = cat(T_582, T_583) @[Cat.scala 20:58] - node T_586 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_587 = cat(UInt<2>("h01"), T_586) @[Cat.scala 20:58] - node T_590 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_591 = cat(UInt<2>("h01"), T_590) @[Cat.scala 20:58] - node T_593 = cat(T_591, UInt<7>("h013")) @[Cat.scala 20:58] - node T_594 = cat(T_584, T_587) @[Cat.scala 20:58] - node T_595 = cat(T_594, UInt<3>("h05")) @[Cat.scala 20:58] - node T_596 = cat(T_595, T_593) @[Cat.scala 20:58] - node T_597 = bits(io.in, 12, 12) @[rvc.scala 44:20] - node T_598 = bits(io.in, 6, 2) @[rvc.scala 44:27] - node T_599 = cat(T_597, T_598) @[Cat.scala 20:58] - node T_601 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_602 = cat(UInt<2>("h01"), T_601) @[Cat.scala 20:58] - node T_605 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_606 = cat(UInt<2>("h01"), T_605) @[Cat.scala 20:58] - node T_608 = cat(T_606, UInt<7>("h013")) @[Cat.scala 20:58] - node T_609 = cat(T_599, T_602) @[Cat.scala 20:58] - node T_610 = cat(T_609, UInt<3>("h05")) @[Cat.scala 20:58] - node T_611 = cat(T_610, T_608) @[Cat.scala 20:58] - node T_613 = or(T_611, UInt<31>("h040000000")) @[rvc.scala 97:23] - node T_614 = bits(io.in, 12, 12) @[rvc.scala 41:30] - node T_615 = bits(T_614, 0, 0) @[Bitwise.scala 33:15] - node T_618 = mux(T_615, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_619 = bits(io.in, 6, 2) @[rvc.scala 41:38] - node T_620 = cat(T_618, T_619) @[Cat.scala 20:58] - node T_622 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_623 = cat(UInt<2>("h01"), T_622) @[Cat.scala 20:58] - node T_626 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_627 = cat(UInt<2>("h01"), T_626) @[Cat.scala 20:58] - node T_629 = cat(T_627, UInt<7>("h013")) @[Cat.scala 20:58] - node T_630 = cat(T_620, T_623) @[Cat.scala 20:58] - node T_631 = cat(T_630, UInt<3>("h07")) @[Cat.scala 20:58] - node T_632 = cat(T_631, T_629) @[Cat.scala 20:58] - node T_641 = bits(io.in, 12, 12) @[rvc.scala 100:70] - node T_642 = bits(io.in, 6, 5) @[rvc.scala 100:77] - node T_643 = cat(T_641, T_642) @[Cat.scala 20:58] - node T_645 = and(T_643, UInt<2>("h03")) @[Package.scala 18:26] - node T_647 = geq(T_643, UInt<3>("h04")) @[Package.scala 19:17] - node T_649 = and(T_645, UInt<1>("h01")) @[Package.scala 18:26] - node T_651 = geq(T_645, UInt<2>("h02")) @[Package.scala 19:17] - node T_653 = and(T_649, UInt<1>("h00")) @[Package.scala 18:26] - node T_655 = geq(T_649, UInt<1>("h01")) @[Package.scala 19:17] - node T_656 = mux(T_655, UInt<2>("h03"), UInt<2>("h02")) @[Package.scala 19:12] - node T_658 = and(T_649, UInt<1>("h00")) @[Package.scala 18:26] - node T_660 = geq(T_649, UInt<1>("h01")) @[Package.scala 19:17] - node T_661 = mux(T_660, UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 19:12] - node T_662 = mux(T_651, T_656, T_661) @[Package.scala 19:12] - node T_664 = and(T_645, UInt<1>("h01")) @[Package.scala 18:26] - node T_666 = geq(T_645, UInt<2>("h02")) @[Package.scala 19:17] - node T_668 = and(T_664, UInt<1>("h00")) @[Package.scala 18:26] - node T_670 = geq(T_664, UInt<1>("h01")) @[Package.scala 19:17] - node T_671 = mux(T_670, UInt<3>("h07"), UInt<3>("h06")) @[Package.scala 19:12] - node T_673 = and(T_664, UInt<1>("h00")) @[Package.scala 18:26] - node T_675 = geq(T_664, UInt<1>("h01")) @[Package.scala 19:17] - node T_676 = mux(T_675, UInt<3>("h04"), UInt<1>("h00")) @[Package.scala 19:12] - node T_677 = mux(T_666, T_671, T_676) @[Package.scala 19:12] - node T_678 = mux(T_647, T_662, T_677) @[Package.scala 19:12] - node T_679 = bits(io.in, 6, 5) @[rvc.scala 101:24] - node T_681 = eq(T_679, UInt<1>("h00")) @[rvc.scala 101:30] - node T_684 = mux(T_681, UInt<31>("h040000000"), UInt<1>("h00")) @[rvc.scala 101:22] - node T_685 = bits(io.in, 12, 12) @[rvc.scala 102:24] - node T_688 = mux(T_685, UInt<7>("h03b"), UInt<7>("h033")) @[rvc.scala 102:22] - node T_690 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_691 = cat(UInt<2>("h01"), T_690) @[Cat.scala 20:58] - node T_693 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_694 = cat(UInt<2>("h01"), T_693) @[Cat.scala 20:58] - node T_696 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_697 = cat(UInt<2>("h01"), T_696) @[Cat.scala 20:58] - node T_698 = cat(T_697, T_688) @[Cat.scala 20:58] - node T_699 = cat(T_691, T_694) @[Cat.scala 20:58] - node T_700 = cat(T_699, T_678) @[Cat.scala 20:58] - node T_701 = cat(T_700, T_698) @[Cat.scala 20:58] - node T_702 = or(T_701, T_684) @[rvc.scala 103:43] - node T_703 = bits(io.in, 11, 10) @[rvc.scala 105:42] - node T_705 = and(T_703, UInt<1>("h01")) @[Package.scala 18:26] - node T_707 = geq(T_703, UInt<2>("h02")) @[Package.scala 19:17] - node T_709 = and(T_705, UInt<1>("h00")) @[Package.scala 18:26] - node T_711 = geq(T_705, UInt<1>("h01")) @[Package.scala 19:17] - node T_712 = mux(T_711, T_702, T_632) @[Package.scala 19:12] - node T_714 = and(T_705, UInt<1>("h00")) @[Package.scala 18:26] - node T_716 = geq(T_705, UInt<1>("h01")) @[Package.scala 19:17] - node T_717 = mux(T_716, T_613, T_596) @[Package.scala 19:12] - node T_718 = mux(T_707, T_712, T_717) @[Package.scala 19:12] - node T_720 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_721 = cat(UInt<2>("h01"), T_720) @[Cat.scala 20:58] - node T_723 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_724 = cat(UInt<2>("h01"), T_723) @[Cat.scala 20:58] - node T_726 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_727 = cat(UInt<2>("h01"), T_726) @[Cat.scala 20:58] - node T_728 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_735 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_735 is invalid @[rvc.scala 19:19] - T_735.bits <= T_718 @[rvc.scala 20:14] - T_735.rd <= T_721 @[rvc.scala 21:12] - T_735.rs1 <= T_724 @[rvc.scala 22:13] - T_735.rs2 <= T_727 @[rvc.scala 23:13] - T_735.rs3 <= T_728 @[rvc.scala 24:13] - node T_741 = bits(io.in, 12, 12) @[rvc.scala 42:28] - node T_742 = bits(T_741, 0, 0) @[Bitwise.scala 33:15] - node T_745 = mux(T_742, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 33:12] - node T_746 = bits(io.in, 8, 8) @[rvc.scala 42:36] - node T_747 = bits(io.in, 10, 9) @[rvc.scala 42:42] - node T_748 = bits(io.in, 6, 6) @[rvc.scala 42:51] - node T_749 = bits(io.in, 7, 7) @[rvc.scala 42:57] - node T_750 = bits(io.in, 2, 2) @[rvc.scala 42:63] - node T_751 = bits(io.in, 11, 11) @[rvc.scala 42:69] - node T_752 = bits(io.in, 5, 3) @[rvc.scala 42:76] - node T_754 = cat(T_752, UInt<1>("h00")) @[Cat.scala 20:58] - node T_755 = cat(T_750, T_751) @[Cat.scala 20:58] - node T_756 = cat(T_755, T_754) @[Cat.scala 20:58] - node T_757 = cat(T_748, T_749) @[Cat.scala 20:58] - node T_758 = cat(T_745, T_746) @[Cat.scala 20:58] - node T_759 = cat(T_758, T_747) @[Cat.scala 20:58] - node T_760 = cat(T_759, T_757) @[Cat.scala 20:58] - node T_761 = cat(T_760, T_756) @[Cat.scala 20:58] - node T_762 = bits(T_761, 20, 20) @[rvc.scala 92:26] - node T_763 = bits(io.in, 12, 12) @[rvc.scala 42:28] - node T_764 = bits(T_763, 0, 0) @[Bitwise.scala 33:15] - node T_767 = mux(T_764, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 33:12] - node T_768 = bits(io.in, 8, 8) @[rvc.scala 42:36] - node T_769 = bits(io.in, 10, 9) @[rvc.scala 42:42] - node T_770 = bits(io.in, 6, 6) @[rvc.scala 42:51] - node T_771 = bits(io.in, 7, 7) @[rvc.scala 42:57] - node T_772 = bits(io.in, 2, 2) @[rvc.scala 42:63] - node T_773 = bits(io.in, 11, 11) @[rvc.scala 42:69] - node T_774 = bits(io.in, 5, 3) @[rvc.scala 42:76] - node T_776 = cat(T_774, UInt<1>("h00")) @[Cat.scala 20:58] - node T_777 = cat(T_772, T_773) @[Cat.scala 20:58] - node T_778 = cat(T_777, T_776) @[Cat.scala 20:58] - node T_779 = cat(T_770, T_771) @[Cat.scala 20:58] - node T_780 = cat(T_767, T_768) @[Cat.scala 20:58] - node T_781 = cat(T_780, T_769) @[Cat.scala 20:58] - node T_782 = cat(T_781, T_779) @[Cat.scala 20:58] - node T_783 = cat(T_782, T_778) @[Cat.scala 20:58] - node T_784 = bits(T_783, 10, 1) @[rvc.scala 92:36] - node T_785 = bits(io.in, 12, 12) @[rvc.scala 42:28] - node T_786 = bits(T_785, 0, 0) @[Bitwise.scala 33:15] - node T_789 = mux(T_786, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 33:12] - node T_790 = bits(io.in, 8, 8) @[rvc.scala 42:36] - node T_791 = bits(io.in, 10, 9) @[rvc.scala 42:42] - node T_792 = bits(io.in, 6, 6) @[rvc.scala 42:51] - node T_793 = bits(io.in, 7, 7) @[rvc.scala 42:57] - node T_794 = bits(io.in, 2, 2) @[rvc.scala 42:63] - node T_795 = bits(io.in, 11, 11) @[rvc.scala 42:69] - node T_796 = bits(io.in, 5, 3) @[rvc.scala 42:76] - node T_798 = cat(T_796, UInt<1>("h00")) @[Cat.scala 20:58] - node T_799 = cat(T_794, T_795) @[Cat.scala 20:58] - node T_800 = cat(T_799, T_798) @[Cat.scala 20:58] - node T_801 = cat(T_792, T_793) @[Cat.scala 20:58] - node T_802 = cat(T_789, T_790) @[Cat.scala 20:58] - node T_803 = cat(T_802, T_791) @[Cat.scala 20:58] - node T_804 = cat(T_803, T_801) @[Cat.scala 20:58] - node T_805 = cat(T_804, T_800) @[Cat.scala 20:58] - node T_806 = bits(T_805, 11, 11) @[rvc.scala 92:48] - node T_807 = bits(io.in, 12, 12) @[rvc.scala 42:28] - node T_808 = bits(T_807, 0, 0) @[Bitwise.scala 33:15] - node T_811 = mux(T_808, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 33:12] - node T_812 = bits(io.in, 8, 8) @[rvc.scala 42:36] - node T_813 = bits(io.in, 10, 9) @[rvc.scala 42:42] - node T_814 = bits(io.in, 6, 6) @[rvc.scala 42:51] - node T_815 = bits(io.in, 7, 7) @[rvc.scala 42:57] - node T_816 = bits(io.in, 2, 2) @[rvc.scala 42:63] - node T_817 = bits(io.in, 11, 11) @[rvc.scala 42:69] - node T_818 = bits(io.in, 5, 3) @[rvc.scala 42:76] - node T_820 = cat(T_818, UInt<1>("h00")) @[Cat.scala 20:58] - node T_821 = cat(T_816, T_817) @[Cat.scala 20:58] - node T_822 = cat(T_821, T_820) @[Cat.scala 20:58] - node T_823 = cat(T_814, T_815) @[Cat.scala 20:58] - node T_824 = cat(T_811, T_812) @[Cat.scala 20:58] - node T_825 = cat(T_824, T_813) @[Cat.scala 20:58] - node T_826 = cat(T_825, T_823) @[Cat.scala 20:58] - node T_827 = cat(T_826, T_822) @[Cat.scala 20:58] - node T_828 = bits(T_827, 19, 12) @[rvc.scala 92:58] - node T_831 = cat(T_828, UInt<5>("h00")) @[Cat.scala 20:58] - node T_832 = cat(T_831, UInt<7>("h06f")) @[Cat.scala 20:58] - node T_833 = cat(T_762, T_784) @[Cat.scala 20:58] - node T_834 = cat(T_833, T_806) @[Cat.scala 20:58] - node T_835 = cat(T_834, T_832) @[Cat.scala 20:58] - node T_838 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_839 = cat(UInt<2>("h01"), T_838) @[Cat.scala 20:58] - node T_841 = bits(io.in, 4, 2) @[rvc.scala 29:30] - node T_842 = cat(UInt<2>("h01"), T_841) @[Cat.scala 20:58] - node T_843 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_850 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_850 is invalid @[rvc.scala 19:19] - T_850.bits <= T_835 @[rvc.scala 20:14] - T_850.rd <= UInt<5>("h00") @[rvc.scala 21:12] - T_850.rs1 <= T_839 @[rvc.scala 22:13] - T_850.rs2 <= T_842 @[rvc.scala 23:13] - T_850.rs3 <= T_843 @[rvc.scala 24:13] - node T_856 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_857 = bits(T_856, 0, 0) @[Bitwise.scala 33:15] - node T_860 = mux(T_857, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_861 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_862 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_863 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_864 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_866 = cat(T_863, T_864) @[Cat.scala 20:58] - node T_867 = cat(T_866, UInt<1>("h00")) @[Cat.scala 20:58] - node T_868 = cat(T_860, T_861) @[Cat.scala 20:58] - node T_869 = cat(T_868, T_862) @[Cat.scala 20:58] - node T_870 = cat(T_869, T_867) @[Cat.scala 20:58] - node T_871 = bits(T_870, 12, 12) @[rvc.scala 93:29] - node T_872 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_873 = bits(T_872, 0, 0) @[Bitwise.scala 33:15] - node T_876 = mux(T_873, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_877 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_878 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_879 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_880 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_882 = cat(T_879, T_880) @[Cat.scala 20:58] - node T_883 = cat(T_882, UInt<1>("h00")) @[Cat.scala 20:58] - node T_884 = cat(T_876, T_877) @[Cat.scala 20:58] - node T_885 = cat(T_884, T_878) @[Cat.scala 20:58] - node T_886 = cat(T_885, T_883) @[Cat.scala 20:58] - node T_887 = bits(T_886, 10, 5) @[rvc.scala 93:39] - node T_890 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_891 = cat(UInt<2>("h01"), T_890) @[Cat.scala 20:58] - node T_893 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_894 = bits(T_893, 0, 0) @[Bitwise.scala 33:15] - node T_897 = mux(T_894, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_898 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_899 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_900 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_901 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_903 = cat(T_900, T_901) @[Cat.scala 20:58] - node T_904 = cat(T_903, UInt<1>("h00")) @[Cat.scala 20:58] - node T_905 = cat(T_897, T_898) @[Cat.scala 20:58] - node T_906 = cat(T_905, T_899) @[Cat.scala 20:58] - node T_907 = cat(T_906, T_904) @[Cat.scala 20:58] - node T_908 = bits(T_907, 4, 1) @[rvc.scala 93:72] - node T_909 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_910 = bits(T_909, 0, 0) @[Bitwise.scala 33:15] - node T_913 = mux(T_910, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_914 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_915 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_916 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_917 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_919 = cat(T_916, T_917) @[Cat.scala 20:58] - node T_920 = cat(T_919, UInt<1>("h00")) @[Cat.scala 20:58] - node T_921 = cat(T_913, T_914) @[Cat.scala 20:58] - node T_922 = cat(T_921, T_915) @[Cat.scala 20:58] - node T_923 = cat(T_922, T_920) @[Cat.scala 20:58] - node T_924 = bits(T_923, 11, 11) @[rvc.scala 93:83] - node T_926 = cat(T_924, UInt<7>("h063")) @[Cat.scala 20:58] - node T_927 = cat(UInt<3>("h00"), T_908) @[Cat.scala 20:58] - node T_928 = cat(T_927, T_926) @[Cat.scala 20:58] - node T_929 = cat(UInt<5>("h00"), T_891) @[Cat.scala 20:58] - node T_930 = cat(T_871, T_887) @[Cat.scala 20:58] - node T_931 = cat(T_930, T_929) @[Cat.scala 20:58] - node T_932 = cat(T_931, T_928) @[Cat.scala 20:58] - node T_934 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_935 = cat(UInt<2>("h01"), T_934) @[Cat.scala 20:58] - node T_937 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_938 = cat(UInt<2>("h01"), T_937) @[Cat.scala 20:58] - node T_940 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_947 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_947 is invalid @[rvc.scala 19:19] - T_947.bits <= T_932 @[rvc.scala 20:14] - T_947.rd <= T_935 @[rvc.scala 21:12] - T_947.rs1 <= T_938 @[rvc.scala 22:13] - T_947.rs2 <= UInt<5>("h00") @[rvc.scala 23:13] - T_947.rs3 <= T_940 @[rvc.scala 24:13] - node T_953 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_954 = bits(T_953, 0, 0) @[Bitwise.scala 33:15] - node T_957 = mux(T_954, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_958 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_959 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_960 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_961 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_963 = cat(T_960, T_961) @[Cat.scala 20:58] - node T_964 = cat(T_963, UInt<1>("h00")) @[Cat.scala 20:58] - node T_965 = cat(T_957, T_958) @[Cat.scala 20:58] - node T_966 = cat(T_965, T_959) @[Cat.scala 20:58] - node T_967 = cat(T_966, T_964) @[Cat.scala 20:58] - node T_968 = bits(T_967, 12, 12) @[rvc.scala 94:29] - node T_969 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_970 = bits(T_969, 0, 0) @[Bitwise.scala 33:15] - node T_973 = mux(T_970, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_974 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_975 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_976 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_977 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_979 = cat(T_976, T_977) @[Cat.scala 20:58] - node T_980 = cat(T_979, UInt<1>("h00")) @[Cat.scala 20:58] - node T_981 = cat(T_973, T_974) @[Cat.scala 20:58] - node T_982 = cat(T_981, T_975) @[Cat.scala 20:58] - node T_983 = cat(T_982, T_980) @[Cat.scala 20:58] - node T_984 = bits(T_983, 10, 5) @[rvc.scala 94:39] - node T_987 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_988 = cat(UInt<2>("h01"), T_987) @[Cat.scala 20:58] - node T_990 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_991 = bits(T_990, 0, 0) @[Bitwise.scala 33:15] - node T_994 = mux(T_991, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_995 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_996 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_997 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_998 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_1000 = cat(T_997, T_998) @[Cat.scala 20:58] - node T_1001 = cat(T_1000, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1002 = cat(T_994, T_995) @[Cat.scala 20:58] - node T_1003 = cat(T_1002, T_996) @[Cat.scala 20:58] - node T_1004 = cat(T_1003, T_1001) @[Cat.scala 20:58] - node T_1005 = bits(T_1004, 4, 1) @[rvc.scala 94:72] - node T_1006 = bits(io.in, 12, 12) @[rvc.scala 43:27] - node T_1007 = bits(T_1006, 0, 0) @[Bitwise.scala 33:15] - node T_1010 = mux(T_1007, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 33:12] - node T_1011 = bits(io.in, 6, 5) @[rvc.scala 43:35] - node T_1012 = bits(io.in, 2, 2) @[rvc.scala 43:43] - node T_1013 = bits(io.in, 11, 10) @[rvc.scala 43:49] - node T_1014 = bits(io.in, 4, 3) @[rvc.scala 43:59] - node T_1016 = cat(T_1013, T_1014) @[Cat.scala 20:58] - node T_1017 = cat(T_1016, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1018 = cat(T_1010, T_1011) @[Cat.scala 20:58] - node T_1019 = cat(T_1018, T_1012) @[Cat.scala 20:58] - node T_1020 = cat(T_1019, T_1017) @[Cat.scala 20:58] - node T_1021 = bits(T_1020, 11, 11) @[rvc.scala 94:83] - node T_1023 = cat(T_1021, UInt<7>("h063")) @[Cat.scala 20:58] - node T_1024 = cat(UInt<3>("h01"), T_1005) @[Cat.scala 20:58] - node T_1025 = cat(T_1024, T_1023) @[Cat.scala 20:58] - node T_1026 = cat(UInt<5>("h00"), T_988) @[Cat.scala 20:58] - node T_1027 = cat(T_968, T_984) @[Cat.scala 20:58] - node T_1028 = cat(T_1027, T_1026) @[Cat.scala 20:58] - node T_1029 = cat(T_1028, T_1025) @[Cat.scala 20:58] - node T_1032 = bits(io.in, 9, 7) @[rvc.scala 28:30] - node T_1033 = cat(UInt<2>("h01"), T_1032) @[Cat.scala 20:58] - node T_1035 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1042 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1042 is invalid @[rvc.scala 19:19] - T_1042.bits <= T_1029 @[rvc.scala 20:14] - T_1042.rd <= UInt<5>("h00") @[rvc.scala 21:12] - T_1042.rs1 <= T_1033 @[rvc.scala 22:13] - T_1042.rs2 <= UInt<5>("h00") @[rvc.scala 23:13] - T_1042.rs3 <= T_1035 @[rvc.scala 24:13] - node T_1048 = bits(io.in, 12, 12) @[rvc.scala 44:20] - node T_1049 = bits(io.in, 6, 2) @[rvc.scala 44:27] - node T_1050 = cat(T_1048, T_1049) @[Cat.scala 20:58] - node T_1051 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1053 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1055 = cat(T_1053, UInt<7>("h013")) @[Cat.scala 20:58] - node T_1056 = cat(T_1050, T_1051) @[Cat.scala 20:58] - node T_1057 = cat(T_1056, UInt<3>("h01")) @[Cat.scala 20:58] - node T_1058 = cat(T_1057, T_1055) @[Cat.scala 20:58] - node T_1059 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1060 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1061 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1062 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1069 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1069 is invalid @[rvc.scala 19:19] - T_1069.bits <= T_1058 @[rvc.scala 20:14] - T_1069.rd <= T_1059 @[rvc.scala 21:12] - T_1069.rs1 <= T_1060 @[rvc.scala 22:13] - T_1069.rs2 <= T_1061 @[rvc.scala 23:13] - T_1069.rs3 <= T_1062 @[rvc.scala 24:13] - node T_1075 = bits(io.in, 4, 2) @[rvc.scala 36:22] - node T_1076 = bits(io.in, 12, 12) @[rvc.scala 36:30] - node T_1077 = bits(io.in, 6, 5) @[rvc.scala 36:37] - node T_1079 = cat(T_1077, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1080 = cat(T_1075, T_1076) @[Cat.scala 20:58] - node T_1081 = cat(T_1080, T_1079) @[Cat.scala 20:58] - node T_1084 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1086 = cat(T_1084, UInt<7>("h07")) @[Cat.scala 20:58] - node T_1087 = cat(T_1081, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1088 = cat(T_1087, UInt<3>("h03")) @[Cat.scala 20:58] - node T_1089 = cat(T_1088, T_1086) @[Cat.scala 20:58] - node T_1090 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1092 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1093 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1100 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1100 is invalid @[rvc.scala 19:19] - T_1100.bits <= T_1089 @[rvc.scala 20:14] - T_1100.rd <= T_1090 @[rvc.scala 21:12] - T_1100.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1100.rs2 <= T_1092 @[rvc.scala 23:13] - T_1100.rs3 <= T_1093 @[rvc.scala 24:13] - node T_1106 = bits(io.in, 3, 2) @[rvc.scala 35:22] - node T_1107 = bits(io.in, 12, 12) @[rvc.scala 35:30] - node T_1108 = bits(io.in, 6, 4) @[rvc.scala 35:37] - node T_1110 = cat(T_1108, UInt<2>("h00")) @[Cat.scala 20:58] - node T_1111 = cat(T_1106, T_1107) @[Cat.scala 20:58] - node T_1112 = cat(T_1111, T_1110) @[Cat.scala 20:58] - node T_1115 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1117 = cat(T_1115, UInt<7>("h03")) @[Cat.scala 20:58] - node T_1118 = cat(T_1112, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1119 = cat(T_1118, UInt<3>("h02")) @[Cat.scala 20:58] - node T_1120 = cat(T_1119, T_1117) @[Cat.scala 20:58] - node T_1121 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1123 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1124 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1131 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1131 is invalid @[rvc.scala 19:19] - T_1131.bits <= T_1120 @[rvc.scala 20:14] - T_1131.rd <= T_1121 @[rvc.scala 21:12] - T_1131.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1131.rs2 <= T_1123 @[rvc.scala 23:13] - T_1131.rs3 <= T_1124 @[rvc.scala 24:13] - node T_1137 = bits(io.in, 4, 2) @[rvc.scala 36:22] - node T_1138 = bits(io.in, 12, 12) @[rvc.scala 36:30] - node T_1139 = bits(io.in, 6, 5) @[rvc.scala 36:37] - node T_1141 = cat(T_1139, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1142 = cat(T_1137, T_1138) @[Cat.scala 20:58] - node T_1143 = cat(T_1142, T_1141) @[Cat.scala 20:58] - node T_1146 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1148 = cat(T_1146, UInt<7>("h03")) @[Cat.scala 20:58] - node T_1149 = cat(T_1143, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1150 = cat(T_1149, UInt<3>("h03")) @[Cat.scala 20:58] - node T_1151 = cat(T_1150, T_1148) @[Cat.scala 20:58] - node T_1152 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1154 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1155 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1162 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1162 is invalid @[rvc.scala 19:19] - T_1162.bits <= T_1151 @[rvc.scala 20:14] - T_1162.rd <= T_1152 @[rvc.scala 21:12] - T_1162.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1162.rs2 <= T_1154 @[rvc.scala 23:13] - T_1162.rs3 <= T_1155 @[rvc.scala 24:13] - node T_1168 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1171 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1173 = cat(T_1171, UInt<7>("h033")) @[Cat.scala 20:58] - node T_1174 = cat(T_1168, UInt<5>("h00")) @[Cat.scala 20:58] - node T_1175 = cat(T_1174, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1176 = cat(T_1175, T_1173) @[Cat.scala 20:58] - node T_1177 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1179 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1180 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1187 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1187 is invalid @[rvc.scala 19:19] - T_1187.bits <= T_1176 @[rvc.scala 20:14] - T_1187.rd <= T_1177 @[rvc.scala 21:12] - T_1187.rs1 <= UInt<5>("h00") @[rvc.scala 22:13] - T_1187.rs2 <= T_1179 @[rvc.scala 23:13] - T_1187.rs3 <= T_1180 @[rvc.scala 24:13] - node T_1193 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1194 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1196 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1198 = cat(T_1196, UInt<7>("h033")) @[Cat.scala 20:58] - node T_1199 = cat(T_1193, T_1194) @[Cat.scala 20:58] - node T_1200 = cat(T_1199, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1201 = cat(T_1200, T_1198) @[Cat.scala 20:58] - node T_1202 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1203 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1204 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1205 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1212 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1212 is invalid @[rvc.scala 19:19] - T_1212.bits <= T_1201 @[rvc.scala 20:14] - T_1212.rd <= T_1202 @[rvc.scala 21:12] - T_1212.rs1 <= T_1203 @[rvc.scala 22:13] - T_1212.rs2 <= T_1204 @[rvc.scala 23:13] - T_1212.rs3 <= T_1205 @[rvc.scala 24:13] - node T_1218 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1219 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1223 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 20:58] - node T_1224 = cat(T_1218, T_1219) @[Cat.scala 20:58] - node T_1225 = cat(T_1224, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1226 = cat(T_1225, T_1223) @[Cat.scala 20:58] - node T_1227 = shr(T_1226, 7) @[rvc.scala 130:29] - node T_1229 = cat(T_1227, UInt<7>("h01f")) @[Cat.scala 20:58] - node T_1230 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1232 = neq(T_1230, UInt<1>("h00")) @[rvc.scala 131:37] - node T_1233 = mux(T_1232, T_1226, T_1229) @[rvc.scala 131:33] - node T_1235 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1236 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1237 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1244 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1244 is invalid @[rvc.scala 19:19] - T_1244.bits <= T_1233 @[rvc.scala 20:14] - T_1244.rd <= UInt<5>("h00") @[rvc.scala 21:12] - T_1244.rs1 <= T_1235 @[rvc.scala 22:13] - T_1244.rs2 <= T_1236 @[rvc.scala 23:13] - T_1244.rs3 <= T_1237 @[rvc.scala 24:13] - node T_1250 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1252 = neq(T_1250, UInt<1>("h00")) @[rvc.scala 132:27] - node T_1253 = mux(T_1252, T_1187, T_1244) @[rvc.scala 132:22] - node T_1259 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1260 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1264 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 20:58] - node T_1265 = cat(T_1259, T_1260) @[Cat.scala 20:58] - node T_1266 = cat(T_1265, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1267 = cat(T_1266, T_1264) @[Cat.scala 20:58] - node T_1268 = shr(T_1226, 7) @[rvc.scala 134:27] - node T_1270 = cat(T_1268, UInt<7>("h073")) @[Cat.scala 20:58] - node T_1272 = or(T_1270, UInt<21>("h0100000")) @[rvc.scala 134:47] - node T_1273 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1275 = neq(T_1273, UInt<1>("h00")) @[rvc.scala 135:37] - node T_1276 = mux(T_1275, T_1267, T_1272) @[rvc.scala 135:33] - node T_1278 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1279 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1280 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1287 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1287 is invalid @[rvc.scala 19:19] - T_1287.bits <= T_1276 @[rvc.scala 20:14] - T_1287.rd <= UInt<5>("h01") @[rvc.scala 21:12] - T_1287.rs1 <= T_1278 @[rvc.scala 22:13] - T_1287.rs2 <= T_1279 @[rvc.scala 23:13] - T_1287.rs3 <= T_1280 @[rvc.scala 24:13] - node T_1293 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1295 = neq(T_1293, UInt<1>("h00")) @[rvc.scala 136:30] - node T_1296 = mux(T_1295, T_1212, T_1287) @[rvc.scala 136:25] - node T_1302 = bits(io.in, 12, 12) @[rvc.scala 137:12] - node T_1303 = mux(T_1302, T_1296, T_1253) @[rvc.scala 137:10] - node T_1309 = bits(io.in, 9, 7) @[rvc.scala 38:22] - node T_1310 = bits(io.in, 12, 10) @[rvc.scala 38:30] - node T_1312 = cat(T_1309, T_1310) @[Cat.scala 20:58] - node T_1313 = cat(T_1312, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1314 = shr(T_1313, 5) @[rvc.scala 121:34] - node T_1315 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1318 = bits(io.in, 9, 7) @[rvc.scala 38:22] - node T_1319 = bits(io.in, 12, 10) @[rvc.scala 38:30] - node T_1321 = cat(T_1318, T_1319) @[Cat.scala 20:58] - node T_1322 = cat(T_1321, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1323 = bits(T_1322, 4, 0) @[rvc.scala 121:67] - node T_1325 = cat(UInt<3>("h03"), T_1323) @[Cat.scala 20:58] - node T_1326 = cat(T_1325, UInt<7>("h027")) @[Cat.scala 20:58] - node T_1327 = cat(T_1314, T_1315) @[Cat.scala 20:58] - node T_1328 = cat(T_1327, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1329 = cat(T_1328, T_1326) @[Cat.scala 20:58] - node T_1330 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1332 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1333 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1340 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1340 is invalid @[rvc.scala 19:19] - T_1340.bits <= T_1329 @[rvc.scala 20:14] - T_1340.rd <= T_1330 @[rvc.scala 21:12] - T_1340.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1340.rs2 <= T_1332 @[rvc.scala 23:13] - T_1340.rs3 <= T_1333 @[rvc.scala 24:13] - node T_1346 = bits(io.in, 8, 7) @[rvc.scala 37:22] - node T_1347 = bits(io.in, 12, 9) @[rvc.scala 37:30] - node T_1349 = cat(T_1346, T_1347) @[Cat.scala 20:58] - node T_1350 = cat(T_1349, UInt<2>("h00")) @[Cat.scala 20:58] - node T_1351 = shr(T_1350, 5) @[rvc.scala 120:33] - node T_1352 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1355 = bits(io.in, 8, 7) @[rvc.scala 37:22] - node T_1356 = bits(io.in, 12, 9) @[rvc.scala 37:30] - node T_1358 = cat(T_1355, T_1356) @[Cat.scala 20:58] - node T_1359 = cat(T_1358, UInt<2>("h00")) @[Cat.scala 20:58] - node T_1360 = bits(T_1359, 4, 0) @[rvc.scala 120:66] - node T_1362 = cat(UInt<3>("h02"), T_1360) @[Cat.scala 20:58] - node T_1363 = cat(T_1362, UInt<7>("h023")) @[Cat.scala 20:58] - node T_1364 = cat(T_1351, T_1352) @[Cat.scala 20:58] - node T_1365 = cat(T_1364, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1366 = cat(T_1365, T_1363) @[Cat.scala 20:58] - node T_1367 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1369 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1370 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1377 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1377 is invalid @[rvc.scala 19:19] - T_1377.bits <= T_1366 @[rvc.scala 20:14] - T_1377.rd <= T_1367 @[rvc.scala 21:12] - T_1377.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1377.rs2 <= T_1369 @[rvc.scala 23:13] - T_1377.rs3 <= T_1370 @[rvc.scala 24:13] - node T_1383 = bits(io.in, 9, 7) @[rvc.scala 38:22] - node T_1384 = bits(io.in, 12, 10) @[rvc.scala 38:30] - node T_1386 = cat(T_1383, T_1384) @[Cat.scala 20:58] - node T_1387 = cat(T_1386, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1388 = shr(T_1387, 5) @[rvc.scala 119:33] - node T_1389 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1392 = bits(io.in, 9, 7) @[rvc.scala 38:22] - node T_1393 = bits(io.in, 12, 10) @[rvc.scala 38:30] - node T_1395 = cat(T_1392, T_1393) @[Cat.scala 20:58] - node T_1396 = cat(T_1395, UInt<3>("h00")) @[Cat.scala 20:58] - node T_1397 = bits(T_1396, 4, 0) @[rvc.scala 119:66] - node T_1399 = cat(UInt<3>("h03"), T_1397) @[Cat.scala 20:58] - node T_1400 = cat(T_1399, UInt<7>("h023")) @[Cat.scala 20:58] - node T_1401 = cat(T_1388, T_1389) @[Cat.scala 20:58] - node T_1402 = cat(T_1401, UInt<5>("h02")) @[Cat.scala 20:58] - node T_1403 = cat(T_1402, T_1400) @[Cat.scala 20:58] - node T_1404 = bits(io.in, 11, 7) @[rvc.scala 31:13] - node T_1406 = bits(io.in, 6, 2) @[rvc.scala 30:14] - node T_1407 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1414 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1414 is invalid @[rvc.scala 19:19] - T_1414.bits <= T_1403 @[rvc.scala 20:14] - T_1414.rd <= T_1404 @[rvc.scala 21:12] - T_1414.rs1 <= UInt<5>("h02") @[rvc.scala 22:13] - T_1414.rs2 <= T_1406 @[rvc.scala 23:13] - T_1414.rs3 <= T_1407 @[rvc.scala 24:13] - node T_1420 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1421 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1422 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1423 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1430 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1430 is invalid @[rvc.scala 19:19] - T_1430.bits <= io.in @[rvc.scala 20:14] - T_1430.rd <= T_1420 @[rvc.scala 21:12] - T_1430.rs1 <= T_1421 @[rvc.scala 22:13] - T_1430.rs2 <= T_1422 @[rvc.scala 23:13] - T_1430.rs3 <= T_1423 @[rvc.scala 24:13] - node T_1436 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1437 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1438 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1439 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1446 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1446 is invalid @[rvc.scala 19:19] - T_1446.bits <= io.in @[rvc.scala 20:14] - T_1446.rd <= T_1436 @[rvc.scala 21:12] - T_1446.rs1 <= T_1437 @[rvc.scala 22:13] - T_1446.rs2 <= T_1438 @[rvc.scala 23:13] - T_1446.rs3 <= T_1439 @[rvc.scala 24:13] - node T_1452 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1453 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1454 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1455 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1462 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1462 is invalid @[rvc.scala 19:19] - T_1462.bits <= io.in @[rvc.scala 20:14] - T_1462.rd <= T_1452 @[rvc.scala 21:12] - T_1462.rs1 <= T_1453 @[rvc.scala 22:13] - T_1462.rs2 <= T_1454 @[rvc.scala 23:13] - T_1462.rs3 <= T_1455 @[rvc.scala 24:13] - node T_1468 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1469 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1470 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1471 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1478 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1478 is invalid @[rvc.scala 19:19] - T_1478.bits <= io.in @[rvc.scala 20:14] - T_1478.rd <= T_1468 @[rvc.scala 21:12] - T_1478.rs1 <= T_1469 @[rvc.scala 22:13] - T_1478.rs2 <= T_1470 @[rvc.scala 23:13] - T_1478.rs3 <= T_1471 @[rvc.scala 24:13] - node T_1484 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1485 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1486 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1487 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1494 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1494 is invalid @[rvc.scala 19:19] - T_1494.bits <= io.in @[rvc.scala 20:14] - T_1494.rd <= T_1484 @[rvc.scala 21:12] - T_1494.rs1 <= T_1485 @[rvc.scala 22:13] - T_1494.rs2 <= T_1486 @[rvc.scala 23:13] - T_1494.rs3 <= T_1487 @[rvc.scala 24:13] - node T_1500 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1501 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1502 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1503 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1510 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1510 is invalid @[rvc.scala 19:19] - T_1510.bits <= io.in @[rvc.scala 20:14] - T_1510.rd <= T_1500 @[rvc.scala 21:12] - T_1510.rs1 <= T_1501 @[rvc.scala 22:13] - T_1510.rs2 <= T_1502 @[rvc.scala 23:13] - T_1510.rs3 <= T_1503 @[rvc.scala 24:13] - node T_1516 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1517 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1518 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1519 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1526 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1526 is invalid @[rvc.scala 19:19] - T_1526.bits <= io.in @[rvc.scala 20:14] - T_1526.rd <= T_1516 @[rvc.scala 21:12] - T_1526.rs1 <= T_1517 @[rvc.scala 22:13] - T_1526.rs2 <= T_1518 @[rvc.scala 23:13] - T_1526.rs3 <= T_1519 @[rvc.scala 24:13] - node T_1532 = bits(io.in, 11, 7) @[rvc.scala 18:36] - node T_1533 = bits(io.in, 19, 15) @[rvc.scala 18:57] - node T_1534 = bits(io.in, 24, 20) @[rvc.scala 18:79] - node T_1535 = bits(io.in, 31, 27) @[rvc.scala 18:101] - wire T_1542 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[rvc.scala 19:19] - T_1542 is invalid @[rvc.scala 19:19] - T_1542.bits <= io.in @[rvc.scala 20:14] - T_1542.rd <= T_1532 @[rvc.scala 21:12] - T_1542.rs1 <= T_1533 @[rvc.scala 22:13] - T_1542.rs2 <= T_1534 @[rvc.scala 23:13] - T_1542.rs3 <= T_1535 @[rvc.scala 24:13] - node T_1548 = bits(io.in, 1, 0) @[rvc.scala 148:12] - node T_1549 = bits(io.in, 15, 13) @[rvc.scala 148:20] - node T_1550 = cat(T_1548, T_1549) @[Cat.scala 20:58] - node T_1552 = and(T_1550, UInt<4>("h0f")) @[Package.scala 18:26] - node T_1554 = geq(T_1550, UInt<5>("h010")) @[Package.scala 19:17] - node T_1556 = and(T_1552, UInt<3>("h07")) @[Package.scala 18:26] - node T_1558 = geq(T_1552, UInt<4>("h08")) @[Package.scala 19:17] - node T_1560 = and(T_1556, UInt<2>("h03")) @[Package.scala 18:26] - node T_1562 = geq(T_1556, UInt<3>("h04")) @[Package.scala 19:17] - node T_1564 = and(T_1560, UInt<1>("h01")) @[Package.scala 18:26] - node T_1566 = geq(T_1560, UInt<2>("h02")) @[Package.scala 19:17] - node T_1568 = and(T_1564, UInt<1>("h00")) @[Package.scala 18:26] - node T_1570 = geq(T_1564, UInt<1>("h01")) @[Package.scala 19:17] - node T_1571 = mux(T_1570, T_1542, T_1526) @[Package.scala 19:12] - node T_1578 = and(T_1564, UInt<1>("h00")) @[Package.scala 18:26] - node T_1580 = geq(T_1564, UInt<1>("h01")) @[Package.scala 19:17] - node T_1581 = mux(T_1580, T_1510, T_1494) @[Package.scala 19:12] - node T_1587 = mux(T_1566, T_1571, T_1581) @[Package.scala 19:12] - node T_1594 = and(T_1560, UInt<1>("h01")) @[Package.scala 18:26] - node T_1596 = geq(T_1560, UInt<2>("h02")) @[Package.scala 19:17] - node T_1598 = and(T_1594, UInt<1>("h00")) @[Package.scala 18:26] - node T_1600 = geq(T_1594, UInt<1>("h01")) @[Package.scala 19:17] - node T_1601 = mux(T_1600, T_1478, T_1462) @[Package.scala 19:12] - node T_1608 = and(T_1594, UInt<1>("h00")) @[Package.scala 18:26] - node T_1610 = geq(T_1594, UInt<1>("h01")) @[Package.scala 19:17] - node T_1611 = mux(T_1610, T_1446, T_1430) @[Package.scala 19:12] - node T_1617 = mux(T_1596, T_1601, T_1611) @[Package.scala 19:12] - node T_1623 = mux(T_1562, T_1587, T_1617) @[Package.scala 19:12] - node T_1630 = and(T_1556, UInt<2>("h03")) @[Package.scala 18:26] - node T_1632 = geq(T_1556, UInt<3>("h04")) @[Package.scala 19:17] - node T_1634 = and(T_1630, UInt<1>("h01")) @[Package.scala 18:26] - node T_1636 = geq(T_1630, UInt<2>("h02")) @[Package.scala 19:17] - node T_1638 = and(T_1634, UInt<1>("h00")) @[Package.scala 18:26] - node T_1640 = geq(T_1634, UInt<1>("h01")) @[Package.scala 19:17] - node T_1641 = mux(T_1640, T_1414, T_1377) @[Package.scala 19:12] - node T_1648 = and(T_1634, UInt<1>("h00")) @[Package.scala 18:26] - node T_1650 = geq(T_1634, UInt<1>("h01")) @[Package.scala 19:17] - node T_1651 = mux(T_1650, T_1340, T_1303) @[Package.scala 19:12] - node T_1657 = mux(T_1636, T_1641, T_1651) @[Package.scala 19:12] - node T_1664 = and(T_1630, UInt<1>("h01")) @[Package.scala 18:26] - node T_1666 = geq(T_1630, UInt<2>("h02")) @[Package.scala 19:17] - node T_1668 = and(T_1664, UInt<1>("h00")) @[Package.scala 18:26] - node T_1670 = geq(T_1664, UInt<1>("h01")) @[Package.scala 19:17] - node T_1671 = mux(T_1670, T_1162, T_1131) @[Package.scala 19:12] - node T_1678 = and(T_1664, UInt<1>("h00")) @[Package.scala 18:26] - node T_1680 = geq(T_1664, UInt<1>("h01")) @[Package.scala 19:17] - node T_1681 = mux(T_1680, T_1100, T_1069) @[Package.scala 19:12] - node T_1687 = mux(T_1666, T_1671, T_1681) @[Package.scala 19:12] - node T_1693 = mux(T_1632, T_1657, T_1687) @[Package.scala 19:12] - node T_1699 = mux(T_1558, T_1623, T_1693) @[Package.scala 19:12] - node T_1706 = and(T_1552, UInt<3>("h07")) @[Package.scala 18:26] - node T_1708 = geq(T_1552, UInt<4>("h08")) @[Package.scala 19:17] - node T_1710 = and(T_1706, UInt<2>("h03")) @[Package.scala 18:26] - node T_1712 = geq(T_1706, UInt<3>("h04")) @[Package.scala 19:17] - node T_1714 = and(T_1710, UInt<1>("h01")) @[Package.scala 18:26] - node T_1716 = geq(T_1710, UInt<2>("h02")) @[Package.scala 19:17] - node T_1718 = and(T_1714, UInt<1>("h00")) @[Package.scala 18:26] - node T_1720 = geq(T_1714, UInt<1>("h01")) @[Package.scala 19:17] - node T_1721 = mux(T_1720, T_1042, T_947) @[Package.scala 19:12] - node T_1728 = and(T_1714, UInt<1>("h00")) @[Package.scala 18:26] - node T_1730 = geq(T_1714, UInt<1>("h01")) @[Package.scala 19:17] - node T_1731 = mux(T_1730, T_850, T_735) @[Package.scala 19:12] - node T_1737 = mux(T_1716, T_1721, T_1731) @[Package.scala 19:12] - node T_1744 = and(T_1710, UInt<1>("h01")) @[Package.scala 18:26] - node T_1746 = geq(T_1710, UInt<2>("h02")) @[Package.scala 19:17] - node T_1748 = and(T_1744, UInt<1>("h00")) @[Package.scala 18:26] - node T_1750 = geq(T_1744, UInt<1>("h01")) @[Package.scala 19:17] - node T_1751 = mux(T_1750, T_576, T_468) @[Package.scala 19:12] - node T_1758 = and(T_1744, UInt<1>("h00")) @[Package.scala 18:26] - node T_1760 = geq(T_1744, UInt<1>("h01")) @[Package.scala 19:17] - node T_1761 = mux(T_1760, T_435, T_397) @[Package.scala 19:12] - node T_1767 = mux(T_1746, T_1751, T_1761) @[Package.scala 19:12] - node T_1773 = mux(T_1712, T_1737, T_1767) @[Package.scala 19:12] - node T_1780 = and(T_1706, UInt<2>("h03")) @[Package.scala 18:26] - node T_1782 = geq(T_1706, UInt<3>("h04")) @[Package.scala 19:17] - node T_1784 = and(T_1780, UInt<1>("h01")) @[Package.scala 18:26] - node T_1786 = geq(T_1780, UInt<2>("h02")) @[Package.scala 19:17] - node T_1788 = and(T_1784, UInt<1>("h00")) @[Package.scala 18:26] - node T_1790 = geq(T_1784, UInt<1>("h01")) @[Package.scala 19:17] - node T_1791 = mux(T_1790, T_364, T_317) @[Package.scala 19:12] - node T_1798 = and(T_1784, UInt<1>("h00")) @[Package.scala 18:26] - node T_1800 = geq(T_1784, UInt<1>("h01")) @[Package.scala 19:17] - node T_1801 = mux(T_1800, T_266, T_219) @[Package.scala 19:12] - node T_1807 = mux(T_1786, T_1791, T_1801) @[Package.scala 19:12] - node T_1814 = and(T_1780, UInt<1>("h01")) @[Package.scala 18:26] - node T_1816 = geq(T_1780, UInt<2>("h02")) @[Package.scala 19:17] - node T_1818 = and(T_1814, UInt<1>("h00")) @[Package.scala 18:26] - node T_1820 = geq(T_1814, UInt<1>("h01")) @[Package.scala 19:17] - node T_1821 = mux(T_1820, T_168, T_129) @[Package.scala 19:12] - node T_1828 = and(T_1814, UInt<1>("h00")) @[Package.scala 18:26] - node T_1830 = geq(T_1814, UInt<1>("h01")) @[Package.scala 19:17] - node T_1831 = mux(T_1830, T_88, T_49) @[Package.scala 19:12] - node T_1837 = mux(T_1816, T_1821, T_1831) @[Package.scala 19:12] - node T_1843 = mux(T_1782, T_1807, T_1837) @[Package.scala 19:12] - node T_1849 = mux(T_1708, T_1773, T_1843) @[Package.scala 19:12] - node T_1855 = mux(T_1554, T_1699, T_1849) @[Package.scala 19:12] - io.out <- T_1855 @[rvc.scala 161:12] - - module IBuf : + node T_8 = bits(io.in, 1, 0) + node T_10 = neq(T_8, UInt<2>("h3")) + io.rvc <= T_10 + node T_11 = bits(io.in, 12, 5) + node T_13 = neq(T_11, UInt<1>("h0")) + node T_16 = mux(T_13, UInt<7>("h13"), UInt<7>("h1f")) + node T_17 = bits(io.in, 10, 7) + node T_18 = bits(io.in, 12, 11) + node T_19 = bits(io.in, 5, 5) + node T_20 = bits(io.in, 6, 6) + node T_22 = cat(T_20, UInt<2>("h0")) + node T_23 = cat(T_17, T_18) + node T_24 = cat(T_23, T_19) + node T_25 = cat(T_24, T_22) + node T_29 = bits(io.in, 4, 2) + node T_30 = cat(UInt<2>("h1"), T_29) + node T_31 = cat(T_30, T_16) + node T_32 = cat(T_25, UInt<5>("h2")) + node T_33 = cat(T_32, UInt<3>("h0")) + node T_34 = cat(T_33, T_31) + node T_36 = bits(io.in, 4, 2) + node T_37 = cat(UInt<2>("h1"), T_36) + node T_40 = bits(io.in, 4, 2) + node T_41 = cat(UInt<2>("h1"), T_40) + node T_42 = bits(io.in, 31, 27) + wire T_49 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_49 is invalid + T_49.bits <= T_34 + T_49.rd <= T_37 + T_49.rs1 <= UInt<5>("h2") + T_49.rs2 <= T_41 + T_49.rs3 <= T_42 + node T_55 = bits(io.in, 6, 5) + node T_56 = bits(io.in, 12, 10) + node T_58 = cat(T_55, T_56) + node T_59 = cat(T_58, UInt<3>("h0")) + node T_61 = bits(io.in, 9, 7) + node T_62 = cat(UInt<2>("h1"), T_61) + node T_65 = bits(io.in, 4, 2) + node T_66 = cat(UInt<2>("h1"), T_65) + node T_68 = cat(T_66, UInt<7>("h7")) + node T_69 = cat(T_59, T_62) + node T_70 = cat(T_69, UInt<3>("h3")) + node T_71 = cat(T_70, T_68) + node T_73 = bits(io.in, 4, 2) + node T_74 = cat(UInt<2>("h1"), T_73) + node T_76 = bits(io.in, 9, 7) + node T_77 = cat(UInt<2>("h1"), T_76) + node T_79 = bits(io.in, 4, 2) + node T_80 = cat(UInt<2>("h1"), T_79) + node T_81 = bits(io.in, 31, 27) + wire T_88 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_88 is invalid + T_88.bits <= T_71 + T_88.rd <= T_74 + T_88.rs1 <= T_77 + T_88.rs2 <= T_80 + T_88.rs3 <= T_81 + node T_94 = bits(io.in, 5, 5) + node T_95 = bits(io.in, 12, 10) + node T_96 = bits(io.in, 6, 6) + node T_98 = cat(T_96, UInt<2>("h0")) + node T_99 = cat(T_94, T_95) + node T_100 = cat(T_99, T_98) + node T_102 = bits(io.in, 9, 7) + node T_103 = cat(UInt<2>("h1"), T_102) + node T_106 = bits(io.in, 4, 2) + node T_107 = cat(UInt<2>("h1"), T_106) + node T_109 = cat(T_107, UInt<7>("h3")) + node T_110 = cat(T_100, T_103) + node T_111 = cat(T_110, UInt<3>("h2")) + node T_112 = cat(T_111, T_109) + node T_114 = bits(io.in, 4, 2) + node T_115 = cat(UInt<2>("h1"), T_114) + node T_117 = bits(io.in, 9, 7) + node T_118 = cat(UInt<2>("h1"), T_117) + node T_120 = bits(io.in, 4, 2) + node T_121 = cat(UInt<2>("h1"), T_120) + node T_122 = bits(io.in, 31, 27) + wire T_129 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_129 is invalid + T_129.bits <= T_112 + T_129.rd <= T_115 + T_129.rs1 <= T_118 + T_129.rs2 <= T_121 + T_129.rs3 <= T_122 + node T_135 = bits(io.in, 6, 5) + node T_136 = bits(io.in, 12, 10) + node T_138 = cat(T_135, T_136) + node T_139 = cat(T_138, UInt<3>("h0")) + node T_141 = bits(io.in, 9, 7) + node T_142 = cat(UInt<2>("h1"), T_141) + node T_145 = bits(io.in, 4, 2) + node T_146 = cat(UInt<2>("h1"), T_145) + node T_148 = cat(T_146, UInt<7>("h3")) + node T_149 = cat(T_139, T_142) + node T_150 = cat(T_149, UInt<3>("h3")) + node T_151 = cat(T_150, T_148) + node T_153 = bits(io.in, 4, 2) + node T_154 = cat(UInt<2>("h1"), T_153) + node T_156 = bits(io.in, 9, 7) + node T_157 = cat(UInt<2>("h1"), T_156) + node T_159 = bits(io.in, 4, 2) + node T_160 = cat(UInt<2>("h1"), T_159) + node T_161 = bits(io.in, 31, 27) + wire T_168 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_168 is invalid + T_168.bits <= T_151 + T_168.rd <= T_154 + T_168.rs1 <= T_157 + T_168.rs2 <= T_160 + T_168.rs3 <= T_161 + node T_174 = bits(io.in, 5, 5) + node T_175 = bits(io.in, 12, 10) + node T_176 = bits(io.in, 6, 6) + node T_178 = cat(T_176, UInt<2>("h0")) + node T_179 = cat(T_174, T_175) + node T_180 = cat(T_179, T_178) + node T_181 = shr(T_180, 5) + node T_183 = bits(io.in, 4, 2) + node T_184 = cat(UInt<2>("h1"), T_183) + node T_186 = bits(io.in, 9, 7) + node T_187 = cat(UInt<2>("h1"), T_186) + node T_189 = bits(io.in, 5, 5) + node T_190 = bits(io.in, 12, 10) + node T_191 = bits(io.in, 6, 6) + node T_193 = cat(T_191, UInt<2>("h0")) + node T_194 = cat(T_189, T_190) + node T_195 = cat(T_194, T_193) + node T_196 = bits(T_195, 4, 0) + node T_198 = cat(UInt<3>("h2"), T_196) + node T_199 = cat(T_198, UInt<7>("h2f")) + node T_200 = cat(T_181, T_184) + node T_201 = cat(T_200, T_187) + node T_202 = cat(T_201, T_199) + node T_204 = bits(io.in, 4, 2) + node T_205 = cat(UInt<2>("h1"), T_204) + node T_207 = bits(io.in, 9, 7) + node T_208 = cat(UInt<2>("h1"), T_207) + node T_210 = bits(io.in, 4, 2) + node T_211 = cat(UInt<2>("h1"), T_210) + node T_212 = bits(io.in, 31, 27) + wire T_219 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_219 is invalid + T_219.bits <= T_202 + T_219.rd <= T_205 + T_219.rs1 <= T_208 + T_219.rs2 <= T_211 + T_219.rs3 <= T_212 + node T_225 = bits(io.in, 6, 5) + node T_226 = bits(io.in, 12, 10) + node T_228 = cat(T_225, T_226) + node T_229 = cat(T_228, UInt<3>("h0")) + node T_230 = shr(T_229, 5) + node T_232 = bits(io.in, 4, 2) + node T_233 = cat(UInt<2>("h1"), T_232) + node T_235 = bits(io.in, 9, 7) + node T_236 = cat(UInt<2>("h1"), T_235) + node T_238 = bits(io.in, 6, 5) + node T_239 = bits(io.in, 12, 10) + node T_241 = cat(T_238, T_239) + node T_242 = cat(T_241, UInt<3>("h0")) + node T_243 = bits(T_242, 4, 0) + node T_245 = cat(UInt<3>("h3"), T_243) + node T_246 = cat(T_245, UInt<7>("h27")) + node T_247 = cat(T_230, T_233) + node T_248 = cat(T_247, T_236) + node T_249 = cat(T_248, T_246) + node T_251 = bits(io.in, 4, 2) + node T_252 = cat(UInt<2>("h1"), T_251) + node T_254 = bits(io.in, 9, 7) + node T_255 = cat(UInt<2>("h1"), T_254) + node T_257 = bits(io.in, 4, 2) + node T_258 = cat(UInt<2>("h1"), T_257) + node T_259 = bits(io.in, 31, 27) + wire T_266 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_266 is invalid + T_266.bits <= T_249 + T_266.rd <= T_252 + T_266.rs1 <= T_255 + T_266.rs2 <= T_258 + T_266.rs3 <= T_259 + node T_272 = bits(io.in, 5, 5) + node T_273 = bits(io.in, 12, 10) + node T_274 = bits(io.in, 6, 6) + node T_276 = cat(T_274, UInt<2>("h0")) + node T_277 = cat(T_272, T_273) + node T_278 = cat(T_277, T_276) + node T_279 = shr(T_278, 5) + node T_281 = bits(io.in, 4, 2) + node T_282 = cat(UInt<2>("h1"), T_281) + node T_284 = bits(io.in, 9, 7) + node T_285 = cat(UInt<2>("h1"), T_284) + node T_287 = bits(io.in, 5, 5) + node T_288 = bits(io.in, 12, 10) + node T_289 = bits(io.in, 6, 6) + node T_291 = cat(T_289, UInt<2>("h0")) + node T_292 = cat(T_287, T_288) + node T_293 = cat(T_292, T_291) + node T_294 = bits(T_293, 4, 0) + node T_296 = cat(UInt<3>("h2"), T_294) + node T_297 = cat(T_296, UInt<7>("h23")) + node T_298 = cat(T_279, T_282) + node T_299 = cat(T_298, T_285) + node T_300 = cat(T_299, T_297) + node T_302 = bits(io.in, 4, 2) + node T_303 = cat(UInt<2>("h1"), T_302) + node T_305 = bits(io.in, 9, 7) + node T_306 = cat(UInt<2>("h1"), T_305) + node T_308 = bits(io.in, 4, 2) + node T_309 = cat(UInt<2>("h1"), T_308) + node T_310 = bits(io.in, 31, 27) + wire T_317 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_317 is invalid + T_317.bits <= T_300 + T_317.rd <= T_303 + T_317.rs1 <= T_306 + T_317.rs2 <= T_309 + T_317.rs3 <= T_310 + node T_323 = bits(io.in, 6, 5) + node T_324 = bits(io.in, 12, 10) + node T_326 = cat(T_323, T_324) + node T_327 = cat(T_326, UInt<3>("h0")) + node T_328 = shr(T_327, 5) + node T_330 = bits(io.in, 4, 2) + node T_331 = cat(UInt<2>("h1"), T_330) + node T_333 = bits(io.in, 9, 7) + node T_334 = cat(UInt<2>("h1"), T_333) + node T_336 = bits(io.in, 6, 5) + node T_337 = bits(io.in, 12, 10) + node T_339 = cat(T_336, T_337) + node T_340 = cat(T_339, UInt<3>("h0")) + node T_341 = bits(T_340, 4, 0) + node T_343 = cat(UInt<3>("h3"), T_341) + node T_344 = cat(T_343, UInt<7>("h23")) + node T_345 = cat(T_328, T_331) + node T_346 = cat(T_345, T_334) + node T_347 = cat(T_346, T_344) + node T_349 = bits(io.in, 4, 2) + node T_350 = cat(UInt<2>("h1"), T_349) + node T_352 = bits(io.in, 9, 7) + node T_353 = cat(UInt<2>("h1"), T_352) + node T_355 = bits(io.in, 4, 2) + node T_356 = cat(UInt<2>("h1"), T_355) + node T_357 = bits(io.in, 31, 27) + wire T_364 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_364 is invalid + T_364.bits <= T_347 + T_364.rd <= T_350 + T_364.rs1 <= T_353 + T_364.rs2 <= T_356 + T_364.rs3 <= T_357 + node T_370 = bits(io.in, 12, 12) + node T_371 = bits(T_370, 0, 0) + node T_374 = mux(T_371, UInt<7>("h7f"), UInt<7>("h0")) + node T_375 = bits(io.in, 6, 2) + node T_376 = cat(T_374, T_375) + node T_377 = bits(io.in, 11, 7) + node T_379 = bits(io.in, 11, 7) + node T_381 = cat(T_379, UInt<7>("h13")) + node T_382 = cat(T_376, T_377) + node T_383 = cat(T_382, UInt<3>("h0")) + node T_384 = cat(T_383, T_381) + node T_385 = bits(io.in, 11, 7) + node T_386 = bits(io.in, 11, 7) + node T_388 = bits(io.in, 4, 2) + node T_389 = cat(UInt<2>("h1"), T_388) + node T_390 = bits(io.in, 31, 27) + wire T_397 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_397 is invalid + T_397.bits <= T_384 + T_397.rd <= T_385 + T_397.rs1 <= T_386 + T_397.rs2 <= T_389 + T_397.rs3 <= T_390 + node T_403 = bits(io.in, 11, 7) + node T_405 = neq(T_403, UInt<1>("h0")) + node T_408 = mux(T_405, UInt<7>("h1b"), UInt<7>("h1f")) + node T_409 = bits(io.in, 12, 12) + node T_410 = bits(T_409, 0, 0) + node T_413 = mux(T_410, UInt<7>("h7f"), UInt<7>("h0")) + node T_414 = bits(io.in, 6, 2) + node T_415 = cat(T_413, T_414) + node T_416 = bits(io.in, 11, 7) + node T_418 = bits(io.in, 11, 7) + node T_419 = cat(T_418, T_408) + node T_420 = cat(T_415, T_416) + node T_421 = cat(T_420, UInt<3>("h0")) + node T_422 = cat(T_421, T_419) + node T_423 = bits(io.in, 11, 7) + node T_424 = bits(io.in, 11, 7) + node T_426 = bits(io.in, 4, 2) + node T_427 = cat(UInt<2>("h1"), T_426) + node T_428 = bits(io.in, 31, 27) + wire T_435 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_435 is invalid + T_435.bits <= T_422 + T_435.rd <= T_423 + T_435.rs1 <= T_424 + T_435.rs2 <= T_427 + T_435.rs3 <= T_428 + node T_441 = bits(io.in, 12, 12) + node T_442 = bits(T_441, 0, 0) + node T_445 = mux(T_442, UInt<7>("h7f"), UInt<7>("h0")) + node T_446 = bits(io.in, 6, 2) + node T_447 = cat(T_445, T_446) + node T_450 = bits(io.in, 11, 7) + node T_452 = cat(T_450, UInt<7>("h13")) + node T_453 = cat(T_447, UInt<5>("h0")) + node T_454 = cat(T_453, UInt<3>("h0")) + node T_455 = cat(T_454, T_452) + node T_456 = bits(io.in, 11, 7) + node T_459 = bits(io.in, 4, 2) + node T_460 = cat(UInt<2>("h1"), T_459) + node T_461 = bits(io.in, 31, 27) + wire T_468 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_468 is invalid + T_468.bits <= T_455 + T_468.rd <= T_456 + T_468.rs1 <= UInt<5>("h0") + T_468.rs2 <= T_460 + T_468.rs3 <= T_461 + node T_474 = bits(io.in, 12, 12) + node T_475 = bits(T_474, 0, 0) + node T_478 = mux(T_475, UInt<7>("h7f"), UInt<7>("h0")) + node T_479 = bits(io.in, 6, 2) + node T_480 = cat(T_478, T_479) + node T_482 = neq(T_480, UInt<1>("h0")) + node T_485 = mux(T_482, UInt<7>("h37"), UInt<7>("h3f")) + node T_486 = bits(io.in, 12, 12) + node T_487 = bits(T_486, 0, 0) + node T_490 = mux(T_487, UInt<15>("h7fff"), UInt<15>("h0")) + node T_491 = bits(io.in, 6, 2) + node T_493 = cat(T_490, T_491) + node T_494 = cat(T_493, UInt<12>("h0")) + node T_495 = bits(T_494, 31, 12) + node T_496 = bits(io.in, 11, 7) + node T_497 = cat(T_495, T_496) + node T_498 = cat(T_497, T_485) + node T_499 = bits(io.in, 11, 7) + node T_500 = bits(io.in, 11, 7) + node T_502 = bits(io.in, 4, 2) + node T_503 = cat(UInt<2>("h1"), T_502) + node T_504 = bits(io.in, 31, 27) + wire T_511 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_511 is invalid + T_511.bits <= T_498 + T_511.rd <= T_499 + T_511.rs1 <= T_500 + T_511.rs2 <= T_503 + T_511.rs3 <= T_504 + node T_517 = bits(io.in, 11, 7) + node T_519 = eq(T_517, UInt<5>("h0")) + node T_520 = bits(io.in, 11, 7) + node T_522 = eq(T_520, UInt<5>("h2")) + node T_523 = or(T_519, T_522) + node T_524 = bits(io.in, 12, 12) + node T_525 = bits(T_524, 0, 0) + node T_528 = mux(T_525, UInt<7>("h7f"), UInt<7>("h0")) + node T_529 = bits(io.in, 6, 2) + node T_530 = cat(T_528, T_529) + node T_532 = neq(T_530, UInt<1>("h0")) + node T_535 = mux(T_532, UInt<7>("h13"), UInt<7>("h1f")) + node T_536 = bits(io.in, 12, 12) + node T_537 = bits(T_536, 0, 0) + node T_540 = mux(T_537, UInt<3>("h7"), UInt<3>("h0")) + node T_541 = bits(io.in, 4, 3) + node T_542 = bits(io.in, 5, 5) + node T_543 = bits(io.in, 2, 2) + node T_544 = bits(io.in, 6, 6) + node T_546 = cat(T_543, T_544) + node T_547 = cat(T_546, UInt<4>("h0")) + node T_548 = cat(T_540, T_541) + node T_549 = cat(T_548, T_542) + node T_550 = cat(T_549, T_547) + node T_551 = bits(io.in, 11, 7) + node T_553 = bits(io.in, 11, 7) + node T_554 = cat(T_553, T_535) + node T_555 = cat(T_550, T_551) + node T_556 = cat(T_555, UInt<3>("h0")) + node T_557 = cat(T_556, T_554) + node T_558 = bits(io.in, 11, 7) + node T_559 = bits(io.in, 11, 7) + node T_561 = bits(io.in, 4, 2) + node T_562 = cat(UInt<2>("h1"), T_561) + node T_563 = bits(io.in, 31, 27) + wire T_570 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_570 is invalid + T_570.bits <= T_557 + T_570.rd <= T_558 + T_570.rs1 <= T_559 + T_570.rs2 <= T_562 + T_570.rs3 <= T_563 + node T_576 = mux(T_523, T_570, T_511) + node T_582 = bits(io.in, 12, 12) + node T_583 = bits(io.in, 6, 2) + node T_584 = cat(T_582, T_583) + node T_586 = bits(io.in, 9, 7) + node T_587 = cat(UInt<2>("h1"), T_586) + node T_590 = bits(io.in, 9, 7) + node T_591 = cat(UInt<2>("h1"), T_590) + node T_593 = cat(T_591, UInt<7>("h13")) + node T_594 = cat(T_584, T_587) + node T_595 = cat(T_594, UInt<3>("h5")) + node T_596 = cat(T_595, T_593) + node T_597 = bits(io.in, 12, 12) + node T_598 = bits(io.in, 6, 2) + node T_599 = cat(T_597, T_598) + node T_601 = bits(io.in, 9, 7) + node T_602 = cat(UInt<2>("h1"), T_601) + node T_605 = bits(io.in, 9, 7) + node T_606 = cat(UInt<2>("h1"), T_605) + node T_608 = cat(T_606, UInt<7>("h13")) + node T_609 = cat(T_599, T_602) + node T_610 = cat(T_609, UInt<3>("h5")) + node T_611 = cat(T_610, T_608) + node T_613 = or(T_611, UInt<31>("h40000000")) + node T_614 = bits(io.in, 12, 12) + node T_615 = bits(T_614, 0, 0) + node T_618 = mux(T_615, UInt<7>("h7f"), UInt<7>("h0")) + node T_619 = bits(io.in, 6, 2) + node T_620 = cat(T_618, T_619) + node T_622 = bits(io.in, 9, 7) + node T_623 = cat(UInt<2>("h1"), T_622) + node T_626 = bits(io.in, 9, 7) + node T_627 = cat(UInt<2>("h1"), T_626) + node T_629 = cat(T_627, UInt<7>("h13")) + node T_630 = cat(T_620, T_623) + node T_631 = cat(T_630, UInt<3>("h7")) + node T_632 = cat(T_631, T_629) + node T_641 = bits(io.in, 12, 12) + node T_642 = bits(io.in, 6, 5) + node T_643 = cat(T_641, T_642) + node T_645 = and(T_643, UInt<2>("h3")) + node T_647 = geq(T_643, UInt<3>("h4")) + node T_649 = and(T_645, UInt<1>("h1")) + node T_651 = geq(T_645, UInt<2>("h2")) + node T_653 = and(T_649, UInt<1>("h0")) + node T_655 = geq(T_649, UInt<1>("h1")) + node T_656 = mux(T_655, UInt<2>("h3"), UInt<2>("h2")) + node T_658 = and(T_649, UInt<1>("h0")) + node T_660 = geq(T_649, UInt<1>("h1")) + node T_661 = mux(T_660, UInt<1>("h0"), UInt<1>("h0")) + node T_662 = mux(T_651, T_656, T_661) + node T_664 = and(T_645, UInt<1>("h1")) + node T_666 = geq(T_645, UInt<2>("h2")) + node T_668 = and(T_664, UInt<1>("h0")) + node T_670 = geq(T_664, UInt<1>("h1")) + node T_671 = mux(T_670, UInt<3>("h7"), UInt<3>("h6")) + node T_673 = and(T_664, UInt<1>("h0")) + node T_675 = geq(T_664, UInt<1>("h1")) + node T_676 = mux(T_675, UInt<3>("h4"), UInt<1>("h0")) + node T_677 = mux(T_666, T_671, T_676) + node T_678 = mux(T_647, T_662, T_677) + node T_679 = bits(io.in, 6, 5) + node T_681 = eq(T_679, UInt<1>("h0")) + node T_684 = mux(T_681, UInt<31>("h40000000"), UInt<1>("h0")) + node T_685 = bits(io.in, 12, 12) + node T_688 = mux(T_685, UInt<7>("h3b"), UInt<7>("h33")) + node T_690 = bits(io.in, 4, 2) + node T_691 = cat(UInt<2>("h1"), T_690) + node T_693 = bits(io.in, 9, 7) + node T_694 = cat(UInt<2>("h1"), T_693) + node T_696 = bits(io.in, 9, 7) + node T_697 = cat(UInt<2>("h1"), T_696) + node T_698 = cat(T_697, T_688) + node T_699 = cat(T_691, T_694) + node T_700 = cat(T_699, T_678) + node T_701 = cat(T_700, T_698) + node T_702 = or(T_701, T_684) + node T_703 = bits(io.in, 11, 10) + node T_705 = and(T_703, UInt<1>("h1")) + node T_707 = geq(T_703, UInt<2>("h2")) + node T_709 = and(T_705, UInt<1>("h0")) + node T_711 = geq(T_705, UInt<1>("h1")) + node T_712 = mux(T_711, T_702, T_632) + node T_714 = and(T_705, UInt<1>("h0")) + node T_716 = geq(T_705, UInt<1>("h1")) + node T_717 = mux(T_716, T_613, T_596) + node T_718 = mux(T_707, T_712, T_717) + node T_720 = bits(io.in, 9, 7) + node T_721 = cat(UInt<2>("h1"), T_720) + node T_723 = bits(io.in, 9, 7) + node T_724 = cat(UInt<2>("h1"), T_723) + node T_726 = bits(io.in, 4, 2) + node T_727 = cat(UInt<2>("h1"), T_726) + node T_728 = bits(io.in, 31, 27) + wire T_735 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_735 is invalid + T_735.bits <= T_718 + T_735.rd <= T_721 + T_735.rs1 <= T_724 + T_735.rs2 <= T_727 + T_735.rs3 <= T_728 + node T_741 = bits(io.in, 12, 12) + node T_742 = bits(T_741, 0, 0) + node T_745 = mux(T_742, UInt<10>("h3ff"), UInt<10>("h0")) + node T_746 = bits(io.in, 8, 8) + node T_747 = bits(io.in, 10, 9) + node T_748 = bits(io.in, 6, 6) + node T_749 = bits(io.in, 7, 7) + node T_750 = bits(io.in, 2, 2) + node T_751 = bits(io.in, 11, 11) + node T_752 = bits(io.in, 5, 3) + node T_754 = cat(T_752, UInt<1>("h0")) + node T_755 = cat(T_750, T_751) + node T_756 = cat(T_755, T_754) + node T_757 = cat(T_748, T_749) + node T_758 = cat(T_745, T_746) + node T_759 = cat(T_758, T_747) + node T_760 = cat(T_759, T_757) + node T_761 = cat(T_760, T_756) + node T_762 = bits(T_761, 20, 20) + node T_763 = bits(io.in, 12, 12) + node T_764 = bits(T_763, 0, 0) + node T_767 = mux(T_764, UInt<10>("h3ff"), UInt<10>("h0")) + node T_768 = bits(io.in, 8, 8) + node T_769 = bits(io.in, 10, 9) + node T_770 = bits(io.in, 6, 6) + node T_771 = bits(io.in, 7, 7) + node T_772 = bits(io.in, 2, 2) + node T_773 = bits(io.in, 11, 11) + node T_774 = bits(io.in, 5, 3) + node T_776 = cat(T_774, UInt<1>("h0")) + node T_777 = cat(T_772, T_773) + node T_778 = cat(T_777, T_776) + node T_779 = cat(T_770, T_771) + node T_780 = cat(T_767, T_768) + node T_781 = cat(T_780, T_769) + node T_782 = cat(T_781, T_779) + node T_783 = cat(T_782, T_778) + node T_784 = bits(T_783, 10, 1) + node T_785 = bits(io.in, 12, 12) + node T_786 = bits(T_785, 0, 0) + node T_789 = mux(T_786, UInt<10>("h3ff"), UInt<10>("h0")) + node T_790 = bits(io.in, 8, 8) + node T_791 = bits(io.in, 10, 9) + node T_792 = bits(io.in, 6, 6) + node T_793 = bits(io.in, 7, 7) + node T_794 = bits(io.in, 2, 2) + node T_795 = bits(io.in, 11, 11) + node T_796 = bits(io.in, 5, 3) + node T_798 = cat(T_796, UInt<1>("h0")) + node T_799 = cat(T_794, T_795) + node T_800 = cat(T_799, T_798) + node T_801 = cat(T_792, T_793) + node T_802 = cat(T_789, T_790) + node T_803 = cat(T_802, T_791) + node T_804 = cat(T_803, T_801) + node T_805 = cat(T_804, T_800) + node T_806 = bits(T_805, 11, 11) + node T_807 = bits(io.in, 12, 12) + node T_808 = bits(T_807, 0, 0) + node T_811 = mux(T_808, UInt<10>("h3ff"), UInt<10>("h0")) + node T_812 = bits(io.in, 8, 8) + node T_813 = bits(io.in, 10, 9) + node T_814 = bits(io.in, 6, 6) + node T_815 = bits(io.in, 7, 7) + node T_816 = bits(io.in, 2, 2) + node T_817 = bits(io.in, 11, 11) + node T_818 = bits(io.in, 5, 3) + node T_820 = cat(T_818, UInt<1>("h0")) + node T_821 = cat(T_816, T_817) + node T_822 = cat(T_821, T_820) + node T_823 = cat(T_814, T_815) + node T_824 = cat(T_811, T_812) + node T_825 = cat(T_824, T_813) + node T_826 = cat(T_825, T_823) + node T_827 = cat(T_826, T_822) + node T_828 = bits(T_827, 19, 12) + node T_831 = cat(T_828, UInt<5>("h0")) + node T_832 = cat(T_831, UInt<7>("h6f")) + node T_833 = cat(T_762, T_784) + node T_834 = cat(T_833, T_806) + node T_835 = cat(T_834, T_832) + node T_838 = bits(io.in, 9, 7) + node T_839 = cat(UInt<2>("h1"), T_838) + node T_841 = bits(io.in, 4, 2) + node T_842 = cat(UInt<2>("h1"), T_841) + node T_843 = bits(io.in, 31, 27) + wire T_850 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_850 is invalid + T_850.bits <= T_835 + T_850.rd <= UInt<5>("h0") + T_850.rs1 <= T_839 + T_850.rs2 <= T_842 + T_850.rs3 <= T_843 + node T_856 = bits(io.in, 12, 12) + node T_857 = bits(T_856, 0, 0) + node T_860 = mux(T_857, UInt<5>("h1f"), UInt<5>("h0")) + node T_861 = bits(io.in, 6, 5) + node T_862 = bits(io.in, 2, 2) + node T_863 = bits(io.in, 11, 10) + node T_864 = bits(io.in, 4, 3) + node T_866 = cat(T_863, T_864) + node T_867 = cat(T_866, UInt<1>("h0")) + node T_868 = cat(T_860, T_861) + node T_869 = cat(T_868, T_862) + node T_870 = cat(T_869, T_867) + node T_871 = bits(T_870, 12, 12) + node T_872 = bits(io.in, 12, 12) + node T_873 = bits(T_872, 0, 0) + node T_876 = mux(T_873, UInt<5>("h1f"), UInt<5>("h0")) + node T_877 = bits(io.in, 6, 5) + node T_878 = bits(io.in, 2, 2) + node T_879 = bits(io.in, 11, 10) + node T_880 = bits(io.in, 4, 3) + node T_882 = cat(T_879, T_880) + node T_883 = cat(T_882, UInt<1>("h0")) + node T_884 = cat(T_876, T_877) + node T_885 = cat(T_884, T_878) + node T_886 = cat(T_885, T_883) + node T_887 = bits(T_886, 10, 5) + node T_890 = bits(io.in, 9, 7) + node T_891 = cat(UInt<2>("h1"), T_890) + node T_893 = bits(io.in, 12, 12) + node T_894 = bits(T_893, 0, 0) + node T_897 = mux(T_894, UInt<5>("h1f"), UInt<5>("h0")) + node T_898 = bits(io.in, 6, 5) + node T_899 = bits(io.in, 2, 2) + node T_900 = bits(io.in, 11, 10) + node T_901 = bits(io.in, 4, 3) + node T_903 = cat(T_900, T_901) + node T_904 = cat(T_903, UInt<1>("h0")) + node T_905 = cat(T_897, T_898) + node T_906 = cat(T_905, T_899) + node T_907 = cat(T_906, T_904) + node T_908 = bits(T_907, 4, 1) + node T_909 = bits(io.in, 12, 12) + node T_910 = bits(T_909, 0, 0) + node T_913 = mux(T_910, UInt<5>("h1f"), UInt<5>("h0")) + node T_914 = bits(io.in, 6, 5) + node T_915 = bits(io.in, 2, 2) + node T_916 = bits(io.in, 11, 10) + node T_917 = bits(io.in, 4, 3) + node T_919 = cat(T_916, T_917) + node T_920 = cat(T_919, UInt<1>("h0")) + node T_921 = cat(T_913, T_914) + node T_922 = cat(T_921, T_915) + node T_923 = cat(T_922, T_920) + node T_924 = bits(T_923, 11, 11) + node T_926 = cat(T_924, UInt<7>("h63")) + node T_927 = cat(UInt<3>("h0"), T_908) + node T_928 = cat(T_927, T_926) + node T_929 = cat(UInt<5>("h0"), T_891) + node T_930 = cat(T_871, T_887) + node T_931 = cat(T_930, T_929) + node T_932 = cat(T_931, T_928) + node T_934 = bits(io.in, 9, 7) + node T_935 = cat(UInt<2>("h1"), T_934) + node T_937 = bits(io.in, 9, 7) + node T_938 = cat(UInt<2>("h1"), T_937) + node T_940 = bits(io.in, 31, 27) + wire T_947 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_947 is invalid + T_947.bits <= T_932 + T_947.rd <= T_935 + T_947.rs1 <= T_938 + T_947.rs2 <= UInt<5>("h0") + T_947.rs3 <= T_940 + node T_953 = bits(io.in, 12, 12) + node T_954 = bits(T_953, 0, 0) + node T_957 = mux(T_954, UInt<5>("h1f"), UInt<5>("h0")) + node T_958 = bits(io.in, 6, 5) + node T_959 = bits(io.in, 2, 2) + node T_960 = bits(io.in, 11, 10) + node T_961 = bits(io.in, 4, 3) + node T_963 = cat(T_960, T_961) + node T_964 = cat(T_963, UInt<1>("h0")) + node T_965 = cat(T_957, T_958) + node T_966 = cat(T_965, T_959) + node T_967 = cat(T_966, T_964) + node T_968 = bits(T_967, 12, 12) + node T_969 = bits(io.in, 12, 12) + node T_970 = bits(T_969, 0, 0) + node T_973 = mux(T_970, UInt<5>("h1f"), UInt<5>("h0")) + node T_974 = bits(io.in, 6, 5) + node T_975 = bits(io.in, 2, 2) + node T_976 = bits(io.in, 11, 10) + node T_977 = bits(io.in, 4, 3) + node T_979 = cat(T_976, T_977) + node T_980 = cat(T_979, UInt<1>("h0")) + node T_981 = cat(T_973, T_974) + node T_982 = cat(T_981, T_975) + node T_983 = cat(T_982, T_980) + node T_984 = bits(T_983, 10, 5) + node T_987 = bits(io.in, 9, 7) + node T_988 = cat(UInt<2>("h1"), T_987) + node T_990 = bits(io.in, 12, 12) + node T_991 = bits(T_990, 0, 0) + node T_994 = mux(T_991, UInt<5>("h1f"), UInt<5>("h0")) + node T_995 = bits(io.in, 6, 5) + node T_996 = bits(io.in, 2, 2) + node T_997 = bits(io.in, 11, 10) + node T_998 = bits(io.in, 4, 3) + node T_1000 = cat(T_997, T_998) + node T_1001 = cat(T_1000, UInt<1>("h0")) + node T_1002 = cat(T_994, T_995) + node T_1003 = cat(T_1002, T_996) + node T_1004 = cat(T_1003, T_1001) + node T_1005 = bits(T_1004, 4, 1) + node T_1006 = bits(io.in, 12, 12) + node T_1007 = bits(T_1006, 0, 0) + node T_1010 = mux(T_1007, UInt<5>("h1f"), UInt<5>("h0")) + node T_1011 = bits(io.in, 6, 5) + node T_1012 = bits(io.in, 2, 2) + node T_1013 = bits(io.in, 11, 10) + node T_1014 = bits(io.in, 4, 3) + node T_1016 = cat(T_1013, T_1014) + node T_1017 = cat(T_1016, UInt<1>("h0")) + node T_1018 = cat(T_1010, T_1011) + node T_1019 = cat(T_1018, T_1012) + node T_1020 = cat(T_1019, T_1017) + node T_1021 = bits(T_1020, 11, 11) + node T_1023 = cat(T_1021, UInt<7>("h63")) + node T_1024 = cat(UInt<3>("h1"), T_1005) + node T_1025 = cat(T_1024, T_1023) + node T_1026 = cat(UInt<5>("h0"), T_988) + node T_1027 = cat(T_968, T_984) + node T_1028 = cat(T_1027, T_1026) + node T_1029 = cat(T_1028, T_1025) + node T_1032 = bits(io.in, 9, 7) + node T_1033 = cat(UInt<2>("h1"), T_1032) + node T_1035 = bits(io.in, 31, 27) + wire T_1042 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1042 is invalid + T_1042.bits <= T_1029 + T_1042.rd <= UInt<5>("h0") + T_1042.rs1 <= T_1033 + T_1042.rs2 <= UInt<5>("h0") + T_1042.rs3 <= T_1035 + node T_1048 = bits(io.in, 12, 12) + node T_1049 = bits(io.in, 6, 2) + node T_1050 = cat(T_1048, T_1049) + node T_1051 = bits(io.in, 11, 7) + node T_1053 = bits(io.in, 11, 7) + node T_1055 = cat(T_1053, UInt<7>("h13")) + node T_1056 = cat(T_1050, T_1051) + node T_1057 = cat(T_1056, UInt<3>("h1")) + node T_1058 = cat(T_1057, T_1055) + node T_1059 = bits(io.in, 11, 7) + node T_1060 = bits(io.in, 11, 7) + node T_1061 = bits(io.in, 6, 2) + node T_1062 = bits(io.in, 31, 27) + wire T_1069 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1069 is invalid + T_1069.bits <= T_1058 + T_1069.rd <= T_1059 + T_1069.rs1 <= T_1060 + T_1069.rs2 <= T_1061 + T_1069.rs3 <= T_1062 + node T_1075 = bits(io.in, 4, 2) + node T_1076 = bits(io.in, 12, 12) + node T_1077 = bits(io.in, 6, 5) + node T_1079 = cat(T_1077, UInt<3>("h0")) + node T_1080 = cat(T_1075, T_1076) + node T_1081 = cat(T_1080, T_1079) + node T_1084 = bits(io.in, 11, 7) + node T_1086 = cat(T_1084, UInt<7>("h7")) + node T_1087 = cat(T_1081, UInt<5>("h2")) + node T_1088 = cat(T_1087, UInt<3>("h3")) + node T_1089 = cat(T_1088, T_1086) + node T_1090 = bits(io.in, 11, 7) + node T_1092 = bits(io.in, 6, 2) + node T_1093 = bits(io.in, 31, 27) + wire T_1100 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1100 is invalid + T_1100.bits <= T_1089 + T_1100.rd <= T_1090 + T_1100.rs1 <= UInt<5>("h2") + T_1100.rs2 <= T_1092 + T_1100.rs3 <= T_1093 + node T_1106 = bits(io.in, 3, 2) + node T_1107 = bits(io.in, 12, 12) + node T_1108 = bits(io.in, 6, 4) + node T_1110 = cat(T_1108, UInt<2>("h0")) + node T_1111 = cat(T_1106, T_1107) + node T_1112 = cat(T_1111, T_1110) + node T_1115 = bits(io.in, 11, 7) + node T_1117 = cat(T_1115, UInt<7>("h3")) + node T_1118 = cat(T_1112, UInt<5>("h2")) + node T_1119 = cat(T_1118, UInt<3>("h2")) + node T_1120 = cat(T_1119, T_1117) + node T_1121 = bits(io.in, 11, 7) + node T_1123 = bits(io.in, 6, 2) + node T_1124 = bits(io.in, 31, 27) + wire T_1131 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1131 is invalid + T_1131.bits <= T_1120 + T_1131.rd <= T_1121 + T_1131.rs1 <= UInt<5>("h2") + T_1131.rs2 <= T_1123 + T_1131.rs3 <= T_1124 + node T_1137 = bits(io.in, 4, 2) + node T_1138 = bits(io.in, 12, 12) + node T_1139 = bits(io.in, 6, 5) + node T_1141 = cat(T_1139, UInt<3>("h0")) + node T_1142 = cat(T_1137, T_1138) + node T_1143 = cat(T_1142, T_1141) + node T_1146 = bits(io.in, 11, 7) + node T_1148 = cat(T_1146, UInt<7>("h3")) + node T_1149 = cat(T_1143, UInt<5>("h2")) + node T_1150 = cat(T_1149, UInt<3>("h3")) + node T_1151 = cat(T_1150, T_1148) + node T_1152 = bits(io.in, 11, 7) + node T_1154 = bits(io.in, 6, 2) + node T_1155 = bits(io.in, 31, 27) + wire T_1162 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1162 is invalid + T_1162.bits <= T_1151 + T_1162.rd <= T_1152 + T_1162.rs1 <= UInt<5>("h2") + T_1162.rs2 <= T_1154 + T_1162.rs3 <= T_1155 + node T_1168 = bits(io.in, 6, 2) + node T_1171 = bits(io.in, 11, 7) + node T_1173 = cat(T_1171, UInt<7>("h33")) + node T_1174 = cat(T_1168, UInt<5>("h0")) + node T_1175 = cat(T_1174, UInt<3>("h0")) + node T_1176 = cat(T_1175, T_1173) + node T_1177 = bits(io.in, 11, 7) + node T_1179 = bits(io.in, 6, 2) + node T_1180 = bits(io.in, 31, 27) + wire T_1187 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1187 is invalid + T_1187.bits <= T_1176 + T_1187.rd <= T_1177 + T_1187.rs1 <= UInt<5>("h0") + T_1187.rs2 <= T_1179 + T_1187.rs3 <= T_1180 + node T_1193 = bits(io.in, 6, 2) + node T_1194 = bits(io.in, 11, 7) + node T_1196 = bits(io.in, 11, 7) + node T_1198 = cat(T_1196, UInt<7>("h33")) + node T_1199 = cat(T_1193, T_1194) + node T_1200 = cat(T_1199, UInt<3>("h0")) + node T_1201 = cat(T_1200, T_1198) + node T_1202 = bits(io.in, 11, 7) + node T_1203 = bits(io.in, 11, 7) + node T_1204 = bits(io.in, 6, 2) + node T_1205 = bits(io.in, 31, 27) + wire T_1212 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1212 is invalid + T_1212.bits <= T_1201 + T_1212.rd <= T_1202 + T_1212.rs1 <= T_1203 + T_1212.rs2 <= T_1204 + T_1212.rs3 <= T_1205 + node T_1218 = bits(io.in, 6, 2) + node T_1219 = bits(io.in, 11, 7) + node T_1223 = cat(UInt<5>("h0"), UInt<7>("h67")) + node T_1224 = cat(T_1218, T_1219) + node T_1225 = cat(T_1224, UInt<3>("h0")) + node T_1226 = cat(T_1225, T_1223) + node T_1227 = shr(T_1226, 7) + node T_1229 = cat(T_1227, UInt<7>("h1f")) + node T_1230 = bits(io.in, 11, 7) + node T_1232 = neq(T_1230, UInt<1>("h0")) + node T_1233 = mux(T_1232, T_1226, T_1229) + node T_1235 = bits(io.in, 11, 7) + node T_1236 = bits(io.in, 6, 2) + node T_1237 = bits(io.in, 31, 27) + wire T_1244 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1244 is invalid + T_1244.bits <= T_1233 + T_1244.rd <= UInt<5>("h0") + T_1244.rs1 <= T_1235 + T_1244.rs2 <= T_1236 + T_1244.rs3 <= T_1237 + node T_1250 = bits(io.in, 6, 2) + node T_1252 = neq(T_1250, UInt<1>("h0")) + node T_1253 = mux(T_1252, T_1187, T_1244) + node T_1259 = bits(io.in, 6, 2) + node T_1260 = bits(io.in, 11, 7) + node T_1264 = cat(UInt<5>("h1"), UInt<7>("h67")) + node T_1265 = cat(T_1259, T_1260) + node T_1266 = cat(T_1265, UInt<3>("h0")) + node T_1267 = cat(T_1266, T_1264) + node T_1268 = shr(T_1226, 7) + node T_1270 = cat(T_1268, UInt<7>("h73")) + node T_1272 = or(T_1270, UInt<21>("h100000")) + node T_1273 = bits(io.in, 11, 7) + node T_1275 = neq(T_1273, UInt<1>("h0")) + node T_1276 = mux(T_1275, T_1267, T_1272) + node T_1278 = bits(io.in, 11, 7) + node T_1279 = bits(io.in, 6, 2) + node T_1280 = bits(io.in, 31, 27) + wire T_1287 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1287 is invalid + T_1287.bits <= T_1276 + T_1287.rd <= UInt<5>("h1") + T_1287.rs1 <= T_1278 + T_1287.rs2 <= T_1279 + T_1287.rs3 <= T_1280 + node T_1293 = bits(io.in, 6, 2) + node T_1295 = neq(T_1293, UInt<1>("h0")) + node T_1296 = mux(T_1295, T_1212, T_1287) + node T_1302 = bits(io.in, 12, 12) + node T_1303 = mux(T_1302, T_1296, T_1253) + node T_1309 = bits(io.in, 9, 7) + node T_1310 = bits(io.in, 12, 10) + node T_1312 = cat(T_1309, T_1310) + node T_1313 = cat(T_1312, UInt<3>("h0")) + node T_1314 = shr(T_1313, 5) + node T_1315 = bits(io.in, 6, 2) + node T_1318 = bits(io.in, 9, 7) + node T_1319 = bits(io.in, 12, 10) + node T_1321 = cat(T_1318, T_1319) + node T_1322 = cat(T_1321, UInt<3>("h0")) + node T_1323 = bits(T_1322, 4, 0) + node T_1325 = cat(UInt<3>("h3"), T_1323) + node T_1326 = cat(T_1325, UInt<7>("h27")) + node T_1327 = cat(T_1314, T_1315) + node T_1328 = cat(T_1327, UInt<5>("h2")) + node T_1329 = cat(T_1328, T_1326) + node T_1330 = bits(io.in, 11, 7) + node T_1332 = bits(io.in, 6, 2) + node T_1333 = bits(io.in, 31, 27) + wire T_1340 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1340 is invalid + T_1340.bits <= T_1329 + T_1340.rd <= T_1330 + T_1340.rs1 <= UInt<5>("h2") + T_1340.rs2 <= T_1332 + T_1340.rs3 <= T_1333 + node T_1346 = bits(io.in, 8, 7) + node T_1347 = bits(io.in, 12, 9) + node T_1349 = cat(T_1346, T_1347) + node T_1350 = cat(T_1349, UInt<2>("h0")) + node T_1351 = shr(T_1350, 5) + node T_1352 = bits(io.in, 6, 2) + node T_1355 = bits(io.in, 8, 7) + node T_1356 = bits(io.in, 12, 9) + node T_1358 = cat(T_1355, T_1356) + node T_1359 = cat(T_1358, UInt<2>("h0")) + node T_1360 = bits(T_1359, 4, 0) + node T_1362 = cat(UInt<3>("h2"), T_1360) + node T_1363 = cat(T_1362, UInt<7>("h23")) + node T_1364 = cat(T_1351, T_1352) + node T_1365 = cat(T_1364, UInt<5>("h2")) + node T_1366 = cat(T_1365, T_1363) + node T_1367 = bits(io.in, 11, 7) + node T_1369 = bits(io.in, 6, 2) + node T_1370 = bits(io.in, 31, 27) + wire T_1377 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1377 is invalid + T_1377.bits <= T_1366 + T_1377.rd <= T_1367 + T_1377.rs1 <= UInt<5>("h2") + T_1377.rs2 <= T_1369 + T_1377.rs3 <= T_1370 + node T_1383 = bits(io.in, 9, 7) + node T_1384 = bits(io.in, 12, 10) + node T_1386 = cat(T_1383, T_1384) + node T_1387 = cat(T_1386, UInt<3>("h0")) + node T_1388 = shr(T_1387, 5) + node T_1389 = bits(io.in, 6, 2) + node T_1392 = bits(io.in, 9, 7) + node T_1393 = bits(io.in, 12, 10) + node T_1395 = cat(T_1392, T_1393) + node T_1396 = cat(T_1395, UInt<3>("h0")) + node T_1397 = bits(T_1396, 4, 0) + node T_1399 = cat(UInt<3>("h3"), T_1397) + node T_1400 = cat(T_1399, UInt<7>("h23")) + node T_1401 = cat(T_1388, T_1389) + node T_1402 = cat(T_1401, UInt<5>("h2")) + node T_1403 = cat(T_1402, T_1400) + node T_1404 = bits(io.in, 11, 7) + node T_1406 = bits(io.in, 6, 2) + node T_1407 = bits(io.in, 31, 27) + wire T_1414 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1414 is invalid + T_1414.bits <= T_1403 + T_1414.rd <= T_1404 + T_1414.rs1 <= UInt<5>("h2") + T_1414.rs2 <= T_1406 + T_1414.rs3 <= T_1407 + node T_1420 = bits(io.in, 11, 7) + node T_1421 = bits(io.in, 19, 15) + node T_1422 = bits(io.in, 24, 20) + node T_1423 = bits(io.in, 31, 27) + wire T_1430 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1430 is invalid + T_1430.bits <= io.in + T_1430.rd <= T_1420 + T_1430.rs1 <= T_1421 + T_1430.rs2 <= T_1422 + T_1430.rs3 <= T_1423 + node T_1436 = bits(io.in, 11, 7) + node T_1437 = bits(io.in, 19, 15) + node T_1438 = bits(io.in, 24, 20) + node T_1439 = bits(io.in, 31, 27) + wire T_1446 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1446 is invalid + T_1446.bits <= io.in + T_1446.rd <= T_1436 + T_1446.rs1 <= T_1437 + T_1446.rs2 <= T_1438 + T_1446.rs3 <= T_1439 + node T_1452 = bits(io.in, 11, 7) + node T_1453 = bits(io.in, 19, 15) + node T_1454 = bits(io.in, 24, 20) + node T_1455 = bits(io.in, 31, 27) + wire T_1462 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1462 is invalid + T_1462.bits <= io.in + T_1462.rd <= T_1452 + T_1462.rs1 <= T_1453 + T_1462.rs2 <= T_1454 + T_1462.rs3 <= T_1455 + node T_1468 = bits(io.in, 11, 7) + node T_1469 = bits(io.in, 19, 15) + node T_1470 = bits(io.in, 24, 20) + node T_1471 = bits(io.in, 31, 27) + wire T_1478 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1478 is invalid + T_1478.bits <= io.in + T_1478.rd <= T_1468 + T_1478.rs1 <= T_1469 + T_1478.rs2 <= T_1470 + T_1478.rs3 <= T_1471 + node T_1484 = bits(io.in, 11, 7) + node T_1485 = bits(io.in, 19, 15) + node T_1486 = bits(io.in, 24, 20) + node T_1487 = bits(io.in, 31, 27) + wire T_1494 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1494 is invalid + T_1494.bits <= io.in + T_1494.rd <= T_1484 + T_1494.rs1 <= T_1485 + T_1494.rs2 <= T_1486 + T_1494.rs3 <= T_1487 + node T_1500 = bits(io.in, 11, 7) + node T_1501 = bits(io.in, 19, 15) + node T_1502 = bits(io.in, 24, 20) + node T_1503 = bits(io.in, 31, 27) + wire T_1510 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1510 is invalid + T_1510.bits <= io.in + T_1510.rd <= T_1500 + T_1510.rs1 <= T_1501 + T_1510.rs2 <= T_1502 + T_1510.rs3 <= T_1503 + node T_1516 = bits(io.in, 11, 7) + node T_1517 = bits(io.in, 19, 15) + node T_1518 = bits(io.in, 24, 20) + node T_1519 = bits(io.in, 31, 27) + wire T_1526 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1526 is invalid + T_1526.bits <= io.in + T_1526.rd <= T_1516 + T_1526.rs1 <= T_1517 + T_1526.rs2 <= T_1518 + T_1526.rs3 <= T_1519 + node T_1532 = bits(io.in, 11, 7) + node T_1533 = bits(io.in, 19, 15) + node T_1534 = bits(io.in, 24, 20) + node T_1535 = bits(io.in, 31, 27) + wire T_1542 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} + T_1542 is invalid + T_1542.bits <= io.in + T_1542.rd <= T_1532 + T_1542.rs1 <= T_1533 + T_1542.rs2 <= T_1534 + T_1542.rs3 <= T_1535 + node T_1548 = bits(io.in, 1, 0) + node T_1549 = bits(io.in, 15, 13) + node T_1550 = cat(T_1548, T_1549) + node T_1552 = and(T_1550, UInt<4>("hf")) + node T_1554 = geq(T_1550, UInt<5>("h10")) + node T_1556 = and(T_1552, UInt<3>("h7")) + node T_1558 = geq(T_1552, UInt<4>("h8")) + node T_1560 = and(T_1556, UInt<2>("h3")) + node T_1562 = geq(T_1556, UInt<3>("h4")) + node T_1564 = and(T_1560, UInt<1>("h1")) + node T_1566 = geq(T_1560, UInt<2>("h2")) + node T_1568 = and(T_1564, UInt<1>("h0")) + node T_1570 = geq(T_1564, UInt<1>("h1")) + node T_1571 = mux(T_1570, T_1542, T_1526) + node T_1578 = and(T_1564, UInt<1>("h0")) + node T_1580 = geq(T_1564, UInt<1>("h1")) + node T_1581 = mux(T_1580, T_1510, T_1494) + node T_1587 = mux(T_1566, T_1571, T_1581) + node T_1594 = and(T_1560, UInt<1>("h1")) + node T_1596 = geq(T_1560, UInt<2>("h2")) + node T_1598 = and(T_1594, UInt<1>("h0")) + node T_1600 = geq(T_1594, UInt<1>("h1")) + node T_1601 = mux(T_1600, T_1478, T_1462) + node T_1608 = and(T_1594, UInt<1>("h0")) + node T_1610 = geq(T_1594, UInt<1>("h1")) + node T_1611 = mux(T_1610, T_1446, T_1430) + node T_1617 = mux(T_1596, T_1601, T_1611) + node T_1623 = mux(T_1562, T_1587, T_1617) + node T_1630 = and(T_1556, UInt<2>("h3")) + node T_1632 = geq(T_1556, UInt<3>("h4")) + node T_1634 = and(T_1630, UInt<1>("h1")) + node T_1636 = geq(T_1630, UInt<2>("h2")) + node T_1638 = and(T_1634, UInt<1>("h0")) + node T_1640 = geq(T_1634, UInt<1>("h1")) + node T_1641 = mux(T_1640, T_1414, T_1377) + node T_1648 = and(T_1634, UInt<1>("h0")) + node T_1650 = geq(T_1634, UInt<1>("h1")) + node T_1651 = mux(T_1650, T_1340, T_1303) + node T_1657 = mux(T_1636, T_1641, T_1651) + node T_1664 = and(T_1630, UInt<1>("h1")) + node T_1666 = geq(T_1630, UInt<2>("h2")) + node T_1668 = and(T_1664, UInt<1>("h0")) + node T_1670 = geq(T_1664, UInt<1>("h1")) + node T_1671 = mux(T_1670, T_1162, T_1131) + node T_1678 = and(T_1664, UInt<1>("h0")) + node T_1680 = geq(T_1664, UInt<1>("h1")) + node T_1681 = mux(T_1680, T_1100, T_1069) + node T_1687 = mux(T_1666, T_1671, T_1681) + node T_1693 = mux(T_1632, T_1657, T_1687) + node T_1699 = mux(T_1558, T_1623, T_1693) + node T_1706 = and(T_1552, UInt<3>("h7")) + node T_1708 = geq(T_1552, UInt<4>("h8")) + node T_1710 = and(T_1706, UInt<2>("h3")) + node T_1712 = geq(T_1706, UInt<3>("h4")) + node T_1714 = and(T_1710, UInt<1>("h1")) + node T_1716 = geq(T_1710, UInt<2>("h2")) + node T_1718 = and(T_1714, UInt<1>("h0")) + node T_1720 = geq(T_1714, UInt<1>("h1")) + node T_1721 = mux(T_1720, T_1042, T_947) + node T_1728 = and(T_1714, UInt<1>("h0")) + node T_1730 = geq(T_1714, UInt<1>("h1")) + node T_1731 = mux(T_1730, T_850, T_735) + node T_1737 = mux(T_1716, T_1721, T_1731) + node T_1744 = and(T_1710, UInt<1>("h1")) + node T_1746 = geq(T_1710, UInt<2>("h2")) + node T_1748 = and(T_1744, UInt<1>("h0")) + node T_1750 = geq(T_1744, UInt<1>("h1")) + node T_1751 = mux(T_1750, T_576, T_468) + node T_1758 = and(T_1744, UInt<1>("h0")) + node T_1760 = geq(T_1744, UInt<1>("h1")) + node T_1761 = mux(T_1760, T_435, T_397) + node T_1767 = mux(T_1746, T_1751, T_1761) + node T_1773 = mux(T_1712, T_1737, T_1767) + node T_1780 = and(T_1706, UInt<2>("h3")) + node T_1782 = geq(T_1706, UInt<3>("h4")) + node T_1784 = and(T_1780, UInt<1>("h1")) + node T_1786 = geq(T_1780, UInt<2>("h2")) + node T_1788 = and(T_1784, UInt<1>("h0")) + node T_1790 = geq(T_1784, UInt<1>("h1")) + node T_1791 = mux(T_1790, T_364, T_317) + node T_1798 = and(T_1784, UInt<1>("h0")) + node T_1800 = geq(T_1784, UInt<1>("h1")) + node T_1801 = mux(T_1800, T_266, T_219) + node T_1807 = mux(T_1786, T_1791, T_1801) + node T_1814 = and(T_1780, UInt<1>("h1")) + node T_1816 = geq(T_1780, UInt<2>("h2")) + node T_1818 = and(T_1814, UInt<1>("h0")) + node T_1820 = geq(T_1814, UInt<1>("h1")) + node T_1821 = mux(T_1820, T_168, T_129) + node T_1828 = and(T_1814, UInt<1>("h0")) + node T_1830 = geq(T_1814, UInt<1>("h1")) + node T_1831 = mux(T_1830, T_88, T_49) + node T_1837 = mux(T_1816, T_1821, T_1831) + node T_1843 = mux(T_1782, T_1807, T_1837) + node T_1849 = mux(T_1708, T_1773, T_1843) + node T_1855 = mux(T_1554, T_1699, T_1849) + io.out <- T_1855 + + module IBuf : input clk : Clock input reset : UInt<1> - output io : {flip imem : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, inst : {flip ready : UInt<1>, valid : UInt<1>, bits : {pf0 : UInt<1>, pf1 : UInt<1>, replay : UInt<1>, btb_hit : UInt<1>, rvc : UInt<1>, inst : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}}}[1]} - + output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { pf0 : UInt<1>, pf1 : UInt<1>, replay : UInt<1>, btb_hit : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}}}[1]} + io is invalid - reg nBufValid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg buf : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}, clk - reg ibufBTBHit : UInt<1>, clk - reg ibufBTBResp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - node pcWordBits = bits(io.imem.bits.pc, 1, 1) @[util.scala 25:13] + reg nBufValid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg buf : { btb : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}, clk with : + reset => (UInt<1>("h0"), buf) + reg ibufBTBHit : UInt<1>, clk with : + reset => (UInt<1>("h0"), ibufBTBHit) + reg ibufBTBResp : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : + reset => (UInt<1>("h0"), ibufBTBResp) + node pcWordBits = bits(io.imem.bits.pc, 1, 1) wire nReady : UInt<2> nReady is invalid - nReady <= UInt<2>("h00") - node T_375 = and(io.imem.bits.btb.valid, io.imem.bits.btb.bits.taken) @[ibuf.scala 41:40] - node T_377 = add(io.imem.bits.btb.bits.bridx, UInt<1>("h01")) @[ibuf.scala 41:100] - node T_379 = mux(T_375, T_377, UInt<2>("h02")) @[ibuf.scala 41:16] - node T_380 = sub(T_379, pcWordBits) @[ibuf.scala 41:124] - node nIC = tail(T_380, 1) @[ibuf.scala 41:124] - node T_381 = sub(nReady, nBufValid) @[ibuf.scala 42:25] - node nICReady = tail(T_381, 1) @[ibuf.scala 42:25] - node T_383 = mux(io.imem.valid, nIC, UInt<1>("h00")) @[ibuf.scala 43:19] - node T_384 = add(T_383, nBufValid) @[ibuf.scala 43:49] - node nValid = tail(T_384, 1) @[ibuf.scala 43:49] - node T_385 = geq(nReady, nBufValid) @[ibuf.scala 44:27] - node T_386 = geq(nICReady, nIC) @[ibuf.scala 44:53] - node T_388 = sub(nIC, nICReady) @[ibuf.scala 44:72] - node T_389 = tail(T_388, 1) @[ibuf.scala 44:72] - node T_390 = geq(UInt<1>("h01"), T_389) @[ibuf.scala 44:65] - node T_391 = or(T_386, T_390) @[ibuf.scala 44:60] - node T_392 = and(T_385, T_391) @[ibuf.scala 44:40] - io.imem.ready <= T_392 @[ibuf.scala 44:17] - node T_393 = geq(nReady, nBufValid) @[ibuf.scala 47:29] - node T_395 = sub(nBufValid, nReady) @[ibuf.scala 47:62] - node T_396 = tail(T_395, 1) @[ibuf.scala 47:62] - node T_397 = mux(T_393, UInt<1>("h00"), T_396) @[ibuf.scala 47:21] - nBufValid <= T_397 @[ibuf.scala 47:15] - node T_398 = geq(nReady, nBufValid) @[ibuf.scala 54:35] - node T_399 = and(io.imem.valid, T_398) @[ibuf.scala 54:25] - node T_400 = lt(nICReady, nIC) @[ibuf.scala 54:60] - node T_401 = and(T_399, T_400) @[ibuf.scala 54:48] - node T_403 = sub(nIC, nICReady) @[ibuf.scala 54:78] - node T_404 = tail(T_403, 1) @[ibuf.scala 54:78] - node T_405 = geq(UInt<1>("h01"), T_404) @[ibuf.scala 54:71] - node T_406 = and(T_401, T_405) @[ibuf.scala 54:66] - when T_406 : @[ibuf.scala 54:90] - node T_407 = add(pcWordBits, nICReady) @[ibuf.scala 55:30] - node T_408 = tail(T_407, 1) @[ibuf.scala 55:30] - node T_409 = sub(nIC, nICReady) @[ibuf.scala 56:24] - node T_410 = tail(T_409, 1) @[ibuf.scala 56:24] - nBufValid <= T_410 @[ibuf.scala 56:17] - buf <- io.imem.bits @[ibuf.scala 57:11] - node T_411 = shr(io.imem.bits.data, 16) @[ibuf.scala 129:58] - node T_412 = cat(T_411, T_411) @[Cat.scala 20:58] - node T_413 = cat(T_412, io.imem.bits.data) @[Cat.scala 20:58] - node T_414 = shl(T_408, 4) @[ibuf.scala 130:19] - node T_415 = dshr(T_413, T_414) @[ibuf.scala 130:10] - node T_416 = bits(T_415, 15, 0) @[ibuf.scala 58:59] - buf.data <= T_416 @[ibuf.scala 58:16] - node T_417 = not(UInt<40>("h03")) @[ibuf.scala 59:35] - node T_418 = and(io.imem.bits.pc, T_417) @[ibuf.scala 59:33] - node T_419 = shl(nICReady, 1) @[ibuf.scala 59:78] - node T_420 = add(io.imem.bits.pc, T_419) @[ibuf.scala 59:66] - node T_421 = tail(T_420, 1) @[ibuf.scala 59:66] - node T_422 = and(T_421, UInt<40>("h03")) @[ibuf.scala 59:107] - node T_423 = or(T_418, T_422) @[ibuf.scala 59:47] - buf.pc <= T_423 @[ibuf.scala 59:14] - ibufBTBHit <= io.imem.bits.btb.valid @[ibuf.scala 60:18] - when io.imem.bits.btb.valid : @[ibuf.scala 61:37] - ibufBTBResp <- io.imem.bits.btb.bits @[ibuf.scala 62:21] - node T_424 = add(io.imem.bits.btb.bits.bridx, nICReady) @[ibuf.scala 63:58] - node T_425 = tail(T_424, 1) @[ibuf.scala 63:58] - ibufBTBResp.bridx <= T_425 @[ibuf.scala 63:27] - skip @[ibuf.scala 61:37] - skip @[ibuf.scala 54:90] - when io.kill : @[ibuf.scala 66:20] - nBufValid <= UInt<1>("h00") @[ibuf.scala 67:17] - skip @[ibuf.scala 66:20] - node T_428 = add(UInt<2>("h02"), nBufValid) @[ibuf.scala 71:32] - node T_429 = tail(T_428, 1) @[ibuf.scala 71:32] - node T_430 = sub(T_429, pcWordBits) @[ibuf.scala 71:44] - node T_431 = tail(T_430, 1) @[ibuf.scala 71:44] - node icShiftAmt = bits(T_431, 1, 0) @[ibuf.scala 71:57] - node T_432 = bits(io.imem.bits.data, 15, 0) @[ibuf.scala 72:87] - node T_433 = cat(T_432, T_432) @[Cat.scala 20:58] - node T_434 = cat(io.imem.bits.data, T_433) @[Cat.scala 20:58] - node T_435 = shr(T_434, 48) @[ibuf.scala 122:58] - node T_436 = cat(T_435, T_435) @[Cat.scala 20:58] - node T_437 = cat(T_436, T_436) @[Cat.scala 20:58] - node T_438 = cat(T_437, T_434) @[Cat.scala 20:58] - node T_439 = shl(icShiftAmt, 4) @[ibuf.scala 123:19] - node T_440 = dshl(T_438, T_439) @[ibuf.scala 123:10] - node icData = bits(T_440, 95, 64) @[util.scala 25:13] - node T_442 = not(UInt<32>("h00")) @[ibuf.scala 74:17] - node T_443 = shl(nBufValid, 4) @[ibuf.scala 74:65] - node T_444 = dshl(T_442, T_443) @[ibuf.scala 74:51] - node icMask = bits(T_444, 31, 0) @[ibuf.scala 74:92] - node T_445 = and(icData, icMask) @[ibuf.scala 75:21] - node T_446 = not(icMask) @[ibuf.scala 75:43] - node T_447 = and(buf.data, T_446) @[ibuf.scala 75:41] - node inst = or(T_445, T_447) @[ibuf.scala 75:30] - node T_449 = dshl(UInt<1>("h01"), nValid) @[OneHot.scala 44:15] - node T_451 = sub(T_449, UInt<1>("h01")) @[ibuf.scala 77:33] - node T_452 = tail(T_451, 1) @[ibuf.scala 77:33] - node valid = bits(T_452, 1, 0) @[ibuf.scala 77:37] - node T_454 = dshl(UInt<1>("h01"), nBufValid) @[OneHot.scala 44:15] - node T_456 = sub(T_454, UInt<1>("h01")) @[ibuf.scala 78:37] - node bufMask = tail(T_456, 1) @[ibuf.scala 78:37] - node T_458 = mux(buf.xcpt_if, bufMask, UInt<1>("h00")) @[ibuf.scala 79:29] - node T_459 = not(bufMask) @[ibuf.scala 79:89] - node T_461 = mux(io.imem.bits.xcpt_if, T_459, UInt<1>("h00")) @[ibuf.scala 79:66] - node T_462 = or(T_458, T_461) @[ibuf.scala 79:61] - node xcpt_if = and(valid, T_462) @[ibuf.scala 79:23] - node T_464 = mux(buf.replay, bufMask, UInt<1>("h00")) @[ibuf.scala 80:31] - node T_465 = not(bufMask) @[ibuf.scala 80:89] - node T_467 = mux(io.imem.bits.replay, T_465, UInt<1>("h00")) @[ibuf.scala 80:67] - node T_468 = or(T_464, T_467) @[ibuf.scala 80:62] - node ic_replay = and(valid, T_468) @[ibuf.scala 80:25] - node T_470 = dshl(UInt<1>("h01"), ibufBTBResp.bridx) @[OneHot.scala 44:15] - node ibufBTBHitMask = mux(ibufBTBHit, T_470, UInt<1>("h00")) @[ibuf.scala 81:27] - node T_472 = add(io.imem.bits.btb.bits.bridx, nBufValid) @[ibuf.scala 82:87] - node T_473 = sub(T_472, pcWordBits) @[ibuf.scala 82:100] - node T_474 = tail(T_473, 1) @[ibuf.scala 82:100] - node T_476 = dshl(UInt<1>("h01"), T_474) @[OneHot.scala 44:15] - node icBTBHitMask = mux(io.imem.bits.btb.valid, T_476, UInt<1>("h00")) @[ibuf.scala 82:25] - node T_478 = and(ibufBTBHitMask, bufMask) @[ibuf.scala 83:35] - node T_479 = not(bufMask) @[ibuf.scala 83:62] - node T_480 = and(icBTBHitMask, T_479) @[ibuf.scala 83:60] - node btbHitMask = or(T_478, T_480) @[ibuf.scala 83:45] - node T_481 = and(ibufBTBHitMask, bufMask) @[ibuf.scala 85:38] - node T_483 = neq(T_481, UInt<1>("h00")) @[ibuf.scala 85:49] - node T_484 = mux(T_483, ibufBTBResp, io.imem.bits.btb.bits) @[ibuf.scala 85:21] - io.btb_resp <- T_484 @[ibuf.scala 85:15] - node T_494 = gt(nBufValid, UInt<1>("h00")) @[ibuf.scala 86:26] - node T_495 = mux(T_494, buf.pc, io.imem.bits.pc) @[ibuf.scala 86:15] - io.pc <= T_495 @[ibuf.scala 86:9] - inst RVCExpander_1 of RVCExpander @[ibuf.scala 90:21] + nReady <= UInt<2>("h0") + node T_375 = and(io.imem.bits.btb.valid, io.imem.bits.btb.bits.taken) + node T_377 = add(io.imem.bits.btb.bits.bridx, UInt<1>("h1")) + node T_379 = mux(T_375, T_377, UInt<2>("h2")) + node T_380 = sub(T_379, pcWordBits) + node nIC = tail(T_380, 1) + node T_381 = sub(nReady, nBufValid) + node nICReady = tail(T_381, 1) + node T_383 = mux(io.imem.valid, nIC, UInt<1>("h0")) + node T_384 = add(T_383, nBufValid) + node nValid = tail(T_384, 1) + node T_385 = geq(nReady, nBufValid) + node T_386 = geq(nICReady, nIC) + node T_388 = sub(nIC, nICReady) + node T_389 = tail(T_388, 1) + node T_390 = geq(UInt<1>("h1"), T_389) + node T_391 = or(T_386, T_390) + node T_392 = and(T_385, T_391) + io.imem.ready <= T_392 + node T_393 = geq(nReady, nBufValid) + node T_395 = sub(nBufValid, nReady) + node T_396 = tail(T_395, 1) + node T_397 = mux(T_393, UInt<1>("h0"), T_396) + nBufValid <= T_397 + node T_398 = geq(nReady, nBufValid) + node T_399 = and(io.imem.valid, T_398) + node T_400 = lt(nICReady, nIC) + node T_401 = and(T_399, T_400) + node T_403 = sub(nIC, nICReady) + node T_404 = tail(T_403, 1) + node T_405 = geq(UInt<1>("h1"), T_404) + node T_406 = and(T_401, T_405) + when T_406 : + node T_407 = add(pcWordBits, nICReady) + node T_408 = tail(T_407, 1) + node T_409 = sub(nIC, nICReady) + node T_410 = tail(T_409, 1) + nBufValid <= T_410 + buf <- io.imem.bits + node T_411 = shr(io.imem.bits.data, 16) + node T_412 = cat(T_411, T_411) + node T_413 = cat(T_412, io.imem.bits.data) + node T_414 = shl(T_408, 4) + node T_415 = dshr(T_413, T_414) + node T_416 = bits(T_415, 15, 0) + buf.data <= T_416 + node T_417 = not(UInt<40>("h3")) + node T_418 = and(io.imem.bits.pc, T_417) + node T_419 = shl(nICReady, 1) + node T_420 = add(io.imem.bits.pc, T_419) + node T_421 = tail(T_420, 1) + node T_422 = and(T_421, UInt<40>("h3")) + node T_423 = or(T_418, T_422) + buf.pc <= T_423 + ibufBTBHit <= io.imem.bits.btb.valid + when io.imem.bits.btb.valid : + ibufBTBResp <- io.imem.bits.btb.bits + node T_424 = add(io.imem.bits.btb.bits.bridx, nICReady) + node T_425 = tail(T_424, 1) + ibufBTBResp.bridx <= T_425 + when io.kill : + nBufValid <= UInt<1>("h0") + node T_428 = add(UInt<2>("h2"), nBufValid) + node T_429 = tail(T_428, 1) + node T_430 = sub(T_429, pcWordBits) + node T_431 = tail(T_430, 1) + node icShiftAmt = bits(T_431, 1, 0) + node T_432 = bits(io.imem.bits.data, 15, 0) + node T_433 = cat(T_432, T_432) + node T_434 = cat(io.imem.bits.data, T_433) + node T_435 = shr(T_434, 48) + node T_436 = cat(T_435, T_435) + node T_437 = cat(T_436, T_436) + node T_438 = cat(T_437, T_434) + node T_439 = shl(icShiftAmt, 4) + node T_440 = dshl(T_438, T_439) + node icData = bits(T_440, 95, 64) + node T_442 = not(UInt<32>("h0")) + node T_443 = shl(nBufValid, 4) + node T_444 = dshl(T_442, T_443) + node icMask = bits(T_444, 31, 0) + node T_445 = and(icData, icMask) + node T_446 = not(icMask) + node T_447 = and(buf.data, T_446) + node inst = or(T_445, T_447) + node T_449 = dshl(UInt<1>("h1"), nValid) + node T_451 = sub(T_449, UInt<1>("h1")) + node T_452 = tail(T_451, 1) + node valid = bits(T_452, 1, 0) + node T_454 = dshl(UInt<1>("h1"), nBufValid) + node T_456 = sub(T_454, UInt<1>("h1")) + node bufMask = tail(T_456, 1) + node T_458 = mux(buf.xcpt_if, bufMask, UInt<1>("h0")) + node T_459 = not(bufMask) + node T_461 = mux(io.imem.bits.xcpt_if, T_459, UInt<1>("h0")) + node T_462 = or(T_458, T_461) + node xcpt_if = and(valid, T_462) + node T_464 = mux(buf.replay, bufMask, UInt<1>("h0")) + node T_465 = not(bufMask) + node T_467 = mux(io.imem.bits.replay, T_465, UInt<1>("h0")) + node T_468 = or(T_464, T_467) + node ic_replay = and(valid, T_468) + node T_470 = dshl(UInt<1>("h1"), ibufBTBResp.bridx) + node ibufBTBHitMask = mux(ibufBTBHit, T_470, UInt<1>("h0")) + node T_472 = add(io.imem.bits.btb.bits.bridx, nBufValid) + node T_473 = sub(T_472, pcWordBits) + node T_474 = tail(T_473, 1) + node T_476 = dshl(UInt<1>("h1"), T_474) + node icBTBHitMask = mux(io.imem.bits.btb.valid, T_476, UInt<1>("h0")) + node T_478 = and(ibufBTBHitMask, bufMask) + node T_479 = not(bufMask) + node T_480 = and(icBTBHitMask, T_479) + node btbHitMask = or(T_478, T_480) + node T_481 = and(ibufBTBHitMask, bufMask) + node T_483 = neq(T_481, UInt<1>("h0")) + node T_484 = mux(T_483, ibufBTBResp, io.imem.bits.btb.bits) + io.btb_resp <- T_484 + node T_494 = gt(nBufValid, UInt<1>("h0")) + node T_495 = mux(T_494, buf.pc, io.imem.bits.pc) + io.pc <= T_495 + inst RVCExpander_1 of RVCExpander RVCExpander_1.io is invalid RVCExpander_1.clk <= clk RVCExpander_1.reset <= reset - RVCExpander_1.io.in <= inst @[ibuf.scala 91:15] - io.inst[0].bits.inst <- RVCExpander_1.io.out @[ibuf.scala 92:26] - node T_497 = dshr(ic_replay, UInt<1>("h00")) @[ibuf.scala 95:29] - node T_498 = bits(T_497, 0, 0) @[ibuf.scala 95:29] - node T_500 = eq(RVCExpander_1.io.rvc, UInt<1>("h00")) @[ibuf.scala 95:37] - node T_501 = dshr(btbHitMask, UInt<1>("h00")) @[ibuf.scala 95:63] - node T_502 = bits(T_501, 0, 0) @[ibuf.scala 95:63] - node T_504 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 95:81] - node T_505 = tail(T_504, 1) @[ibuf.scala 95:81] - node T_506 = dshr(ic_replay, T_505) @[ibuf.scala 95:79] - node T_507 = bits(T_506, 0, 0) @[ibuf.scala 95:79] - node T_508 = or(T_502, T_507) @[ibuf.scala 95:67] - node T_509 = and(T_500, T_508) @[ibuf.scala 95:49] - node T_510 = or(T_498, T_509) @[ibuf.scala 95:33] - node T_511 = dshr(valid, UInt<1>("h00")) @[ibuf.scala 96:32] - node T_512 = bits(T_511, 0, 0) @[ibuf.scala 96:32] - node T_514 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 96:61] - node T_515 = tail(T_514, 1) @[ibuf.scala 96:61] - node T_516 = dshr(valid, T_515) @[ibuf.scala 96:59] - node T_517 = bits(T_516, 0, 0) @[ibuf.scala 96:59] - node T_518 = or(RVCExpander_1.io.rvc, T_517) @[ibuf.scala 96:51] - node T_520 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 96:77] - node T_521 = tail(T_520, 1) @[ibuf.scala 96:77] - node T_522 = dshr(xcpt_if, T_521) @[ibuf.scala 96:75] - node T_523 = bits(T_522, 0, 0) @[ibuf.scala 96:75] - node T_524 = or(T_518, T_523) @[ibuf.scala 96:65] - node T_525 = or(T_524, T_510) @[ibuf.scala 96:81] - node T_526 = and(T_512, T_525) @[ibuf.scala 96:36] - io.inst[0].valid <= T_526 @[ibuf.scala 96:24] - node T_527 = dshr(xcpt_if, UInt<1>("h00")) @[ibuf.scala 97:37] - node T_528 = bits(T_527, 0, 0) @[ibuf.scala 97:37] - io.inst[0].bits.pf0 <= T_528 @[ibuf.scala 97:27] - node T_530 = eq(RVCExpander_1.io.rvc, UInt<1>("h00")) @[ibuf.scala 98:30] - node T_532 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 98:54] - node T_533 = tail(T_532, 1) @[ibuf.scala 98:54] - node T_534 = dshr(xcpt_if, T_533) @[ibuf.scala 98:52] - node T_535 = bits(T_534, 0, 0) @[ibuf.scala 98:52] - node T_536 = and(T_530, T_535) @[ibuf.scala 98:42] - io.inst[0].bits.pf1 <= T_536 @[ibuf.scala 98:27] - io.inst[0].bits.replay <= T_510 @[ibuf.scala 99:30] - node T_537 = dshr(btbHitMask, UInt<1>("h00")) @[ibuf.scala 100:44] - node T_538 = bits(T_537, 0, 0) @[ibuf.scala 100:44] - node T_540 = eq(RVCExpander_1.io.rvc, UInt<1>("h00")) @[ibuf.scala 100:52] - node T_542 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 100:79] - node T_543 = tail(T_542, 1) @[ibuf.scala 100:79] - node T_544 = dshr(btbHitMask, T_543) @[ibuf.scala 100:77] - node T_545 = bits(T_544, 0, 0) @[ibuf.scala 100:77] - node T_546 = and(T_540, T_545) @[ibuf.scala 100:64] - node T_547 = or(T_538, T_546) @[ibuf.scala 100:48] - io.inst[0].bits.btb_hit <= T_547 @[ibuf.scala 100:31] - io.inst[0].bits.rvc <= RVCExpander_1.io.rvc @[ibuf.scala 101:27] - node T_548 = and(io.inst[0].ready, io.inst[0].valid) @[Decoupled.scala 21:42] - when T_548 : @[ibuf.scala 103:32] - node T_550 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 103:61] - node T_551 = tail(T_550, 1) @[ibuf.scala 103:61] - node T_553 = add(UInt<1>("h00"), UInt<2>("h02")) @[ibuf.scala 103:66] - node T_554 = tail(T_553, 1) @[ibuf.scala 103:66] - node T_555 = mux(RVCExpander_1.io.rvc, T_551, T_554) @[ibuf.scala 103:47] - nReady <= T_555 @[ibuf.scala 103:41] - skip @[ibuf.scala 103:32] - node T_557 = add(UInt<1>("h00"), UInt<1>("h01")) @[ibuf.scala 105:36] - node T_558 = tail(T_557, 1) @[ibuf.scala 105:36] - node T_560 = add(UInt<1>("h00"), UInt<2>("h02")) @[ibuf.scala 105:41] - node T_561 = tail(T_560, 1) @[ibuf.scala 105:41] - node T_562 = mux(RVCExpander_1.io.rvc, T_558, T_561) @[ibuf.scala 105:22] - node T_563 = shr(inst, 16) @[ibuf.scala 105:70] - node T_564 = shr(inst, 32) @[ibuf.scala 105:85] - node T_565 = mux(RVCExpander_1.io.rvc, T_563, T_564) @[ibuf.scala 105:49] - - module CSRFile : + RVCExpander_1.io.in <= inst + io.inst[0].bits.inst <- RVCExpander_1.io.out + node T_497 = dshr(ic_replay, UInt<1>("h0")) + node T_498 = bits(T_497, 0, 0) + node T_500 = eq(RVCExpander_1.io.rvc, UInt<1>("h0")) + node T_501 = dshr(btbHitMask, UInt<1>("h0")) + node T_502 = bits(T_501, 0, 0) + node T_504 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_505 = tail(T_504, 1) + node T_506 = dshr(ic_replay, T_505) + node T_507 = bits(T_506, 0, 0) + node T_508 = or(T_502, T_507) + node T_509 = and(T_500, T_508) + node T_510 = or(T_498, T_509) + node T_511 = dshr(valid, UInt<1>("h0")) + node T_512 = bits(T_511, 0, 0) + node T_514 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_515 = tail(T_514, 1) + node T_516 = dshr(valid, T_515) + node T_517 = bits(T_516, 0, 0) + node T_518 = or(RVCExpander_1.io.rvc, T_517) + node T_520 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_521 = tail(T_520, 1) + node T_522 = dshr(xcpt_if, T_521) + node T_523 = bits(T_522, 0, 0) + node T_524 = or(T_518, T_523) + node T_525 = or(T_524, T_510) + node T_526 = and(T_512, T_525) + io.inst[0].valid <= T_526 + node T_527 = dshr(xcpt_if, UInt<1>("h0")) + node T_528 = bits(T_527, 0, 0) + io.inst[0].bits.pf0 <= T_528 + node T_530 = eq(RVCExpander_1.io.rvc, UInt<1>("h0")) + node T_532 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_533 = tail(T_532, 1) + node T_534 = dshr(xcpt_if, T_533) + node T_535 = bits(T_534, 0, 0) + node T_536 = and(T_530, T_535) + io.inst[0].bits.pf1 <= T_536 + io.inst[0].bits.replay <= T_510 + node T_537 = dshr(btbHitMask, UInt<1>("h0")) + node T_538 = bits(T_537, 0, 0) + node T_540 = eq(RVCExpander_1.io.rvc, UInt<1>("h0")) + node T_542 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_543 = tail(T_542, 1) + node T_544 = dshr(btbHitMask, T_543) + node T_545 = bits(T_544, 0, 0) + node T_546 = and(T_540, T_545) + node T_547 = or(T_538, T_546) + io.inst[0].bits.btb_hit <= T_547 + io.inst[0].bits.rvc <= RVCExpander_1.io.rvc + node T_548 = and(io.inst[0].ready, io.inst[0].valid) + when T_548 : + node T_550 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_551 = tail(T_550, 1) + node T_553 = add(UInt<1>("h0"), UInt<2>("h2")) + node T_554 = tail(T_553, 1) + node T_555 = mux(RVCExpander_1.io.rvc, T_551, T_554) + nReady <= T_555 + node T_557 = add(UInt<1>("h0"), UInt<1>("h1")) + node T_558 = tail(T_557, 1) + node T_560 = add(UInt<1>("h0"), UInt<2>("h2")) + node T_561 = tail(T_560, 1) + node T_562 = mux(RVCExpander_1.io.rvc, T_558, T_561) + node T_563 = shr(inst, 16) + node T_564 = shr(inst, 32) + node T_565 = mux(RVCExpander_1.io.rvc, T_563, T_564) + + module CSRFile : input clk : Clock input reset : UInt<1> - output io : {flip prci : {reset : UInt<1>, id : UInt<1>, interrupts : {meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : {asid : UInt<7>, ppn : UInt<38>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, flip badaddr : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[0], fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>}, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip events : UInt<1>[0]} - + output io : { flip prci : { reset : UInt<1>, id : UInt<1>, interrupts : { meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { asid : UInt<7>, ppn : UInt<38>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, flip badaddr : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, autl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, utl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[0], fpu_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>}, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip events : UInt<1>[0]} + io is invalid - wire T_5008 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[csr.scala 161:55] - T_5008 is invalid @[csr.scala 161:55] + wire T_5008 : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + T_5008 is invalid wire T_5035 : UInt<99> T_5035 is invalid - T_5035 <= UInt<1>("h00") - node T_5036 = bits(T_5035, 0, 0) @[csr.scala 161:55] - T_5008.uie <= T_5036 @[csr.scala 161:55] - node T_5037 = bits(T_5035, 1, 1) @[csr.scala 161:55] - T_5008.sie <= T_5037 @[csr.scala 161:55] - node T_5038 = bits(T_5035, 2, 2) @[csr.scala 161:55] - T_5008.hie <= T_5038 @[csr.scala 161:55] - node T_5039 = bits(T_5035, 3, 3) @[csr.scala 161:55] - T_5008.mie <= T_5039 @[csr.scala 161:55] - node T_5040 = bits(T_5035, 4, 4) @[csr.scala 161:55] - T_5008.upie <= T_5040 @[csr.scala 161:55] - node T_5041 = bits(T_5035, 5, 5) @[csr.scala 161:55] - T_5008.spie <= T_5041 @[csr.scala 161:55] - node T_5042 = bits(T_5035, 6, 6) @[csr.scala 161:55] - T_5008.hpie <= T_5042 @[csr.scala 161:55] - node T_5043 = bits(T_5035, 7, 7) @[csr.scala 161:55] - T_5008.mpie <= T_5043 @[csr.scala 161:55] - node T_5044 = bits(T_5035, 8, 8) @[csr.scala 161:55] - T_5008.spp <= T_5044 @[csr.scala 161:55] - node T_5045 = bits(T_5035, 10, 9) @[csr.scala 161:55] - T_5008.hpp <= T_5045 @[csr.scala 161:55] - node T_5046 = bits(T_5035, 12, 11) @[csr.scala 161:55] - T_5008.mpp <= T_5046 @[csr.scala 161:55] - node T_5047 = bits(T_5035, 14, 13) @[csr.scala 161:55] - T_5008.fs <= T_5047 @[csr.scala 161:55] - node T_5048 = bits(T_5035, 16, 15) @[csr.scala 161:55] - T_5008.xs <= T_5048 @[csr.scala 161:55] - node T_5049 = bits(T_5035, 17, 17) @[csr.scala 161:55] - T_5008.mprv <= T_5049 @[csr.scala 161:55] - node T_5050 = bits(T_5035, 18, 18) @[csr.scala 161:55] - T_5008.pum <= T_5050 @[csr.scala 161:55] - node T_5051 = bits(T_5035, 19, 19) @[csr.scala 161:55] - T_5008.mxr <= T_5051 @[csr.scala 161:55] - node T_5052 = bits(T_5035, 23, 20) @[csr.scala 161:55] - T_5008.zero1 <= T_5052 @[csr.scala 161:55] - node T_5053 = bits(T_5035, 28, 24) @[csr.scala 161:55] - T_5008.vm <= T_5053 @[csr.scala 161:55] - node T_5054 = bits(T_5035, 30, 29) @[csr.scala 161:55] - T_5008.zero2 <= T_5054 @[csr.scala 161:55] - node T_5055 = bits(T_5035, 31, 31) @[csr.scala 161:55] - T_5008.sd_rv32 <= T_5055 @[csr.scala 161:55] - node T_5056 = bits(T_5035, 62, 32) @[csr.scala 161:55] - T_5008.zero3 <= T_5056 @[csr.scala 161:55] - node T_5057 = bits(T_5035, 63, 63) @[csr.scala 161:55] - T_5008.sd <= T_5057 @[csr.scala 161:55] - node T_5058 = bits(T_5035, 65, 64) @[csr.scala 161:55] - T_5008.prv <= T_5058 @[csr.scala 161:55] - node T_5059 = bits(T_5035, 97, 66) @[csr.scala 161:55] - T_5008.isa <= T_5059 @[csr.scala 161:55] - node T_5060 = bits(T_5035, 98, 98) @[csr.scala 161:55] - T_5008.debug <= T_5060 @[csr.scala 161:55] - wire reset_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + T_5035 <= UInt<1>("h0") + node T_5036 = bits(T_5035, 0, 0) + T_5008.uie <= T_5036 + node T_5037 = bits(T_5035, 1, 1) + T_5008.sie <= T_5037 + node T_5038 = bits(T_5035, 2, 2) + T_5008.hie <= T_5038 + node T_5039 = bits(T_5035, 3, 3) + T_5008.mie <= T_5039 + node T_5040 = bits(T_5035, 4, 4) + T_5008.upie <= T_5040 + node T_5041 = bits(T_5035, 5, 5) + T_5008.spie <= T_5041 + node T_5042 = bits(T_5035, 6, 6) + T_5008.hpie <= T_5042 + node T_5043 = bits(T_5035, 7, 7) + T_5008.mpie <= T_5043 + node T_5044 = bits(T_5035, 8, 8) + T_5008.spp <= T_5044 + node T_5045 = bits(T_5035, 10, 9) + T_5008.hpp <= T_5045 + node T_5046 = bits(T_5035, 12, 11) + T_5008.mpp <= T_5046 + node T_5047 = bits(T_5035, 14, 13) + T_5008.fs <= T_5047 + node T_5048 = bits(T_5035, 16, 15) + T_5008.xs <= T_5048 + node T_5049 = bits(T_5035, 17, 17) + T_5008.mprv <= T_5049 + node T_5050 = bits(T_5035, 18, 18) + T_5008.pum <= T_5050 + node T_5051 = bits(T_5035, 19, 19) + T_5008.mxr <= T_5051 + node T_5052 = bits(T_5035, 23, 20) + T_5008.zero1 <= T_5052 + node T_5053 = bits(T_5035, 28, 24) + T_5008.vm <= T_5053 + node T_5054 = bits(T_5035, 30, 29) + T_5008.zero2 <= T_5054 + node T_5055 = bits(T_5035, 31, 31) + T_5008.sd_rv32 <= T_5055 + node T_5056 = bits(T_5035, 62, 32) + T_5008.zero3 <= T_5056 + node T_5057 = bits(T_5035, 63, 63) + T_5008.sd <= T_5057 + node T_5058 = bits(T_5035, 65, 64) + T_5008.prv <= T_5058 + node T_5059 = bits(T_5035, 97, 66) + T_5008.isa <= T_5059 + node T_5060 = bits(T_5035, 98, 98) + T_5008.debug <= T_5060 + wire reset_mstatus : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} reset_mstatus is invalid reset_mstatus <- T_5008 - reset_mstatus.mpp <= UInt<2>("h03") @[csr.scala 162:21] - reset_mstatus.prv <= UInt<2>("h03") @[csr.scala 163:21] - reg reg_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clk with : (reset => (reset, reset_mstatus)) + reset_mstatus.mpp <= UInt<2>("h3") + reset_mstatus.prv <= UInt<2>("h3") + reg reg_mstatus : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clk with : + reset => (reset, reset_mstatus) wire new_prv : UInt new_prv is invalid new_prv <= reg_mstatus.prv - node T_5114 = eq(new_prv, UInt<2>("h02")) @[csr.scala 642:27] - node T_5116 = mux(T_5114, UInt<1>("h00"), new_prv) @[csr.scala 642:21] - reg_mstatus.prv <= T_5116 @[csr.scala 167:19] - wire T_5154 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[csr.scala 169:49] - T_5154 is invalid @[csr.scala 169:49] + node T_5114 = eq(new_prv, UInt<2>("h2")) + node T_5116 = mux(T_5114, UInt<1>("h0"), new_prv) + reg_mstatus.prv <= T_5116 + wire T_5154 : { xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} + T_5154 is invalid wire T_5173 : UInt<32> T_5173 is invalid - T_5173 <= UInt<1>("h00") - node T_5174 = bits(T_5173, 1, 0) @[csr.scala 169:49] - T_5154.prv <= T_5174 @[csr.scala 169:49] - node T_5175 = bits(T_5173, 2, 2) @[csr.scala 169:49] - T_5154.step <= T_5175 @[csr.scala 169:49] - node T_5176 = bits(T_5173, 3, 3) @[csr.scala 169:49] - T_5154.halt <= T_5176 @[csr.scala 169:49] - node T_5177 = bits(T_5173, 4, 4) @[csr.scala 169:49] - T_5154.zero1 <= T_5177 @[csr.scala 169:49] - node T_5178 = bits(T_5173, 5, 5) @[csr.scala 169:49] - T_5154.debugint <= T_5178 @[csr.scala 169:49] - node T_5179 = bits(T_5173, 8, 6) @[csr.scala 169:49] - T_5154.cause <= T_5179 @[csr.scala 169:49] - node T_5180 = bits(T_5173, 9, 9) @[csr.scala 169:49] - T_5154.stoptime <= T_5180 @[csr.scala 169:49] - node T_5181 = bits(T_5173, 10, 10) @[csr.scala 169:49] - T_5154.stopcycle <= T_5181 @[csr.scala 169:49] - node T_5182 = bits(T_5173, 11, 11) @[csr.scala 169:49] - T_5154.zero2 <= T_5182 @[csr.scala 169:49] - node T_5183 = bits(T_5173, 12, 12) @[csr.scala 169:49] - T_5154.ebreaku <= T_5183 @[csr.scala 169:49] - node T_5184 = bits(T_5173, 13, 13) @[csr.scala 169:49] - T_5154.ebreaks <= T_5184 @[csr.scala 169:49] - node T_5185 = bits(T_5173, 14, 14) @[csr.scala 169:49] - T_5154.ebreakh <= T_5185 @[csr.scala 169:49] - node T_5186 = bits(T_5173, 15, 15) @[csr.scala 169:49] - T_5154.ebreakm <= T_5186 @[csr.scala 169:49] - node T_5187 = bits(T_5173, 27, 16) @[csr.scala 169:49] - T_5154.zero3 <= T_5187 @[csr.scala 169:49] - node T_5188 = bits(T_5173, 28, 28) @[csr.scala 169:49] - T_5154.fullreset <= T_5188 @[csr.scala 169:49] - node T_5189 = bits(T_5173, 29, 29) @[csr.scala 169:49] - T_5154.ndreset <= T_5189 @[csr.scala 169:49] - node T_5190 = bits(T_5173, 31, 30) @[csr.scala 169:49] - T_5154.xdebugver <= T_5190 @[csr.scala 169:49] - wire reset_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} + T_5173 <= UInt<1>("h0") + node T_5174 = bits(T_5173, 1, 0) + T_5154.prv <= T_5174 + node T_5175 = bits(T_5173, 2, 2) + T_5154.step <= T_5175 + node T_5176 = bits(T_5173, 3, 3) + T_5154.halt <= T_5176 + node T_5177 = bits(T_5173, 4, 4) + T_5154.zero1 <= T_5177 + node T_5178 = bits(T_5173, 5, 5) + T_5154.debugint <= T_5178 + node T_5179 = bits(T_5173, 8, 6) + T_5154.cause <= T_5179 + node T_5180 = bits(T_5173, 9, 9) + T_5154.stoptime <= T_5180 + node T_5181 = bits(T_5173, 10, 10) + T_5154.stopcycle <= T_5181 + node T_5182 = bits(T_5173, 11, 11) + T_5154.zero2 <= T_5182 + node T_5183 = bits(T_5173, 12, 12) + T_5154.ebreaku <= T_5183 + node T_5184 = bits(T_5173, 13, 13) + T_5154.ebreaks <= T_5184 + node T_5185 = bits(T_5173, 14, 14) + T_5154.ebreakh <= T_5185 + node T_5186 = bits(T_5173, 15, 15) + T_5154.ebreakm <= T_5186 + node T_5187 = bits(T_5173, 27, 16) + T_5154.zero3 <= T_5187 + node T_5188 = bits(T_5173, 28, 28) + T_5154.fullreset <= T_5188 + node T_5189 = bits(T_5173, 29, 29) + T_5154.ndreset <= T_5189 + node T_5190 = bits(T_5173, 31, 30) + T_5154.xdebugver <= T_5190 + wire reset_dcsr : { xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} reset_dcsr is invalid reset_dcsr <- T_5154 - reset_dcsr.xdebugver <= UInt<1>("h01") @[csr.scala 170:24] - reset_dcsr.prv <= UInt<2>("h03") @[csr.scala 171:18] - reg reg_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}, clk with : (reset => (reset, reset_dcsr)) - wire T_5256 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[csr.scala 175:43] - T_5256 is invalid @[csr.scala 175:43] + reset_dcsr.xdebugver <= UInt<1>("h1") + reset_dcsr.prv <= UInt<2>("h3") + reg reg_dcsr : { xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}, clk with : + reset => (reset, reset_dcsr) + wire T_5256 : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5256 is invalid wire T_5271 : UInt<13> T_5271 is invalid - T_5271 <= UInt<1>("h00") - node T_5272 = bits(T_5271, 0, 0) @[csr.scala 175:43] - T_5256.usip <= T_5272 @[csr.scala 175:43] - node T_5273 = bits(T_5271, 1, 1) @[csr.scala 175:43] - T_5256.ssip <= T_5273 @[csr.scala 175:43] - node T_5274 = bits(T_5271, 2, 2) @[csr.scala 175:43] - T_5256.hsip <= T_5274 @[csr.scala 175:43] - node T_5275 = bits(T_5271, 3, 3) @[csr.scala 175:43] - T_5256.msip <= T_5275 @[csr.scala 175:43] - node T_5276 = bits(T_5271, 4, 4) @[csr.scala 175:43] - T_5256.utip <= T_5276 @[csr.scala 175:43] - node T_5277 = bits(T_5271, 5, 5) @[csr.scala 175:43] - T_5256.stip <= T_5277 @[csr.scala 175:43] - node T_5278 = bits(T_5271, 6, 6) @[csr.scala 175:43] - T_5256.htip <= T_5278 @[csr.scala 175:43] - node T_5279 = bits(T_5271, 7, 7) @[csr.scala 175:43] - T_5256.mtip <= T_5279 @[csr.scala 175:43] - node T_5280 = bits(T_5271, 8, 8) @[csr.scala 175:43] - T_5256.ueip <= T_5280 @[csr.scala 175:43] - node T_5281 = bits(T_5271, 9, 9) @[csr.scala 175:43] - T_5256.seip <= T_5281 @[csr.scala 175:43] - node T_5282 = bits(T_5271, 10, 10) @[csr.scala 175:43] - T_5256.heip <= T_5282 @[csr.scala 175:43] - node T_5283 = bits(T_5271, 11, 11) @[csr.scala 175:43] - T_5256.meip <= T_5283 @[csr.scala 175:43] - node T_5284 = bits(T_5271, 12, 12) @[csr.scala 175:43] - T_5256.rocc <= T_5284 @[csr.scala 175:43] - wire T_5285 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5271 <= UInt<1>("h0") + node T_5272 = bits(T_5271, 0, 0) + T_5256.usip <= T_5272 + node T_5273 = bits(T_5271, 1, 1) + T_5256.ssip <= T_5273 + node T_5274 = bits(T_5271, 2, 2) + T_5256.hsip <= T_5274 + node T_5275 = bits(T_5271, 3, 3) + T_5256.msip <= T_5275 + node T_5276 = bits(T_5271, 4, 4) + T_5256.utip <= T_5276 + node T_5277 = bits(T_5271, 5, 5) + T_5256.stip <= T_5277 + node T_5278 = bits(T_5271, 6, 6) + T_5256.htip <= T_5278 + node T_5279 = bits(T_5271, 7, 7) + T_5256.mtip <= T_5279 + node T_5280 = bits(T_5271, 8, 8) + T_5256.ueip <= T_5280 + node T_5281 = bits(T_5271, 9, 9) + T_5256.seip <= T_5281 + node T_5282 = bits(T_5271, 10, 10) + T_5256.heip <= T_5282 + node T_5283 = bits(T_5271, 11, 11) + T_5256.meip <= T_5283 + node T_5284 = bits(T_5271, 12, 12) + T_5256.rocc <= T_5284 + wire T_5285 : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5285 is invalid T_5285 <- T_5256 - T_5285.ssip <= UInt<1>("h01") @[csr.scala 176:14] - T_5285.msip <= UInt<1>("h01") @[csr.scala 177:14] - T_5285.stip <= UInt<1>("h01") @[csr.scala 178:14] - T_5285.mtip <= UInt<1>("h01") @[csr.scala 179:14] - T_5285.meip <= UInt<1>("h01") @[csr.scala 180:14] - T_5285.seip <= UInt<1>("h01") @[csr.scala 181:14] - T_5285.rocc <= UInt<1>("h00") @[csr.scala 182:14] - wire T_5306 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5285.ssip <= UInt<1>("h1") + T_5285.msip <= UInt<1>("h1") + T_5285.stip <= UInt<1>("h1") + T_5285.mtip <= UInt<1>("h1") + T_5285.meip <= UInt<1>("h1") + T_5285.seip <= UInt<1>("h1") + T_5285.rocc <= UInt<1>("h0") + wire T_5306 : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5306 is invalid T_5306 <- T_5285 - T_5306.msip <= UInt<1>("h00") @[csr.scala 185:14] - T_5306.mtip <= UInt<1>("h00") @[csr.scala 186:14] - T_5306.meip <= UInt<1>("h00") @[csr.scala 187:14] - node T_5323 = cat(T_5285.hsip, T_5285.ssip) @[csr.scala 189:10] - node T_5324 = cat(T_5323, T_5285.usip) @[csr.scala 189:10] - node T_5325 = cat(T_5285.stip, T_5285.utip) @[csr.scala 189:10] - node T_5326 = cat(T_5325, T_5285.msip) @[csr.scala 189:10] - node T_5327 = cat(T_5326, T_5324) @[csr.scala 189:10] - node T_5328 = cat(T_5285.ueip, T_5285.mtip) @[csr.scala 189:10] - node T_5329 = cat(T_5328, T_5285.htip) @[csr.scala 189:10] - node T_5330 = cat(T_5285.heip, T_5285.seip) @[csr.scala 189:10] - node T_5331 = cat(T_5285.rocc, T_5285.meip) @[csr.scala 189:10] - node T_5332 = cat(T_5331, T_5330) @[csr.scala 189:10] - node T_5333 = cat(T_5332, T_5329) @[csr.scala 189:10] - node supported_interrupts = cat(T_5333, T_5327) @[csr.scala 189:10] - node T_5334 = cat(T_5306.hsip, T_5306.ssip) @[csr.scala 189:22] - node T_5335 = cat(T_5334, T_5306.usip) @[csr.scala 189:22] - node T_5336 = cat(T_5306.stip, T_5306.utip) @[csr.scala 189:22] - node T_5337 = cat(T_5336, T_5306.msip) @[csr.scala 189:22] - node T_5338 = cat(T_5337, T_5335) @[csr.scala 189:22] - node T_5339 = cat(T_5306.ueip, T_5306.mtip) @[csr.scala 189:22] - node T_5340 = cat(T_5339, T_5306.htip) @[csr.scala 189:22] - node T_5341 = cat(T_5306.heip, T_5306.seip) @[csr.scala 189:22] - node T_5342 = cat(T_5306.rocc, T_5306.meip) @[csr.scala 189:22] - node T_5343 = cat(T_5342, T_5341) @[csr.scala 189:22] - node T_5344 = cat(T_5343, T_5340) @[csr.scala 189:22] - node delegable_interrupts = cat(T_5344, T_5338) @[csr.scala 189:22] - node exception = or(io.exception, io.csr_xcpt) @[csr.scala 199:32] - reg reg_debug : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg reg_dpc : UInt<40>, clk - reg reg_dscratch : UInt<64>, clk - reg reg_singleStepped : UInt<1>, clk - node T_5349 = bits(io.retire, 0, 0) @[csr.scala 205:18] - node T_5350 = or(T_5349, exception) @[csr.scala 205:22] - when T_5350 : @[csr.scala 205:36] - reg_singleStepped <= UInt<1>("h01") @[csr.scala 205:56] - skip @[csr.scala 205:36] - node T_5353 = eq(io.singleStep, UInt<1>("h00")) @[csr.scala 206:9] - when T_5353 : @[csr.scala 206:25] - reg_singleStepped <= UInt<1>("h00") @[csr.scala 206:45] - skip @[csr.scala 206:25] - node T_5356 = eq(io.singleStep, UInt<1>("h00")) @[csr.scala 207:10] - node T_5358 = leq(io.retire, UInt<1>("h01")) @[csr.scala 207:38] - node T_5359 = or(T_5356, T_5358) @[csr.scala 207:25] - node T_5360 = or(T_5359, reset) @[csr.scala 207:9] - node T_5362 = eq(T_5360, UInt<1>("h00")) @[csr.scala 207:9] - when T_5362 : @[csr.scala 207:9] - printf(clk, UInt<1>(1), "Assertion failed\n at csr.scala:207 assert(!io.singleStep || io.retire <= UInt(1))\n") @[csr.scala 207:9] - stop(clk, UInt<1>(1), 1) @[csr.scala 207:9] - skip @[csr.scala 207:9] - node T_5364 = eq(reg_singleStepped, UInt<1>("h00")) @[csr.scala 208:10] - node T_5366 = eq(io.retire, UInt<1>("h00")) @[csr.scala 208:42] - node T_5367 = or(T_5364, T_5366) @[csr.scala 208:29] - node T_5368 = or(T_5367, reset) @[csr.scala 208:9] - node T_5370 = eq(T_5368, UInt<1>("h00")) @[csr.scala 208:9] - when T_5370 : @[csr.scala 208:9] - printf(clk, UInt<1>(1), "Assertion failed\n at csr.scala:208 assert(!reg_singleStepped || io.retire === UInt(0))\n") @[csr.scala 208:9] - stop(clk, UInt<1>(1), 1) @[csr.scala 208:9] - skip @[csr.scala 208:9] - reg reg_tselect : UInt<1>, clk - reg reg_bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[2], clk - reg reg_mie : UInt<64>, clk - reg reg_mideleg : UInt<64>, clk - reg reg_medeleg : UInt<64>, clk - reg reg_mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk - reg reg_mepc : UInt<40>, clk - reg reg_mcause : UInt<64>, clk - reg reg_mbadaddr : UInt<40>, clk - reg reg_mscratch : UInt<64>, clk - reg reg_mtvec : UInt<32>, clk with : (reset => (reset, UInt<32>("h01010"))) - reg reg_mucounteren : UInt<32>, clk - reg reg_mscounteren : UInt<32>, clk - reg reg_sepc : UInt<40>, clk - reg reg_scause : UInt<64>, clk - reg reg_sbadaddr : UInt<40>, clk - reg reg_sscratch : UInt<64>, clk - reg reg_stvec : UInt<39>, clk - reg reg_sptbr : {asid : UInt<7>, ppn : UInt<38>}, clk - reg reg_wfi : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg reg_fflags : UInt<5>, clk - reg reg_frm : UInt<3>, clk - reg T_5600 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_5601 = add(T_5600, io.retire) @[util.scala 135:33] - T_5600 <= T_5601 @[util.scala 136:9] - reg T_5603 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_5604 = bits(T_5601, 6, 6) @[util.scala 140:20] - when T_5604 : @[util.scala 140:34] - node T_5606 = add(T_5603, UInt<1>("h01")) @[util.scala 140:43] - node T_5607 = tail(T_5606, 1) @[util.scala 140:43] - T_5603 <= T_5607 @[util.scala 140:38] - skip @[util.scala 140:34] - node T_5608 = cat(T_5603, T_5600) @[Cat.scala 20:58] - reg T_5611 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_5612 = add(T_5611, UInt<1>("h01")) @[util.scala 135:33] - T_5611 <= T_5612 @[util.scala 136:9] - reg T_5614 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) - node T_5615 = bits(T_5612, 6, 6) @[util.scala 140:20] - when T_5615 : @[util.scala 140:34] - node T_5617 = add(T_5614, UInt<1>("h01")) @[util.scala 140:43] - node T_5618 = tail(T_5617, 1) @[util.scala 140:43] - T_5614 <= T_5618 @[util.scala 140:38] - skip @[util.scala 140:34] - node T_5619 = cat(T_5614, T_5611) @[Cat.scala 20:58] - wire mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5306.msip <= UInt<1>("h0") + T_5306.mtip <= UInt<1>("h0") + T_5306.meip <= UInt<1>("h0") + node T_5323 = cat(T_5285.hsip, T_5285.ssip) + node T_5324 = cat(T_5323, T_5285.usip) + node T_5325 = cat(T_5285.stip, T_5285.utip) + node T_5326 = cat(T_5325, T_5285.msip) + node T_5327 = cat(T_5326, T_5324) + node T_5328 = cat(T_5285.ueip, T_5285.mtip) + node T_5329 = cat(T_5328, T_5285.htip) + node T_5330 = cat(T_5285.heip, T_5285.seip) + node T_5331 = cat(T_5285.rocc, T_5285.meip) + node T_5332 = cat(T_5331, T_5330) + node T_5333 = cat(T_5332, T_5329) + node supported_interrupts = cat(T_5333, T_5327) + node T_5334 = cat(T_5306.hsip, T_5306.ssip) + node T_5335 = cat(T_5334, T_5306.usip) + node T_5336 = cat(T_5306.stip, T_5306.utip) + node T_5337 = cat(T_5336, T_5306.msip) + node T_5338 = cat(T_5337, T_5335) + node T_5339 = cat(T_5306.ueip, T_5306.mtip) + node T_5340 = cat(T_5339, T_5306.htip) + node T_5341 = cat(T_5306.heip, T_5306.seip) + node T_5342 = cat(T_5306.rocc, T_5306.meip) + node T_5343 = cat(T_5342, T_5341) + node T_5344 = cat(T_5343, T_5340) + node delegable_interrupts = cat(T_5344, T_5338) + node exception = or(io.exception, io.csr_xcpt) + reg reg_debug : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg reg_dpc : UInt<40>, clk with : + reset => (UInt<1>("h0"), reg_dpc) + reg reg_dscratch : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_dscratch) + reg reg_singleStepped : UInt<1>, clk with : + reset => (UInt<1>("h0"), reg_singleStepped) + node T_5349 = bits(io.retire, 0, 0) + node T_5350 = or(T_5349, exception) + when T_5350 : + reg_singleStepped <= UInt<1>("h1") + node T_5353 = eq(io.singleStep, UInt<1>("h0")) + when T_5353 : + reg_singleStepped <= UInt<1>("h0") + node T_5356 = eq(io.singleStep, UInt<1>("h0")) + node T_5358 = leq(io.retire, UInt<1>("h1")) + node T_5359 = or(T_5356, T_5358) + node T_5360 = or(T_5359, reset) + node T_5362 = eq(T_5360, UInt<1>("h0")) + when T_5362 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at csr.scala:207 assert(!io.singleStep || io.retire <= UInt(1))\n") + stop(clk, UInt<1>("h1"), 1) + node T_5364 = eq(reg_singleStepped, UInt<1>("h0")) + node T_5366 = eq(io.retire, UInt<1>("h0")) + node T_5367 = or(T_5364, T_5366) + node T_5368 = or(T_5367, reset) + node T_5370 = eq(T_5368, UInt<1>("h0")) + when T_5370 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at csr.scala:208 assert(!reg_singleStepped || io.retire === UInt(0))\n") + stop(clk, UInt<1>("h1"), 1) + reg reg_tselect : UInt<1>, clk with : + reset => (UInt<1>("h0"), reg_tselect) + reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[2], clk with : + reset => (UInt<1>("h0"), reg_bp) + reg reg_mie : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_mie) + reg reg_mideleg : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_mideleg) + reg reg_medeleg : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_medeleg) + reg reg_mip : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : + reset => (UInt<1>("h0"), reg_mip) + reg reg_mepc : UInt<40>, clk with : + reset => (UInt<1>("h0"), reg_mepc) + reg reg_mcause : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_mcause) + reg reg_mbadaddr : UInt<40>, clk with : + reset => (UInt<1>("h0"), reg_mbadaddr) + reg reg_mscratch : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_mscratch) + reg reg_mtvec : UInt<32>, clk with : + reset => (reset, UInt<32>("h1010")) + reg reg_mucounteren : UInt<32>, clk with : + reset => (UInt<1>("h0"), reg_mucounteren) + reg reg_mscounteren : UInt<32>, clk with : + reset => (UInt<1>("h0"), reg_mscounteren) + reg reg_sepc : UInt<40>, clk with : + reset => (UInt<1>("h0"), reg_sepc) + reg reg_scause : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_scause) + reg reg_sbadaddr : UInt<40>, clk with : + reset => (UInt<1>("h0"), reg_sbadaddr) + reg reg_sscratch : UInt<64>, clk with : + reset => (UInt<1>("h0"), reg_sscratch) + reg reg_stvec : UInt<39>, clk with : + reset => (UInt<1>("h0"), reg_stvec) + reg reg_sptbr : { asid : UInt<7>, ppn : UInt<38>}, clk with : + reset => (UInt<1>("h0"), reg_sptbr) + reg reg_wfi : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg reg_fflags : UInt<5>, clk with : + reset => (UInt<1>("h0"), reg_fflags) + reg reg_frm : UInt<3>, clk with : + reset => (UInt<1>("h0"), reg_frm) + reg T_5600 : UInt<6>, clk with : + reset => (reset, UInt<6>("h0")) + node T_5601 = add(T_5600, io.retire) + T_5600 <= T_5601 + reg T_5603 : UInt<58>, clk with : + reset => (reset, UInt<58>("h0")) + node T_5604 = bits(T_5601, 6, 6) + when T_5604 : + node T_5606 = add(T_5603, UInt<1>("h1")) + node T_5607 = tail(T_5606, 1) + T_5603 <= T_5607 + node T_5608 = cat(T_5603, T_5600) + reg T_5611 : UInt<6>, clk with : + reset => (reset, UInt<6>("h0")) + node T_5612 = add(T_5611, UInt<1>("h1")) + T_5611 <= T_5612 + reg T_5614 : UInt<58>, clk with : + reset => (reset, UInt<58>("h0")) + node T_5615 = bits(T_5612, 6, 6) + when T_5615 : + node T_5617 = add(T_5614, UInt<1>("h1")) + node T_5618 = tail(T_5617, 1) + T_5614 <= T_5618 + node T_5619 = cat(T_5614, T_5611) + wire mip : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} mip is invalid mip <- reg_mip - mip.rocc <= io.rocc.interrupt @[csr.scala 243:12] - node T_5633 = cat(mip.hsip, mip.ssip) @[csr.scala 244:22] - node T_5634 = cat(T_5633, mip.usip) @[csr.scala 244:22] - node T_5635 = cat(mip.stip, mip.utip) @[csr.scala 244:22] - node T_5636 = cat(T_5635, mip.msip) @[csr.scala 244:22] - node T_5637 = cat(T_5636, T_5634) @[csr.scala 244:22] - node T_5638 = cat(mip.ueip, mip.mtip) @[csr.scala 244:22] - node T_5639 = cat(T_5638, mip.htip) @[csr.scala 244:22] - node T_5640 = cat(mip.heip, mip.seip) @[csr.scala 244:22] - node T_5641 = cat(mip.rocc, mip.meip) @[csr.scala 244:22] - node T_5642 = cat(T_5641, T_5640) @[csr.scala 244:22] - node T_5643 = cat(T_5642, T_5639) @[csr.scala 244:22] - node T_5644 = cat(T_5643, T_5637) @[csr.scala 244:22] - node read_mip = and(T_5644, supported_interrupts) @[csr.scala 244:29] - node pending_interrupts = and(read_mip, reg_mie) @[csr.scala 246:37] - node T_5646 = eq(reg_debug, UInt<1>("h00")) @[csr.scala 247:26] - node T_5648 = lt(reg_mstatus.prv, UInt<2>("h03")) @[csr.scala 247:57] - node T_5650 = eq(reg_mstatus.prv, UInt<2>("h03")) @[csr.scala 247:85] - node T_5651 = and(T_5650, reg_mstatus.mie) @[csr.scala 247:95] - node T_5652 = or(T_5648, T_5651) @[csr.scala 247:65] - node T_5653 = and(T_5646, T_5652) @[csr.scala 247:37] - node T_5654 = not(reg_mideleg) @[csr.scala 247:138] - node T_5655 = and(pending_interrupts, T_5654) @[csr.scala 247:136] - node m_interrupts = mux(T_5653, T_5655, UInt<1>("h00")) @[csr.scala 247:25] - node T_5658 = eq(reg_debug, UInt<1>("h00")) @[csr.scala 248:26] - node T_5660 = lt(reg_mstatus.prv, UInt<1>("h01")) @[csr.scala 248:57] - node T_5662 = eq(reg_mstatus.prv, UInt<1>("h01")) @[csr.scala 248:85] - node T_5663 = and(T_5662, reg_mstatus.sie) @[csr.scala 248:95] - node T_5664 = or(T_5660, T_5663) @[csr.scala 248:65] - node T_5665 = and(T_5658, T_5664) @[csr.scala 248:37] - node T_5666 = and(pending_interrupts, reg_mideleg) @[csr.scala 248:136] - node s_interrupts = mux(T_5665, T_5666, UInt<1>("h00")) @[csr.scala 248:25] - node all_interrupts = or(m_interrupts, s_interrupts) @[csr.scala 249:37] - node T_5669 = bits(all_interrupts, 0, 0) @[OneHot.scala 35:40] - node T_5670 = bits(all_interrupts, 1, 1) @[OneHot.scala 35:40] - node T_5671 = bits(all_interrupts, 2, 2) @[OneHot.scala 35:40] - node T_5672 = bits(all_interrupts, 3, 3) @[OneHot.scala 35:40] - node T_5673 = bits(all_interrupts, 4, 4) @[OneHot.scala 35:40] - node T_5674 = bits(all_interrupts, 5, 5) @[OneHot.scala 35:40] - node T_5675 = bits(all_interrupts, 6, 6) @[OneHot.scala 35:40] - node T_5676 = bits(all_interrupts, 7, 7) @[OneHot.scala 35:40] - node T_5677 = bits(all_interrupts, 8, 8) @[OneHot.scala 35:40] - node T_5678 = bits(all_interrupts, 9, 9) @[OneHot.scala 35:40] - node T_5679 = bits(all_interrupts, 10, 10) @[OneHot.scala 35:40] - node T_5680 = bits(all_interrupts, 11, 11) @[OneHot.scala 35:40] - node T_5681 = bits(all_interrupts, 12, 12) @[OneHot.scala 35:40] - node T_5682 = bits(all_interrupts, 13, 13) @[OneHot.scala 35:40] - node T_5683 = bits(all_interrupts, 14, 14) @[OneHot.scala 35:40] - node T_5684 = bits(all_interrupts, 15, 15) @[OneHot.scala 35:40] - node T_5685 = bits(all_interrupts, 16, 16) @[OneHot.scala 35:40] - node T_5686 = bits(all_interrupts, 17, 17) @[OneHot.scala 35:40] - node T_5687 = bits(all_interrupts, 18, 18) @[OneHot.scala 35:40] - node T_5688 = bits(all_interrupts, 19, 19) @[OneHot.scala 35:40] - node T_5689 = bits(all_interrupts, 20, 20) @[OneHot.scala 35:40] - node T_5690 = bits(all_interrupts, 21, 21) @[OneHot.scala 35:40] - node T_5691 = bits(all_interrupts, 22, 22) @[OneHot.scala 35:40] - node T_5692 = bits(all_interrupts, 23, 23) @[OneHot.scala 35:40] - node T_5693 = bits(all_interrupts, 24, 24) @[OneHot.scala 35:40] - node T_5694 = bits(all_interrupts, 25, 25) @[OneHot.scala 35:40] - node T_5695 = bits(all_interrupts, 26, 26) @[OneHot.scala 35:40] - node T_5696 = bits(all_interrupts, 27, 27) @[OneHot.scala 35:40] - node T_5697 = bits(all_interrupts, 28, 28) @[OneHot.scala 35:40] - node T_5698 = bits(all_interrupts, 29, 29) @[OneHot.scala 35:40] - node T_5699 = bits(all_interrupts, 30, 30) @[OneHot.scala 35:40] - node T_5700 = bits(all_interrupts, 31, 31) @[OneHot.scala 35:40] - node T_5701 = bits(all_interrupts, 32, 32) @[OneHot.scala 35:40] - node T_5702 = bits(all_interrupts, 33, 33) @[OneHot.scala 35:40] - node T_5703 = bits(all_interrupts, 34, 34) @[OneHot.scala 35:40] - node T_5704 = bits(all_interrupts, 35, 35) @[OneHot.scala 35:40] - node T_5705 = bits(all_interrupts, 36, 36) @[OneHot.scala 35:40] - node T_5706 = bits(all_interrupts, 37, 37) @[OneHot.scala 35:40] - node T_5707 = bits(all_interrupts, 38, 38) @[OneHot.scala 35:40] - node T_5708 = bits(all_interrupts, 39, 39) @[OneHot.scala 35:40] - node T_5709 = bits(all_interrupts, 40, 40) @[OneHot.scala 35:40] - node T_5710 = bits(all_interrupts, 41, 41) @[OneHot.scala 35:40] - node T_5711 = bits(all_interrupts, 42, 42) @[OneHot.scala 35:40] - node T_5712 = bits(all_interrupts, 43, 43) @[OneHot.scala 35:40] - node T_5713 = bits(all_interrupts, 44, 44) @[OneHot.scala 35:40] - node T_5714 = bits(all_interrupts, 45, 45) @[OneHot.scala 35:40] - node T_5715 = bits(all_interrupts, 46, 46) @[OneHot.scala 35:40] - node T_5716 = bits(all_interrupts, 47, 47) @[OneHot.scala 35:40] - node T_5717 = bits(all_interrupts, 48, 48) @[OneHot.scala 35:40] - node T_5718 = bits(all_interrupts, 49, 49) @[OneHot.scala 35:40] - node T_5719 = bits(all_interrupts, 50, 50) @[OneHot.scala 35:40] - node T_5720 = bits(all_interrupts, 51, 51) @[OneHot.scala 35:40] - node T_5721 = bits(all_interrupts, 52, 52) @[OneHot.scala 35:40] - node T_5722 = bits(all_interrupts, 53, 53) @[OneHot.scala 35:40] - node T_5723 = bits(all_interrupts, 54, 54) @[OneHot.scala 35:40] - node T_5724 = bits(all_interrupts, 55, 55) @[OneHot.scala 35:40] - node T_5725 = bits(all_interrupts, 56, 56) @[OneHot.scala 35:40] - node T_5726 = bits(all_interrupts, 57, 57) @[OneHot.scala 35:40] - node T_5727 = bits(all_interrupts, 58, 58) @[OneHot.scala 35:40] - node T_5728 = bits(all_interrupts, 59, 59) @[OneHot.scala 35:40] - node T_5729 = bits(all_interrupts, 60, 60) @[OneHot.scala 35:40] - node T_5730 = bits(all_interrupts, 61, 61) @[OneHot.scala 35:40] - node T_5731 = bits(all_interrupts, 62, 62) @[OneHot.scala 35:40] - node T_5732 = bits(all_interrupts, 63, 63) @[OneHot.scala 35:40] - node T_5797 = mux(T_5731, UInt<6>("h03e"), UInt<6>("h03f")) @[Mux.scala 31:69] - node T_5798 = mux(T_5730, UInt<6>("h03d"), T_5797) @[Mux.scala 31:69] - node T_5799 = mux(T_5729, UInt<6>("h03c"), T_5798) @[Mux.scala 31:69] - node T_5800 = mux(T_5728, UInt<6>("h03b"), T_5799) @[Mux.scala 31:69] - node T_5801 = mux(T_5727, UInt<6>("h03a"), T_5800) @[Mux.scala 31:69] - node T_5802 = mux(T_5726, UInt<6>("h039"), T_5801) @[Mux.scala 31:69] - node T_5803 = mux(T_5725, UInt<6>("h038"), T_5802) @[Mux.scala 31:69] - node T_5804 = mux(T_5724, UInt<6>("h037"), T_5803) @[Mux.scala 31:69] - node T_5805 = mux(T_5723, UInt<6>("h036"), T_5804) @[Mux.scala 31:69] - node T_5806 = mux(T_5722, UInt<6>("h035"), T_5805) @[Mux.scala 31:69] - node T_5807 = mux(T_5721, UInt<6>("h034"), T_5806) @[Mux.scala 31:69] - node T_5808 = mux(T_5720, UInt<6>("h033"), T_5807) @[Mux.scala 31:69] - node T_5809 = mux(T_5719, UInt<6>("h032"), T_5808) @[Mux.scala 31:69] - node T_5810 = mux(T_5718, UInt<6>("h031"), T_5809) @[Mux.scala 31:69] - node T_5811 = mux(T_5717, UInt<6>("h030"), T_5810) @[Mux.scala 31:69] - node T_5812 = mux(T_5716, UInt<6>("h02f"), T_5811) @[Mux.scala 31:69] - node T_5813 = mux(T_5715, UInt<6>("h02e"), T_5812) @[Mux.scala 31:69] - node T_5814 = mux(T_5714, UInt<6>("h02d"), T_5813) @[Mux.scala 31:69] - node T_5815 = mux(T_5713, UInt<6>("h02c"), T_5814) @[Mux.scala 31:69] - node T_5816 = mux(T_5712, UInt<6>("h02b"), T_5815) @[Mux.scala 31:69] - node T_5817 = mux(T_5711, UInt<6>("h02a"), T_5816) @[Mux.scala 31:69] - node T_5818 = mux(T_5710, UInt<6>("h029"), T_5817) @[Mux.scala 31:69] - node T_5819 = mux(T_5709, UInt<6>("h028"), T_5818) @[Mux.scala 31:69] - node T_5820 = mux(T_5708, UInt<6>("h027"), T_5819) @[Mux.scala 31:69] - node T_5821 = mux(T_5707, UInt<6>("h026"), T_5820) @[Mux.scala 31:69] - node T_5822 = mux(T_5706, UInt<6>("h025"), T_5821) @[Mux.scala 31:69] - node T_5823 = mux(T_5705, UInt<6>("h024"), T_5822) @[Mux.scala 31:69] - node T_5824 = mux(T_5704, UInt<6>("h023"), T_5823) @[Mux.scala 31:69] - node T_5825 = mux(T_5703, UInt<6>("h022"), T_5824) @[Mux.scala 31:69] - node T_5826 = mux(T_5702, UInt<6>("h021"), T_5825) @[Mux.scala 31:69] - node T_5827 = mux(T_5701, UInt<6>("h020"), T_5826) @[Mux.scala 31:69] - node T_5828 = mux(T_5700, UInt<5>("h01f"), T_5827) @[Mux.scala 31:69] - node T_5829 = mux(T_5699, UInt<5>("h01e"), T_5828) @[Mux.scala 31:69] - node T_5830 = mux(T_5698, UInt<5>("h01d"), T_5829) @[Mux.scala 31:69] - node T_5831 = mux(T_5697, UInt<5>("h01c"), T_5830) @[Mux.scala 31:69] - node T_5832 = mux(T_5696, UInt<5>("h01b"), T_5831) @[Mux.scala 31:69] - node T_5833 = mux(T_5695, UInt<5>("h01a"), T_5832) @[Mux.scala 31:69] - node T_5834 = mux(T_5694, UInt<5>("h019"), T_5833) @[Mux.scala 31:69] - node T_5835 = mux(T_5693, UInt<5>("h018"), T_5834) @[Mux.scala 31:69] - node T_5836 = mux(T_5692, UInt<5>("h017"), T_5835) @[Mux.scala 31:69] - node T_5837 = mux(T_5691, UInt<5>("h016"), T_5836) @[Mux.scala 31:69] - node T_5838 = mux(T_5690, UInt<5>("h015"), T_5837) @[Mux.scala 31:69] - node T_5839 = mux(T_5689, UInt<5>("h014"), T_5838) @[Mux.scala 31:69] - node T_5840 = mux(T_5688, UInt<5>("h013"), T_5839) @[Mux.scala 31:69] - node T_5841 = mux(T_5687, UInt<5>("h012"), T_5840) @[Mux.scala 31:69] - node T_5842 = mux(T_5686, UInt<5>("h011"), T_5841) @[Mux.scala 31:69] - node T_5843 = mux(T_5685, UInt<5>("h010"), T_5842) @[Mux.scala 31:69] - node T_5844 = mux(T_5684, UInt<4>("h0f"), T_5843) @[Mux.scala 31:69] - node T_5845 = mux(T_5683, UInt<4>("h0e"), T_5844) @[Mux.scala 31:69] - node T_5846 = mux(T_5682, UInt<4>("h0d"), T_5845) @[Mux.scala 31:69] - node T_5847 = mux(T_5681, UInt<4>("h0c"), T_5846) @[Mux.scala 31:69] - node T_5848 = mux(T_5680, UInt<4>("h0b"), T_5847) @[Mux.scala 31:69] - node T_5849 = mux(T_5679, UInt<4>("h0a"), T_5848) @[Mux.scala 31:69] - node T_5850 = mux(T_5678, UInt<4>("h09"), T_5849) @[Mux.scala 31:69] - node T_5851 = mux(T_5677, UInt<4>("h08"), T_5850) @[Mux.scala 31:69] - node T_5852 = mux(T_5676, UInt<3>("h07"), T_5851) @[Mux.scala 31:69] - node T_5853 = mux(T_5675, UInt<3>("h06"), T_5852) @[Mux.scala 31:69] - node T_5854 = mux(T_5674, UInt<3>("h05"), T_5853) @[Mux.scala 31:69] - node T_5855 = mux(T_5673, UInt<3>("h04"), T_5854) @[Mux.scala 31:69] - node T_5856 = mux(T_5672, UInt<2>("h03"), T_5855) @[Mux.scala 31:69] - node T_5857 = mux(T_5671, UInt<2>("h02"), T_5856) @[Mux.scala 31:69] - node T_5858 = mux(T_5670, UInt<1>("h01"), T_5857) @[Mux.scala 31:69] - node T_5859 = mux(T_5669, UInt<1>("h00"), T_5858) @[Mux.scala 31:69] - node T_5860 = add(UInt<64>("h08000000000000000"), T_5859) @[csr.scala 251:37] - node interruptCause = tail(T_5860, 1) @[csr.scala 251:37] - node T_5862 = neq(all_interrupts, UInt<1>("h00")) @[csr.scala 252:34] - node T_5864 = eq(io.singleStep, UInt<1>("h00")) @[csr.scala 252:41] - node T_5865 = and(T_5862, T_5864) @[csr.scala 252:38] - node T_5866 = or(T_5865, reg_singleStepped) @[csr.scala 252:56] - io.interrupt <= T_5866 @[csr.scala 252:16] - io.interrupt_cause <= interruptCause @[csr.scala 253:22] - io.bp[0] <- reg_bp[0] @[csr.scala 254:9] - node T_5868 = and(UInt<1>("h01"), reg_dcsr.debugint) @[csr.scala 257:26] - node T_5870 = eq(reg_debug, UInt<1>("h00")) @[csr.scala 257:50] - node T_5871 = and(T_5868, T_5870) @[csr.scala 257:47] - when T_5871 : @[csr.scala 257:62] - io.interrupt <= UInt<1>("h01") @[csr.scala 258:18] - io.interrupt_cause <= UInt<64>("h0800000000000000d") @[csr.scala 259:24] - skip @[csr.scala 257:62] - node system_insn = eq(io.rw.cmd, UInt<3>("h04")) @[csr.scala 262:31] - node T_5874 = neq(io.rw.cmd, UInt<3>("h00")) @[csr.scala 263:27] - node T_5876 = eq(system_insn, UInt<1>("h00")) @[csr.scala 263:40] - node cpu_ren = and(T_5874, T_5876) @[csr.scala 263:37] - node T_5877 = neq(io.rw.cmd, UInt<3>("h05")) @[csr.scala 264:38] - node cpu_wen = and(cpu_ren, T_5877) @[csr.scala 264:25] - reg reg_misa : UInt, clk with : (reset => (reset, UInt<64>("h0800000000014112d"))) - node T_5879 = cat(io.status.hie, io.status.sie) @[csr.scala 278:38] - node T_5880 = cat(T_5879, io.status.uie) @[csr.scala 278:38] - node T_5881 = cat(io.status.spie, io.status.upie) @[csr.scala 278:38] - node T_5882 = cat(T_5881, io.status.mie) @[csr.scala 278:38] - node T_5883 = cat(T_5882, T_5880) @[csr.scala 278:38] - node T_5884 = cat(io.status.spp, io.status.mpie) @[csr.scala 278:38] - node T_5885 = cat(T_5884, io.status.hpie) @[csr.scala 278:38] - node T_5886 = cat(io.status.fs, io.status.mpp) @[csr.scala 278:38] - node T_5887 = cat(T_5886, io.status.hpp) @[csr.scala 278:38] - node T_5888 = cat(T_5887, T_5885) @[csr.scala 278:38] - node T_5889 = cat(T_5888, T_5883) @[csr.scala 278:38] - node T_5890 = cat(io.status.pum, io.status.mprv) @[csr.scala 278:38] - node T_5891 = cat(T_5890, io.status.xs) @[csr.scala 278:38] - node T_5892 = cat(io.status.vm, io.status.zero1) @[csr.scala 278:38] - node T_5893 = cat(T_5892, io.status.mxr) @[csr.scala 278:38] - node T_5894 = cat(T_5893, T_5891) @[csr.scala 278:38] - node T_5895 = cat(io.status.zero3, io.status.sd_rv32) @[csr.scala 278:38] - node T_5896 = cat(T_5895, io.status.zero2) @[csr.scala 278:38] - node T_5897 = cat(io.status.prv, io.status.sd) @[csr.scala 278:38] - node T_5898 = cat(io.status.debug, io.status.isa) @[csr.scala 278:38] - node T_5899 = cat(T_5898, T_5897) @[csr.scala 278:38] - node T_5900 = cat(T_5899, T_5896) @[csr.scala 278:38] - node T_5901 = cat(T_5900, T_5894) @[csr.scala 278:38] - node T_5902 = cat(T_5901, T_5889) @[csr.scala 278:38] - node read_mstatus = bits(T_5902, 63, 0) @[csr.scala 278:40] - node T_5920 = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) @[csr.scala 282:48] - node T_5921 = cat(T_5920, reg_bp[reg_tselect].control.r) @[csr.scala 282:48] - node T_5922 = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) @[csr.scala 282:48] - node T_5923 = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) @[csr.scala 282:48] - node T_5924 = cat(T_5923, T_5922) @[csr.scala 282:48] - node T_5925 = cat(T_5924, T_5921) @[csr.scala 282:48] - node T_5926 = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) @[csr.scala 282:48] - node T_5927 = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) @[csr.scala 282:48] - node T_5928 = cat(T_5927, T_5926) @[csr.scala 282:48] - node T_5929 = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) @[csr.scala 282:48] - node T_5930 = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) @[csr.scala 282:48] - node T_5931 = cat(T_5930, T_5929) @[csr.scala 282:48] - node T_5932 = cat(T_5931, T_5928) @[csr.scala 282:48] - node T_5933 = cat(T_5932, T_5925) @[csr.scala 282:48] - node T_5951 = bits(reg_bp[reg_tselect].address, 38, 38) @[util.scala 21:38] - node T_5952 = bits(T_5951, 0, 0) @[Bitwise.scala 33:15] - node T_5955 = mux(T_5952, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 33:12] - node T_5956 = cat(T_5955, reg_bp[reg_tselect].address) @[Cat.scala 20:58] - node T_5960 = bits(reg_mepc, 39, 39) @[util.scala 21:38] - node T_5961 = bits(T_5960, 0, 0) @[Bitwise.scala 33:15] - node T_5964 = mux(T_5961, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12] - node T_5965 = cat(T_5964, reg_mepc) @[Cat.scala 20:58] - node T_5966 = bits(reg_mbadaddr, 39, 39) @[util.scala 21:38] - node T_5967 = bits(T_5966, 0, 0) @[Bitwise.scala 33:15] - node T_5970 = mux(T_5967, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12] - node T_5971 = cat(T_5970, reg_mbadaddr) @[Cat.scala 20:58] - node T_5972 = cat(reg_dcsr.step, reg_dcsr.prv) @[csr.scala 303:27] - node T_5973 = cat(reg_dcsr.zero1, reg_dcsr.halt) @[csr.scala 303:27] - node T_5974 = cat(T_5973, T_5972) @[csr.scala 303:27] - node T_5975 = cat(reg_dcsr.cause, reg_dcsr.debugint) @[csr.scala 303:27] - node T_5976 = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) @[csr.scala 303:27] - node T_5977 = cat(T_5976, T_5975) @[csr.scala 303:27] - node T_5978 = cat(T_5977, T_5974) @[csr.scala 303:27] - node T_5979 = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) @[csr.scala 303:27] - node T_5980 = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) @[csr.scala 303:27] - node T_5981 = cat(T_5980, T_5979) @[csr.scala 303:27] - node T_5982 = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) @[csr.scala 303:27] - node T_5983 = cat(reg_dcsr.xdebugver, reg_dcsr.ndreset) @[csr.scala 303:27] - node T_5984 = cat(T_5983, reg_dcsr.fullreset) @[csr.scala 303:27] - node T_5985 = cat(T_5984, T_5982) @[csr.scala 303:27] - node T_5986 = cat(T_5985, T_5981) @[csr.scala 303:27] - node T_5987 = cat(T_5986, T_5978) @[csr.scala 303:27] - node T_5988 = cat(reg_frm, reg_fflags) @[Cat.scala 20:58] - node T_5991 = and(reg_mie, reg_mideleg) @[csr.scala 326:28] - node T_5992 = and(read_mip, reg_mideleg) @[csr.scala 327:29] - wire T_5993 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + mip.rocc <= io.rocc.interrupt + node T_5633 = cat(mip.hsip, mip.ssip) + node T_5634 = cat(T_5633, mip.usip) + node T_5635 = cat(mip.stip, mip.utip) + node T_5636 = cat(T_5635, mip.msip) + node T_5637 = cat(T_5636, T_5634) + node T_5638 = cat(mip.ueip, mip.mtip) + node T_5639 = cat(T_5638, mip.htip) + node T_5640 = cat(mip.heip, mip.seip) + node T_5641 = cat(mip.rocc, mip.meip) + node T_5642 = cat(T_5641, T_5640) + node T_5643 = cat(T_5642, T_5639) + node T_5644 = cat(T_5643, T_5637) + node read_mip = and(T_5644, supported_interrupts) + node pending_interrupts = and(read_mip, reg_mie) + node T_5646 = eq(reg_debug, UInt<1>("h0")) + node T_5648 = lt(reg_mstatus.prv, UInt<2>("h3")) + node T_5650 = eq(reg_mstatus.prv, UInt<2>("h3")) + node T_5651 = and(T_5650, reg_mstatus.mie) + node T_5652 = or(T_5648, T_5651) + node T_5653 = and(T_5646, T_5652) + node T_5654 = not(reg_mideleg) + node T_5655 = and(pending_interrupts, T_5654) + node m_interrupts = mux(T_5653, T_5655, UInt<1>("h0")) + node T_5658 = eq(reg_debug, UInt<1>("h0")) + node T_5660 = lt(reg_mstatus.prv, UInt<1>("h1")) + node T_5662 = eq(reg_mstatus.prv, UInt<1>("h1")) + node T_5663 = and(T_5662, reg_mstatus.sie) + node T_5664 = or(T_5660, T_5663) + node T_5665 = and(T_5658, T_5664) + node T_5666 = and(pending_interrupts, reg_mideleg) + node s_interrupts = mux(T_5665, T_5666, UInt<1>("h0")) + node all_interrupts = or(m_interrupts, s_interrupts) + node T_5669 = bits(all_interrupts, 0, 0) + node T_5670 = bits(all_interrupts, 1, 1) + node T_5671 = bits(all_interrupts, 2, 2) + node T_5672 = bits(all_interrupts, 3, 3) + node T_5673 = bits(all_interrupts, 4, 4) + node T_5674 = bits(all_interrupts, 5, 5) + node T_5675 = bits(all_interrupts, 6, 6) + node T_5676 = bits(all_interrupts, 7, 7) + node T_5677 = bits(all_interrupts, 8, 8) + node T_5678 = bits(all_interrupts, 9, 9) + node T_5679 = bits(all_interrupts, 10, 10) + node T_5680 = bits(all_interrupts, 11, 11) + node T_5681 = bits(all_interrupts, 12, 12) + node T_5682 = bits(all_interrupts, 13, 13) + node T_5683 = bits(all_interrupts, 14, 14) + node T_5684 = bits(all_interrupts, 15, 15) + node T_5685 = bits(all_interrupts, 16, 16) + node T_5686 = bits(all_interrupts, 17, 17) + node T_5687 = bits(all_interrupts, 18, 18) + node T_5688 = bits(all_interrupts, 19, 19) + node T_5689 = bits(all_interrupts, 20, 20) + node T_5690 = bits(all_interrupts, 21, 21) + node T_5691 = bits(all_interrupts, 22, 22) + node T_5692 = bits(all_interrupts, 23, 23) + node T_5693 = bits(all_interrupts, 24, 24) + node T_5694 = bits(all_interrupts, 25, 25) + node T_5695 = bits(all_interrupts, 26, 26) + node T_5696 = bits(all_interrupts, 27, 27) + node T_5697 = bits(all_interrupts, 28, 28) + node T_5698 = bits(all_interrupts, 29, 29) + node T_5699 = bits(all_interrupts, 30, 30) + node T_5700 = bits(all_interrupts, 31, 31) + node T_5701 = bits(all_interrupts, 32, 32) + node T_5702 = bits(all_interrupts, 33, 33) + node T_5703 = bits(all_interrupts, 34, 34) + node T_5704 = bits(all_interrupts, 35, 35) + node T_5705 = bits(all_interrupts, 36, 36) + node T_5706 = bits(all_interrupts, 37, 37) + node T_5707 = bits(all_interrupts, 38, 38) + node T_5708 = bits(all_interrupts, 39, 39) + node T_5709 = bits(all_interrupts, 40, 40) + node T_5710 = bits(all_interrupts, 41, 41) + node T_5711 = bits(all_interrupts, 42, 42) + node T_5712 = bits(all_interrupts, 43, 43) + node T_5713 = bits(all_interrupts, 44, 44) + node T_5714 = bits(all_interrupts, 45, 45) + node T_5715 = bits(all_interrupts, 46, 46) + node T_5716 = bits(all_interrupts, 47, 47) + node T_5717 = bits(all_interrupts, 48, 48) + node T_5718 = bits(all_interrupts, 49, 49) + node T_5719 = bits(all_interrupts, 50, 50) + node T_5720 = bits(all_interrupts, 51, 51) + node T_5721 = bits(all_interrupts, 52, 52) + node T_5722 = bits(all_interrupts, 53, 53) + node T_5723 = bits(all_interrupts, 54, 54) + node T_5724 = bits(all_interrupts, 55, 55) + node T_5725 = bits(all_interrupts, 56, 56) + node T_5726 = bits(all_interrupts, 57, 57) + node T_5727 = bits(all_interrupts, 58, 58) + node T_5728 = bits(all_interrupts, 59, 59) + node T_5729 = bits(all_interrupts, 60, 60) + node T_5730 = bits(all_interrupts, 61, 61) + node T_5731 = bits(all_interrupts, 62, 62) + node T_5732 = bits(all_interrupts, 63, 63) + node T_5797 = mux(T_5731, UInt<6>("h3e"), UInt<6>("h3f")) + node T_5798 = mux(T_5730, UInt<6>("h3d"), T_5797) + node T_5799 = mux(T_5729, UInt<6>("h3c"), T_5798) + node T_5800 = mux(T_5728, UInt<6>("h3b"), T_5799) + node T_5801 = mux(T_5727, UInt<6>("h3a"), T_5800) + node T_5802 = mux(T_5726, UInt<6>("h39"), T_5801) + node T_5803 = mux(T_5725, UInt<6>("h38"), T_5802) + node T_5804 = mux(T_5724, UInt<6>("h37"), T_5803) + node T_5805 = mux(T_5723, UInt<6>("h36"), T_5804) + node T_5806 = mux(T_5722, UInt<6>("h35"), T_5805) + node T_5807 = mux(T_5721, UInt<6>("h34"), T_5806) + node T_5808 = mux(T_5720, UInt<6>("h33"), T_5807) + node T_5809 = mux(T_5719, UInt<6>("h32"), T_5808) + node T_5810 = mux(T_5718, UInt<6>("h31"), T_5809) + node T_5811 = mux(T_5717, UInt<6>("h30"), T_5810) + node T_5812 = mux(T_5716, UInt<6>("h2f"), T_5811) + node T_5813 = mux(T_5715, UInt<6>("h2e"), T_5812) + node T_5814 = mux(T_5714, UInt<6>("h2d"), T_5813) + node T_5815 = mux(T_5713, UInt<6>("h2c"), T_5814) + node T_5816 = mux(T_5712, UInt<6>("h2b"), T_5815) + node T_5817 = mux(T_5711, UInt<6>("h2a"), T_5816) + node T_5818 = mux(T_5710, UInt<6>("h29"), T_5817) + node T_5819 = mux(T_5709, UInt<6>("h28"), T_5818) + node T_5820 = mux(T_5708, UInt<6>("h27"), T_5819) + node T_5821 = mux(T_5707, UInt<6>("h26"), T_5820) + node T_5822 = mux(T_5706, UInt<6>("h25"), T_5821) + node T_5823 = mux(T_5705, UInt<6>("h24"), T_5822) + node T_5824 = mux(T_5704, UInt<6>("h23"), T_5823) + node T_5825 = mux(T_5703, UInt<6>("h22"), T_5824) + node T_5826 = mux(T_5702, UInt<6>("h21"), T_5825) + node T_5827 = mux(T_5701, UInt<6>("h20"), T_5826) + node T_5828 = mux(T_5700, UInt<5>("h1f"), T_5827) + node T_5829 = mux(T_5699, UInt<5>("h1e"), T_5828) + node T_5830 = mux(T_5698, UInt<5>("h1d"), T_5829) + node T_5831 = mux(T_5697, UInt<5>("h1c"), T_5830) + node T_5832 = mux(T_5696, UInt<5>("h1b"), T_5831) + node T_5833 = mux(T_5695, UInt<5>("h1a"), T_5832) + node T_5834 = mux(T_5694, UInt<5>("h19"), T_5833) + node T_5835 = mux(T_5693, UInt<5>("h18"), T_5834) + node T_5836 = mux(T_5692, UInt<5>("h17"), T_5835) + node T_5837 = mux(T_5691, UInt<5>("h16"), T_5836) + node T_5838 = mux(T_5690, UInt<5>("h15"), T_5837) + node T_5839 = mux(T_5689, UInt<5>("h14"), T_5838) + node T_5840 = mux(T_5688, UInt<5>("h13"), T_5839) + node T_5841 = mux(T_5687, UInt<5>("h12"), T_5840) + node T_5842 = mux(T_5686, UInt<5>("h11"), T_5841) + node T_5843 = mux(T_5685, UInt<5>("h10"), T_5842) + node T_5844 = mux(T_5684, UInt<4>("hf"), T_5843) + node T_5845 = mux(T_5683, UInt<4>("he"), T_5844) + node T_5846 = mux(T_5682, UInt<4>("hd"), T_5845) + node T_5847 = mux(T_5681, UInt<4>("hc"), T_5846) + node T_5848 = mux(T_5680, UInt<4>("hb"), T_5847) + node T_5849 = mux(T_5679, UInt<4>("ha"), T_5848) + node T_5850 = mux(T_5678, UInt<4>("h9"), T_5849) + node T_5851 = mux(T_5677, UInt<4>("h8"), T_5850) + node T_5852 = mux(T_5676, UInt<3>("h7"), T_5851) + node T_5853 = mux(T_5675, UInt<3>("h6"), T_5852) + node T_5854 = mux(T_5674, UInt<3>("h5"), T_5853) + node T_5855 = mux(T_5673, UInt<3>("h4"), T_5854) + node T_5856 = mux(T_5672, UInt<2>("h3"), T_5855) + node T_5857 = mux(T_5671, UInt<2>("h2"), T_5856) + node T_5858 = mux(T_5670, UInt<1>("h1"), T_5857) + node T_5859 = mux(T_5669, UInt<1>("h0"), T_5858) + node T_5860 = add(UInt<64>("h8000000000000000"), T_5859) + node interruptCause = tail(T_5860, 1) + node T_5862 = neq(all_interrupts, UInt<1>("h0")) + node T_5864 = eq(io.singleStep, UInt<1>("h0")) + node T_5865 = and(T_5862, T_5864) + node T_5866 = or(T_5865, reg_singleStepped) + io.interrupt <= T_5866 + io.interrupt_cause <= interruptCause + io.bp[0] <- reg_bp[0] + node T_5868 = and(UInt<1>("h1"), reg_dcsr.debugint) + node T_5870 = eq(reg_debug, UInt<1>("h0")) + node T_5871 = and(T_5868, T_5870) + when T_5871 : + io.interrupt <= UInt<1>("h1") + io.interrupt_cause <= UInt<64>("h800000000000000d") + node system_insn = eq(io.rw.cmd, UInt<3>("h4")) + node T_5874 = neq(io.rw.cmd, UInt<3>("h0")) + node T_5876 = eq(system_insn, UInt<1>("h0")) + node cpu_ren = and(T_5874, T_5876) + node T_5877 = neq(io.rw.cmd, UInt<3>("h5")) + node cpu_wen = and(cpu_ren, T_5877) + reg reg_misa : UInt, clk with : + reset => (reset, UInt<64>("h800000000014112d")) + node T_5879 = cat(io.status.hie, io.status.sie) + node T_5880 = cat(T_5879, io.status.uie) + node T_5881 = cat(io.status.spie, io.status.upie) + node T_5882 = cat(T_5881, io.status.mie) + node T_5883 = cat(T_5882, T_5880) + node T_5884 = cat(io.status.spp, io.status.mpie) + node T_5885 = cat(T_5884, io.status.hpie) + node T_5886 = cat(io.status.fs, io.status.mpp) + node T_5887 = cat(T_5886, io.status.hpp) + node T_5888 = cat(T_5887, T_5885) + node T_5889 = cat(T_5888, T_5883) + node T_5890 = cat(io.status.pum, io.status.mprv) + node T_5891 = cat(T_5890, io.status.xs) + node T_5892 = cat(io.status.vm, io.status.zero1) + node T_5893 = cat(T_5892, io.status.mxr) + node T_5894 = cat(T_5893, T_5891) + node T_5895 = cat(io.status.zero3, io.status.sd_rv32) + node T_5896 = cat(T_5895, io.status.zero2) + node T_5897 = cat(io.status.prv, io.status.sd) + node T_5898 = cat(io.status.debug, io.status.isa) + node T_5899 = cat(T_5898, T_5897) + node T_5900 = cat(T_5899, T_5896) + node T_5901 = cat(T_5900, T_5894) + node T_5902 = cat(T_5901, T_5889) + node read_mstatus = bits(T_5902, 63, 0) + node T_5920 = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) + node T_5921 = cat(T_5920, reg_bp[reg_tselect].control.r) + node T_5922 = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) + node T_5923 = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) + node T_5924 = cat(T_5923, T_5922) + node T_5925 = cat(T_5924, T_5921) + node T_5926 = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) + node T_5927 = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) + node T_5928 = cat(T_5927, T_5926) + node T_5929 = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) + node T_5930 = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) + node T_5931 = cat(T_5930, T_5929) + node T_5932 = cat(T_5931, T_5928) + node T_5933 = cat(T_5932, T_5925) + node T_5951 = bits(reg_bp[reg_tselect].address, 38, 38) + node T_5952 = bits(T_5951, 0, 0) + node T_5955 = mux(T_5952, UInt<25>("h1ffffff"), UInt<25>("h0")) + node T_5956 = cat(T_5955, reg_bp[reg_tselect].address) + node T_5960 = bits(reg_mepc, 39, 39) + node T_5961 = bits(T_5960, 0, 0) + node T_5964 = mux(T_5961, UInt<24>("hffffff"), UInt<24>("h0")) + node T_5965 = cat(T_5964, reg_mepc) + node T_5966 = bits(reg_mbadaddr, 39, 39) + node T_5967 = bits(T_5966, 0, 0) + node T_5970 = mux(T_5967, UInt<24>("hffffff"), UInt<24>("h0")) + node T_5971 = cat(T_5970, reg_mbadaddr) + node T_5972 = cat(reg_dcsr.step, reg_dcsr.prv) + node T_5973 = cat(reg_dcsr.zero1, reg_dcsr.halt) + node T_5974 = cat(T_5973, T_5972) + node T_5975 = cat(reg_dcsr.cause, reg_dcsr.debugint) + node T_5976 = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) + node T_5977 = cat(T_5976, T_5975) + node T_5978 = cat(T_5977, T_5974) + node T_5979 = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) + node T_5980 = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) + node T_5981 = cat(T_5980, T_5979) + node T_5982 = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) + node T_5983 = cat(reg_dcsr.xdebugver, reg_dcsr.ndreset) + node T_5984 = cat(T_5983, reg_dcsr.fullreset) + node T_5985 = cat(T_5984, T_5982) + node T_5986 = cat(T_5985, T_5981) + node T_5987 = cat(T_5986, T_5978) + node T_5988 = cat(reg_frm, reg_fflags) + node T_5991 = and(reg_mie, reg_mideleg) + node T_5992 = and(read_mip, reg_mideleg) + wire T_5993 : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} T_5993 is invalid T_5993 <- io.status - T_5993.vm <= UInt<1>("h00") @[csr.scala 329:21] - T_5993.mprv <= UInt<1>("h00") @[csr.scala 330:23] - T_5993.mpp <= UInt<1>("h00") @[csr.scala 331:22] - T_5993.hpp <= UInt<1>("h00") @[csr.scala 332:22] - T_5993.mpie <= UInt<1>("h00") @[csr.scala 333:23] - T_5993.hpie <= UInt<1>("h00") @[csr.scala 334:23] - T_5993.mie <= UInt<1>("h00") @[csr.scala 335:22] - T_5993.hie <= UInt<1>("h00") @[csr.scala 336:22] - node T_6027 = cat(T_5993.hie, T_5993.sie) @[csr.scala 338:57] - node T_6028 = cat(T_6027, T_5993.uie) @[csr.scala 338:57] - node T_6029 = cat(T_5993.spie, T_5993.upie) @[csr.scala 338:57] - node T_6030 = cat(T_6029, T_5993.mie) @[csr.scala 338:57] - node T_6031 = cat(T_6030, T_6028) @[csr.scala 338:57] - node T_6032 = cat(T_5993.spp, T_5993.mpie) @[csr.scala 338:57] - node T_6033 = cat(T_6032, T_5993.hpie) @[csr.scala 338:57] - node T_6034 = cat(T_5993.fs, T_5993.mpp) @[csr.scala 338:57] - node T_6035 = cat(T_6034, T_5993.hpp) @[csr.scala 338:57] - node T_6036 = cat(T_6035, T_6033) @[csr.scala 338:57] - node T_6037 = cat(T_6036, T_6031) @[csr.scala 338:57] - node T_6038 = cat(T_5993.pum, T_5993.mprv) @[csr.scala 338:57] - node T_6039 = cat(T_6038, T_5993.xs) @[csr.scala 338:57] - node T_6040 = cat(T_5993.vm, T_5993.zero1) @[csr.scala 338:57] - node T_6041 = cat(T_6040, T_5993.mxr) @[csr.scala 338:57] - node T_6042 = cat(T_6041, T_6039) @[csr.scala 338:57] - node T_6043 = cat(T_5993.zero3, T_5993.sd_rv32) @[csr.scala 338:57] - node T_6044 = cat(T_6043, T_5993.zero2) @[csr.scala 338:57] - node T_6045 = cat(T_5993.prv, T_5993.sd) @[csr.scala 338:57] - node T_6046 = cat(T_5993.debug, T_5993.isa) @[csr.scala 338:57] - node T_6047 = cat(T_6046, T_6045) @[csr.scala 338:57] - node T_6048 = cat(T_6047, T_6044) @[csr.scala 338:57] - node T_6049 = cat(T_6048, T_6042) @[csr.scala 338:57] - node T_6050 = cat(T_6049, T_6037) @[csr.scala 338:57] - node T_6051 = bits(T_6050, 63, 0) @[csr.scala 338:60] - node T_6052 = bits(reg_sbadaddr, 39, 39) @[util.scala 21:38] - node T_6053 = bits(T_6052, 0, 0) @[Bitwise.scala 33:15] - node T_6056 = mux(T_6053, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12] - node T_6057 = cat(T_6056, reg_sbadaddr) @[Cat.scala 20:58] - node T_6058 = cat(reg_sptbr.asid, reg_sptbr.ppn) @[csr.scala 344:45] - node T_6059 = bits(reg_sepc, 39, 39) @[util.scala 21:38] - node T_6060 = bits(T_6059, 0, 0) @[Bitwise.scala 33:15] - node T_6063 = mux(T_6060, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12] - node T_6064 = cat(T_6063, reg_sepc) @[Cat.scala 20:58] - node T_6065 = bits(reg_stvec, 38, 38) @[util.scala 21:38] - node T_6066 = bits(T_6065, 0, 0) @[Bitwise.scala 33:15] - node T_6069 = mux(T_6066, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 33:12] - node T_6070 = cat(T_6069, reg_stvec) @[Cat.scala 20:58] - node T_6072 = eq(io.rw.addr, UInt<11>("h07a0")) @[csr.scala 372:73] - node T_6074 = eq(io.rw.addr, UInt<11>("h07a1")) @[csr.scala 372:73] - node T_6076 = eq(io.rw.addr, UInt<11>("h07a2")) @[csr.scala 372:73] - node T_6078 = eq(io.rw.addr, UInt<12>("h0f13")) @[csr.scala 372:73] - node T_6080 = eq(io.rw.addr, UInt<12>("h0f12")) @[csr.scala 372:73] - node T_6082 = eq(io.rw.addr, UInt<12>("h0f11")) @[csr.scala 372:73] - node T_6084 = eq(io.rw.addr, UInt<12>("h0b00")) @[csr.scala 372:73] - node T_6086 = eq(io.rw.addr, UInt<12>("h0b02")) @[csr.scala 372:73] - node T_6088 = eq(io.rw.addr, UInt<10>("h0301")) @[csr.scala 372:73] - node T_6090 = eq(io.rw.addr, UInt<10>("h0300")) @[csr.scala 372:73] - node T_6092 = eq(io.rw.addr, UInt<10>("h0305")) @[csr.scala 372:73] - node T_6094 = eq(io.rw.addr, UInt<10>("h0344")) @[csr.scala 372:73] - node T_6096 = eq(io.rw.addr, UInt<10>("h0304")) @[csr.scala 372:73] - node T_6098 = eq(io.rw.addr, UInt<10>("h0303")) @[csr.scala 372:73] - node T_6100 = eq(io.rw.addr, UInt<10>("h0302")) @[csr.scala 372:73] - node T_6102 = eq(io.rw.addr, UInt<10>("h0340")) @[csr.scala 372:73] - node T_6104 = eq(io.rw.addr, UInt<10>("h0341")) @[csr.scala 372:73] - node T_6106 = eq(io.rw.addr, UInt<10>("h0343")) @[csr.scala 372:73] - node T_6108 = eq(io.rw.addr, UInt<10>("h0342")) @[csr.scala 372:73] - node T_6110 = eq(io.rw.addr, UInt<12>("h0f14")) @[csr.scala 372:73] - node T_6112 = eq(io.rw.addr, UInt<11>("h07b0")) @[csr.scala 372:73] - node T_6114 = eq(io.rw.addr, UInt<11>("h07b1")) @[csr.scala 372:73] - node T_6116 = eq(io.rw.addr, UInt<11>("h07b2")) @[csr.scala 372:73] - node T_6118 = eq(io.rw.addr, UInt<1>("h01")) @[csr.scala 372:73] - node T_6120 = eq(io.rw.addr, UInt<2>("h02")) @[csr.scala 372:73] - node T_6122 = eq(io.rw.addr, UInt<2>("h03")) @[csr.scala 372:73] - node T_6124 = eq(io.rw.addr, UInt<10>("h0323")) @[csr.scala 372:73] - node T_6126 = eq(io.rw.addr, UInt<12>("h0b03")) @[csr.scala 372:73] - node T_6128 = eq(io.rw.addr, UInt<12>("h0c03")) @[csr.scala 372:73] - node T_6130 = eq(io.rw.addr, UInt<10>("h0324")) @[csr.scala 372:73] - node T_6132 = eq(io.rw.addr, UInt<12>("h0b04")) @[csr.scala 372:73] - node T_6134 = eq(io.rw.addr, UInt<12>("h0c04")) @[csr.scala 372:73] - node T_6136 = eq(io.rw.addr, UInt<10>("h0325")) @[csr.scala 372:73] - node T_6138 = eq(io.rw.addr, UInt<12>("h0b05")) @[csr.scala 372:73] - node T_6140 = eq(io.rw.addr, UInt<12>("h0c05")) @[csr.scala 372:73] - node T_6142 = eq(io.rw.addr, UInt<10>("h0326")) @[csr.scala 372:73] - node T_6144 = eq(io.rw.addr, UInt<12>("h0b06")) @[csr.scala 372:73] - node T_6146 = eq(io.rw.addr, UInt<12>("h0c06")) @[csr.scala 372:73] - node T_6148 = eq(io.rw.addr, UInt<10>("h0327")) @[csr.scala 372:73] - node T_6150 = eq(io.rw.addr, UInt<12>("h0b07")) @[csr.scala 372:73] - node T_6152 = eq(io.rw.addr, UInt<12>("h0c07")) @[csr.scala 372:73] - node T_6154 = eq(io.rw.addr, UInt<10>("h0328")) @[csr.scala 372:73] - node T_6156 = eq(io.rw.addr, UInt<12>("h0b08")) @[csr.scala 372:73] - node T_6158 = eq(io.rw.addr, UInt<12>("h0c08")) @[csr.scala 372:73] - node T_6160 = eq(io.rw.addr, UInt<10>("h0329")) @[csr.scala 372:73] - node T_6162 = eq(io.rw.addr, UInt<12>("h0b09")) @[csr.scala 372:73] - node T_6164 = eq(io.rw.addr, UInt<12>("h0c09")) @[csr.scala 372:73] - node T_6166 = eq(io.rw.addr, UInt<10>("h032a")) @[csr.scala 372:73] - node T_6168 = eq(io.rw.addr, UInt<12>("h0b0a")) @[csr.scala 372:73] - node T_6170 = eq(io.rw.addr, UInt<12>("h0c0a")) @[csr.scala 372:73] - node T_6172 = eq(io.rw.addr, UInt<10>("h032b")) @[csr.scala 372:73] - node T_6174 = eq(io.rw.addr, UInt<12>("h0b0b")) @[csr.scala 372:73] - node T_6176 = eq(io.rw.addr, UInt<12>("h0c0b")) @[csr.scala 372:73] - node T_6178 = eq(io.rw.addr, UInt<10>("h032c")) @[csr.scala 372:73] - node T_6180 = eq(io.rw.addr, UInt<12>("h0b0c")) @[csr.scala 372:73] - node T_6182 = eq(io.rw.addr, UInt<12>("h0c0c")) @[csr.scala 372:73] - node T_6184 = eq(io.rw.addr, UInt<10>("h032d")) @[csr.scala 372:73] - node T_6186 = eq(io.rw.addr, UInt<12>("h0b0d")) @[csr.scala 372:73] - node T_6188 = eq(io.rw.addr, UInt<12>("h0c0d")) @[csr.scala 372:73] - node T_6190 = eq(io.rw.addr, UInt<10>("h032e")) @[csr.scala 372:73] - node T_6192 = eq(io.rw.addr, UInt<12>("h0b0e")) @[csr.scala 372:73] - node T_6194 = eq(io.rw.addr, UInt<12>("h0c0e")) @[csr.scala 372:73] - node T_6196 = eq(io.rw.addr, UInt<10>("h032f")) @[csr.scala 372:73] - node T_6198 = eq(io.rw.addr, UInt<12>("h0b0f")) @[csr.scala 372:73] - node T_6200 = eq(io.rw.addr, UInt<12>("h0c0f")) @[csr.scala 372:73] - node T_6202 = eq(io.rw.addr, UInt<10>("h0330")) @[csr.scala 372:73] - node T_6204 = eq(io.rw.addr, UInt<12>("h0b10")) @[csr.scala 372:73] - node T_6206 = eq(io.rw.addr, UInt<12>("h0c10")) @[csr.scala 372:73] - node T_6208 = eq(io.rw.addr, UInt<10>("h0331")) @[csr.scala 372:73] - node T_6210 = eq(io.rw.addr, UInt<12>("h0b11")) @[csr.scala 372:73] - node T_6212 = eq(io.rw.addr, UInt<12>("h0c11")) @[csr.scala 372:73] - node T_6214 = eq(io.rw.addr, UInt<10>("h0332")) @[csr.scala 372:73] - node T_6216 = eq(io.rw.addr, UInt<12>("h0b12")) @[csr.scala 372:73] - node T_6218 = eq(io.rw.addr, UInt<12>("h0c12")) @[csr.scala 372:73] - node T_6220 = eq(io.rw.addr, UInt<10>("h0333")) @[csr.scala 372:73] - node T_6222 = eq(io.rw.addr, UInt<12>("h0b13")) @[csr.scala 372:73] - node T_6224 = eq(io.rw.addr, UInt<12>("h0c13")) @[csr.scala 372:73] - node T_6226 = eq(io.rw.addr, UInt<10>("h0334")) @[csr.scala 372:73] - node T_6228 = eq(io.rw.addr, UInt<12>("h0b14")) @[csr.scala 372:73] - node T_6230 = eq(io.rw.addr, UInt<12>("h0c14")) @[csr.scala 372:73] - node T_6232 = eq(io.rw.addr, UInt<10>("h0335")) @[csr.scala 372:73] - node T_6234 = eq(io.rw.addr, UInt<12>("h0b15")) @[csr.scala 372:73] - node T_6236 = eq(io.rw.addr, UInt<12>("h0c15")) @[csr.scala 372:73] - node T_6238 = eq(io.rw.addr, UInt<10>("h0336")) @[csr.scala 372:73] - node T_6240 = eq(io.rw.addr, UInt<12>("h0b16")) @[csr.scala 372:73] - node T_6242 = eq(io.rw.addr, UInt<12>("h0c16")) @[csr.scala 372:73] - node T_6244 = eq(io.rw.addr, UInt<10>("h0337")) @[csr.scala 372:73] - node T_6246 = eq(io.rw.addr, UInt<12>("h0b17")) @[csr.scala 372:73] - node T_6248 = eq(io.rw.addr, UInt<12>("h0c17")) @[csr.scala 372:73] - node T_6250 = eq(io.rw.addr, UInt<10>("h0338")) @[csr.scala 372:73] - node T_6252 = eq(io.rw.addr, UInt<12>("h0b18")) @[csr.scala 372:73] - node T_6254 = eq(io.rw.addr, UInt<12>("h0c18")) @[csr.scala 372:73] - node T_6256 = eq(io.rw.addr, UInt<10>("h0339")) @[csr.scala 372:73] - node T_6258 = eq(io.rw.addr, UInt<12>("h0b19")) @[csr.scala 372:73] - node T_6260 = eq(io.rw.addr, UInt<12>("h0c19")) @[csr.scala 372:73] - node T_6262 = eq(io.rw.addr, UInt<10>("h033a")) @[csr.scala 372:73] - node T_6264 = eq(io.rw.addr, UInt<12>("h0b1a")) @[csr.scala 372:73] - node T_6266 = eq(io.rw.addr, UInt<12>("h0c1a")) @[csr.scala 372:73] - node T_6268 = eq(io.rw.addr, UInt<10>("h033b")) @[csr.scala 372:73] - node T_6270 = eq(io.rw.addr, UInt<12>("h0b1b")) @[csr.scala 372:73] - node T_6272 = eq(io.rw.addr, UInt<12>("h0c1b")) @[csr.scala 372:73] - node T_6274 = eq(io.rw.addr, UInt<10>("h033c")) @[csr.scala 372:73] - node T_6276 = eq(io.rw.addr, UInt<12>("h0b1c")) @[csr.scala 372:73] - node T_6278 = eq(io.rw.addr, UInt<12>("h0c1c")) @[csr.scala 372:73] - node T_6280 = eq(io.rw.addr, UInt<10>("h033d")) @[csr.scala 372:73] - node T_6282 = eq(io.rw.addr, UInt<12>("h0b1d")) @[csr.scala 372:73] - node T_6284 = eq(io.rw.addr, UInt<12>("h0c1d")) @[csr.scala 372:73] - node T_6286 = eq(io.rw.addr, UInt<10>("h033e")) @[csr.scala 372:73] - node T_6288 = eq(io.rw.addr, UInt<12>("h0b1e")) @[csr.scala 372:73] - node T_6290 = eq(io.rw.addr, UInt<12>("h0c1e")) @[csr.scala 372:73] - node T_6292 = eq(io.rw.addr, UInt<10>("h033f")) @[csr.scala 372:73] - node T_6294 = eq(io.rw.addr, UInt<12>("h0b1f")) @[csr.scala 372:73] - node T_6296 = eq(io.rw.addr, UInt<12>("h0c1f")) @[csr.scala 372:73] - node T_6298 = eq(io.rw.addr, UInt<9>("h0100")) @[csr.scala 372:73] - node T_6300 = eq(io.rw.addr, UInt<9>("h0144")) @[csr.scala 372:73] - node T_6302 = eq(io.rw.addr, UInt<9>("h0104")) @[csr.scala 372:73] - node T_6304 = eq(io.rw.addr, UInt<9>("h0140")) @[csr.scala 372:73] - node T_6306 = eq(io.rw.addr, UInt<9>("h0142")) @[csr.scala 372:73] - node T_6308 = eq(io.rw.addr, UInt<9>("h0143")) @[csr.scala 372:73] - node T_6310 = eq(io.rw.addr, UInt<9>("h0180")) @[csr.scala 372:73] - node T_6312 = eq(io.rw.addr, UInt<9>("h0141")) @[csr.scala 372:73] - node T_6314 = eq(io.rw.addr, UInt<9>("h0105")) @[csr.scala 372:73] - node T_6316 = eq(io.rw.addr, UInt<10>("h0321")) @[csr.scala 372:73] - node T_6318 = eq(io.rw.addr, UInt<10>("h0320")) @[csr.scala 372:73] - node T_6320 = eq(io.rw.addr, UInt<12>("h0c00")) @[csr.scala 372:73] - node T_6322 = eq(io.rw.addr, UInt<12>("h0c02")) @[csr.scala 372:73] - node T_6323 = or(T_6072, T_6074) @[csr.scala 373:48] - node T_6324 = or(T_6323, T_6076) @[csr.scala 373:48] - node T_6325 = or(T_6324, T_6078) @[csr.scala 373:48] - node T_6326 = or(T_6325, T_6080) @[csr.scala 373:48] - node T_6327 = or(T_6326, T_6082) @[csr.scala 373:48] - node T_6328 = or(T_6327, T_6084) @[csr.scala 373:48] - node T_6329 = or(T_6328, T_6086) @[csr.scala 373:48] - node T_6330 = or(T_6329, T_6088) @[csr.scala 373:48] - node T_6331 = or(T_6330, T_6090) @[csr.scala 373:48] - node T_6332 = or(T_6331, T_6092) @[csr.scala 373:48] - node T_6333 = or(T_6332, T_6094) @[csr.scala 373:48] - node T_6334 = or(T_6333, T_6096) @[csr.scala 373:48] - node T_6335 = or(T_6334, T_6098) @[csr.scala 373:48] - node T_6336 = or(T_6335, T_6100) @[csr.scala 373:48] - node T_6337 = or(T_6336, T_6102) @[csr.scala 373:48] - node T_6338 = or(T_6337, T_6104) @[csr.scala 373:48] - node T_6339 = or(T_6338, T_6106) @[csr.scala 373:48] - node T_6340 = or(T_6339, T_6108) @[csr.scala 373:48] - node T_6341 = or(T_6340, T_6110) @[csr.scala 373:48] - node T_6342 = or(T_6341, T_6112) @[csr.scala 373:48] - node T_6343 = or(T_6342, T_6114) @[csr.scala 373:48] - node T_6344 = or(T_6343, T_6116) @[csr.scala 373:48] - node T_6345 = or(T_6344, T_6118) @[csr.scala 373:48] - node T_6346 = or(T_6345, T_6120) @[csr.scala 373:48] - node T_6347 = or(T_6346, T_6122) @[csr.scala 373:48] - node T_6348 = or(T_6347, T_6124) @[csr.scala 373:48] - node T_6349 = or(T_6348, T_6126) @[csr.scala 373:48] - node T_6350 = or(T_6349, T_6128) @[csr.scala 373:48] - node T_6351 = or(T_6350, T_6130) @[csr.scala 373:48] - node T_6352 = or(T_6351, T_6132) @[csr.scala 373:48] - node T_6353 = or(T_6352, T_6134) @[csr.scala 373:48] - node T_6354 = or(T_6353, T_6136) @[csr.scala 373:48] - node T_6355 = or(T_6354, T_6138) @[csr.scala 373:48] - node T_6356 = or(T_6355, T_6140) @[csr.scala 373:48] - node T_6357 = or(T_6356, T_6142) @[csr.scala 373:48] - node T_6358 = or(T_6357, T_6144) @[csr.scala 373:48] - node T_6359 = or(T_6358, T_6146) @[csr.scala 373:48] - node T_6360 = or(T_6359, T_6148) @[csr.scala 373:48] - node T_6361 = or(T_6360, T_6150) @[csr.scala 373:48] - node T_6362 = or(T_6361, T_6152) @[csr.scala 373:48] - node T_6363 = or(T_6362, T_6154) @[csr.scala 373:48] - node T_6364 = or(T_6363, T_6156) @[csr.scala 373:48] - node T_6365 = or(T_6364, T_6158) @[csr.scala 373:48] - node T_6366 = or(T_6365, T_6160) @[csr.scala 373:48] - node T_6367 = or(T_6366, T_6162) @[csr.scala 373:48] - node T_6368 = or(T_6367, T_6164) @[csr.scala 373:48] - node T_6369 = or(T_6368, T_6166) @[csr.scala 373:48] - node T_6370 = or(T_6369, T_6168) @[csr.scala 373:48] - node T_6371 = or(T_6370, T_6170) @[csr.scala 373:48] - node T_6372 = or(T_6371, T_6172) @[csr.scala 373:48] - node T_6373 = or(T_6372, T_6174) @[csr.scala 373:48] - node T_6374 = or(T_6373, T_6176) @[csr.scala 373:48] - node T_6375 = or(T_6374, T_6178) @[csr.scala 373:48] - node T_6376 = or(T_6375, T_6180) @[csr.scala 373:48] - node T_6377 = or(T_6376, T_6182) @[csr.scala 373:48] - node T_6378 = or(T_6377, T_6184) @[csr.scala 373:48] - node T_6379 = or(T_6378, T_6186) @[csr.scala 373:48] - node T_6380 = or(T_6379, T_6188) @[csr.scala 373:48] - node T_6381 = or(T_6380, T_6190) @[csr.scala 373:48] - node T_6382 = or(T_6381, T_6192) @[csr.scala 373:48] - node T_6383 = or(T_6382, T_6194) @[csr.scala 373:48] - node T_6384 = or(T_6383, T_6196) @[csr.scala 373:48] - node T_6385 = or(T_6384, T_6198) @[csr.scala 373:48] - node T_6386 = or(T_6385, T_6200) @[csr.scala 373:48] - node T_6387 = or(T_6386, T_6202) @[csr.scala 373:48] - node T_6388 = or(T_6387, T_6204) @[csr.scala 373:48] - node T_6389 = or(T_6388, T_6206) @[csr.scala 373:48] - node T_6390 = or(T_6389, T_6208) @[csr.scala 373:48] - node T_6391 = or(T_6390, T_6210) @[csr.scala 373:48] - node T_6392 = or(T_6391, T_6212) @[csr.scala 373:48] - node T_6393 = or(T_6392, T_6214) @[csr.scala 373:48] - node T_6394 = or(T_6393, T_6216) @[csr.scala 373:48] - node T_6395 = or(T_6394, T_6218) @[csr.scala 373:48] - node T_6396 = or(T_6395, T_6220) @[csr.scala 373:48] - node T_6397 = or(T_6396, T_6222) @[csr.scala 373:48] - node T_6398 = or(T_6397, T_6224) @[csr.scala 373:48] - node T_6399 = or(T_6398, T_6226) @[csr.scala 373:48] - node T_6400 = or(T_6399, T_6228) @[csr.scala 373:48] - node T_6401 = or(T_6400, T_6230) @[csr.scala 373:48] - node T_6402 = or(T_6401, T_6232) @[csr.scala 373:48] - node T_6403 = or(T_6402, T_6234) @[csr.scala 373:48] - node T_6404 = or(T_6403, T_6236) @[csr.scala 373:48] - node T_6405 = or(T_6404, T_6238) @[csr.scala 373:48] - node T_6406 = or(T_6405, T_6240) @[csr.scala 373:48] - node T_6407 = or(T_6406, T_6242) @[csr.scala 373:48] - node T_6408 = or(T_6407, T_6244) @[csr.scala 373:48] - node T_6409 = or(T_6408, T_6246) @[csr.scala 373:48] - node T_6410 = or(T_6409, T_6248) @[csr.scala 373:48] - node T_6411 = or(T_6410, T_6250) @[csr.scala 373:48] - node T_6412 = or(T_6411, T_6252) @[csr.scala 373:48] - node T_6413 = or(T_6412, T_6254) @[csr.scala 373:48] - node T_6414 = or(T_6413, T_6256) @[csr.scala 373:48] - node T_6415 = or(T_6414, T_6258) @[csr.scala 373:48] - node T_6416 = or(T_6415, T_6260) @[csr.scala 373:48] - node T_6417 = or(T_6416, T_6262) @[csr.scala 373:48] - node T_6418 = or(T_6417, T_6264) @[csr.scala 373:48] - node T_6419 = or(T_6418, T_6266) @[csr.scala 373:48] - node T_6420 = or(T_6419, T_6268) @[csr.scala 373:48] - node T_6421 = or(T_6420, T_6270) @[csr.scala 373:48] - node T_6422 = or(T_6421, T_6272) @[csr.scala 373:48] - node T_6423 = or(T_6422, T_6274) @[csr.scala 373:48] - node T_6424 = or(T_6423, T_6276) @[csr.scala 373:48] - node T_6425 = or(T_6424, T_6278) @[csr.scala 373:48] - node T_6426 = or(T_6425, T_6280) @[csr.scala 373:48] - node T_6427 = or(T_6426, T_6282) @[csr.scala 373:48] - node T_6428 = or(T_6427, T_6284) @[csr.scala 373:48] - node T_6429 = or(T_6428, T_6286) @[csr.scala 373:48] - node T_6430 = or(T_6429, T_6288) @[csr.scala 373:48] - node T_6431 = or(T_6430, T_6290) @[csr.scala 373:48] - node T_6432 = or(T_6431, T_6292) @[csr.scala 373:48] - node T_6433 = or(T_6432, T_6294) @[csr.scala 373:48] - node T_6434 = or(T_6433, T_6296) @[csr.scala 373:48] - node T_6435 = or(T_6434, T_6298) @[csr.scala 373:48] - node T_6436 = or(T_6435, T_6300) @[csr.scala 373:48] - node T_6437 = or(T_6436, T_6302) @[csr.scala 373:48] - node T_6438 = or(T_6437, T_6304) @[csr.scala 373:48] - node T_6439 = or(T_6438, T_6306) @[csr.scala 373:48] - node T_6440 = or(T_6439, T_6308) @[csr.scala 373:48] - node T_6441 = or(T_6440, T_6310) @[csr.scala 373:48] - node T_6442 = or(T_6441, T_6312) @[csr.scala 373:48] - node T_6443 = or(T_6442, T_6314) @[csr.scala 373:48] - node T_6444 = or(T_6443, T_6316) @[csr.scala 373:48] - node T_6445 = or(T_6444, T_6318) @[csr.scala 373:48] - node T_6446 = or(T_6445, T_6320) @[csr.scala 373:48] - node addr_valid = or(T_6446, T_6322) @[csr.scala 373:48] - node T_6447 = or(T_6118, T_6120) @[csr.scala 374:90] - node fp_csr = or(T_6447, T_6122) @[csr.scala 374:90] - node T_6449 = geq(io.rw.addr, UInt<12>("h0c00")) @[csr.scala 375:43] - node T_6451 = lt(io.rw.addr, UInt<12>("h0c20")) @[csr.scala 375:73] - node hpm_csr = and(T_6449, T_6451) @[csr.scala 375:59] - node T_6453 = eq(reg_mstatus.prv, UInt<2>("h03")) @[csr.scala 376:45] - node T_6454 = or(reg_debug, T_6453) @[csr.scala 376:26] - node T_6456 = eq(reg_mstatus.prv, UInt<1>("h01")) @[csr.scala 377:22] - node T_6457 = bits(io.rw.addr, 4, 0) @[csr.scala 377:61] - node T_6458 = dshr(reg_mscounteren, T_6457) @[csr.scala 377:50] - node T_6459 = bits(T_6458, 0, 0) @[csr.scala 377:50] - node T_6460 = and(T_6456, T_6459) @[csr.scala 377:32] - node T_6461 = or(T_6454, T_6460) @[csr.scala 376:55] - node T_6463 = eq(reg_mstatus.prv, UInt<1>("h00")) @[csr.scala 378:22] - node T_6464 = bits(io.rw.addr, 4, 0) @[csr.scala 378:61] - node T_6465 = dshr(reg_mucounteren, T_6464) @[csr.scala 378:50] - node T_6466 = bits(T_6465, 0, 0) @[csr.scala 378:50] - node T_6467 = and(T_6463, T_6466) @[csr.scala 378:32] - node hpm_en = or(T_6461, T_6467) @[csr.scala 377:89] - node csr_addr_priv = bits(io.rw.addr, 9, 8) @[csr.scala 379:33] - node T_6470 = and(io.rw.addr, UInt<8>("h090")) @[csr.scala 384:51] - node T_6472 = eq(T_6470, UInt<8>("h090")) @[csr.scala 384:69] - node csr_debug = and(UInt<1>("h01"), T_6472) @[csr.scala 384:36] - node T_6474 = eq(csr_debug, UInt<1>("h00")) @[csr.scala 385:39] - node T_6475 = geq(reg_mstatus.prv, csr_addr_priv) @[csr.scala 385:69] - node T_6476 = and(T_6474, T_6475) @[csr.scala 385:50] - node priv_sufficient = or(reg_debug, T_6476) @[csr.scala 385:35] - node T_6477 = bits(io.rw.addr, 11, 10) @[csr.scala 386:29] - node T_6478 = not(T_6477) @[csr.scala 386:37] - node read_only = eq(T_6478, UInt<1>("h00")) @[csr.scala 386:37] - node T_6480 = and(cpu_wen, priv_sufficient) @[csr.scala 387:21] - node T_6482 = eq(read_only, UInt<1>("h00")) @[csr.scala 387:43] - node wen = and(T_6480, T_6482) @[csr.scala 387:40] - node T_6483 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47] - node T_6484 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47] - node T_6485 = or(T_6483, T_6484) @[Package.scala 7:62] - node T_6487 = mux(T_6485, io.rw.rdata, UInt<1>("h00")) @[csr.scala 389:19] - node T_6488 = neq(io.rw.cmd, UInt<3>("h03")) @[csr.scala 390:30] - node T_6490 = mux(T_6488, io.rw.wdata, UInt<1>("h00")) @[csr.scala 390:19] - node T_6491 = or(T_6487, T_6490) @[csr.scala 389:75] - node T_6492 = eq(io.rw.cmd, UInt<3>("h03")) @[csr.scala 391:30] - node T_6494 = mux(T_6492, io.rw.wdata, UInt<1>("h00")) @[csr.scala 391:19] - node T_6495 = not(T_6494) @[csr.scala 391:15] - node wdata = and(T_6491, T_6495) @[csr.scala 390:64] - node do_system_insn = and(priv_sufficient, system_insn) @[csr.scala 393:40] - node T_6497 = bits(io.rw.addr, 2, 0) @[csr.scala 394:37] - node opcode = dshl(UInt<1>("h01"), T_6497) @[csr.scala 394:24] - node T_6498 = bits(opcode, 0, 0) @[csr.scala 395:43] - node insn_call = and(do_system_insn, T_6498) @[csr.scala 395:34] - node T_6499 = bits(opcode, 1, 1) @[csr.scala 396:44] - node insn_break = and(do_system_insn, T_6499) @[csr.scala 396:35] - node T_6500 = bits(opcode, 2, 2) @[csr.scala 397:42] - node insn_ret = and(do_system_insn, T_6500) @[csr.scala 397:33] - node T_6501 = bits(opcode, 4, 4) @[csr.scala 398:48] - node insn_sfence_vm = and(do_system_insn, T_6501) @[csr.scala 398:39] - node T_6502 = bits(opcode, 5, 5) @[csr.scala 399:42] - node insn_wfi = and(do_system_insn, T_6502) @[csr.scala 399:33] - node T_6503 = and(cpu_wen, read_only) @[csr.scala 401:27] - node T_6505 = eq(priv_sufficient, UInt<1>("h00")) @[csr.scala 402:18] - node T_6507 = eq(addr_valid, UInt<1>("h00")) @[csr.scala 402:38] - node T_6508 = or(T_6505, T_6507) @[csr.scala 402:35] - node T_6510 = eq(hpm_en, UInt<1>("h00")) @[csr.scala 402:65] - node T_6511 = and(hpm_csr, T_6510) @[csr.scala 402:62] - node T_6512 = or(T_6508, T_6511) @[csr.scala 402:50] - node T_6514 = neq(io.status.fs, UInt<1>("h00")) @[csr.scala 402:103] - node T_6515 = bits(reg_misa, 5, 5) @[csr.scala 402:118] - node T_6516 = and(T_6514, T_6515) @[csr.scala 402:107] - node T_6518 = eq(T_6516, UInt<1>("h00")) @[csr.scala 402:88] - node T_6519 = and(fp_csr, T_6518) @[csr.scala 402:85] - node T_6520 = or(T_6512, T_6519) @[csr.scala 402:74] - node T_6521 = and(cpu_ren, T_6520) @[csr.scala 402:14] - node T_6522 = or(T_6503, T_6521) @[csr.scala 401:41] - node T_6524 = eq(priv_sufficient, UInt<1>("h00")) @[csr.scala 403:21] - node T_6525 = and(system_insn, T_6524) @[csr.scala 403:18] - node T_6526 = or(T_6522, T_6525) @[csr.scala 402:132] - node T_6527 = or(T_6526, insn_call) @[csr.scala 403:39] - node T_6528 = or(T_6527, insn_break) @[csr.scala 404:15] - io.csr_xcpt <= T_6528 @[csr.scala 401:15] - when insn_wfi : @[csr.scala 406:19] - reg_wfi <= UInt<1>("h01") @[csr.scala 406:29] - skip @[csr.scala 406:19] - node T_6531 = neq(pending_interrupts, UInt<1>("h00")) @[csr.scala 407:28] - when T_6531 : @[csr.scala 407:33] - reg_wfi <= UInt<1>("h00") @[csr.scala 407:43] - skip @[csr.scala 407:33] - node T_6534 = eq(io.csr_xcpt, UInt<1>("h00")) @[csr.scala 410:9] - node T_6536 = add(reg_mstatus.prv, UInt<4>("h08")) @[csr.scala 411:36] - node T_6537 = tail(T_6536, 1) @[csr.scala 411:36] - node T_6540 = mux(insn_break, UInt<2>("h03"), UInt<2>("h02")) @[csr.scala 412:14] - node T_6541 = mux(insn_call, T_6537, T_6540) @[csr.scala 411:8] - node cause = mux(T_6534, io.cause, T_6541) @[csr.scala 410:8] - node cause_lsbs = bits(cause, 5, 0) @[csr.scala 413:25] - node T_6542 = bits(cause, 63, 63) @[csr.scala 414:30] - node T_6544 = eq(cause_lsbs, UInt<4>("h0d")) @[csr.scala 414:53] - node causeIsDebugInt = and(T_6542, T_6544) @[csr.scala 414:39] - node T_6545 = bits(cause, 63, 63) @[csr.scala 415:35] - node T_6547 = eq(T_6545, UInt<1>("h00")) @[csr.scala 415:29] - node T_6549 = eq(cause_lsbs, UInt<4>("h0d")) @[csr.scala 415:58] - node causeIsDebugTrigger = and(T_6547, T_6549) @[csr.scala 415:44] - node T_6550 = bits(cause, 63, 63) @[csr.scala 416:33] - node T_6552 = eq(T_6550, UInt<1>("h00")) @[csr.scala 416:27] - node T_6553 = and(T_6552, insn_break) @[csr.scala 416:42] - node T_6554 = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) @[Cat.scala 20:58] - node T_6555 = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) @[Cat.scala 20:58] - node T_6556 = cat(T_6555, T_6554) @[Cat.scala 20:58] - node T_6557 = dshr(T_6556, reg_mstatus.prv) @[csr.scala 416:134] - node T_6558 = bits(T_6557, 0, 0) @[csr.scala 416:134] - node causeIsDebugBreak = and(T_6553, T_6558) @[csr.scala 416:56] - node T_6560 = or(reg_singleStepped, causeIsDebugInt) @[csr.scala 417:60] - node T_6561 = or(T_6560, causeIsDebugTrigger) @[csr.scala 417:79] - node T_6562 = or(T_6561, causeIsDebugBreak) @[csr.scala 417:102] - node T_6563 = or(T_6562, reg_debug) @[csr.scala 417:123] - node trapToDebug = and(UInt<1>("h01"), T_6563) @[csr.scala 417:38] - node T_6566 = lt(reg_mstatus.prv, UInt<2>("h03")) @[csr.scala 418:51] - node T_6567 = and(UInt<1>("h01"), T_6566) @[csr.scala 418:32] - node T_6568 = bits(cause, 63, 63) @[csr.scala 418:71] - node T_6569 = dshr(reg_mideleg, cause_lsbs) @[csr.scala 418:92] - node T_6570 = bits(T_6569, 0, 0) @[csr.scala 418:92] - node T_6571 = dshr(reg_medeleg, cause_lsbs) @[csr.scala 418:117] - node T_6572 = bits(T_6571, 0, 0) @[csr.scala 418:117] - node T_6573 = mux(T_6568, T_6570, T_6572) @[csr.scala 418:65] - node delegate = and(T_6567, T_6573) @[csr.scala 418:59] - node debugTVec = mux(reg_debug, UInt<12>("h0808"), UInt<12>("h0800")) @[csr.scala 419:22] - node T_6576 = bits(reg_stvec, 38, 38) @[util.scala 21:38] - node T_6577 = cat(T_6576, reg_stvec) @[Cat.scala 20:58] - node T_6578 = mux(delegate, T_6577, reg_mtvec) @[csr.scala 420:45] - node tvec = mux(trapToDebug, debugTVec, T_6578) @[csr.scala 420:17] - node T_6580 = bits(csr_addr_priv, 1, 1) @[csr.scala 421:72] - node T_6582 = eq(T_6580, UInt<1>("h00")) @[csr.scala 421:58] - node T_6583 = and(UInt<1>("h01"), T_6582) @[csr.scala 421:55] - node T_6584 = mux(T_6583, reg_sepc, reg_mepc) @[csr.scala 421:40] - node epc = mux(csr_debug, reg_dpc, T_6584) @[csr.scala 421:16] - io.fatc <= insn_sfence_vm @[csr.scala 422:11] - node T_6585 = mux(exception, tvec, epc) @[csr.scala 423:17] - io.evec <= T_6585 @[csr.scala 423:11] - io.ptbr <- reg_sptbr @[csr.scala 424:11] - io.eret <= insn_ret @[csr.scala 425:11] - node T_6587 = eq(reg_debug, UInt<1>("h00")) @[csr.scala 426:37] - node T_6588 = and(reg_dcsr.step, T_6587) @[csr.scala 426:34] - io.singleStep <= T_6588 @[csr.scala 426:17] - io.status <- reg_mstatus @[csr.scala 427:13] - node T_6589 = not(io.status.fs) @[csr.scala 428:32] - node T_6591 = eq(T_6589, UInt<1>("h00")) @[csr.scala 428:32] - node T_6592 = not(io.status.xs) @[csr.scala 428:53] - node T_6594 = eq(T_6592, UInt<1>("h00")) @[csr.scala 428:53] - node T_6595 = or(T_6591, T_6594) @[csr.scala 428:37] - io.status.sd <= T_6595 @[csr.scala 428:16] - io.status.debug <= reg_debug @[csr.scala 429:19] - io.status.isa <= reg_misa @[csr.scala 430:17] - when exception : @[csr.scala 434:20] - node T_6596 = not(io.pc) @[csr.scala 435:17] - node T_6598 = or(T_6596, UInt<1>("h01")) @[csr.scala 435:24] - node T_6599 = not(T_6598) @[csr.scala 435:15] - node T_6600 = dshr(read_mstatus, reg_mstatus.prv) @[csr.scala 436:27] - node T_6601 = bits(T_6600, 0, 0) @[csr.scala 436:27] - node T_6609 = eq(cause, UInt<2>("h03")) @[Package.scala 7:47] - node T_6610 = eq(cause, UInt<3>("h04")) @[Package.scala 7:47] - node T_6611 = eq(cause, UInt<3>("h06")) @[Package.scala 7:47] - node T_6612 = eq(cause, UInt<1>("h00")) @[Package.scala 7:47] - node T_6613 = eq(cause, UInt<3>("h05")) @[Package.scala 7:47] - node T_6614 = eq(cause, UInt<3>("h07")) @[Package.scala 7:47] - node T_6615 = eq(cause, UInt<1>("h01")) @[Package.scala 7:47] - node T_6616 = or(T_6609, T_6610) @[Package.scala 7:62] - node T_6617 = or(T_6616, T_6611) @[Package.scala 7:62] - node T_6618 = or(T_6617, T_6612) @[Package.scala 7:62] - node T_6619 = or(T_6618, T_6613) @[Package.scala 7:62] - node T_6620 = or(T_6619, T_6614) @[Package.scala 7:62] - node T_6621 = or(T_6620, T_6615) @[Package.scala 7:62] - when trapToDebug : @[csr.scala 442:24] - reg_debug <= UInt<1>("h01") @[csr.scala 443:17] - reg_dpc <= T_6599 @[csr.scala 444:15] - node T_6627 = mux(causeIsDebugTrigger, UInt<2>("h02"), UInt<1>("h01")) @[csr.scala 445:84] - node T_6628 = mux(causeIsDebugInt, UInt<2>("h03"), T_6627) @[csr.scala 445:54] - node T_6629 = mux(reg_singleStepped, UInt<3>("h04"), T_6628) @[csr.scala 445:28] - reg_dcsr.cause <= T_6629 @[csr.scala 445:22] - reg_dcsr.prv <= reg_mstatus.prv @[csr.scala 446:20] - skip @[csr.scala 442:24] - node T_6631 = eq(trapToDebug, UInt<1>("h00")) @[csr.scala 442:24] - node T_6632 = and(T_6631, delegate) @[csr.scala 447:27] - when T_6632 : @[csr.scala 447:27] - node T_6633 = not(T_6599) @[csr.scala 659:28] - node T_6634 = bits(reg_misa, 2, 2) @[csr.scala 659:46] - node T_6636 = eq(T_6634, UInt<1>("h00")) @[csr.scala 659:37] - node T_6638 = cat(T_6636, UInt<1>("h01")) @[Cat.scala 20:58] - node T_6639 = or(T_6633, T_6638) @[csr.scala 659:31] - node T_6640 = not(T_6639) @[csr.scala 659:26] - reg_sepc <= T_6640 @[csr.scala 448:16] - reg_scause <= cause @[csr.scala 449:18] - when T_6621 : @[csr.scala 450:28] - reg_sbadaddr <= io.badaddr @[csr.scala 450:43] - skip @[csr.scala 450:28] - reg_mstatus.spie <= T_6601 @[csr.scala 451:24] - reg_mstatus.spp <= reg_mstatus.prv @[csr.scala 452:23] - reg_mstatus.sie <= UInt<1>("h00") @[csr.scala 453:23] - new_prv <= UInt<1>("h01") @[csr.scala 454:15] - skip @[csr.scala 447:27] - node T_6644 = eq(trapToDebug, UInt<1>("h00")) @[csr.scala 442:24] - node T_6646 = eq(delegate, UInt<1>("h00")) @[csr.scala 447:27] - node T_6647 = and(T_6644, T_6646) @[csr.scala 447:27] - when T_6647 : @[csr.scala 455:17] - node T_6648 = not(T_6599) @[csr.scala 659:28] - node T_6649 = bits(reg_misa, 2, 2) @[csr.scala 659:46] - node T_6651 = eq(T_6649, UInt<1>("h00")) @[csr.scala 659:37] - node T_6653 = cat(T_6651, UInt<1>("h01")) @[Cat.scala 20:58] - node T_6654 = or(T_6648, T_6653) @[csr.scala 659:31] - node T_6655 = not(T_6654) @[csr.scala 659:26] - reg_mepc <= T_6655 @[csr.scala 456:16] - reg_mcause <= cause @[csr.scala 457:18] - when T_6621 : @[csr.scala 458:28] - reg_mbadaddr <= io.badaddr @[csr.scala 458:43] - skip @[csr.scala 458:28] - reg_mstatus.mpie <= T_6601 @[csr.scala 459:24] - reg_mstatus.mpp <= reg_mstatus.prv @[csr.scala 460:23] - reg_mstatus.mie <= UInt<1>("h00") @[csr.scala 461:23] - new_prv <= UInt<2>("h03") @[csr.scala 462:15] - skip @[csr.scala 455:17] - skip @[csr.scala 434:20] - when insn_ret : @[csr.scala 466:19] - node T_6659 = bits(csr_addr_priv, 1, 1) @[csr.scala 467:42] - node T_6661 = eq(T_6659, UInt<1>("h00")) @[csr.scala 467:28] - node T_6662 = and(UInt<1>("h01"), T_6661) @[csr.scala 467:25] - when T_6662 : @[csr.scala 467:47] - node T_6663 = bits(reg_mstatus.spp, 0, 0) @[csr.scala 468:29] - when T_6663 : @[csr.scala 468:37] - reg_mstatus.sie <= reg_mstatus.spie @[csr.scala 468:55] - skip @[csr.scala 468:37] - reg_mstatus.spie <= UInt<1>("h00") @[csr.scala 469:24] - reg_mstatus.spp <= UInt<1>("h00") @[csr.scala 470:23] - new_prv <= reg_mstatus.spp @[csr.scala 471:15] - skip @[csr.scala 467:47] - node T_6667 = eq(T_6662, UInt<1>("h00")) @[csr.scala 467:47] - node T_6668 = and(T_6667, csr_debug) @[csr.scala 472:28] - when T_6668 : @[csr.scala 472:28] - new_prv <= reg_dcsr.prv @[csr.scala 473:15] - reg_debug <= UInt<1>("h00") @[csr.scala 474:17] - skip @[csr.scala 472:28] - node T_6671 = eq(T_6662, UInt<1>("h00")) @[csr.scala 467:47] - node T_6673 = eq(csr_debug, UInt<1>("h00")) @[csr.scala 472:28] - node T_6674 = and(T_6671, T_6673) @[csr.scala 472:28] - when T_6674 : @[csr.scala 475:17] - node T_6675 = bits(reg_mstatus.mpp, 1, 1) @[csr.scala 476:28] - when T_6675 : @[csr.scala 476:33] - reg_mstatus.mie <= reg_mstatus.mpie @[csr.scala 476:51] - skip @[csr.scala 476:33] - node T_6677 = bits(reg_mstatus.mpp, 0, 0) @[csr.scala 477:50] - node T_6678 = and(UInt<1>("h01"), T_6677) @[csr.scala 477:32] - node T_6680 = eq(T_6675, UInt<1>("h00")) @[csr.scala 476:33] - node T_6681 = and(T_6680, T_6678) @[csr.scala 477:55] - when T_6681 : @[csr.scala 477:55] - reg_mstatus.sie <= reg_mstatus.mpie @[csr.scala 477:73] - skip @[csr.scala 477:55] - reg_mstatus.mpie <= UInt<1>("h00") @[csr.scala 478:24] - node T_6685 = eq(UInt<1>("h00"), UInt<2>("h02")) @[csr.scala 642:27] - node T_6687 = mux(T_6685, UInt<1>("h00"), UInt<1>("h00")) @[csr.scala 642:21] - reg_mstatus.mpp <= T_6687 @[csr.scala 479:23] - new_prv <= reg_mstatus.mpp @[csr.scala 480:15] - skip @[csr.scala 475:17] - skip @[csr.scala 466:19] - node T_6688 = add(io.exception, io.csr_xcpt) @[Bitwise.scala 21:55] - node T_6689 = add(insn_ret, T_6688) @[Bitwise.scala 21:55] - node T_6691 = leq(T_6689, UInt<1>("h01")) @[csr.scala 484:67] - node T_6692 = or(T_6691, reset) @[csr.scala 484:9] - node T_6694 = eq(T_6692, UInt<1>("h00")) @[csr.scala 484:9] - when T_6694 : @[csr.scala 484:9] - printf(clk, UInt<1>(1), "Assertion failed: these conditions must be mutually exclusive\n at csr.scala:484 assert(PopCount(insn_ret :: io.exception :: io.csr_xcpt :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n") @[csr.scala 484:9] - stop(clk, UInt<1>(1), 1) @[csr.scala 484:9] - skip @[csr.scala 484:9] - io.time <= T_5619 @[csr.scala 486:11] - io.csr_stall <= reg_wfi @[csr.scala 487:16] - node T_6696 = mux(T_6072, reg_tselect, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6698 = mux(T_6074, T_5933, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6700 = mux(T_6076, T_5956, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6702 = mux(T_6078, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6704 = mux(T_6080, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6706 = mux(T_6082, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6708 = mux(T_6084, T_5619, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6710 = mux(T_6086, T_5608, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6712 = mux(T_6088, reg_misa, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6714 = mux(T_6090, read_mstatus, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6716 = mux(T_6092, reg_mtvec, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6718 = mux(T_6094, read_mip, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6720 = mux(T_6096, reg_mie, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6722 = mux(T_6098, reg_mideleg, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6724 = mux(T_6100, reg_medeleg, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6726 = mux(T_6102, reg_mscratch, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6728 = mux(T_6104, T_5965, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6730 = mux(T_6106, T_5971, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6732 = mux(T_6108, reg_mcause, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6734 = mux(T_6110, io.prci.id, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6736 = mux(T_6112, T_5987, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6738 = mux(T_6114, reg_dpc, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6740 = mux(T_6116, reg_dscratch, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6742 = mux(T_6118, reg_fflags, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6744 = mux(T_6120, reg_frm, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6746 = mux(T_6122, T_5988, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6748 = mux(T_6124, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6750 = mux(T_6126, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6752 = mux(T_6128, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6754 = mux(T_6130, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6756 = mux(T_6132, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6758 = mux(T_6134, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6760 = mux(T_6136, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6762 = mux(T_6138, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6764 = mux(T_6140, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6766 = mux(T_6142, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6768 = mux(T_6144, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6770 = mux(T_6146, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6772 = mux(T_6148, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6774 = mux(T_6150, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6776 = mux(T_6152, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6778 = mux(T_6154, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6780 = mux(T_6156, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6782 = mux(T_6158, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6784 = mux(T_6160, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6786 = mux(T_6162, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6788 = mux(T_6164, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6790 = mux(T_6166, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6792 = mux(T_6168, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6794 = mux(T_6170, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6796 = mux(T_6172, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6798 = mux(T_6174, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6800 = mux(T_6176, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6802 = mux(T_6178, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6804 = mux(T_6180, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6806 = mux(T_6182, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6808 = mux(T_6184, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6810 = mux(T_6186, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6812 = mux(T_6188, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6814 = mux(T_6190, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6816 = mux(T_6192, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6818 = mux(T_6194, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6820 = mux(T_6196, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6822 = mux(T_6198, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6824 = mux(T_6200, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6826 = mux(T_6202, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6828 = mux(T_6204, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6830 = mux(T_6206, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6832 = mux(T_6208, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6834 = mux(T_6210, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6836 = mux(T_6212, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6838 = mux(T_6214, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6840 = mux(T_6216, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6842 = mux(T_6218, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6844 = mux(T_6220, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6846 = mux(T_6222, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6848 = mux(T_6224, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6850 = mux(T_6226, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6852 = mux(T_6228, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6854 = mux(T_6230, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6856 = mux(T_6232, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6858 = mux(T_6234, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6860 = mux(T_6236, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6862 = mux(T_6238, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6864 = mux(T_6240, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6866 = mux(T_6242, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6868 = mux(T_6244, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6870 = mux(T_6246, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6872 = mux(T_6248, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6874 = mux(T_6250, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6876 = mux(T_6252, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6878 = mux(T_6254, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6880 = mux(T_6256, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6882 = mux(T_6258, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6884 = mux(T_6260, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6886 = mux(T_6262, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6888 = mux(T_6264, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6890 = mux(T_6266, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6892 = mux(T_6268, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6894 = mux(T_6270, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6896 = mux(T_6272, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6898 = mux(T_6274, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6900 = mux(T_6276, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6902 = mux(T_6278, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6904 = mux(T_6280, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6906 = mux(T_6282, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6908 = mux(T_6284, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6910 = mux(T_6286, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6912 = mux(T_6288, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6914 = mux(T_6290, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6916 = mux(T_6292, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6918 = mux(T_6294, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6920 = mux(T_6296, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 18:72] - node T_6922 = mux(T_6298, T_6051, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6924 = mux(T_6300, T_5992, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6926 = mux(T_6302, T_5991, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6928 = mux(T_6304, reg_sscratch, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6930 = mux(T_6306, reg_scause, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6932 = mux(T_6308, T_6057, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6934 = mux(T_6310, T_6058, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6936 = mux(T_6312, T_6064, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6938 = mux(T_6314, T_6070, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6940 = mux(T_6316, reg_mscounteren, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6942 = mux(T_6318, reg_mucounteren, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6944 = mux(T_6320, T_5619, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6946 = mux(T_6322, T_5608, UInt<1>("h00")) @[Mux.scala 18:72] - node T_6948 = or(T_6696, T_6698) @[Mux.scala 18:72] - node T_6949 = or(T_6948, T_6700) @[Mux.scala 18:72] - node T_6950 = or(T_6949, T_6702) @[Mux.scala 18:72] - node T_6951 = or(T_6950, T_6704) @[Mux.scala 18:72] - node T_6952 = or(T_6951, T_6706) @[Mux.scala 18:72] - node T_6953 = or(T_6952, T_6708) @[Mux.scala 18:72] - node T_6954 = or(T_6953, T_6710) @[Mux.scala 18:72] - node T_6955 = or(T_6954, T_6712) @[Mux.scala 18:72] - node T_6956 = or(T_6955, T_6714) @[Mux.scala 18:72] - node T_6957 = or(T_6956, T_6716) @[Mux.scala 18:72] - node T_6958 = or(T_6957, T_6718) @[Mux.scala 18:72] - node T_6959 = or(T_6958, T_6720) @[Mux.scala 18:72] - node T_6960 = or(T_6959, T_6722) @[Mux.scala 18:72] - node T_6961 = or(T_6960, T_6724) @[Mux.scala 18:72] - node T_6962 = or(T_6961, T_6726) @[Mux.scala 18:72] - node T_6963 = or(T_6962, T_6728) @[Mux.scala 18:72] - node T_6964 = or(T_6963, T_6730) @[Mux.scala 18:72] - node T_6965 = or(T_6964, T_6732) @[Mux.scala 18:72] - node T_6966 = or(T_6965, T_6734) @[Mux.scala 18:72] - node T_6967 = or(T_6966, T_6736) @[Mux.scala 18:72] - node T_6968 = or(T_6967, T_6738) @[Mux.scala 18:72] - node T_6969 = or(T_6968, T_6740) @[Mux.scala 18:72] - node T_6970 = or(T_6969, T_6742) @[Mux.scala 18:72] - node T_6971 = or(T_6970, T_6744) @[Mux.scala 18:72] - node T_6972 = or(T_6971, T_6746) @[Mux.scala 18:72] - node T_6973 = or(T_6972, T_6748) @[Mux.scala 18:72] - node T_6974 = or(T_6973, T_6750) @[Mux.scala 18:72] - node T_6975 = or(T_6974, T_6752) @[Mux.scala 18:72] - node T_6976 = or(T_6975, T_6754) @[Mux.scala 18:72] - node T_6977 = or(T_6976, T_6756) @[Mux.scala 18:72] - node T_6978 = or(T_6977, T_6758) @[Mux.scala 18:72] - node T_6979 = or(T_6978, T_6760) @[Mux.scala 18:72] - node T_6980 = or(T_6979, T_6762) @[Mux.scala 18:72] - node T_6981 = or(T_6980, T_6764) @[Mux.scala 18:72] - node T_6982 = or(T_6981, T_6766) @[Mux.scala 18:72] - node T_6983 = or(T_6982, T_6768) @[Mux.scala 18:72] - node T_6984 = or(T_6983, T_6770) @[Mux.scala 18:72] - node T_6985 = or(T_6984, T_6772) @[Mux.scala 18:72] - node T_6986 = or(T_6985, T_6774) @[Mux.scala 18:72] - node T_6987 = or(T_6986, T_6776) @[Mux.scala 18:72] - node T_6988 = or(T_6987, T_6778) @[Mux.scala 18:72] - node T_6989 = or(T_6988, T_6780) @[Mux.scala 18:72] - node T_6990 = or(T_6989, T_6782) @[Mux.scala 18:72] - node T_6991 = or(T_6990, T_6784) @[Mux.scala 18:72] - node T_6992 = or(T_6991, T_6786) @[Mux.scala 18:72] - node T_6993 = or(T_6992, T_6788) @[Mux.scala 18:72] - node T_6994 = or(T_6993, T_6790) @[Mux.scala 18:72] - node T_6995 = or(T_6994, T_6792) @[Mux.scala 18:72] - node T_6996 = or(T_6995, T_6794) @[Mux.scala 18:72] - node T_6997 = or(T_6996, T_6796) @[Mux.scala 18:72] - node T_6998 = or(T_6997, T_6798) @[Mux.scala 18:72] - node T_6999 = or(T_6998, T_6800) @[Mux.scala 18:72] - node T_7000 = or(T_6999, T_6802) @[Mux.scala 18:72] - node T_7001 = or(T_7000, T_6804) @[Mux.scala 18:72] - node T_7002 = or(T_7001, T_6806) @[Mux.scala 18:72] - node T_7003 = or(T_7002, T_6808) @[Mux.scala 18:72] - node T_7004 = or(T_7003, T_6810) @[Mux.scala 18:72] - node T_7005 = or(T_7004, T_6812) @[Mux.scala 18:72] - node T_7006 = or(T_7005, T_6814) @[Mux.scala 18:72] - node T_7007 = or(T_7006, T_6816) @[Mux.scala 18:72] - node T_7008 = or(T_7007, T_6818) @[Mux.scala 18:72] - node T_7009 = or(T_7008, T_6820) @[Mux.scala 18:72] - node T_7010 = or(T_7009, T_6822) @[Mux.scala 18:72] - node T_7011 = or(T_7010, T_6824) @[Mux.scala 18:72] - node T_7012 = or(T_7011, T_6826) @[Mux.scala 18:72] - node T_7013 = or(T_7012, T_6828) @[Mux.scala 18:72] - node T_7014 = or(T_7013, T_6830) @[Mux.scala 18:72] - node T_7015 = or(T_7014, T_6832) @[Mux.scala 18:72] - node T_7016 = or(T_7015, T_6834) @[Mux.scala 18:72] - node T_7017 = or(T_7016, T_6836) @[Mux.scala 18:72] - node T_7018 = or(T_7017, T_6838) @[Mux.scala 18:72] - node T_7019 = or(T_7018, T_6840) @[Mux.scala 18:72] - node T_7020 = or(T_7019, T_6842) @[Mux.scala 18:72] - node T_7021 = or(T_7020, T_6844) @[Mux.scala 18:72] - node T_7022 = or(T_7021, T_6846) @[Mux.scala 18:72] - node T_7023 = or(T_7022, T_6848) @[Mux.scala 18:72] - node T_7024 = or(T_7023, T_6850) @[Mux.scala 18:72] - node T_7025 = or(T_7024, T_6852) @[Mux.scala 18:72] - node T_7026 = or(T_7025, T_6854) @[Mux.scala 18:72] - node T_7027 = or(T_7026, T_6856) @[Mux.scala 18:72] - node T_7028 = or(T_7027, T_6858) @[Mux.scala 18:72] - node T_7029 = or(T_7028, T_6860) @[Mux.scala 18:72] - node T_7030 = or(T_7029, T_6862) @[Mux.scala 18:72] - node T_7031 = or(T_7030, T_6864) @[Mux.scala 18:72] - node T_7032 = or(T_7031, T_6866) @[Mux.scala 18:72] - node T_7033 = or(T_7032, T_6868) @[Mux.scala 18:72] - node T_7034 = or(T_7033, T_6870) @[Mux.scala 18:72] - node T_7035 = or(T_7034, T_6872) @[Mux.scala 18:72] - node T_7036 = or(T_7035, T_6874) @[Mux.scala 18:72] - node T_7037 = or(T_7036, T_6876) @[Mux.scala 18:72] - node T_7038 = or(T_7037, T_6878) @[Mux.scala 18:72] - node T_7039 = or(T_7038, T_6880) @[Mux.scala 18:72] - node T_7040 = or(T_7039, T_6882) @[Mux.scala 18:72] - node T_7041 = or(T_7040, T_6884) @[Mux.scala 18:72] - node T_7042 = or(T_7041, T_6886) @[Mux.scala 18:72] - node T_7043 = or(T_7042, T_6888) @[Mux.scala 18:72] - node T_7044 = or(T_7043, T_6890) @[Mux.scala 18:72] - node T_7045 = or(T_7044, T_6892) @[Mux.scala 18:72] - node T_7046 = or(T_7045, T_6894) @[Mux.scala 18:72] - node T_7047 = or(T_7046, T_6896) @[Mux.scala 18:72] - node T_7048 = or(T_7047, T_6898) @[Mux.scala 18:72] - node T_7049 = or(T_7048, T_6900) @[Mux.scala 18:72] - node T_7050 = or(T_7049, T_6902) @[Mux.scala 18:72] - node T_7051 = or(T_7050, T_6904) @[Mux.scala 18:72] - node T_7052 = or(T_7051, T_6906) @[Mux.scala 18:72] - node T_7053 = or(T_7052, T_6908) @[Mux.scala 18:72] - node T_7054 = or(T_7053, T_6910) @[Mux.scala 18:72] - node T_7055 = or(T_7054, T_6912) @[Mux.scala 18:72] - node T_7056 = or(T_7055, T_6914) @[Mux.scala 18:72] - node T_7057 = or(T_7056, T_6916) @[Mux.scala 18:72] - node T_7058 = or(T_7057, T_6918) @[Mux.scala 18:72] - node T_7059 = or(T_7058, T_6920) @[Mux.scala 18:72] - node T_7060 = or(T_7059, T_6922) @[Mux.scala 18:72] - node T_7061 = or(T_7060, T_6924) @[Mux.scala 18:72] - node T_7062 = or(T_7061, T_6926) @[Mux.scala 18:72] - node T_7063 = or(T_7062, T_6928) @[Mux.scala 18:72] - node T_7064 = or(T_7063, T_6930) @[Mux.scala 18:72] - node T_7065 = or(T_7064, T_6932) @[Mux.scala 18:72] - node T_7066 = or(T_7065, T_6934) @[Mux.scala 18:72] - node T_7067 = or(T_7066, T_6936) @[Mux.scala 18:72] - node T_7068 = or(T_7067, T_6938) @[Mux.scala 18:72] - node T_7069 = or(T_7068, T_6940) @[Mux.scala 18:72] - node T_7070 = or(T_7069, T_6942) @[Mux.scala 18:72] - node T_7071 = or(T_7070, T_6944) @[Mux.scala 18:72] - node T_7072 = or(T_7071, T_6946) @[Mux.scala 18:72] + T_5993.vm <= UInt<1>("h0") + T_5993.mprv <= UInt<1>("h0") + T_5993.mpp <= UInt<1>("h0") + T_5993.hpp <= UInt<1>("h0") + T_5993.mpie <= UInt<1>("h0") + T_5993.hpie <= UInt<1>("h0") + T_5993.mie <= UInt<1>("h0") + T_5993.hie <= UInt<1>("h0") + node T_6027 = cat(T_5993.hie, T_5993.sie) + node T_6028 = cat(T_6027, T_5993.uie) + node T_6029 = cat(T_5993.spie, T_5993.upie) + node T_6030 = cat(T_6029, T_5993.mie) + node T_6031 = cat(T_6030, T_6028) + node T_6032 = cat(T_5993.spp, T_5993.mpie) + node T_6033 = cat(T_6032, T_5993.hpie) + node T_6034 = cat(T_5993.fs, T_5993.mpp) + node T_6035 = cat(T_6034, T_5993.hpp) + node T_6036 = cat(T_6035, T_6033) + node T_6037 = cat(T_6036, T_6031) + node T_6038 = cat(T_5993.pum, T_5993.mprv) + node T_6039 = cat(T_6038, T_5993.xs) + node T_6040 = cat(T_5993.vm, T_5993.zero1) + node T_6041 = cat(T_6040, T_5993.mxr) + node T_6042 = cat(T_6041, T_6039) + node T_6043 = cat(T_5993.zero3, T_5993.sd_rv32) + node T_6044 = cat(T_6043, T_5993.zero2) + node T_6045 = cat(T_5993.prv, T_5993.sd) + node T_6046 = cat(T_5993.debug, T_5993.isa) + node T_6047 = cat(T_6046, T_6045) + node T_6048 = cat(T_6047, T_6044) + node T_6049 = cat(T_6048, T_6042) + node T_6050 = cat(T_6049, T_6037) + node T_6051 = bits(T_6050, 63, 0) + node T_6052 = bits(reg_sbadaddr, 39, 39) + node T_6053 = bits(T_6052, 0, 0) + node T_6056 = mux(T_6053, UInt<24>("hffffff"), UInt<24>("h0")) + node T_6057 = cat(T_6056, reg_sbadaddr) + node T_6058 = cat(reg_sptbr.asid, reg_sptbr.ppn) + node T_6059 = bits(reg_sepc, 39, 39) + node T_6060 = bits(T_6059, 0, 0) + node T_6063 = mux(T_6060, UInt<24>("hffffff"), UInt<24>("h0")) + node T_6064 = cat(T_6063, reg_sepc) + node T_6065 = bits(reg_stvec, 38, 38) + node T_6066 = bits(T_6065, 0, 0) + node T_6069 = mux(T_6066, UInt<25>("h1ffffff"), UInt<25>("h0")) + node T_6070 = cat(T_6069, reg_stvec) + node T_6072 = eq(io.rw.addr, UInt<11>("h7a0")) + node T_6074 = eq(io.rw.addr, UInt<11>("h7a1")) + node T_6076 = eq(io.rw.addr, UInt<11>("h7a2")) + node T_6078 = eq(io.rw.addr, UInt<12>("hf13")) + node T_6080 = eq(io.rw.addr, UInt<12>("hf12")) + node T_6082 = eq(io.rw.addr, UInt<12>("hf11")) + node T_6084 = eq(io.rw.addr, UInt<12>("hb00")) + node T_6086 = eq(io.rw.addr, UInt<12>("hb02")) + node T_6088 = eq(io.rw.addr, UInt<10>("h301")) + node T_6090 = eq(io.rw.addr, UInt<10>("h300")) + node T_6092 = eq(io.rw.addr, UInt<10>("h305")) + node T_6094 = eq(io.rw.addr, UInt<10>("h344")) + node T_6096 = eq(io.rw.addr, UInt<10>("h304")) + node T_6098 = eq(io.rw.addr, UInt<10>("h303")) + node T_6100 = eq(io.rw.addr, UInt<10>("h302")) + node T_6102 = eq(io.rw.addr, UInt<10>("h340")) + node T_6104 = eq(io.rw.addr, UInt<10>("h341")) + node T_6106 = eq(io.rw.addr, UInt<10>("h343")) + node T_6108 = eq(io.rw.addr, UInt<10>("h342")) + node T_6110 = eq(io.rw.addr, UInt<12>("hf14")) + node T_6112 = eq(io.rw.addr, UInt<11>("h7b0")) + node T_6114 = eq(io.rw.addr, UInt<11>("h7b1")) + node T_6116 = eq(io.rw.addr, UInt<11>("h7b2")) + node T_6118 = eq(io.rw.addr, UInt<1>("h1")) + node T_6120 = eq(io.rw.addr, UInt<2>("h2")) + node T_6122 = eq(io.rw.addr, UInt<2>("h3")) + node T_6124 = eq(io.rw.addr, UInt<10>("h323")) + node T_6126 = eq(io.rw.addr, UInt<12>("hb03")) + node T_6128 = eq(io.rw.addr, UInt<12>("hc03")) + node T_6130 = eq(io.rw.addr, UInt<10>("h324")) + node T_6132 = eq(io.rw.addr, UInt<12>("hb04")) + node T_6134 = eq(io.rw.addr, UInt<12>("hc04")) + node T_6136 = eq(io.rw.addr, UInt<10>("h325")) + node T_6138 = eq(io.rw.addr, UInt<12>("hb05")) + node T_6140 = eq(io.rw.addr, UInt<12>("hc05")) + node T_6142 = eq(io.rw.addr, UInt<10>("h326")) + node T_6144 = eq(io.rw.addr, UInt<12>("hb06")) + node T_6146 = eq(io.rw.addr, UInt<12>("hc06")) + node T_6148 = eq(io.rw.addr, UInt<10>("h327")) + node T_6150 = eq(io.rw.addr, UInt<12>("hb07")) + node T_6152 = eq(io.rw.addr, UInt<12>("hc07")) + node T_6154 = eq(io.rw.addr, UInt<10>("h328")) + node T_6156 = eq(io.rw.addr, UInt<12>("hb08")) + node T_6158 = eq(io.rw.addr, UInt<12>("hc08")) + node T_6160 = eq(io.rw.addr, UInt<10>("h329")) + node T_6162 = eq(io.rw.addr, UInt<12>("hb09")) + node T_6164 = eq(io.rw.addr, UInt<12>("hc09")) + node T_6166 = eq(io.rw.addr, UInt<10>("h32a")) + node T_6168 = eq(io.rw.addr, UInt<12>("hb0a")) + node T_6170 = eq(io.rw.addr, UInt<12>("hc0a")) + node T_6172 = eq(io.rw.addr, UInt<10>("h32b")) + node T_6174 = eq(io.rw.addr, UInt<12>("hb0b")) + node T_6176 = eq(io.rw.addr, UInt<12>("hc0b")) + node T_6178 = eq(io.rw.addr, UInt<10>("h32c")) + node T_6180 = eq(io.rw.addr, UInt<12>("hb0c")) + node T_6182 = eq(io.rw.addr, UInt<12>("hc0c")) + node T_6184 = eq(io.rw.addr, UInt<10>("h32d")) + node T_6186 = eq(io.rw.addr, UInt<12>("hb0d")) + node T_6188 = eq(io.rw.addr, UInt<12>("hc0d")) + node T_6190 = eq(io.rw.addr, UInt<10>("h32e")) + node T_6192 = eq(io.rw.addr, UInt<12>("hb0e")) + node T_6194 = eq(io.rw.addr, UInt<12>("hc0e")) + node T_6196 = eq(io.rw.addr, UInt<10>("h32f")) + node T_6198 = eq(io.rw.addr, UInt<12>("hb0f")) + node T_6200 = eq(io.rw.addr, UInt<12>("hc0f")) + node T_6202 = eq(io.rw.addr, UInt<10>("h330")) + node T_6204 = eq(io.rw.addr, UInt<12>("hb10")) + node T_6206 = eq(io.rw.addr, UInt<12>("hc10")) + node T_6208 = eq(io.rw.addr, UInt<10>("h331")) + node T_6210 = eq(io.rw.addr, UInt<12>("hb11")) + node T_6212 = eq(io.rw.addr, UInt<12>("hc11")) + node T_6214 = eq(io.rw.addr, UInt<10>("h332")) + node T_6216 = eq(io.rw.addr, UInt<12>("hb12")) + node T_6218 = eq(io.rw.addr, UInt<12>("hc12")) + node T_6220 = eq(io.rw.addr, UInt<10>("h333")) + node T_6222 = eq(io.rw.addr, UInt<12>("hb13")) + node T_6224 = eq(io.rw.addr, UInt<12>("hc13")) + node T_6226 = eq(io.rw.addr, UInt<10>("h334")) + node T_6228 = eq(io.rw.addr, UInt<12>("hb14")) + node T_6230 = eq(io.rw.addr, UInt<12>("hc14")) + node T_6232 = eq(io.rw.addr, UInt<10>("h335")) + node T_6234 = eq(io.rw.addr, UInt<12>("hb15")) + node T_6236 = eq(io.rw.addr, UInt<12>("hc15")) + node T_6238 = eq(io.rw.addr, UInt<10>("h336")) + node T_6240 = eq(io.rw.addr, UInt<12>("hb16")) + node T_6242 = eq(io.rw.addr, UInt<12>("hc16")) + node T_6244 = eq(io.rw.addr, UInt<10>("h337")) + node T_6246 = eq(io.rw.addr, UInt<12>("hb17")) + node T_6248 = eq(io.rw.addr, UInt<12>("hc17")) + node T_6250 = eq(io.rw.addr, UInt<10>("h338")) + node T_6252 = eq(io.rw.addr, UInt<12>("hb18")) + node T_6254 = eq(io.rw.addr, UInt<12>("hc18")) + node T_6256 = eq(io.rw.addr, UInt<10>("h339")) + node T_6258 = eq(io.rw.addr, UInt<12>("hb19")) + node T_6260 = eq(io.rw.addr, UInt<12>("hc19")) + node T_6262 = eq(io.rw.addr, UInt<10>("h33a")) + node T_6264 = eq(io.rw.addr, UInt<12>("hb1a")) + node T_6266 = eq(io.rw.addr, UInt<12>("hc1a")) + node T_6268 = eq(io.rw.addr, UInt<10>("h33b")) + node T_6270 = eq(io.rw.addr, UInt<12>("hb1b")) + node T_6272 = eq(io.rw.addr, UInt<12>("hc1b")) + node T_6274 = eq(io.rw.addr, UInt<10>("h33c")) + node T_6276 = eq(io.rw.addr, UInt<12>("hb1c")) + node T_6278 = eq(io.rw.addr, UInt<12>("hc1c")) + node T_6280 = eq(io.rw.addr, UInt<10>("h33d")) + node T_6282 = eq(io.rw.addr, UInt<12>("hb1d")) + node T_6284 = eq(io.rw.addr, UInt<12>("hc1d")) + node T_6286 = eq(io.rw.addr, UInt<10>("h33e")) + node T_6288 = eq(io.rw.addr, UInt<12>("hb1e")) + node T_6290 = eq(io.rw.addr, UInt<12>("hc1e")) + node T_6292 = eq(io.rw.addr, UInt<10>("h33f")) + node T_6294 = eq(io.rw.addr, UInt<12>("hb1f")) + node T_6296 = eq(io.rw.addr, UInt<12>("hc1f")) + node T_6298 = eq(io.rw.addr, UInt<9>("h100")) + node T_6300 = eq(io.rw.addr, UInt<9>("h144")) + node T_6302 = eq(io.rw.addr, UInt<9>("h104")) + node T_6304 = eq(io.rw.addr, UInt<9>("h140")) + node T_6306 = eq(io.rw.addr, UInt<9>("h142")) + node T_6308 = eq(io.rw.addr, UInt<9>("h143")) + node T_6310 = eq(io.rw.addr, UInt<9>("h180")) + node T_6312 = eq(io.rw.addr, UInt<9>("h141")) + node T_6314 = eq(io.rw.addr, UInt<9>("h105")) + node T_6316 = eq(io.rw.addr, UInt<10>("h321")) + node T_6318 = eq(io.rw.addr, UInt<10>("h320")) + node T_6320 = eq(io.rw.addr, UInt<12>("hc00")) + node T_6322 = eq(io.rw.addr, UInt<12>("hc02")) + node T_6323 = or(T_6072, T_6074) + node T_6324 = or(T_6323, T_6076) + node T_6325 = or(T_6324, T_6078) + node T_6326 = or(T_6325, T_6080) + node T_6327 = or(T_6326, T_6082) + node T_6328 = or(T_6327, T_6084) + node T_6329 = or(T_6328, T_6086) + node T_6330 = or(T_6329, T_6088) + node T_6331 = or(T_6330, T_6090) + node T_6332 = or(T_6331, T_6092) + node T_6333 = or(T_6332, T_6094) + node T_6334 = or(T_6333, T_6096) + node T_6335 = or(T_6334, T_6098) + node T_6336 = or(T_6335, T_6100) + node T_6337 = or(T_6336, T_6102) + node T_6338 = or(T_6337, T_6104) + node T_6339 = or(T_6338, T_6106) + node T_6340 = or(T_6339, T_6108) + node T_6341 = or(T_6340, T_6110) + node T_6342 = or(T_6341, T_6112) + node T_6343 = or(T_6342, T_6114) + node T_6344 = or(T_6343, T_6116) + node T_6345 = or(T_6344, T_6118) + node T_6346 = or(T_6345, T_6120) + node T_6347 = or(T_6346, T_6122) + node T_6348 = or(T_6347, T_6124) + node T_6349 = or(T_6348, T_6126) + node T_6350 = or(T_6349, T_6128) + node T_6351 = or(T_6350, T_6130) + node T_6352 = or(T_6351, T_6132) + node T_6353 = or(T_6352, T_6134) + node T_6354 = or(T_6353, T_6136) + node T_6355 = or(T_6354, T_6138) + node T_6356 = or(T_6355, T_6140) + node T_6357 = or(T_6356, T_6142) + node T_6358 = or(T_6357, T_6144) + node T_6359 = or(T_6358, T_6146) + node T_6360 = or(T_6359, T_6148) + node T_6361 = or(T_6360, T_6150) + node T_6362 = or(T_6361, T_6152) + node T_6363 = or(T_6362, T_6154) + node T_6364 = or(T_6363, T_6156) + node T_6365 = or(T_6364, T_6158) + node T_6366 = or(T_6365, T_6160) + node T_6367 = or(T_6366, T_6162) + node T_6368 = or(T_6367, T_6164) + node T_6369 = or(T_6368, T_6166) + node T_6370 = or(T_6369, T_6168) + node T_6371 = or(T_6370, T_6170) + node T_6372 = or(T_6371, T_6172) + node T_6373 = or(T_6372, T_6174) + node T_6374 = or(T_6373, T_6176) + node T_6375 = or(T_6374, T_6178) + node T_6376 = or(T_6375, T_6180) + node T_6377 = or(T_6376, T_6182) + node T_6378 = or(T_6377, T_6184) + node T_6379 = or(T_6378, T_6186) + node T_6380 = or(T_6379, T_6188) + node T_6381 = or(T_6380, T_6190) + node T_6382 = or(T_6381, T_6192) + node T_6383 = or(T_6382, T_6194) + node T_6384 = or(T_6383, T_6196) + node T_6385 = or(T_6384, T_6198) + node T_6386 = or(T_6385, T_6200) + node T_6387 = or(T_6386, T_6202) + node T_6388 = or(T_6387, T_6204) + node T_6389 = or(T_6388, T_6206) + node T_6390 = or(T_6389, T_6208) + node T_6391 = or(T_6390, T_6210) + node T_6392 = or(T_6391, T_6212) + node T_6393 = or(T_6392, T_6214) + node T_6394 = or(T_6393, T_6216) + node T_6395 = or(T_6394, T_6218) + node T_6396 = or(T_6395, T_6220) + node T_6397 = or(T_6396, T_6222) + node T_6398 = or(T_6397, T_6224) + node T_6399 = or(T_6398, T_6226) + node T_6400 = or(T_6399, T_6228) + node T_6401 = or(T_6400, T_6230) + node T_6402 = or(T_6401, T_6232) + node T_6403 = or(T_6402, T_6234) + node T_6404 = or(T_6403, T_6236) + node T_6405 = or(T_6404, T_6238) + node T_6406 = or(T_6405, T_6240) + node T_6407 = or(T_6406, T_6242) + node T_6408 = or(T_6407, T_6244) + node T_6409 = or(T_6408, T_6246) + node T_6410 = or(T_6409, T_6248) + node T_6411 = or(T_6410, T_6250) + node T_6412 = or(T_6411, T_6252) + node T_6413 = or(T_6412, T_6254) + node T_6414 = or(T_6413, T_6256) + node T_6415 = or(T_6414, T_6258) + node T_6416 = or(T_6415, T_6260) + node T_6417 = or(T_6416, T_6262) + node T_6418 = or(T_6417, T_6264) + node T_6419 = or(T_6418, T_6266) + node T_6420 = or(T_6419, T_6268) + node T_6421 = or(T_6420, T_6270) + node T_6422 = or(T_6421, T_6272) + node T_6423 = or(T_6422, T_6274) + node T_6424 = or(T_6423, T_6276) + node T_6425 = or(T_6424, T_6278) + node T_6426 = or(T_6425, T_6280) + node T_6427 = or(T_6426, T_6282) + node T_6428 = or(T_6427, T_6284) + node T_6429 = or(T_6428, T_6286) + node T_6430 = or(T_6429, T_6288) + node T_6431 = or(T_6430, T_6290) + node T_6432 = or(T_6431, T_6292) + node T_6433 = or(T_6432, T_6294) + node T_6434 = or(T_6433, T_6296) + node T_6435 = or(T_6434, T_6298) + node T_6436 = or(T_6435, T_6300) + node T_6437 = or(T_6436, T_6302) + node T_6438 = or(T_6437, T_6304) + node T_6439 = or(T_6438, T_6306) + node T_6440 = or(T_6439, T_6308) + node T_6441 = or(T_6440, T_6310) + node T_6442 = or(T_6441, T_6312) + node T_6443 = or(T_6442, T_6314) + node T_6444 = or(T_6443, T_6316) + node T_6445 = or(T_6444, T_6318) + node T_6446 = or(T_6445, T_6320) + node addr_valid = or(T_6446, T_6322) + node T_6447 = or(T_6118, T_6120) + node fp_csr = or(T_6447, T_6122) + node T_6449 = geq(io.rw.addr, UInt<12>("hc00")) + node T_6451 = lt(io.rw.addr, UInt<12>("hc20")) + node hpm_csr = and(T_6449, T_6451) + node T_6453 = eq(reg_mstatus.prv, UInt<2>("h3")) + node T_6454 = or(reg_debug, T_6453) + node T_6456 = eq(reg_mstatus.prv, UInt<1>("h1")) + node T_6457 = bits(io.rw.addr, 4, 0) + node T_6458 = dshr(reg_mscounteren, T_6457) + node T_6459 = bits(T_6458, 0, 0) + node T_6460 = and(T_6456, T_6459) + node T_6461 = or(T_6454, T_6460) + node T_6463 = eq(reg_mstatus.prv, UInt<1>("h0")) + node T_6464 = bits(io.rw.addr, 4, 0) + node T_6465 = dshr(reg_mucounteren, T_6464) + node T_6466 = bits(T_6465, 0, 0) + node T_6467 = and(T_6463, T_6466) + node hpm_en = or(T_6461, T_6467) + node csr_addr_priv = bits(io.rw.addr, 9, 8) + node T_6470 = and(io.rw.addr, UInt<8>("h90")) + node T_6472 = eq(T_6470, UInt<8>("h90")) + node csr_debug = and(UInt<1>("h1"), T_6472) + node T_6474 = eq(csr_debug, UInt<1>("h0")) + node T_6475 = geq(reg_mstatus.prv, csr_addr_priv) + node T_6476 = and(T_6474, T_6475) + node priv_sufficient = or(reg_debug, T_6476) + node T_6477 = bits(io.rw.addr, 11, 10) + node T_6478 = not(T_6477) + node read_only = eq(T_6478, UInt<1>("h0")) + node T_6480 = and(cpu_wen, priv_sufficient) + node T_6482 = eq(read_only, UInt<1>("h0")) + node wen = and(T_6480, T_6482) + node T_6483 = eq(io.rw.cmd, UInt<3>("h2")) + node T_6484 = eq(io.rw.cmd, UInt<3>("h3")) + node T_6485 = or(T_6483, T_6484) + node T_6487 = mux(T_6485, io.rw.rdata, UInt<1>("h0")) + node T_6488 = neq(io.rw.cmd, UInt<3>("h3")) + node T_6490 = mux(T_6488, io.rw.wdata, UInt<1>("h0")) + node T_6491 = or(T_6487, T_6490) + node T_6492 = eq(io.rw.cmd, UInt<3>("h3")) + node T_6494 = mux(T_6492, io.rw.wdata, UInt<1>("h0")) + node T_6495 = not(T_6494) + node wdata = and(T_6491, T_6495) + node do_system_insn = and(priv_sufficient, system_insn) + node T_6497 = bits(io.rw.addr, 2, 0) + node opcode = dshl(UInt<1>("h1"), T_6497) + node T_6498 = bits(opcode, 0, 0) + node insn_call = and(do_system_insn, T_6498) + node T_6499 = bits(opcode, 1, 1) + node insn_break = and(do_system_insn, T_6499) + node T_6500 = bits(opcode, 2, 2) + node insn_ret = and(do_system_insn, T_6500) + node T_6501 = bits(opcode, 4, 4) + node insn_sfence_vm = and(do_system_insn, T_6501) + node T_6502 = bits(opcode, 5, 5) + node insn_wfi = and(do_system_insn, T_6502) + node T_6503 = and(cpu_wen, read_only) + node T_6505 = eq(priv_sufficient, UInt<1>("h0")) + node T_6507 = eq(addr_valid, UInt<1>("h0")) + node T_6508 = or(T_6505, T_6507) + node T_6510 = eq(hpm_en, UInt<1>("h0")) + node T_6511 = and(hpm_csr, T_6510) + node T_6512 = or(T_6508, T_6511) + node T_6514 = neq(io.status.fs, UInt<1>("h0")) + node T_6515 = bits(reg_misa, 5, 5) + node T_6516 = and(T_6514, T_6515) + node T_6518 = eq(T_6516, UInt<1>("h0")) + node T_6519 = and(fp_csr, T_6518) + node T_6520 = or(T_6512, T_6519) + node T_6521 = and(cpu_ren, T_6520) + node T_6522 = or(T_6503, T_6521) + node T_6524 = eq(priv_sufficient, UInt<1>("h0")) + node T_6525 = and(system_insn, T_6524) + node T_6526 = or(T_6522, T_6525) + node T_6527 = or(T_6526, insn_call) + node T_6528 = or(T_6527, insn_break) + io.csr_xcpt <= T_6528 + when insn_wfi : + reg_wfi <= UInt<1>("h1") + node T_6531 = neq(pending_interrupts, UInt<1>("h0")) + when T_6531 : + reg_wfi <= UInt<1>("h0") + node T_6534 = eq(io.csr_xcpt, UInt<1>("h0")) + node T_6536 = add(reg_mstatus.prv, UInt<4>("h8")) + node T_6537 = tail(T_6536, 1) + node T_6540 = mux(insn_break, UInt<2>("h3"), UInt<2>("h2")) + node T_6541 = mux(insn_call, T_6537, T_6540) + node cause = mux(T_6534, io.cause, T_6541) + node cause_lsbs = bits(cause, 5, 0) + node T_6542 = bits(cause, 63, 63) + node T_6544 = eq(cause_lsbs, UInt<4>("hd")) + node causeIsDebugInt = and(T_6542, T_6544) + node T_6545 = bits(cause, 63, 63) + node T_6547 = eq(T_6545, UInt<1>("h0")) + node T_6549 = eq(cause_lsbs, UInt<4>("hd")) + node causeIsDebugTrigger = and(T_6547, T_6549) + node T_6550 = bits(cause, 63, 63) + node T_6552 = eq(T_6550, UInt<1>("h0")) + node T_6553 = and(T_6552, insn_break) + node T_6554 = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) + node T_6555 = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) + node T_6556 = cat(T_6555, T_6554) + node T_6557 = dshr(T_6556, reg_mstatus.prv) + node T_6558 = bits(T_6557, 0, 0) + node causeIsDebugBreak = and(T_6553, T_6558) + node T_6560 = or(reg_singleStepped, causeIsDebugInt) + node T_6561 = or(T_6560, causeIsDebugTrigger) + node T_6562 = or(T_6561, causeIsDebugBreak) + node T_6563 = or(T_6562, reg_debug) + node trapToDebug = and(UInt<1>("h1"), T_6563) + node T_6566 = lt(reg_mstatus.prv, UInt<2>("h3")) + node T_6567 = and(UInt<1>("h1"), T_6566) + node T_6568 = bits(cause, 63, 63) + node T_6569 = dshr(reg_mideleg, cause_lsbs) + node T_6570 = bits(T_6569, 0, 0) + node T_6571 = dshr(reg_medeleg, cause_lsbs) + node T_6572 = bits(T_6571, 0, 0) + node T_6573 = mux(T_6568, T_6570, T_6572) + node delegate = and(T_6567, T_6573) + node debugTVec = mux(reg_debug, UInt<12>("h808"), UInt<12>("h800")) + node T_6576 = bits(reg_stvec, 38, 38) + node T_6577 = cat(T_6576, reg_stvec) + node T_6578 = mux(delegate, T_6577, reg_mtvec) + node tvec = mux(trapToDebug, debugTVec, T_6578) + node T_6580 = bits(csr_addr_priv, 1, 1) + node T_6582 = eq(T_6580, UInt<1>("h0")) + node T_6583 = and(UInt<1>("h1"), T_6582) + node T_6584 = mux(T_6583, reg_sepc, reg_mepc) + node epc = mux(csr_debug, reg_dpc, T_6584) + io.fatc <= insn_sfence_vm + node T_6585 = mux(exception, tvec, epc) + io.evec <= T_6585 + io.ptbr <- reg_sptbr + io.eret <= insn_ret + node T_6587 = eq(reg_debug, UInt<1>("h0")) + node T_6588 = and(reg_dcsr.step, T_6587) + io.singleStep <= T_6588 + io.status <- reg_mstatus + node T_6589 = not(io.status.fs) + node T_6591 = eq(T_6589, UInt<1>("h0")) + node T_6592 = not(io.status.xs) + node T_6594 = eq(T_6592, UInt<1>("h0")) + node T_6595 = or(T_6591, T_6594) + io.status.sd <= T_6595 + io.status.debug <= reg_debug + io.status.isa <= reg_misa + when exception : + node T_6596 = not(io.pc) + node T_6598 = or(T_6596, UInt<1>("h1")) + node T_6599 = not(T_6598) + node T_6600 = dshr(read_mstatus, reg_mstatus.prv) + node T_6601 = bits(T_6600, 0, 0) + node T_6609 = eq(cause, UInt<2>("h3")) + node T_6610 = eq(cause, UInt<3>("h4")) + node T_6611 = eq(cause, UInt<3>("h6")) + node T_6612 = eq(cause, UInt<1>("h0")) + node T_6613 = eq(cause, UInt<3>("h5")) + node T_6614 = eq(cause, UInt<3>("h7")) + node T_6615 = eq(cause, UInt<1>("h1")) + node T_6616 = or(T_6609, T_6610) + node T_6617 = or(T_6616, T_6611) + node T_6618 = or(T_6617, T_6612) + node T_6619 = or(T_6618, T_6613) + node T_6620 = or(T_6619, T_6614) + node T_6621 = or(T_6620, T_6615) + when trapToDebug : + reg_debug <= UInt<1>("h1") + reg_dpc <= T_6599 + node T_6627 = mux(causeIsDebugTrigger, UInt<2>("h2"), UInt<1>("h1")) + node T_6628 = mux(causeIsDebugInt, UInt<2>("h3"), T_6627) + node T_6629 = mux(reg_singleStepped, UInt<3>("h4"), T_6628) + reg_dcsr.cause <= T_6629 + reg_dcsr.prv <= reg_mstatus.prv + node T_6631 = eq(trapToDebug, UInt<1>("h0")) + node T_6632 = and(T_6631, delegate) + when T_6632 : + node T_6633 = not(T_6599) + node T_6634 = bits(reg_misa, 2, 2) + node T_6636 = eq(T_6634, UInt<1>("h0")) + node T_6638 = cat(T_6636, UInt<1>("h1")) + node T_6639 = or(T_6633, T_6638) + node T_6640 = not(T_6639) + reg_sepc <= T_6640 + reg_scause <= cause + when T_6621 : + reg_sbadaddr <= io.badaddr + reg_mstatus.spie <= T_6601 + reg_mstatus.spp <= reg_mstatus.prv + reg_mstatus.sie <= UInt<1>("h0") + new_prv <= UInt<1>("h1") + node T_6644 = eq(trapToDebug, UInt<1>("h0")) + node T_6646 = eq(delegate, UInt<1>("h0")) + node T_6647 = and(T_6644, T_6646) + when T_6647 : + node T_6648 = not(T_6599) + node T_6649 = bits(reg_misa, 2, 2) + node T_6651 = eq(T_6649, UInt<1>("h0")) + node T_6653 = cat(T_6651, UInt<1>("h1")) + node T_6654 = or(T_6648, T_6653) + node T_6655 = not(T_6654) + reg_mepc <= T_6655 + reg_mcause <= cause + when T_6621 : + reg_mbadaddr <= io.badaddr + reg_mstatus.mpie <= T_6601 + reg_mstatus.mpp <= reg_mstatus.prv + reg_mstatus.mie <= UInt<1>("h0") + new_prv <= UInt<2>("h3") + when insn_ret : + node T_6659 = bits(csr_addr_priv, 1, 1) + node T_6661 = eq(T_6659, UInt<1>("h0")) + node T_6662 = and(UInt<1>("h1"), T_6661) + when T_6662 : + node T_6663 = bits(reg_mstatus.spp, 0, 0) + when T_6663 : + reg_mstatus.sie <= reg_mstatus.spie + reg_mstatus.spie <= UInt<1>("h0") + reg_mstatus.spp <= UInt<1>("h0") + new_prv <= reg_mstatus.spp + node T_6667 = eq(T_6662, UInt<1>("h0")) + node T_6668 = and(T_6667, csr_debug) + when T_6668 : + new_prv <= reg_dcsr.prv + reg_debug <= UInt<1>("h0") + node T_6671 = eq(T_6662, UInt<1>("h0")) + node T_6673 = eq(csr_debug, UInt<1>("h0")) + node T_6674 = and(T_6671, T_6673) + when T_6674 : + node T_6675 = bits(reg_mstatus.mpp, 1, 1) + when T_6675 : + reg_mstatus.mie <= reg_mstatus.mpie + node T_6677 = bits(reg_mstatus.mpp, 0, 0) + node T_6678 = and(UInt<1>("h1"), T_6677) + node T_6680 = eq(T_6675, UInt<1>("h0")) + node T_6681 = and(T_6680, T_6678) + when T_6681 : + reg_mstatus.sie <= reg_mstatus.mpie + reg_mstatus.mpie <= UInt<1>("h0") + node T_6685 = eq(UInt<1>("h0"), UInt<2>("h2")) + node T_6687 = mux(T_6685, UInt<1>("h0"), UInt<1>("h0")) + reg_mstatus.mpp <= T_6687 + new_prv <= reg_mstatus.mpp + node T_6688 = add(io.exception, io.csr_xcpt) + node T_6689 = add(insn_ret, T_6688) + node T_6691 = leq(T_6689, UInt<1>("h1")) + node T_6692 = or(T_6691, reset) + node T_6694 = eq(T_6692, UInt<1>("h0")) + when T_6694 : + printf(clk, UInt<1>("h1"), "Assertion failed: these conditions must be mutually exclusive\n at csr.scala:484 assert(PopCount(insn_ret :: io.exception :: io.csr_xcpt :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n") + stop(clk, UInt<1>("h1"), 1) + io.time <= T_5619 + io.csr_stall <= reg_wfi + node T_6696 = mux(T_6072, reg_tselect, UInt<1>("h0")) + node T_6698 = mux(T_6074, T_5933, UInt<1>("h0")) + node T_6700 = mux(T_6076, T_5956, UInt<1>("h0")) + node T_6702 = mux(T_6078, UInt<1>("h0"), UInt<1>("h0")) + node T_6704 = mux(T_6080, UInt<1>("h0"), UInt<1>("h0")) + node T_6706 = mux(T_6082, UInt<1>("h0"), UInt<1>("h0")) + node T_6708 = mux(T_6084, T_5619, UInt<1>("h0")) + node T_6710 = mux(T_6086, T_5608, UInt<1>("h0")) + node T_6712 = mux(T_6088, reg_misa, UInt<1>("h0")) + node T_6714 = mux(T_6090, read_mstatus, UInt<1>("h0")) + node T_6716 = mux(T_6092, reg_mtvec, UInt<1>("h0")) + node T_6718 = mux(T_6094, read_mip, UInt<1>("h0")) + node T_6720 = mux(T_6096, reg_mie, UInt<1>("h0")) + node T_6722 = mux(T_6098, reg_mideleg, UInt<1>("h0")) + node T_6724 = mux(T_6100, reg_medeleg, UInt<1>("h0")) + node T_6726 = mux(T_6102, reg_mscratch, UInt<1>("h0")) + node T_6728 = mux(T_6104, T_5965, UInt<1>("h0")) + node T_6730 = mux(T_6106, T_5971, UInt<1>("h0")) + node T_6732 = mux(T_6108, reg_mcause, UInt<1>("h0")) + node T_6734 = mux(T_6110, io.prci.id, UInt<1>("h0")) + node T_6736 = mux(T_6112, T_5987, UInt<1>("h0")) + node T_6738 = mux(T_6114, reg_dpc, UInt<1>("h0")) + node T_6740 = mux(T_6116, reg_dscratch, UInt<1>("h0")) + node T_6742 = mux(T_6118, reg_fflags, UInt<1>("h0")) + node T_6744 = mux(T_6120, reg_frm, UInt<1>("h0")) + node T_6746 = mux(T_6122, T_5988, UInt<1>("h0")) + node T_6748 = mux(T_6124, UInt<1>("h0"), UInt<1>("h0")) + node T_6750 = mux(T_6126, UInt<1>("h0"), UInt<1>("h0")) + node T_6752 = mux(T_6128, UInt<1>("h0"), UInt<1>("h0")) + node T_6754 = mux(T_6130, UInt<1>("h0"), UInt<1>("h0")) + node T_6756 = mux(T_6132, UInt<1>("h0"), UInt<1>("h0")) + node T_6758 = mux(T_6134, UInt<1>("h0"), UInt<1>("h0")) + node T_6760 = mux(T_6136, UInt<1>("h0"), UInt<1>("h0")) + node T_6762 = mux(T_6138, UInt<1>("h0"), UInt<1>("h0")) + node T_6764 = mux(T_6140, UInt<1>("h0"), UInt<1>("h0")) + node T_6766 = mux(T_6142, UInt<1>("h0"), UInt<1>("h0")) + node T_6768 = mux(T_6144, UInt<1>("h0"), UInt<1>("h0")) + node T_6770 = mux(T_6146, UInt<1>("h0"), UInt<1>("h0")) + node T_6772 = mux(T_6148, UInt<1>("h0"), UInt<1>("h0")) + node T_6774 = mux(T_6150, UInt<1>("h0"), UInt<1>("h0")) + node T_6776 = mux(T_6152, UInt<1>("h0"), UInt<1>("h0")) + node T_6778 = mux(T_6154, UInt<1>("h0"), UInt<1>("h0")) + node T_6780 = mux(T_6156, UInt<1>("h0"), UInt<1>("h0")) + node T_6782 = mux(T_6158, UInt<1>("h0"), UInt<1>("h0")) + node T_6784 = mux(T_6160, UInt<1>("h0"), UInt<1>("h0")) + node T_6786 = mux(T_6162, UInt<1>("h0"), UInt<1>("h0")) + node T_6788 = mux(T_6164, UInt<1>("h0"), UInt<1>("h0")) + node T_6790 = mux(T_6166, UInt<1>("h0"), UInt<1>("h0")) + node T_6792 = mux(T_6168, UInt<1>("h0"), UInt<1>("h0")) + node T_6794 = mux(T_6170, UInt<1>("h0"), UInt<1>("h0")) + node T_6796 = mux(T_6172, UInt<1>("h0"), UInt<1>("h0")) + node T_6798 = mux(T_6174, UInt<1>("h0"), UInt<1>("h0")) + node T_6800 = mux(T_6176, UInt<1>("h0"), UInt<1>("h0")) + node T_6802 = mux(T_6178, UInt<1>("h0"), UInt<1>("h0")) + node T_6804 = mux(T_6180, UInt<1>("h0"), UInt<1>("h0")) + node T_6806 = mux(T_6182, UInt<1>("h0"), UInt<1>("h0")) + node T_6808 = mux(T_6184, UInt<1>("h0"), UInt<1>("h0")) + node T_6810 = mux(T_6186, UInt<1>("h0"), UInt<1>("h0")) + node T_6812 = mux(T_6188, UInt<1>("h0"), UInt<1>("h0")) + node T_6814 = mux(T_6190, UInt<1>("h0"), UInt<1>("h0")) + node T_6816 = mux(T_6192, UInt<1>("h0"), UInt<1>("h0")) + node T_6818 = mux(T_6194, UInt<1>("h0"), UInt<1>("h0")) + node T_6820 = mux(T_6196, UInt<1>("h0"), UInt<1>("h0")) + node T_6822 = mux(T_6198, UInt<1>("h0"), UInt<1>("h0")) + node T_6824 = mux(T_6200, UInt<1>("h0"), UInt<1>("h0")) + node T_6826 = mux(T_6202, UInt<1>("h0"), UInt<1>("h0")) + node T_6828 = mux(T_6204, UInt<1>("h0"), UInt<1>("h0")) + node T_6830 = mux(T_6206, UInt<1>("h0"), UInt<1>("h0")) + node T_6832 = mux(T_6208, UInt<1>("h0"), UInt<1>("h0")) + node T_6834 = mux(T_6210, UInt<1>("h0"), UInt<1>("h0")) + node T_6836 = mux(T_6212, UInt<1>("h0"), UInt<1>("h0")) + node T_6838 = mux(T_6214, UInt<1>("h0"), UInt<1>("h0")) + node T_6840 = mux(T_6216, UInt<1>("h0"), UInt<1>("h0")) + node T_6842 = mux(T_6218, UInt<1>("h0"), UInt<1>("h0")) + node T_6844 = mux(T_6220, UInt<1>("h0"), UInt<1>("h0")) + node T_6846 = mux(T_6222, UInt<1>("h0"), UInt<1>("h0")) + node T_6848 = mux(T_6224, UInt<1>("h0"), UInt<1>("h0")) + node T_6850 = mux(T_6226, UInt<1>("h0"), UInt<1>("h0")) + node T_6852 = mux(T_6228, UInt<1>("h0"), UInt<1>("h0")) + node T_6854 = mux(T_6230, UInt<1>("h0"), UInt<1>("h0")) + node T_6856 = mux(T_6232, UInt<1>("h0"), UInt<1>("h0")) + node T_6858 = mux(T_6234, UInt<1>("h0"), UInt<1>("h0")) + node T_6860 = mux(T_6236, UInt<1>("h0"), UInt<1>("h0")) + node T_6862 = mux(T_6238, UInt<1>("h0"), UInt<1>("h0")) + node T_6864 = mux(T_6240, UInt<1>("h0"), UInt<1>("h0")) + node T_6866 = mux(T_6242, UInt<1>("h0"), UInt<1>("h0")) + node T_6868 = mux(T_6244, UInt<1>("h0"), UInt<1>("h0")) + node T_6870 = mux(T_6246, UInt<1>("h0"), UInt<1>("h0")) + node T_6872 = mux(T_6248, UInt<1>("h0"), UInt<1>("h0")) + node T_6874 = mux(T_6250, UInt<1>("h0"), UInt<1>("h0")) + node T_6876 = mux(T_6252, UInt<1>("h0"), UInt<1>("h0")) + node T_6878 = mux(T_6254, UInt<1>("h0"), UInt<1>("h0")) + node T_6880 = mux(T_6256, UInt<1>("h0"), UInt<1>("h0")) + node T_6882 = mux(T_6258, UInt<1>("h0"), UInt<1>("h0")) + node T_6884 = mux(T_6260, UInt<1>("h0"), UInt<1>("h0")) + node T_6886 = mux(T_6262, UInt<1>("h0"), UInt<1>("h0")) + node T_6888 = mux(T_6264, UInt<1>("h0"), UInt<1>("h0")) + node T_6890 = mux(T_6266, UInt<1>("h0"), UInt<1>("h0")) + node T_6892 = mux(T_6268, UInt<1>("h0"), UInt<1>("h0")) + node T_6894 = mux(T_6270, UInt<1>("h0"), UInt<1>("h0")) + node T_6896 = mux(T_6272, UInt<1>("h0"), UInt<1>("h0")) + node T_6898 = mux(T_6274, UInt<1>("h0"), UInt<1>("h0")) + node T_6900 = mux(T_6276, UInt<1>("h0"), UInt<1>("h0")) + node T_6902 = mux(T_6278, UInt<1>("h0"), UInt<1>("h0")) + node T_6904 = mux(T_6280, UInt<1>("h0"), UInt<1>("h0")) + node T_6906 = mux(T_6282, UInt<1>("h0"), UInt<1>("h0")) + node T_6908 = mux(T_6284, UInt<1>("h0"), UInt<1>("h0")) + node T_6910 = mux(T_6286, UInt<1>("h0"), UInt<1>("h0")) + node T_6912 = mux(T_6288, UInt<1>("h0"), UInt<1>("h0")) + node T_6914 = mux(T_6290, UInt<1>("h0"), UInt<1>("h0")) + node T_6916 = mux(T_6292, UInt<1>("h0"), UInt<1>("h0")) + node T_6918 = mux(T_6294, UInt<1>("h0"), UInt<1>("h0")) + node T_6920 = mux(T_6296, UInt<1>("h0"), UInt<1>("h0")) + node T_6922 = mux(T_6298, T_6051, UInt<1>("h0")) + node T_6924 = mux(T_6300, T_5992, UInt<1>("h0")) + node T_6926 = mux(T_6302, T_5991, UInt<1>("h0")) + node T_6928 = mux(T_6304, reg_sscratch, UInt<1>("h0")) + node T_6930 = mux(T_6306, reg_scause, UInt<1>("h0")) + node T_6932 = mux(T_6308, T_6057, UInt<1>("h0")) + node T_6934 = mux(T_6310, T_6058, UInt<1>("h0")) + node T_6936 = mux(T_6312, T_6064, UInt<1>("h0")) + node T_6938 = mux(T_6314, T_6070, UInt<1>("h0")) + node T_6940 = mux(T_6316, reg_mscounteren, UInt<1>("h0")) + node T_6942 = mux(T_6318, reg_mucounteren, UInt<1>("h0")) + node T_6944 = mux(T_6320, T_5619, UInt<1>("h0")) + node T_6946 = mux(T_6322, T_5608, UInt<1>("h0")) + node T_6948 = or(T_6696, T_6698) + node T_6949 = or(T_6948, T_6700) + node T_6950 = or(T_6949, T_6702) + node T_6951 = or(T_6950, T_6704) + node T_6952 = or(T_6951, T_6706) + node T_6953 = or(T_6952, T_6708) + node T_6954 = or(T_6953, T_6710) + node T_6955 = or(T_6954, T_6712) + node T_6956 = or(T_6955, T_6714) + node T_6957 = or(T_6956, T_6716) + node T_6958 = or(T_6957, T_6718) + node T_6959 = or(T_6958, T_6720) + node T_6960 = or(T_6959, T_6722) + node T_6961 = or(T_6960, T_6724) + node T_6962 = or(T_6961, T_6726) + node T_6963 = or(T_6962, T_6728) + node T_6964 = or(T_6963, T_6730) + node T_6965 = or(T_6964, T_6732) + node T_6966 = or(T_6965, T_6734) + node T_6967 = or(T_6966, T_6736) + node T_6968 = or(T_6967, T_6738) + node T_6969 = or(T_6968, T_6740) + node T_6970 = or(T_6969, T_6742) + node T_6971 = or(T_6970, T_6744) + node T_6972 = or(T_6971, T_6746) + node T_6973 = or(T_6972, T_6748) + node T_6974 = or(T_6973, T_6750) + node T_6975 = or(T_6974, T_6752) + node T_6976 = or(T_6975, T_6754) + node T_6977 = or(T_6976, T_6756) + node T_6978 = or(T_6977, T_6758) + node T_6979 = or(T_6978, T_6760) + node T_6980 = or(T_6979, T_6762) + node T_6981 = or(T_6980, T_6764) + node T_6982 = or(T_6981, T_6766) + node T_6983 = or(T_6982, T_6768) + node T_6984 = or(T_6983, T_6770) + node T_6985 = or(T_6984, T_6772) + node T_6986 = or(T_6985, T_6774) + node T_6987 = or(T_6986, T_6776) + node T_6988 = or(T_6987, T_6778) + node T_6989 = or(T_6988, T_6780) + node T_6990 = or(T_6989, T_6782) + node T_6991 = or(T_6990, T_6784) + node T_6992 = or(T_6991, T_6786) + node T_6993 = or(T_6992, T_6788) + node T_6994 = or(T_6993, T_6790) + node T_6995 = or(T_6994, T_6792) + node T_6996 = or(T_6995, T_6794) + node T_6997 = or(T_6996, T_6796) + node T_6998 = or(T_6997, T_6798) + node T_6999 = or(T_6998, T_6800) + node T_7000 = or(T_6999, T_6802) + node T_7001 = or(T_7000, T_6804) + node T_7002 = or(T_7001, T_6806) + node T_7003 = or(T_7002, T_6808) + node T_7004 = or(T_7003, T_6810) + node T_7005 = or(T_7004, T_6812) + node T_7006 = or(T_7005, T_6814) + node T_7007 = or(T_7006, T_6816) + node T_7008 = or(T_7007, T_6818) + node T_7009 = or(T_7008, T_6820) + node T_7010 = or(T_7009, T_6822) + node T_7011 = or(T_7010, T_6824) + node T_7012 = or(T_7011, T_6826) + node T_7013 = or(T_7012, T_6828) + node T_7014 = or(T_7013, T_6830) + node T_7015 = or(T_7014, T_6832) + node T_7016 = or(T_7015, T_6834) + node T_7017 = or(T_7016, T_6836) + node T_7018 = or(T_7017, T_6838) + node T_7019 = or(T_7018, T_6840) + node T_7020 = or(T_7019, T_6842) + node T_7021 = or(T_7020, T_6844) + node T_7022 = or(T_7021, T_6846) + node T_7023 = or(T_7022, T_6848) + node T_7024 = or(T_7023, T_6850) + node T_7025 = or(T_7024, T_6852) + node T_7026 = or(T_7025, T_6854) + node T_7027 = or(T_7026, T_6856) + node T_7028 = or(T_7027, T_6858) + node T_7029 = or(T_7028, T_6860) + node T_7030 = or(T_7029, T_6862) + node T_7031 = or(T_7030, T_6864) + node T_7032 = or(T_7031, T_6866) + node T_7033 = or(T_7032, T_6868) + node T_7034 = or(T_7033, T_6870) + node T_7035 = or(T_7034, T_6872) + node T_7036 = or(T_7035, T_6874) + node T_7037 = or(T_7036, T_6876) + node T_7038 = or(T_7037, T_6878) + node T_7039 = or(T_7038, T_6880) + node T_7040 = or(T_7039, T_6882) + node T_7041 = or(T_7040, T_6884) + node T_7042 = or(T_7041, T_6886) + node T_7043 = or(T_7042, T_6888) + node T_7044 = or(T_7043, T_6890) + node T_7045 = or(T_7044, T_6892) + node T_7046 = or(T_7045, T_6894) + node T_7047 = or(T_7046, T_6896) + node T_7048 = or(T_7047, T_6898) + node T_7049 = or(T_7048, T_6900) + node T_7050 = or(T_7049, T_6902) + node T_7051 = or(T_7050, T_6904) + node T_7052 = or(T_7051, T_6906) + node T_7053 = or(T_7052, T_6908) + node T_7054 = or(T_7053, T_6910) + node T_7055 = or(T_7054, T_6912) + node T_7056 = or(T_7055, T_6914) + node T_7057 = or(T_7056, T_6916) + node T_7058 = or(T_7057, T_6918) + node T_7059 = or(T_7058, T_6920) + node T_7060 = or(T_7059, T_6922) + node T_7061 = or(T_7060, T_6924) + node T_7062 = or(T_7061, T_6926) + node T_7063 = or(T_7062, T_6928) + node T_7064 = or(T_7063, T_6930) + node T_7065 = or(T_7064, T_6932) + node T_7066 = or(T_7065, T_6934) + node T_7067 = or(T_7066, T_6936) + node T_7068 = or(T_7067, T_6938) + node T_7069 = or(T_7068, T_6940) + node T_7070 = or(T_7069, T_6942) + node T_7071 = or(T_7070, T_6944) + node T_7072 = or(T_7071, T_6946) wire T_7073 : UInt T_7073 is invalid - T_7073 <= T_7072 @[Mux.scala 18:72] - io.rw.rdata <= T_7073 @[csr.scala 489:15] - io.fcsr_rm <= reg_frm @[csr.scala 491:14] - when io.fcsr_flags.valid : @[csr.scala 492:30] - node T_7074 = or(reg_fflags, io.fcsr_flags.bits) @[csr.scala 493:30] - reg_fflags <= T_7074 @[csr.scala 493:16] - skip @[csr.scala 492:30] - when wen : @[csr.scala 496:14] - when T_6090 : @[csr.scala 497:39] - wire T_7127 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[csr.scala 498:47] - T_7127 is invalid @[csr.scala 498:47] + T_7073 <= T_7072 + io.rw.rdata <= T_7073 + io.fcsr_rm <= reg_frm + when io.fcsr_flags.valid : + node T_7074 = or(reg_fflags, io.fcsr_flags.bits) + reg_fflags <= T_7074 + when wen : + when T_6090 : + wire T_7127 : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + T_7127 is invalid wire T_7154 : UInt<99> T_7154 is invalid T_7154 <= wdata - node T_7155 = bits(T_7154, 0, 0) @[csr.scala 498:47] - T_7127.uie <= T_7155 @[csr.scala 498:47] - node T_7156 = bits(T_7154, 1, 1) @[csr.scala 498:47] - T_7127.sie <= T_7156 @[csr.scala 498:47] - node T_7157 = bits(T_7154, 2, 2) @[csr.scala 498:47] - T_7127.hie <= T_7157 @[csr.scala 498:47] - node T_7158 = bits(T_7154, 3, 3) @[csr.scala 498:47] - T_7127.mie <= T_7158 @[csr.scala 498:47] - node T_7159 = bits(T_7154, 4, 4) @[csr.scala 498:47] - T_7127.upie <= T_7159 @[csr.scala 498:47] - node T_7160 = bits(T_7154, 5, 5) @[csr.scala 498:47] - T_7127.spie <= T_7160 @[csr.scala 498:47] - node T_7161 = bits(T_7154, 6, 6) @[csr.scala 498:47] - T_7127.hpie <= T_7161 @[csr.scala 498:47] - node T_7162 = bits(T_7154, 7, 7) @[csr.scala 498:47] - T_7127.mpie <= T_7162 @[csr.scala 498:47] - node T_7163 = bits(T_7154, 8, 8) @[csr.scala 498:47] - T_7127.spp <= T_7163 @[csr.scala 498:47] - node T_7164 = bits(T_7154, 10, 9) @[csr.scala 498:47] - T_7127.hpp <= T_7164 @[csr.scala 498:47] - node T_7165 = bits(T_7154, 12, 11) @[csr.scala 498:47] - T_7127.mpp <= T_7165 @[csr.scala 498:47] - node T_7166 = bits(T_7154, 14, 13) @[csr.scala 498:47] - T_7127.fs <= T_7166 @[csr.scala 498:47] - node T_7167 = bits(T_7154, 16, 15) @[csr.scala 498:47] - T_7127.xs <= T_7167 @[csr.scala 498:47] - node T_7168 = bits(T_7154, 17, 17) @[csr.scala 498:47] - T_7127.mprv <= T_7168 @[csr.scala 498:47] - node T_7169 = bits(T_7154, 18, 18) @[csr.scala 498:47] - T_7127.pum <= T_7169 @[csr.scala 498:47] - node T_7170 = bits(T_7154, 19, 19) @[csr.scala 498:47] - T_7127.mxr <= T_7170 @[csr.scala 498:47] - node T_7171 = bits(T_7154, 23, 20) @[csr.scala 498:47] - T_7127.zero1 <= T_7171 @[csr.scala 498:47] - node T_7172 = bits(T_7154, 28, 24) @[csr.scala 498:47] - T_7127.vm <= T_7172 @[csr.scala 498:47] - node T_7173 = bits(T_7154, 30, 29) @[csr.scala 498:47] - T_7127.zero2 <= T_7173 @[csr.scala 498:47] - node T_7174 = bits(T_7154, 31, 31) @[csr.scala 498:47] - T_7127.sd_rv32 <= T_7174 @[csr.scala 498:47] - node T_7175 = bits(T_7154, 62, 32) @[csr.scala 498:47] - T_7127.zero3 <= T_7175 @[csr.scala 498:47] - node T_7176 = bits(T_7154, 63, 63) @[csr.scala 498:47] - T_7127.sd <= T_7176 @[csr.scala 498:47] - node T_7177 = bits(T_7154, 65, 64) @[csr.scala 498:47] - T_7127.prv <= T_7177 @[csr.scala 498:47] - node T_7178 = bits(T_7154, 97, 66) @[csr.scala 498:47] - T_7127.isa <= T_7178 @[csr.scala 498:47] - node T_7179 = bits(T_7154, 98, 98) @[csr.scala 498:47] - T_7127.debug <= T_7179 @[csr.scala 498:47] - reg_mstatus.mie <= T_7127.mie @[csr.scala 499:23] - reg_mstatus.mpie <= T_7127.mpie @[csr.scala 500:24] - reg_mstatus.mprv <= T_7127.mprv @[csr.scala 503:26] - reg_mstatus.mpp <= T_7127.mpp @[csr.scala 504:25] - reg_mstatus.mxr <= T_7127.mxr @[csr.scala 506:27] - reg_mstatus.pum <= T_7127.pum @[csr.scala 507:27] - reg_mstatus.spp <= T_7127.spp @[csr.scala 508:27] - reg_mstatus.spie <= T_7127.spie @[csr.scala 509:28] - reg_mstatus.sie <= T_7127.sie @[csr.scala 510:27] - node T_7181 = eq(T_7127.vm, UInt<1>("h00")) @[csr.scala 517:30] - when T_7181 : @[csr.scala 517:37] - reg_mstatus.vm <= UInt<1>("h00") @[csr.scala 517:54] - skip @[csr.scala 517:37] - node T_7184 = eq(T_7127.vm, UInt<4>("h09")) @[csr.scala 518:30] - when T_7184 : @[csr.scala 518:41] - reg_mstatus.vm <= UInt<4>("h09") @[csr.scala 518:58] - skip @[csr.scala 518:41] - node T_7187 = neq(T_7127.fs, UInt<1>("h00")) @[csr.scala 520:73] - node T_7188 = bits(T_7187, 0, 0) @[Bitwise.scala 33:15] - node T_7191 = mux(T_7188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 33:12] - reg_mstatus.fs <= T_7191 @[csr.scala 520:47] - skip @[csr.scala 497:39] - when T_6088 : @[csr.scala 523:36] - node T_7193 = bits(wdata, 5, 5) @[csr.scala 525:20] - node T_7194 = not(wdata) @[csr.scala 526:21] - node T_7196 = eq(T_7193, UInt<1>("h00")) @[csr.scala 526:31] - node T_7197 = shl(T_7196, 3) @[csr.scala 526:34] - node T_7198 = or(T_7194, T_7197) @[csr.scala 526:28] - node T_7199 = not(T_7198) @[csr.scala 526:19] - node T_7200 = and(T_7199, UInt<13>("h0102d")) @[csr.scala 526:51] - node T_7201 = not(UInt<13>("h0102d")) @[csr.scala 526:71] - node T_7202 = and(reg_misa, T_7201) @[csr.scala 526:69] - node T_7203 = or(T_7200, T_7202) @[csr.scala 526:58] - reg_misa <= T_7203 @[csr.scala 526:16] - skip @[csr.scala 523:36] - when T_6094 : @[csr.scala 528:35] - wire T_7232 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[csr.scala 529:39] - T_7232 is invalid @[csr.scala 529:39] - node T_7246 = bits(wdata, 0, 0) @[csr.scala 529:39] - T_7232.usip <= T_7246 @[csr.scala 529:39] - node T_7247 = bits(wdata, 1, 1) @[csr.scala 529:39] - T_7232.ssip <= T_7247 @[csr.scala 529:39] - node T_7248 = bits(wdata, 2, 2) @[csr.scala 529:39] - T_7232.hsip <= T_7248 @[csr.scala 529:39] - node T_7249 = bits(wdata, 3, 3) @[csr.scala 529:39] - T_7232.msip <= T_7249 @[csr.scala 529:39] - node T_7250 = bits(wdata, 4, 4) @[csr.scala 529:39] - T_7232.utip <= T_7250 @[csr.scala 529:39] - node T_7251 = bits(wdata, 5, 5) @[csr.scala 529:39] - T_7232.stip <= T_7251 @[csr.scala 529:39] - node T_7252 = bits(wdata, 6, 6) @[csr.scala 529:39] - T_7232.htip <= T_7252 @[csr.scala 529:39] - node T_7253 = bits(wdata, 7, 7) @[csr.scala 529:39] - T_7232.mtip <= T_7253 @[csr.scala 529:39] - node T_7254 = bits(wdata, 8, 8) @[csr.scala 529:39] - T_7232.ueip <= T_7254 @[csr.scala 529:39] - node T_7255 = bits(wdata, 9, 9) @[csr.scala 529:39] - T_7232.seip <= T_7255 @[csr.scala 529:39] - node T_7256 = bits(wdata, 10, 10) @[csr.scala 529:39] - T_7232.heip <= T_7256 @[csr.scala 529:39] - node T_7257 = bits(wdata, 11, 11) @[csr.scala 529:39] - T_7232.meip <= T_7257 @[csr.scala 529:39] - node T_7258 = bits(wdata, 12, 12) @[csr.scala 529:39] - T_7232.rocc <= T_7258 @[csr.scala 529:39] - reg_mip.ssip <= T_7232.ssip @[csr.scala 531:22] - reg_mip.stip <= T_7232.stip @[csr.scala 532:22] - skip @[csr.scala 528:35] - when T_6096 : @[csr.scala 535:40] - node T_7259 = and(wdata, supported_interrupts) @[csr.scala 535:59] - reg_mie <= T_7259 @[csr.scala 535:50] - skip @[csr.scala 535:40] - when T_6104 : @[csr.scala 536:40] - node T_7260 = not(wdata) @[csr.scala 659:28] - node T_7261 = bits(reg_misa, 2, 2) @[csr.scala 659:46] - node T_7263 = eq(T_7261, UInt<1>("h00")) @[csr.scala 659:37] - node T_7265 = cat(T_7263, UInt<1>("h01")) @[Cat.scala 20:58] - node T_7266 = or(T_7260, T_7265) @[csr.scala 659:31] - node T_7267 = not(T_7266) @[csr.scala 659:26] - reg_mepc <= T_7267 @[csr.scala 536:51] - skip @[csr.scala 536:40] - when T_6102 : @[csr.scala 537:40] - reg_mscratch <= wdata @[csr.scala 537:55] - skip @[csr.scala 537:40] - when T_6092 : @[csr.scala 539:40] - node T_7268 = shr(wdata, 2) @[csr.scala 539:61] - node T_7269 = shl(T_7268, 2) @[csr.scala 539:66] - reg_mtvec <= T_7269 @[csr.scala 539:52] - skip @[csr.scala 539:40] - when T_6108 : @[csr.scala 540:40] - node T_7271 = and(wdata, UInt<64>("h0800000000000001f")) @[csr.scala 540:62] - reg_mcause <= T_7271 @[csr.scala 540:53] - skip @[csr.scala 540:40] - when T_6106 : @[csr.scala 541:40] - node T_7272 = bits(wdata, 39, 0) @[csr.scala 541:63] - reg_mbadaddr <= T_7272 @[csr.scala 541:55] - skip @[csr.scala 541:40] - when T_6084 : @[csr.scala 656:31] - T_5611 <= wdata @[util.scala 147:11] - node T_7273 = shr(wdata, 6) @[util.scala 148:28] - T_5614 <= T_7273 @[util.scala 148:23] - skip @[csr.scala 656:31] - when T_6086 : @[csr.scala 656:31] - T_5600 <= wdata @[util.scala 147:11] - node T_7274 = shr(wdata, 6) @[util.scala 148:28] - T_5603 <= T_7274 @[util.scala 148:23] - skip @[csr.scala 656:31] - when T_6118 : @[csr.scala 552:40] - reg_fflags <= wdata @[csr.scala 552:53] - skip @[csr.scala 552:40] - when T_6120 : @[csr.scala 553:40] - reg_frm <= wdata @[csr.scala 553:50] - skip @[csr.scala 553:40] - when T_6122 : @[csr.scala 554:40] - reg_fflags <= wdata @[csr.scala 554:53] - node T_7275 = shr(wdata, 5) @[csr.scala 554:80] - reg_frm <= T_7275 @[csr.scala 554:71] - skip @[csr.scala 554:40] - when T_6112 : @[csr.scala 557:38] - wire T_7312 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[csr.scala 558:43] - T_7312 is invalid @[csr.scala 558:43] - node T_7330 = bits(wdata, 1, 0) @[csr.scala 558:43] - T_7312.prv <= T_7330 @[csr.scala 558:43] - node T_7331 = bits(wdata, 2, 2) @[csr.scala 558:43] - T_7312.step <= T_7331 @[csr.scala 558:43] - node T_7332 = bits(wdata, 3, 3) @[csr.scala 558:43] - T_7312.halt <= T_7332 @[csr.scala 558:43] - node T_7333 = bits(wdata, 4, 4) @[csr.scala 558:43] - T_7312.zero1 <= T_7333 @[csr.scala 558:43] - node T_7334 = bits(wdata, 5, 5) @[csr.scala 558:43] - T_7312.debugint <= T_7334 @[csr.scala 558:43] - node T_7335 = bits(wdata, 8, 6) @[csr.scala 558:43] - T_7312.cause <= T_7335 @[csr.scala 558:43] - node T_7336 = bits(wdata, 9, 9) @[csr.scala 558:43] - T_7312.stoptime <= T_7336 @[csr.scala 558:43] - node T_7337 = bits(wdata, 10, 10) @[csr.scala 558:43] - T_7312.stopcycle <= T_7337 @[csr.scala 558:43] - node T_7338 = bits(wdata, 11, 11) @[csr.scala 558:43] - T_7312.zero2 <= T_7338 @[csr.scala 558:43] - node T_7339 = bits(wdata, 12, 12) @[csr.scala 558:43] - T_7312.ebreaku <= T_7339 @[csr.scala 558:43] - node T_7340 = bits(wdata, 13, 13) @[csr.scala 558:43] - T_7312.ebreaks <= T_7340 @[csr.scala 558:43] - node T_7341 = bits(wdata, 14, 14) @[csr.scala 558:43] - T_7312.ebreakh <= T_7341 @[csr.scala 558:43] - node T_7342 = bits(wdata, 15, 15) @[csr.scala 558:43] - T_7312.ebreakm <= T_7342 @[csr.scala 558:43] - node T_7343 = bits(wdata, 27, 16) @[csr.scala 558:43] - T_7312.zero3 <= T_7343 @[csr.scala 558:43] - node T_7344 = bits(wdata, 28, 28) @[csr.scala 558:43] - T_7312.fullreset <= T_7344 @[csr.scala 558:43] - node T_7345 = bits(wdata, 29, 29) @[csr.scala 558:43] - T_7312.ndreset <= T_7345 @[csr.scala 558:43] - node T_7346 = bits(wdata, 31, 30) @[csr.scala 558:43] - T_7312.xdebugver <= T_7346 @[csr.scala 558:43] - reg_dcsr.halt <= T_7312.halt @[csr.scala 559:23] - reg_dcsr.step <= T_7312.step @[csr.scala 560:23] - reg_dcsr.ebreakm <= T_7312.ebreakm @[csr.scala 561:26] - reg_dcsr.ebreaks <= T_7312.ebreaks @[csr.scala 562:39] - reg_dcsr.ebreaku <= T_7312.ebreaku @[csr.scala 563:41] - reg_dcsr.prv <= T_7312.prv @[csr.scala 564:37] - skip @[csr.scala 557:38] - when T_6114 : @[csr.scala 566:42] - node T_7347 = not(wdata) @[csr.scala 566:57] - node T_7349 = or(T_7347, UInt<1>("h01")) @[csr.scala 566:64] - node T_7350 = not(T_7349) @[csr.scala 566:55] - reg_dpc <= T_7350 @[csr.scala 566:52] - skip @[csr.scala 566:42] - when T_6116 : @[csr.scala 567:42] - reg_dscratch <= wdata @[csr.scala 567:57] - skip @[csr.scala 567:42] - when T_6298 : @[csr.scala 570:41] - wire T_7403 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[csr.scala 571:49] - T_7403 is invalid @[csr.scala 571:49] + node T_7155 = bits(T_7154, 0, 0) + T_7127.uie <= T_7155 + node T_7156 = bits(T_7154, 1, 1) + T_7127.sie <= T_7156 + node T_7157 = bits(T_7154, 2, 2) + T_7127.hie <= T_7157 + node T_7158 = bits(T_7154, 3, 3) + T_7127.mie <= T_7158 + node T_7159 = bits(T_7154, 4, 4) + T_7127.upie <= T_7159 + node T_7160 = bits(T_7154, 5, 5) + T_7127.spie <= T_7160 + node T_7161 = bits(T_7154, 6, 6) + T_7127.hpie <= T_7161 + node T_7162 = bits(T_7154, 7, 7) + T_7127.mpie <= T_7162 + node T_7163 = bits(T_7154, 8, 8) + T_7127.spp <= T_7163 + node T_7164 = bits(T_7154, 10, 9) + T_7127.hpp <= T_7164 + node T_7165 = bits(T_7154, 12, 11) + T_7127.mpp <= T_7165 + node T_7166 = bits(T_7154, 14, 13) + T_7127.fs <= T_7166 + node T_7167 = bits(T_7154, 16, 15) + T_7127.xs <= T_7167 + node T_7168 = bits(T_7154, 17, 17) + T_7127.mprv <= T_7168 + node T_7169 = bits(T_7154, 18, 18) + T_7127.pum <= T_7169 + node T_7170 = bits(T_7154, 19, 19) + T_7127.mxr <= T_7170 + node T_7171 = bits(T_7154, 23, 20) + T_7127.zero1 <= T_7171 + node T_7172 = bits(T_7154, 28, 24) + T_7127.vm <= T_7172 + node T_7173 = bits(T_7154, 30, 29) + T_7127.zero2 <= T_7173 + node T_7174 = bits(T_7154, 31, 31) + T_7127.sd_rv32 <= T_7174 + node T_7175 = bits(T_7154, 62, 32) + T_7127.zero3 <= T_7175 + node T_7176 = bits(T_7154, 63, 63) + T_7127.sd <= T_7176 + node T_7177 = bits(T_7154, 65, 64) + T_7127.prv <= T_7177 + node T_7178 = bits(T_7154, 97, 66) + T_7127.isa <= T_7178 + node T_7179 = bits(T_7154, 98, 98) + T_7127.debug <= T_7179 + reg_mstatus.mie <= T_7127.mie + reg_mstatus.mpie <= T_7127.mpie + reg_mstatus.mprv <= T_7127.mprv + reg_mstatus.mpp <= T_7127.mpp + reg_mstatus.mxr <= T_7127.mxr + reg_mstatus.pum <= T_7127.pum + reg_mstatus.spp <= T_7127.spp + reg_mstatus.spie <= T_7127.spie + reg_mstatus.sie <= T_7127.sie + node T_7181 = eq(T_7127.vm, UInt<1>("h0")) + when T_7181 : + reg_mstatus.vm <= UInt<1>("h0") + node T_7184 = eq(T_7127.vm, UInt<4>("h9")) + when T_7184 : + reg_mstatus.vm <= UInt<4>("h9") + node T_7187 = neq(T_7127.fs, UInt<1>("h0")) + node T_7188 = bits(T_7187, 0, 0) + node T_7191 = mux(T_7188, UInt<2>("h3"), UInt<2>("h0")) + reg_mstatus.fs <= T_7191 + when T_6088 : + node T_7193 = bits(wdata, 5, 5) + node T_7194 = not(wdata) + node T_7196 = eq(T_7193, UInt<1>("h0")) + node T_7197 = shl(T_7196, 3) + node T_7198 = or(T_7194, T_7197) + node T_7199 = not(T_7198) + node T_7200 = and(T_7199, UInt<13>("h102d")) + node T_7201 = not(UInt<13>("h102d")) + node T_7202 = and(reg_misa, T_7201) + node T_7203 = or(T_7200, T_7202) + reg_misa <= T_7203 + when T_6094 : + wire T_7232 : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_7232 is invalid + node T_7246 = bits(wdata, 0, 0) + T_7232.usip <= T_7246 + node T_7247 = bits(wdata, 1, 1) + T_7232.ssip <= T_7247 + node T_7248 = bits(wdata, 2, 2) + T_7232.hsip <= T_7248 + node T_7249 = bits(wdata, 3, 3) + T_7232.msip <= T_7249 + node T_7250 = bits(wdata, 4, 4) + T_7232.utip <= T_7250 + node T_7251 = bits(wdata, 5, 5) + T_7232.stip <= T_7251 + node T_7252 = bits(wdata, 6, 6) + T_7232.htip <= T_7252 + node T_7253 = bits(wdata, 7, 7) + T_7232.mtip <= T_7253 + node T_7254 = bits(wdata, 8, 8) + T_7232.ueip <= T_7254 + node T_7255 = bits(wdata, 9, 9) + T_7232.seip <= T_7255 + node T_7256 = bits(wdata, 10, 10) + T_7232.heip <= T_7256 + node T_7257 = bits(wdata, 11, 11) + T_7232.meip <= T_7257 + node T_7258 = bits(wdata, 12, 12) + T_7232.rocc <= T_7258 + reg_mip.ssip <= T_7232.ssip + reg_mip.stip <= T_7232.stip + when T_6096 : + node T_7259 = and(wdata, supported_interrupts) + reg_mie <= T_7259 + when T_6104 : + node T_7260 = not(wdata) + node T_7261 = bits(reg_misa, 2, 2) + node T_7263 = eq(T_7261, UInt<1>("h0")) + node T_7265 = cat(T_7263, UInt<1>("h1")) + node T_7266 = or(T_7260, T_7265) + node T_7267 = not(T_7266) + reg_mepc <= T_7267 + when T_6102 : + reg_mscratch <= wdata + when T_6092 : + node T_7268 = shr(wdata, 2) + node T_7269 = shl(T_7268, 2) + reg_mtvec <= T_7269 + when T_6108 : + node T_7271 = and(wdata, UInt<64>("h800000000000001f")) + reg_mcause <= T_7271 + when T_6106 : + node T_7272 = bits(wdata, 39, 0) + reg_mbadaddr <= T_7272 + when T_6084 : + T_5611 <= wdata + node T_7273 = shr(wdata, 6) + T_5614 <= T_7273 + when T_6086 : + T_5600 <= wdata + node T_7274 = shr(wdata, 6) + T_5603 <= T_7274 + when T_6118 : + reg_fflags <= wdata + when T_6120 : + reg_frm <= wdata + when T_6122 : + reg_fflags <= wdata + node T_7275 = shr(wdata, 5) + reg_frm <= T_7275 + when T_6112 : + wire T_7312 : { xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} + T_7312 is invalid + node T_7330 = bits(wdata, 1, 0) + T_7312.prv <= T_7330 + node T_7331 = bits(wdata, 2, 2) + T_7312.step <= T_7331 + node T_7332 = bits(wdata, 3, 3) + T_7312.halt <= T_7332 + node T_7333 = bits(wdata, 4, 4) + T_7312.zero1 <= T_7333 + node T_7334 = bits(wdata, 5, 5) + T_7312.debugint <= T_7334 + node T_7335 = bits(wdata, 8, 6) + T_7312.cause <= T_7335 + node T_7336 = bits(wdata, 9, 9) + T_7312.stoptime <= T_7336 + node T_7337 = bits(wdata, 10, 10) + T_7312.stopcycle <= T_7337 + node T_7338 = bits(wdata, 11, 11) + T_7312.zero2 <= T_7338 + node T_7339 = bits(wdata, 12, 12) + T_7312.ebreaku <= T_7339 + node T_7340 = bits(wdata, 13, 13) + T_7312.ebreaks <= T_7340 + node T_7341 = bits(wdata, 14, 14) + T_7312.ebreakh <= T_7341 + node T_7342 = bits(wdata, 15, 15) + T_7312.ebreakm <= T_7342 + node T_7343 = bits(wdata, 27, 16) + T_7312.zero3 <= T_7343 + node T_7344 = bits(wdata, 28, 28) + T_7312.fullreset <= T_7344 + node T_7345 = bits(wdata, 29, 29) + T_7312.ndreset <= T_7345 + node T_7346 = bits(wdata, 31, 30) + T_7312.xdebugver <= T_7346 + reg_dcsr.halt <= T_7312.halt + reg_dcsr.step <= T_7312.step + reg_dcsr.ebreakm <= T_7312.ebreakm + reg_dcsr.ebreaks <= T_7312.ebreaks + reg_dcsr.ebreaku <= T_7312.ebreaku + reg_dcsr.prv <= T_7312.prv + when T_6114 : + node T_7347 = not(wdata) + node T_7349 = or(T_7347, UInt<1>("h1")) + node T_7350 = not(T_7349) + reg_dpc <= T_7350 + when T_6116 : + reg_dscratch <= wdata + when T_6298 : + wire T_7403 : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + T_7403 is invalid wire T_7430 : UInt<99> T_7430 is invalid T_7430 <= wdata - node T_7431 = bits(T_7430, 0, 0) @[csr.scala 571:49] - T_7403.uie <= T_7431 @[csr.scala 571:49] - node T_7432 = bits(T_7430, 1, 1) @[csr.scala 571:49] - T_7403.sie <= T_7432 @[csr.scala 571:49] - node T_7433 = bits(T_7430, 2, 2) @[csr.scala 571:49] - T_7403.hie <= T_7433 @[csr.scala 571:49] - node T_7434 = bits(T_7430, 3, 3) @[csr.scala 571:49] - T_7403.mie <= T_7434 @[csr.scala 571:49] - node T_7435 = bits(T_7430, 4, 4) @[csr.scala 571:49] - T_7403.upie <= T_7435 @[csr.scala 571:49] - node T_7436 = bits(T_7430, 5, 5) @[csr.scala 571:49] - T_7403.spie <= T_7436 @[csr.scala 571:49] - node T_7437 = bits(T_7430, 6, 6) @[csr.scala 571:49] - T_7403.hpie <= T_7437 @[csr.scala 571:49] - node T_7438 = bits(T_7430, 7, 7) @[csr.scala 571:49] - T_7403.mpie <= T_7438 @[csr.scala 571:49] - node T_7439 = bits(T_7430, 8, 8) @[csr.scala 571:49] - T_7403.spp <= T_7439 @[csr.scala 571:49] - node T_7440 = bits(T_7430, 10, 9) @[csr.scala 571:49] - T_7403.hpp <= T_7440 @[csr.scala 571:49] - node T_7441 = bits(T_7430, 12, 11) @[csr.scala 571:49] - T_7403.mpp <= T_7441 @[csr.scala 571:49] - node T_7442 = bits(T_7430, 14, 13) @[csr.scala 571:49] - T_7403.fs <= T_7442 @[csr.scala 571:49] - node T_7443 = bits(T_7430, 16, 15) @[csr.scala 571:49] - T_7403.xs <= T_7443 @[csr.scala 571:49] - node T_7444 = bits(T_7430, 17, 17) @[csr.scala 571:49] - T_7403.mprv <= T_7444 @[csr.scala 571:49] - node T_7445 = bits(T_7430, 18, 18) @[csr.scala 571:49] - T_7403.pum <= T_7445 @[csr.scala 571:49] - node T_7446 = bits(T_7430, 19, 19) @[csr.scala 571:49] - T_7403.mxr <= T_7446 @[csr.scala 571:49] - node T_7447 = bits(T_7430, 23, 20) @[csr.scala 571:49] - T_7403.zero1 <= T_7447 @[csr.scala 571:49] - node T_7448 = bits(T_7430, 28, 24) @[csr.scala 571:49] - T_7403.vm <= T_7448 @[csr.scala 571:49] - node T_7449 = bits(T_7430, 30, 29) @[csr.scala 571:49] - T_7403.zero2 <= T_7449 @[csr.scala 571:49] - node T_7450 = bits(T_7430, 31, 31) @[csr.scala 571:49] - T_7403.sd_rv32 <= T_7450 @[csr.scala 571:49] - node T_7451 = bits(T_7430, 62, 32) @[csr.scala 571:49] - T_7403.zero3 <= T_7451 @[csr.scala 571:49] - node T_7452 = bits(T_7430, 63, 63) @[csr.scala 571:49] - T_7403.sd <= T_7452 @[csr.scala 571:49] - node T_7453 = bits(T_7430, 65, 64) @[csr.scala 571:49] - T_7403.prv <= T_7453 @[csr.scala 571:49] - node T_7454 = bits(T_7430, 97, 66) @[csr.scala 571:49] - T_7403.isa <= T_7454 @[csr.scala 571:49] - node T_7455 = bits(T_7430, 98, 98) @[csr.scala 571:49] - T_7403.debug <= T_7455 @[csr.scala 571:49] - reg_mstatus.sie <= T_7403.sie @[csr.scala 572:25] - reg_mstatus.spie <= T_7403.spie @[csr.scala 573:26] - reg_mstatus.spp <= T_7403.spp @[csr.scala 574:25] - reg_mstatus.pum <= T_7403.pum @[csr.scala 575:25] - node T_7457 = neq(T_7403.fs, UInt<1>("h00")) @[csr.scala 576:50] - node T_7458 = bits(T_7457, 0, 0) @[Bitwise.scala 33:15] - node T_7461 = mux(T_7458, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 33:12] - reg_mstatus.fs <= T_7461 @[csr.scala 576:24] - skip @[csr.scala 570:41] - when T_6300 : @[csr.scala 579:37] - wire T_7490 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[csr.scala 580:41] - T_7490 is invalid @[csr.scala 580:41] - node T_7504 = bits(wdata, 0, 0) @[csr.scala 580:41] - T_7490.usip <= T_7504 @[csr.scala 580:41] - node T_7505 = bits(wdata, 1, 1) @[csr.scala 580:41] - T_7490.ssip <= T_7505 @[csr.scala 580:41] - node T_7506 = bits(wdata, 2, 2) @[csr.scala 580:41] - T_7490.hsip <= T_7506 @[csr.scala 580:41] - node T_7507 = bits(wdata, 3, 3) @[csr.scala 580:41] - T_7490.msip <= T_7507 @[csr.scala 580:41] - node T_7508 = bits(wdata, 4, 4) @[csr.scala 580:41] - T_7490.utip <= T_7508 @[csr.scala 580:41] - node T_7509 = bits(wdata, 5, 5) @[csr.scala 580:41] - T_7490.stip <= T_7509 @[csr.scala 580:41] - node T_7510 = bits(wdata, 6, 6) @[csr.scala 580:41] - T_7490.htip <= T_7510 @[csr.scala 580:41] - node T_7511 = bits(wdata, 7, 7) @[csr.scala 580:41] - T_7490.mtip <= T_7511 @[csr.scala 580:41] - node T_7512 = bits(wdata, 8, 8) @[csr.scala 580:41] - T_7490.ueip <= T_7512 @[csr.scala 580:41] - node T_7513 = bits(wdata, 9, 9) @[csr.scala 580:41] - T_7490.seip <= T_7513 @[csr.scala 580:41] - node T_7514 = bits(wdata, 10, 10) @[csr.scala 580:41] - T_7490.heip <= T_7514 @[csr.scala 580:41] - node T_7515 = bits(wdata, 11, 11) @[csr.scala 580:41] - T_7490.meip <= T_7515 @[csr.scala 580:41] - node T_7516 = bits(wdata, 12, 12) @[csr.scala 580:41] - T_7490.rocc <= T_7516 @[csr.scala 580:41] - reg_mip.ssip <= T_7490.ssip @[csr.scala 581:22] - skip @[csr.scala 579:37] - when T_6302 : @[csr.scala 583:42] - node T_7517 = not(reg_mideleg) @[csr.scala 583:66] - node T_7518 = and(reg_mie, T_7517) @[csr.scala 583:64] - node T_7519 = and(wdata, reg_mideleg) @[csr.scala 583:89] - node T_7520 = or(T_7518, T_7519) @[csr.scala 583:80] - reg_mie <= T_7520 @[csr.scala 583:52] - skip @[csr.scala 583:42] - when T_6304 : @[csr.scala 584:42] - reg_sscratch <= wdata @[csr.scala 584:57] - skip @[csr.scala 584:42] - when T_6310 : @[csr.scala 585:42] - node T_7521 = bits(wdata, 19, 0) @[csr.scala 585:66] - reg_sptbr.ppn <= T_7521 @[csr.scala 585:58] - skip @[csr.scala 585:42] - when T_6312 : @[csr.scala 586:42] - node T_7522 = not(wdata) @[csr.scala 659:28] - node T_7523 = bits(reg_misa, 2, 2) @[csr.scala 659:46] - node T_7525 = eq(T_7523, UInt<1>("h00")) @[csr.scala 659:37] - node T_7527 = cat(T_7525, UInt<1>("h01")) @[Cat.scala 20:58] - node T_7528 = or(T_7522, T_7527) @[csr.scala 659:31] - node T_7529 = not(T_7528) @[csr.scala 659:26] - reg_sepc <= T_7529 @[csr.scala 586:53] - skip @[csr.scala 586:42] - when T_6314 : @[csr.scala 587:42] - node T_7530 = shr(wdata, 2) @[csr.scala 587:63] - node T_7531 = shl(T_7530, 2) @[csr.scala 587:68] - reg_stvec <= T_7531 @[csr.scala 587:54] - skip @[csr.scala 587:42] - when T_6306 : @[csr.scala 588:42] - node T_7533 = and(wdata, UInt<64>("h0800000000000001f")) @[csr.scala 588:64] - reg_scause <= T_7533 @[csr.scala 588:55] - skip @[csr.scala 588:42] - when T_6308 : @[csr.scala 589:42] - node T_7534 = bits(wdata, 39, 0) @[csr.scala 589:65] - reg_sbadaddr <= T_7534 @[csr.scala 589:57] - skip @[csr.scala 589:42] - when T_6098 : @[csr.scala 590:42] - node T_7535 = and(wdata, delegable_interrupts) @[csr.scala 590:65] - reg_mideleg <= T_7535 @[csr.scala 590:56] - skip @[csr.scala 590:42] - when T_6100 : @[csr.scala 591:42] - node T_7536 = and(wdata, UInt<9>("h01ab")) @[csr.scala 591:65] - reg_medeleg <= T_7536 @[csr.scala 591:56] - skip @[csr.scala 591:42] - when T_6316 : @[csr.scala 592:45] - node T_7538 = and(wdata, UInt<3>("h07")) @[csr.scala 592:72] - reg_mscounteren <= T_7538 @[csr.scala 592:63] - skip @[csr.scala 592:45] - when T_6318 : @[csr.scala 595:45] - node T_7540 = and(wdata, UInt<3>("h07")) @[csr.scala 595:72] - reg_mucounteren <= T_7540 @[csr.scala 595:63] - skip @[csr.scala 595:45] - when T_6072 : @[csr.scala 598:41] - reg_tselect <= wdata @[csr.scala 598:55] - skip @[csr.scala 598:41] - node T_7559 = eq(reg_bp[reg_tselect].control.dmode, UInt<1>("h00")) @[csr.scala 601:13] - node T_7560 = or(T_7559, reg_debug) @[csr.scala 601:31] - when T_7560 : @[csr.scala 601:45] - when T_6074 : @[csr.scala 602:42] - wire T_7593 : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[csr.scala 603:48] - T_7593 is invalid @[csr.scala 603:48] - node T_7609 = bits(wdata, 0, 0) @[csr.scala 603:48] - T_7593.r <= T_7609 @[csr.scala 603:48] - node T_7610 = bits(wdata, 1, 1) @[csr.scala 603:48] - T_7593.w <= T_7610 @[csr.scala 603:48] - node T_7611 = bits(wdata, 2, 2) @[csr.scala 603:48] - T_7593.x <= T_7611 @[csr.scala 603:48] - node T_7612 = bits(wdata, 3, 3) @[csr.scala 603:48] - T_7593.u <= T_7612 @[csr.scala 603:48] - node T_7613 = bits(wdata, 4, 4) @[csr.scala 603:48] - T_7593.s <= T_7613 @[csr.scala 603:48] - node T_7614 = bits(wdata, 5, 5) @[csr.scala 603:48] - T_7593.h <= T_7614 @[csr.scala 603:48] - node T_7615 = bits(wdata, 6, 6) @[csr.scala 603:48] - T_7593.m <= T_7615 @[csr.scala 603:48] - node T_7616 = bits(wdata, 8, 7) @[csr.scala 603:48] - T_7593.tmatch <= T_7616 @[csr.scala 603:48] - node T_7617 = bits(wdata, 10, 9) @[csr.scala 603:48] - T_7593.zero <= T_7617 @[csr.scala 603:48] - node T_7618 = bits(wdata, 11, 11) @[csr.scala 603:48] - T_7593.chain <= T_7618 @[csr.scala 603:48] - node T_7619 = bits(wdata, 12, 12) @[csr.scala 603:48] - T_7593.action <= T_7619 @[csr.scala 603:48] - node T_7620 = bits(wdata, 52, 13) @[csr.scala 603:48] - T_7593.reserved <= T_7620 @[csr.scala 603:48] - node T_7621 = bits(wdata, 58, 53) @[csr.scala 603:48] - T_7593.maskmax <= T_7621 @[csr.scala 603:48] - node T_7622 = bits(wdata, 59, 59) @[csr.scala 603:48] - T_7593.dmode <= T_7622 @[csr.scala 603:48] - node T_7623 = bits(wdata, 63, 60) @[csr.scala 603:48] - T_7593.ttype <= T_7623 @[csr.scala 603:48] - node T_7624 = and(T_7593.dmode, reg_debug) @[csr.scala 604:36] - reg_bp[reg_tselect].control <- T_7593 @[csr.scala 605:22] - reg_bp[reg_tselect].control.dmode <= T_7624 @[csr.scala 606:28] - node T_7625 = and(T_7624, T_7593.action) @[csr.scala 607:38] - reg_bp[reg_tselect].control.action <= T_7625 @[csr.scala 607:29] - skip @[csr.scala 602:42] - when T_6076 : @[csr.scala 609:42] - reg_bp[reg_tselect].address <= wdata @[csr.scala 609:55] - skip @[csr.scala 609:42] - skip @[csr.scala 601:45] - skip @[csr.scala 496:14] - reg_mip <- io.prci.interrupts @[csr.scala 614:11] - reg_dcsr.debugint <= io.prci.interrupts.debug @[csr.scala 615:21] - reg_sptbr.asid <= UInt<1>("h00") @[csr.scala 617:18] - reg_tselect <= UInt<1>("h00") @[csr.scala 618:38] - reg_bp[0].control.chain <= UInt<1>("h00") @[csr.scala 620:42] - reg_bp[0].control.ttype <= UInt<2>("h02") @[csr.scala 622:15] - reg_bp[0].control.maskmax <= UInt<3>("h04") @[csr.scala 623:17] - reg_bp[0].control.reserved <= UInt<1>("h00") @[csr.scala 624:18] - reg_bp[0].control.zero <= UInt<1>("h00") @[csr.scala 625:14] - reg_bp[0].control.h <= UInt<1>("h00") @[csr.scala 626:11] - when reset : @[csr.scala 630:18] - reg_bp[0].control.action <= UInt<1>("h00") @[csr.scala 631:18] - reg_bp[0].control.dmode <= UInt<1>("h00") @[csr.scala 632:17] - reg_bp[0].control.r <= UInt<1>("h00") @[csr.scala 633:13] - reg_bp[0].control.w <= UInt<1>("h00") @[csr.scala 634:13] - reg_bp[0].control.x <= UInt<1>("h00") @[csr.scala 635:13] - skip @[csr.scala 630:18] - reg_bp[1].control.ttype <= UInt<2>("h02") @[csr.scala 622:15] - reg_bp[1].control.maskmax <= UInt<3>("h04") @[csr.scala 623:17] - reg_bp[1].control.reserved <= UInt<1>("h00") @[csr.scala 624:18] - reg_bp[1].control.zero <= UInt<1>("h00") @[csr.scala 625:14] - reg_bp[1].control.h <= UInt<1>("h00") @[csr.scala 626:11] - when reset : @[csr.scala 630:18] - reg_bp[1].control.action <= UInt<1>("h00") @[csr.scala 631:18] - reg_bp[1].control.dmode <= UInt<1>("h00") @[csr.scala 632:17] - reg_bp[1].control.r <= UInt<1>("h00") @[csr.scala 633:13] - reg_bp[1].control.w <= UInt<1>("h00") @[csr.scala 634:13] - reg_bp[1].control.x <= UInt<1>("h00") @[csr.scala 635:13] - skip @[csr.scala 630:18] - wire T_7686 : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>} @[csr.scala 639:28] - T_7686 is invalid @[csr.scala 639:28] + node T_7431 = bits(T_7430, 0, 0) + T_7403.uie <= T_7431 + node T_7432 = bits(T_7430, 1, 1) + T_7403.sie <= T_7432 + node T_7433 = bits(T_7430, 2, 2) + T_7403.hie <= T_7433 + node T_7434 = bits(T_7430, 3, 3) + T_7403.mie <= T_7434 + node T_7435 = bits(T_7430, 4, 4) + T_7403.upie <= T_7435 + node T_7436 = bits(T_7430, 5, 5) + T_7403.spie <= T_7436 + node T_7437 = bits(T_7430, 6, 6) + T_7403.hpie <= T_7437 + node T_7438 = bits(T_7430, 7, 7) + T_7403.mpie <= T_7438 + node T_7439 = bits(T_7430, 8, 8) + T_7403.spp <= T_7439 + node T_7440 = bits(T_7430, 10, 9) + T_7403.hpp <= T_7440 + node T_7441 = bits(T_7430, 12, 11) + T_7403.mpp <= T_7441 + node T_7442 = bits(T_7430, 14, 13) + T_7403.fs <= T_7442 + node T_7443 = bits(T_7430, 16, 15) + T_7403.xs <= T_7443 + node T_7444 = bits(T_7430, 17, 17) + T_7403.mprv <= T_7444 + node T_7445 = bits(T_7430, 18, 18) + T_7403.pum <= T_7445 + node T_7446 = bits(T_7430, 19, 19) + T_7403.mxr <= T_7446 + node T_7447 = bits(T_7430, 23, 20) + T_7403.zero1 <= T_7447 + node T_7448 = bits(T_7430, 28, 24) + T_7403.vm <= T_7448 + node T_7449 = bits(T_7430, 30, 29) + T_7403.zero2 <= T_7449 + node T_7450 = bits(T_7430, 31, 31) + T_7403.sd_rv32 <= T_7450 + node T_7451 = bits(T_7430, 62, 32) + T_7403.zero3 <= T_7451 + node T_7452 = bits(T_7430, 63, 63) + T_7403.sd <= T_7452 + node T_7453 = bits(T_7430, 65, 64) + T_7403.prv <= T_7453 + node T_7454 = bits(T_7430, 97, 66) + T_7403.isa <= T_7454 + node T_7455 = bits(T_7430, 98, 98) + T_7403.debug <= T_7455 + reg_mstatus.sie <= T_7403.sie + reg_mstatus.spie <= T_7403.spie + reg_mstatus.spp <= T_7403.spp + reg_mstatus.pum <= T_7403.pum + node T_7457 = neq(T_7403.fs, UInt<1>("h0")) + node T_7458 = bits(T_7457, 0, 0) + node T_7461 = mux(T_7458, UInt<2>("h3"), UInt<2>("h0")) + reg_mstatus.fs <= T_7461 + when T_6300 : + wire T_7490 : { rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_7490 is invalid + node T_7504 = bits(wdata, 0, 0) + T_7490.usip <= T_7504 + node T_7505 = bits(wdata, 1, 1) + T_7490.ssip <= T_7505 + node T_7506 = bits(wdata, 2, 2) + T_7490.hsip <= T_7506 + node T_7507 = bits(wdata, 3, 3) + T_7490.msip <= T_7507 + node T_7508 = bits(wdata, 4, 4) + T_7490.utip <= T_7508 + node T_7509 = bits(wdata, 5, 5) + T_7490.stip <= T_7509 + node T_7510 = bits(wdata, 6, 6) + T_7490.htip <= T_7510 + node T_7511 = bits(wdata, 7, 7) + T_7490.mtip <= T_7511 + node T_7512 = bits(wdata, 8, 8) + T_7490.ueip <= T_7512 + node T_7513 = bits(wdata, 9, 9) + T_7490.seip <= T_7513 + node T_7514 = bits(wdata, 10, 10) + T_7490.heip <= T_7514 + node T_7515 = bits(wdata, 11, 11) + T_7490.meip <= T_7515 + node T_7516 = bits(wdata, 12, 12) + T_7490.rocc <= T_7516 + reg_mip.ssip <= T_7490.ssip + when T_6302 : + node T_7517 = not(reg_mideleg) + node T_7518 = and(reg_mie, T_7517) + node T_7519 = and(wdata, reg_mideleg) + node T_7520 = or(T_7518, T_7519) + reg_mie <= T_7520 + when T_6304 : + reg_sscratch <= wdata + when T_6310 : + node T_7521 = bits(wdata, 19, 0) + reg_sptbr.ppn <= T_7521 + when T_6312 : + node T_7522 = not(wdata) + node T_7523 = bits(reg_misa, 2, 2) + node T_7525 = eq(T_7523, UInt<1>("h0")) + node T_7527 = cat(T_7525, UInt<1>("h1")) + node T_7528 = or(T_7522, T_7527) + node T_7529 = not(T_7528) + reg_sepc <= T_7529 + when T_6314 : + node T_7530 = shr(wdata, 2) + node T_7531 = shl(T_7530, 2) + reg_stvec <= T_7531 + when T_6306 : + node T_7533 = and(wdata, UInt<64>("h800000000000001f")) + reg_scause <= T_7533 + when T_6308 : + node T_7534 = bits(wdata, 39, 0) + reg_sbadaddr <= T_7534 + when T_6098 : + node T_7535 = and(wdata, delegable_interrupts) + reg_mideleg <= T_7535 + when T_6100 : + node T_7536 = and(wdata, UInt<9>("h1ab")) + reg_medeleg <= T_7536 + when T_6316 : + node T_7538 = and(wdata, UInt<3>("h7")) + reg_mscounteren <= T_7538 + when T_6318 : + node T_7540 = and(wdata, UInt<3>("h7")) + reg_mucounteren <= T_7540 + when T_6072 : + reg_tselect <= wdata + node T_7559 = eq(reg_bp[reg_tselect].control.dmode, UInt<1>("h0")) + node T_7560 = or(T_7559, reg_debug) + when T_7560 : + when T_6074 : + wire T_7593 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_7593 is invalid + node T_7609 = bits(wdata, 0, 0) + T_7593.r <= T_7609 + node T_7610 = bits(wdata, 1, 1) + T_7593.w <= T_7610 + node T_7611 = bits(wdata, 2, 2) + T_7593.x <= T_7611 + node T_7612 = bits(wdata, 3, 3) + T_7593.u <= T_7612 + node T_7613 = bits(wdata, 4, 4) + T_7593.s <= T_7613 + node T_7614 = bits(wdata, 5, 5) + T_7593.h <= T_7614 + node T_7615 = bits(wdata, 6, 6) + T_7593.m <= T_7615 + node T_7616 = bits(wdata, 8, 7) + T_7593.tmatch <= T_7616 + node T_7617 = bits(wdata, 10, 9) + T_7593.zero <= T_7617 + node T_7618 = bits(wdata, 11, 11) + T_7593.chain <= T_7618 + node T_7619 = bits(wdata, 12, 12) + T_7593.action <= T_7619 + node T_7620 = bits(wdata, 52, 13) + T_7593.reserved <= T_7620 + node T_7621 = bits(wdata, 58, 53) + T_7593.maskmax <= T_7621 + node T_7622 = bits(wdata, 59, 59) + T_7593.dmode <= T_7622 + node T_7623 = bits(wdata, 63, 60) + T_7593.ttype <= T_7623 + node T_7624 = and(T_7593.dmode, reg_debug) + reg_bp[reg_tselect].control <- T_7593 + reg_bp[reg_tselect].control.dmode <= T_7624 + node T_7625 = and(T_7624, T_7593.action) + reg_bp[reg_tselect].control.action <= T_7625 + when T_6076 : + reg_bp[reg_tselect].address <= wdata + reg_mip <- io.prci.interrupts + reg_dcsr.debugint <= io.prci.interrupts.debug + reg_sptbr.asid <= UInt<1>("h0") + reg_tselect <= UInt<1>("h0") + reg_bp[0].control.chain <= UInt<1>("h0") + reg_bp[0].control.ttype <= UInt<2>("h2") + reg_bp[0].control.maskmax <= UInt<3>("h4") + reg_bp[0].control.reserved <= UInt<1>("h0") + reg_bp[0].control.zero <= UInt<1>("h0") + reg_bp[0].control.h <= UInt<1>("h0") + when reset : + reg_bp[0].control.action <= UInt<1>("h0") + reg_bp[0].control.dmode <= UInt<1>("h0") + reg_bp[0].control.r <= UInt<1>("h0") + reg_bp[0].control.w <= UInt<1>("h0") + reg_bp[0].control.x <= UInt<1>("h0") + reg_bp[1].control.ttype <= UInt<2>("h2") + reg_bp[1].control.maskmax <= UInt<3>("h4") + reg_bp[1].control.reserved <= UInt<1>("h0") + reg_bp[1].control.zero <= UInt<1>("h0") + reg_bp[1].control.h <= UInt<1>("h0") + when reset : + reg_bp[1].control.action <= UInt<1>("h0") + reg_bp[1].control.dmode <= UInt<1>("h0") + reg_bp[1].control.r <= UInt<1>("h0") + reg_bp[1].control.w <= UInt<1>("h0") + reg_bp[1].control.x <= UInt<1>("h0") + wire T_7686 : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>} + T_7686 is invalid wire T_7705 : UInt<103> T_7705 is invalid - T_7705 <= UInt<1>("h00") - node T_7706 = bits(T_7705, 38, 0) @[csr.scala 639:28] - T_7686.address <= T_7706 @[csr.scala 639:28] - node T_7707 = bits(T_7705, 39, 39) @[csr.scala 639:28] - T_7686.control.r <= T_7707 @[csr.scala 639:28] - node T_7708 = bits(T_7705, 40, 40) @[csr.scala 639:28] - T_7686.control.w <= T_7708 @[csr.scala 639:28] - node T_7709 = bits(T_7705, 41, 41) @[csr.scala 639:28] - T_7686.control.x <= T_7709 @[csr.scala 639:28] - node T_7710 = bits(T_7705, 42, 42) @[csr.scala 639:28] - T_7686.control.u <= T_7710 @[csr.scala 639:28] - node T_7711 = bits(T_7705, 43, 43) @[csr.scala 639:28] - T_7686.control.s <= T_7711 @[csr.scala 639:28] - node T_7712 = bits(T_7705, 44, 44) @[csr.scala 639:28] - T_7686.control.h <= T_7712 @[csr.scala 639:28] - node T_7713 = bits(T_7705, 45, 45) @[csr.scala 639:28] - T_7686.control.m <= T_7713 @[csr.scala 639:28] - node T_7714 = bits(T_7705, 47, 46) @[csr.scala 639:28] - T_7686.control.tmatch <= T_7714 @[csr.scala 639:28] - node T_7715 = bits(T_7705, 49, 48) @[csr.scala 639:28] - T_7686.control.zero <= T_7715 @[csr.scala 639:28] - node T_7716 = bits(T_7705, 50, 50) @[csr.scala 639:28] - T_7686.control.chain <= T_7716 @[csr.scala 639:28] - node T_7717 = bits(T_7705, 51, 51) @[csr.scala 639:28] - T_7686.control.action <= T_7717 @[csr.scala 639:28] - node T_7718 = bits(T_7705, 91, 52) @[csr.scala 639:28] - T_7686.control.reserved <= T_7718 @[csr.scala 639:28] - node T_7719 = bits(T_7705, 97, 92) @[csr.scala 639:28] - T_7686.control.maskmax <= T_7719 @[csr.scala 639:28] - node T_7720 = bits(T_7705, 98, 98) @[csr.scala 639:28] - T_7686.control.dmode <= T_7720 @[csr.scala 639:28] - node T_7721 = bits(T_7705, 102, 99) @[csr.scala 639:28] - T_7686.control.ttype <= T_7721 @[csr.scala 639:28] - reg_bp[1] <- T_7686 @[csr.scala 639:8] - - module BreakpointUnit : + T_7705 <= UInt<1>("h0") + node T_7706 = bits(T_7705, 38, 0) + T_7686.address <= T_7706 + node T_7707 = bits(T_7705, 39, 39) + T_7686.control.r <= T_7707 + node T_7708 = bits(T_7705, 40, 40) + T_7686.control.w <= T_7708 + node T_7709 = bits(T_7705, 41, 41) + T_7686.control.x <= T_7709 + node T_7710 = bits(T_7705, 42, 42) + T_7686.control.u <= T_7710 + node T_7711 = bits(T_7705, 43, 43) + T_7686.control.s <= T_7711 + node T_7712 = bits(T_7705, 44, 44) + T_7686.control.h <= T_7712 + node T_7713 = bits(T_7705, 45, 45) + T_7686.control.m <= T_7713 + node T_7714 = bits(T_7705, 47, 46) + T_7686.control.tmatch <= T_7714 + node T_7715 = bits(T_7705, 49, 48) + T_7686.control.zero <= T_7715 + node T_7716 = bits(T_7705, 50, 50) + T_7686.control.chain <= T_7716 + node T_7717 = bits(T_7705, 51, 51) + T_7686.control.action <= T_7717 + node T_7718 = bits(T_7705, 91, 52) + T_7686.control.reserved <= T_7718 + node T_7719 = bits(T_7705, 97, 92) + T_7686.control.maskmax <= T_7719 + node T_7720 = bits(T_7705, 98, 98) + T_7686.control.dmode <= T_7720 + node T_7721 = bits(T_7705, 102, 99) + T_7686.control.ttype <= T_7721 + reg_bp[1] <- T_7686 + + module BreakpointUnit : input clk : Clock input reset : UInt<1> - output io : {flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip pc : UInt<39>, flip ea : UInt<39>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>} - + output io : { flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip pc : UInt<39>, flip ea : UInt<39>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>} + io is invalid - io.xcpt_if <= UInt<1>("h00") @[breakpoint.scala 63:14] - io.xcpt_ld <= UInt<1>("h00") @[breakpoint.scala 64:14] - io.xcpt_st <= UInt<1>("h00") @[breakpoint.scala 65:14] - io.debug_if <= UInt<1>("h00") @[breakpoint.scala 66:15] - io.debug_ld <= UInt<1>("h00") @[breakpoint.scala 67:15] - io.debug_st <= UInt<1>("h00") @[breakpoint.scala 68:15] - node T_214 = eq(io.status.debug, UInt<1>("h00")) @[breakpoint.scala 29:35] - node T_215 = cat(io.bp[0].control.s, io.bp[0].control.u) @[Cat.scala 20:58] - node T_216 = cat(io.bp[0].control.m, io.bp[0].control.h) @[Cat.scala 20:58] - node T_217 = cat(T_216, T_215) @[Cat.scala 20:58] - node T_218 = dshr(T_217, io.status.prv) @[breakpoint.scala 29:68] - node T_219 = bits(T_218, 0, 0) @[breakpoint.scala 29:68] - node T_220 = and(T_214, T_219) @[breakpoint.scala 29:50] - node T_221 = and(T_220, UInt<1>("h01")) @[breakpoint.scala 72:16] - node T_222 = and(T_221, io.bp[0].control.r) @[breakpoint.scala 72:22] - node T_223 = bits(io.bp[0].control.tmatch, 1, 1) @[breakpoint.scala 46:23] - node T_224 = geq(io.ea, io.bp[0].address) @[breakpoint.scala 43:8] - node T_225 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 43:36] - node T_226 = xor(T_224, T_225) @[breakpoint.scala 43:20] - node T_227 = not(io.ea) @[breakpoint.scala 40:6] - node T_228 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_229 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_230 = and(T_228, T_229) @[breakpoint.scala 37:73] - node T_231 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_232 = and(T_230, T_231) @[breakpoint.scala 37:73] - node T_233 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_234 = and(T_232, T_233) @[breakpoint.scala 37:73] - node T_235 = cat(T_230, T_228) @[Cat.scala 20:58] - node T_236 = cat(T_234, T_232) @[Cat.scala 20:58] - node T_237 = cat(T_236, T_235) @[Cat.scala 20:58] - node T_238 = or(T_227, T_237) @[breakpoint.scala 40:9] - node T_239 = not(io.bp[0].address) @[breakpoint.scala 40:24] - node T_240 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_241 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_242 = and(T_240, T_241) @[breakpoint.scala 37:73] - node T_243 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_244 = and(T_242, T_243) @[breakpoint.scala 37:73] - node T_245 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_246 = and(T_244, T_245) @[breakpoint.scala 37:73] - node T_247 = cat(T_242, T_240) @[Cat.scala 20:58] - node T_248 = cat(T_246, T_244) @[Cat.scala 20:58] - node T_249 = cat(T_248, T_247) @[Cat.scala 20:58] - node T_250 = or(T_239, T_249) @[breakpoint.scala 40:33] - node T_251 = eq(T_238, T_250) @[breakpoint.scala 40:19] - node T_252 = mux(T_223, T_226, T_251) @[breakpoint.scala 46:8] - node T_253 = and(T_222, T_252) @[breakpoint.scala 72:38] - node T_254 = and(T_220, UInt<1>("h01")) @[breakpoint.scala 73:16] - node T_255 = and(T_254, io.bp[0].control.w) @[breakpoint.scala 73:22] - node T_256 = bits(io.bp[0].control.tmatch, 1, 1) @[breakpoint.scala 46:23] - node T_257 = geq(io.ea, io.bp[0].address) @[breakpoint.scala 43:8] - node T_258 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 43:36] - node T_259 = xor(T_257, T_258) @[breakpoint.scala 43:20] - node T_260 = not(io.ea) @[breakpoint.scala 40:6] - node T_261 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_262 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_263 = and(T_261, T_262) @[breakpoint.scala 37:73] - node T_264 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_265 = and(T_263, T_264) @[breakpoint.scala 37:73] - node T_266 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_267 = and(T_265, T_266) @[breakpoint.scala 37:73] - node T_268 = cat(T_263, T_261) @[Cat.scala 20:58] - node T_269 = cat(T_267, T_265) @[Cat.scala 20:58] - node T_270 = cat(T_269, T_268) @[Cat.scala 20:58] - node T_271 = or(T_260, T_270) @[breakpoint.scala 40:9] - node T_272 = not(io.bp[0].address) @[breakpoint.scala 40:24] - node T_273 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_274 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_275 = and(T_273, T_274) @[breakpoint.scala 37:73] - node T_276 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_277 = and(T_275, T_276) @[breakpoint.scala 37:73] - node T_278 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_279 = and(T_277, T_278) @[breakpoint.scala 37:73] - node T_280 = cat(T_275, T_273) @[Cat.scala 20:58] - node T_281 = cat(T_279, T_277) @[Cat.scala 20:58] - node T_282 = cat(T_281, T_280) @[Cat.scala 20:58] - node T_283 = or(T_272, T_282) @[breakpoint.scala 40:33] - node T_284 = eq(T_271, T_283) @[breakpoint.scala 40:19] - node T_285 = mux(T_256, T_259, T_284) @[breakpoint.scala 46:8] - node T_286 = and(T_255, T_285) @[breakpoint.scala 73:38] - node T_287 = and(T_220, UInt<1>("h01")) @[breakpoint.scala 74:16] - node T_288 = and(T_287, io.bp[0].control.x) @[breakpoint.scala 74:22] - node T_289 = bits(io.bp[0].control.tmatch, 1, 1) @[breakpoint.scala 46:23] - node T_290 = geq(io.pc, io.bp[0].address) @[breakpoint.scala 43:8] - node T_291 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 43:36] - node T_292 = xor(T_290, T_291) @[breakpoint.scala 43:20] - node T_293 = not(io.pc) @[breakpoint.scala 40:6] - node T_294 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_295 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_296 = and(T_294, T_295) @[breakpoint.scala 37:73] - node T_297 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_298 = and(T_296, T_297) @[breakpoint.scala 37:73] - node T_299 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_300 = and(T_298, T_299) @[breakpoint.scala 37:73] - node T_301 = cat(T_296, T_294) @[Cat.scala 20:58] - node T_302 = cat(T_300, T_298) @[Cat.scala 20:58] - node T_303 = cat(T_302, T_301) @[Cat.scala 20:58] - node T_304 = or(T_293, T_303) @[breakpoint.scala 40:9] - node T_305 = not(io.bp[0].address) @[breakpoint.scala 40:24] - node T_306 = bits(io.bp[0].control.tmatch, 0, 0) @[breakpoint.scala 37:56] - node T_307 = bits(io.bp[0].address, 0, 0) @[breakpoint.scala 37:83] - node T_308 = and(T_306, T_307) @[breakpoint.scala 37:73] - node T_309 = bits(io.bp[0].address, 1, 1) @[breakpoint.scala 37:83] - node T_310 = and(T_308, T_309) @[breakpoint.scala 37:73] - node T_311 = bits(io.bp[0].address, 2, 2) @[breakpoint.scala 37:83] - node T_312 = and(T_310, T_311) @[breakpoint.scala 37:73] - node T_313 = cat(T_308, T_306) @[Cat.scala 20:58] - node T_314 = cat(T_312, T_310) @[Cat.scala 20:58] - node T_315 = cat(T_314, T_313) @[Cat.scala 20:58] - node T_316 = or(T_305, T_315) @[breakpoint.scala 40:33] - node T_317 = eq(T_304, T_316) @[breakpoint.scala 40:19] - node T_318 = mux(T_289, T_292, T_317) @[breakpoint.scala 46:8] - node T_319 = and(T_288, T_318) @[breakpoint.scala 74:38] - node T_321 = eq(io.bp[0].control.chain, UInt<1>("h00")) @[breakpoint.scala 75:15] - node T_322 = and(T_321, T_253) @[breakpoint.scala 77:15] - when T_322 : @[breakpoint.scala 77:21] - node T_324 = eq(io.bp[0].control.action, UInt<1>("h00")) @[breakpoint.scala 77:37] - io.xcpt_ld <= T_324 @[breakpoint.scala 77:34] - io.debug_ld <= io.bp[0].control.action @[breakpoint.scala 77:69] - skip @[breakpoint.scala 77:21] - node T_325 = and(T_321, T_286) @[breakpoint.scala 78:15] - when T_325 : @[breakpoint.scala 78:21] - node T_327 = eq(io.bp[0].control.action, UInt<1>("h00")) @[breakpoint.scala 78:37] - io.xcpt_st <= T_327 @[breakpoint.scala 78:34] - io.debug_st <= io.bp[0].control.action @[breakpoint.scala 78:69] - skip @[breakpoint.scala 78:21] - node T_328 = and(T_321, T_319) @[breakpoint.scala 79:15] - when T_328 : @[breakpoint.scala 79:21] - node T_330 = eq(io.bp[0].control.action, UInt<1>("h00")) @[breakpoint.scala 79:37] - io.xcpt_if <= T_330 @[breakpoint.scala 79:34] - io.debug_if <= io.bp[0].control.action @[breakpoint.scala 79:69] - skip @[breakpoint.scala 79:21] - node T_331 = or(T_321, T_253) @[breakpoint.scala 81:10] - node T_332 = or(T_321, T_286) @[breakpoint.scala 81:20] - node T_333 = or(T_321, T_319) @[breakpoint.scala 81:30] - - module ALU : + io.xcpt_if <= UInt<1>("h0") + io.xcpt_ld <= UInt<1>("h0") + io.xcpt_st <= UInt<1>("h0") + io.debug_if <= UInt<1>("h0") + io.debug_ld <= UInt<1>("h0") + io.debug_st <= UInt<1>("h0") + node T_214 = eq(io.status.debug, UInt<1>("h0")) + node T_215 = cat(io.bp[0].control.s, io.bp[0].control.u) + node T_216 = cat(io.bp[0].control.m, io.bp[0].control.h) + node T_217 = cat(T_216, T_215) + node T_218 = dshr(T_217, io.status.prv) + node T_219 = bits(T_218, 0, 0) + node T_220 = and(T_214, T_219) + node T_221 = and(T_220, UInt<1>("h1")) + node T_222 = and(T_221, io.bp[0].control.r) + node T_223 = bits(io.bp[0].control.tmatch, 1, 1) + node T_224 = geq(io.ea, io.bp[0].address) + node T_225 = bits(io.bp[0].control.tmatch, 0, 0) + node T_226 = xor(T_224, T_225) + node T_227 = not(io.ea) + node T_228 = bits(io.bp[0].control.tmatch, 0, 0) + node T_229 = bits(io.bp[0].address, 0, 0) + node T_230 = and(T_228, T_229) + node T_231 = bits(io.bp[0].address, 1, 1) + node T_232 = and(T_230, T_231) + node T_233 = bits(io.bp[0].address, 2, 2) + node T_234 = and(T_232, T_233) + node T_235 = cat(T_230, T_228) + node T_236 = cat(T_234, T_232) + node T_237 = cat(T_236, T_235) + node T_238 = or(T_227, T_237) + node T_239 = not(io.bp[0].address) + node T_240 = bits(io.bp[0].control.tmatch, 0, 0) + node T_241 = bits(io.bp[0].address, 0, 0) + node T_242 = and(T_240, T_241) + node T_243 = bits(io.bp[0].address, 1, 1) + node T_244 = and(T_242, T_243) + node T_245 = bits(io.bp[0].address, 2, 2) + node T_246 = and(T_244, T_245) + node T_247 = cat(T_242, T_240) + node T_248 = cat(T_246, T_244) + node T_249 = cat(T_248, T_247) + node T_250 = or(T_239, T_249) + node T_251 = eq(T_238, T_250) + node T_252 = mux(T_223, T_226, T_251) + node T_253 = and(T_222, T_252) + node T_254 = and(T_220, UInt<1>("h1")) + node T_255 = and(T_254, io.bp[0].control.w) + node T_256 = bits(io.bp[0].control.tmatch, 1, 1) + node T_257 = geq(io.ea, io.bp[0].address) + node T_258 = bits(io.bp[0].control.tmatch, 0, 0) + node T_259 = xor(T_257, T_258) + node T_260 = not(io.ea) + node T_261 = bits(io.bp[0].control.tmatch, 0, 0) + node T_262 = bits(io.bp[0].address, 0, 0) + node T_263 = and(T_261, T_262) + node T_264 = bits(io.bp[0].address, 1, 1) + node T_265 = and(T_263, T_264) + node T_266 = bits(io.bp[0].address, 2, 2) + node T_267 = and(T_265, T_266) + node T_268 = cat(T_263, T_261) + node T_269 = cat(T_267, T_265) + node T_270 = cat(T_269, T_268) + node T_271 = or(T_260, T_270) + node T_272 = not(io.bp[0].address) + node T_273 = bits(io.bp[0].control.tmatch, 0, 0) + node T_274 = bits(io.bp[0].address, 0, 0) + node T_275 = and(T_273, T_274) + node T_276 = bits(io.bp[0].address, 1, 1) + node T_277 = and(T_275, T_276) + node T_278 = bits(io.bp[0].address, 2, 2) + node T_279 = and(T_277, T_278) + node T_280 = cat(T_275, T_273) + node T_281 = cat(T_279, T_277) + node T_282 = cat(T_281, T_280) + node T_283 = or(T_272, T_282) + node T_284 = eq(T_271, T_283) + node T_285 = mux(T_256, T_259, T_284) + node T_286 = and(T_255, T_285) + node T_287 = and(T_220, UInt<1>("h1")) + node T_288 = and(T_287, io.bp[0].control.x) + node T_289 = bits(io.bp[0].control.tmatch, 1, 1) + node T_290 = geq(io.pc, io.bp[0].address) + node T_291 = bits(io.bp[0].control.tmatch, 0, 0) + node T_292 = xor(T_290, T_291) + node T_293 = not(io.pc) + node T_294 = bits(io.bp[0].control.tmatch, 0, 0) + node T_295 = bits(io.bp[0].address, 0, 0) + node T_296 = and(T_294, T_295) + node T_297 = bits(io.bp[0].address, 1, 1) + node T_298 = and(T_296, T_297) + node T_299 = bits(io.bp[0].address, 2, 2) + node T_300 = and(T_298, T_299) + node T_301 = cat(T_296, T_294) + node T_302 = cat(T_300, T_298) + node T_303 = cat(T_302, T_301) + node T_304 = or(T_293, T_303) + node T_305 = not(io.bp[0].address) + node T_306 = bits(io.bp[0].control.tmatch, 0, 0) + node T_307 = bits(io.bp[0].address, 0, 0) + node T_308 = and(T_306, T_307) + node T_309 = bits(io.bp[0].address, 1, 1) + node T_310 = and(T_308, T_309) + node T_311 = bits(io.bp[0].address, 2, 2) + node T_312 = and(T_310, T_311) + node T_313 = cat(T_308, T_306) + node T_314 = cat(T_312, T_310) + node T_315 = cat(T_314, T_313) + node T_316 = or(T_305, T_315) + node T_317 = eq(T_304, T_316) + node T_318 = mux(T_289, T_292, T_317) + node T_319 = and(T_288, T_318) + node T_321 = eq(io.bp[0].control.chain, UInt<1>("h0")) + node T_322 = and(T_321, T_253) + when T_322 : + node T_324 = eq(io.bp[0].control.action, UInt<1>("h0")) + io.xcpt_ld <= T_324 + io.debug_ld <= io.bp[0].control.action + node T_325 = and(T_321, T_286) + when T_325 : + node T_327 = eq(io.bp[0].control.action, UInt<1>("h0")) + io.xcpt_st <= T_327 + io.debug_st <= io.bp[0].control.action + node T_328 = and(T_321, T_319) + when T_328 : + node T_330 = eq(io.bp[0].control.action, UInt<1>("h0")) + io.xcpt_if <= T_330 + io.debug_if <= io.bp[0].control.action + node T_331 = or(T_321, T_253) + node T_332 = or(T_321, T_286) + node T_333 = or(T_321, T_319) + + module ALU : input clk : Clock input reset : UInt<1> - output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} - + output io : { flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} + io is invalid - node T_7 = bits(io.fn, 3, 3) @[dpath_alu.scala 39:29] - node T_8 = not(io.in2) @[dpath_alu.scala 59:35] - node in2_inv = mux(T_7, T_8, io.in2) @[dpath_alu.scala 59:20] - node in1_xor_in2 = xor(io.in1, in2_inv) @[dpath_alu.scala 60:28] - node T_9 = add(io.in1, in2_inv) @[dpath_alu.scala 61:26] - node T_10 = tail(T_9, 1) @[dpath_alu.scala 61:26] - node T_11 = bits(io.fn, 3, 3) @[dpath_alu.scala 39:29] - node T_12 = add(T_10, T_11) @[dpath_alu.scala 61:36] - node T_13 = tail(T_12, 1) @[dpath_alu.scala 61:36] - io.adder_out <= T_13 @[dpath_alu.scala 61:16] - node T_14 = bits(io.fn, 0, 0) @[dpath_alu.scala 42:35] - node T_15 = bits(io.fn, 3, 3) @[dpath_alu.scala 43:30] - node T_17 = eq(T_15, UInt<1>("h00")) @[dpath_alu.scala 43:26] - node T_19 = eq(in1_xor_in2, UInt<1>("h00")) @[dpath_alu.scala 65:35] - node T_20 = bits(io.in1, 63, 63) @[dpath_alu.scala 66:15] - node T_21 = bits(io.in2, 63, 63) @[dpath_alu.scala 66:34] - node T_22 = eq(T_20, T_21) @[dpath_alu.scala 66:24] - node T_23 = bits(io.adder_out, 63, 63) @[dpath_alu.scala 66:56] - node T_24 = bits(io.fn, 1, 1) @[dpath_alu.scala 41:35] - node T_25 = bits(io.in2, 63, 63) @[dpath_alu.scala 67:35] - node T_26 = bits(io.in1, 63, 63) @[dpath_alu.scala 67:51] - node T_27 = mux(T_24, T_25, T_26) @[dpath_alu.scala 67:8] - node T_28 = mux(T_22, T_23, T_27) @[dpath_alu.scala 66:8] - node T_29 = mux(T_17, T_19, T_28) @[dpath_alu.scala 65:8] - node T_30 = xor(T_14, T_29) @[dpath_alu.scala 64:36] - io.cmp_out <= T_30 @[dpath_alu.scala 64:14] - node T_31 = bits(io.fn, 3, 3) @[dpath_alu.scala 39:29] - node T_32 = bits(io.in1, 31, 31) @[dpath_alu.scala 74:55] - node T_33 = and(T_31, T_32) @[dpath_alu.scala 74:46] - node T_34 = bits(T_33, 0, 0) @[Bitwise.scala 33:15] - node T_37 = mux(T_34, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_38 = eq(io.dw, UInt<1>("h01")) @[dpath_alu.scala 75:31] - node T_39 = bits(io.in1, 63, 32) @[dpath_alu.scala 75:48] - node T_40 = mux(T_38, T_39, T_37) @[dpath_alu.scala 75:24] - node T_41 = bits(io.in2, 5, 5) @[dpath_alu.scala 76:29] - node T_42 = eq(io.dw, UInt<1>("h01")) @[dpath_alu.scala 76:42] - node T_43 = and(T_41, T_42) @[dpath_alu.scala 76:33] - node T_44 = bits(io.in2, 4, 0) @[dpath_alu.scala 76:60] - node shamt = cat(T_43, T_44) @[Cat.scala 20:58] - node T_45 = bits(io.in1, 31, 0) @[dpath_alu.scala 77:34] - node shin_r = cat(T_40, T_45) @[Cat.scala 20:58] - node T_46 = eq(io.fn, UInt<3>("h05")) @[dpath_alu.scala 79:24] - node T_47 = eq(io.fn, UInt<4>("h0b")) @[dpath_alu.scala 79:44] - node T_48 = or(T_46, T_47) @[dpath_alu.scala 79:35] - node T_51 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 58:47] - node T_52 = xor(UInt<64>("h0ffffffffffffffff"), T_51) @[Bitwise.scala 58:21] - node T_53 = shr(shin_r, 32) @[Bitwise.scala 59:21] - node T_54 = and(T_53, T_52) @[Bitwise.scala 59:31] - node T_55 = bits(shin_r, 31, 0) @[Bitwise.scala 59:46] - node T_56 = shl(T_55, 32) @[Bitwise.scala 59:65] - node T_57 = not(T_52) @[Bitwise.scala 59:77] - node T_58 = and(T_56, T_57) @[Bitwise.scala 59:75] - node T_59 = or(T_54, T_58) @[Bitwise.scala 59:39] - node T_60 = bits(T_52, 47, 0) @[Bitwise.scala 58:28] - node T_61 = shl(T_60, 16) @[Bitwise.scala 58:47] - node T_62 = xor(T_52, T_61) @[Bitwise.scala 58:21] - node T_63 = shr(T_59, 16) @[Bitwise.scala 59:21] - node T_64 = and(T_63, T_62) @[Bitwise.scala 59:31] - node T_65 = bits(T_59, 47, 0) @[Bitwise.scala 59:46] - node T_66 = shl(T_65, 16) @[Bitwise.scala 59:65] - node T_67 = not(T_62) @[Bitwise.scala 59:77] - node T_68 = and(T_66, T_67) @[Bitwise.scala 59:75] - node T_69 = or(T_64, T_68) @[Bitwise.scala 59:39] - node T_70 = bits(T_62, 55, 0) @[Bitwise.scala 58:28] - node T_71 = shl(T_70, 8) @[Bitwise.scala 58:47] - node T_72 = xor(T_62, T_71) @[Bitwise.scala 58:21] - node T_73 = shr(T_69, 8) @[Bitwise.scala 59:21] - node T_74 = and(T_73, T_72) @[Bitwise.scala 59:31] - node T_75 = bits(T_69, 55, 0) @[Bitwise.scala 59:46] - node T_76 = shl(T_75, 8) @[Bitwise.scala 59:65] - node T_77 = not(T_72) @[Bitwise.scala 59:77] - node T_78 = and(T_76, T_77) @[Bitwise.scala 59:75] - node T_79 = or(T_74, T_78) @[Bitwise.scala 59:39] - node T_80 = bits(T_72, 59, 0) @[Bitwise.scala 58:28] - node T_81 = shl(T_80, 4) @[Bitwise.scala 58:47] - node T_82 = xor(T_72, T_81) @[Bitwise.scala 58:21] - node T_83 = shr(T_79, 4) @[Bitwise.scala 59:21] - node T_84 = and(T_83, T_82) @[Bitwise.scala 59:31] - node T_85 = bits(T_79, 59, 0) @[Bitwise.scala 59:46] - node T_86 = shl(T_85, 4) @[Bitwise.scala 59:65] - node T_87 = not(T_82) @[Bitwise.scala 59:77] - node T_88 = and(T_86, T_87) @[Bitwise.scala 59:75] - node T_89 = or(T_84, T_88) @[Bitwise.scala 59:39] - node T_90 = bits(T_82, 61, 0) @[Bitwise.scala 58:28] - node T_91 = shl(T_90, 2) @[Bitwise.scala 58:47] - node T_92 = xor(T_82, T_91) @[Bitwise.scala 58:21] - node T_93 = shr(T_89, 2) @[Bitwise.scala 59:21] - node T_94 = and(T_93, T_92) @[Bitwise.scala 59:31] - node T_95 = bits(T_89, 61, 0) @[Bitwise.scala 59:46] - node T_96 = shl(T_95, 2) @[Bitwise.scala 59:65] - node T_97 = not(T_92) @[Bitwise.scala 59:77] - node T_98 = and(T_96, T_97) @[Bitwise.scala 59:75] - node T_99 = or(T_94, T_98) @[Bitwise.scala 59:39] - node T_100 = bits(T_92, 62, 0) @[Bitwise.scala 58:28] - node T_101 = shl(T_100, 1) @[Bitwise.scala 58:47] - node T_102 = xor(T_92, T_101) @[Bitwise.scala 58:21] - node T_103 = shr(T_99, 1) @[Bitwise.scala 59:21] - node T_104 = and(T_103, T_102) @[Bitwise.scala 59:31] - node T_105 = bits(T_99, 62, 0) @[Bitwise.scala 59:46] - node T_106 = shl(T_105, 1) @[Bitwise.scala 59:65] - node T_107 = not(T_102) @[Bitwise.scala 59:77] - node T_108 = and(T_106, T_107) @[Bitwise.scala 59:75] - node T_109 = or(T_104, T_108) @[Bitwise.scala 59:39] - node shin = mux(T_48, shin_r, T_109) @[dpath_alu.scala 79:17] - node T_110 = bits(io.fn, 3, 3) @[dpath_alu.scala 39:29] - node T_111 = bits(shin, 63, 63) @[dpath_alu.scala 80:41] - node T_112 = and(T_110, T_111) @[dpath_alu.scala 80:35] - node T_113 = cat(T_112, shin) @[Cat.scala 20:58] - node T_114 = asSInt(T_113) @[dpath_alu.scala 80:57] - node T_115 = dshr(T_114, shamt) @[dpath_alu.scala 80:64] - node shout_r = bits(T_115, 63, 0) @[dpath_alu.scala 80:73] - node T_118 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 58:47] - node T_119 = xor(UInt<64>("h0ffffffffffffffff"), T_118) @[Bitwise.scala 58:21] - node T_120 = shr(shout_r, 32) @[Bitwise.scala 59:21] - node T_121 = and(T_120, T_119) @[Bitwise.scala 59:31] - node T_122 = bits(shout_r, 31, 0) @[Bitwise.scala 59:46] - node T_123 = shl(T_122, 32) @[Bitwise.scala 59:65] - node T_124 = not(T_119) @[Bitwise.scala 59:77] - node T_125 = and(T_123, T_124) @[Bitwise.scala 59:75] - node T_126 = or(T_121, T_125) @[Bitwise.scala 59:39] - node T_127 = bits(T_119, 47, 0) @[Bitwise.scala 58:28] - node T_128 = shl(T_127, 16) @[Bitwise.scala 58:47] - node T_129 = xor(T_119, T_128) @[Bitwise.scala 58:21] - node T_130 = shr(T_126, 16) @[Bitwise.scala 59:21] - node T_131 = and(T_130, T_129) @[Bitwise.scala 59:31] - node T_132 = bits(T_126, 47, 0) @[Bitwise.scala 59:46] - node T_133 = shl(T_132, 16) @[Bitwise.scala 59:65] - node T_134 = not(T_129) @[Bitwise.scala 59:77] - node T_135 = and(T_133, T_134) @[Bitwise.scala 59:75] - node T_136 = or(T_131, T_135) @[Bitwise.scala 59:39] - node T_137 = bits(T_129, 55, 0) @[Bitwise.scala 58:28] - node T_138 = shl(T_137, 8) @[Bitwise.scala 58:47] - node T_139 = xor(T_129, T_138) @[Bitwise.scala 58:21] - node T_140 = shr(T_136, 8) @[Bitwise.scala 59:21] - node T_141 = and(T_140, T_139) @[Bitwise.scala 59:31] - node T_142 = bits(T_136, 55, 0) @[Bitwise.scala 59:46] - node T_143 = shl(T_142, 8) @[Bitwise.scala 59:65] - node T_144 = not(T_139) @[Bitwise.scala 59:77] - node T_145 = and(T_143, T_144) @[Bitwise.scala 59:75] - node T_146 = or(T_141, T_145) @[Bitwise.scala 59:39] - node T_147 = bits(T_139, 59, 0) @[Bitwise.scala 58:28] - node T_148 = shl(T_147, 4) @[Bitwise.scala 58:47] - node T_149 = xor(T_139, T_148) @[Bitwise.scala 58:21] - node T_150 = shr(T_146, 4) @[Bitwise.scala 59:21] - node T_151 = and(T_150, T_149) @[Bitwise.scala 59:31] - node T_152 = bits(T_146, 59, 0) @[Bitwise.scala 59:46] - node T_153 = shl(T_152, 4) @[Bitwise.scala 59:65] - node T_154 = not(T_149) @[Bitwise.scala 59:77] - node T_155 = and(T_153, T_154) @[Bitwise.scala 59:75] - node T_156 = or(T_151, T_155) @[Bitwise.scala 59:39] - node T_157 = bits(T_149, 61, 0) @[Bitwise.scala 58:28] - node T_158 = shl(T_157, 2) @[Bitwise.scala 58:47] - node T_159 = xor(T_149, T_158) @[Bitwise.scala 58:21] - node T_160 = shr(T_156, 2) @[Bitwise.scala 59:21] - node T_161 = and(T_160, T_159) @[Bitwise.scala 59:31] - node T_162 = bits(T_156, 61, 0) @[Bitwise.scala 59:46] - node T_163 = shl(T_162, 2) @[Bitwise.scala 59:65] - node T_164 = not(T_159) @[Bitwise.scala 59:77] - node T_165 = and(T_163, T_164) @[Bitwise.scala 59:75] - node T_166 = or(T_161, T_165) @[Bitwise.scala 59:39] - node T_167 = bits(T_159, 62, 0) @[Bitwise.scala 58:28] - node T_168 = shl(T_167, 1) @[Bitwise.scala 58:47] - node T_169 = xor(T_159, T_168) @[Bitwise.scala 58:21] - node T_170 = shr(T_166, 1) @[Bitwise.scala 59:21] - node T_171 = and(T_170, T_169) @[Bitwise.scala 59:31] - node T_172 = bits(T_166, 62, 0) @[Bitwise.scala 59:46] - node T_173 = shl(T_172, 1) @[Bitwise.scala 59:65] - node T_174 = not(T_169) @[Bitwise.scala 59:77] - node T_175 = and(T_173, T_174) @[Bitwise.scala 59:75] - node shout_l = or(T_171, T_175) @[Bitwise.scala 59:39] - node T_176 = eq(io.fn, UInt<3>("h05")) @[dpath_alu.scala 82:25] - node T_177 = eq(io.fn, UInt<4>("h0b")) @[dpath_alu.scala 82:44] - node T_178 = or(T_176, T_177) @[dpath_alu.scala 82:35] - node T_180 = mux(T_178, shout_r, UInt<1>("h00")) @[dpath_alu.scala 82:18] - node T_181 = eq(io.fn, UInt<1>("h01")) @[dpath_alu.scala 83:25] - node T_183 = mux(T_181, shout_l, UInt<1>("h00")) @[dpath_alu.scala 83:18] - node shout = or(T_180, T_183) @[dpath_alu.scala 82:74] - node T_184 = eq(io.fn, UInt<3>("h04")) @[dpath_alu.scala 86:25] - node T_185 = eq(io.fn, UInt<3>("h06")) @[dpath_alu.scala 86:45] - node T_186 = or(T_184, T_185) @[dpath_alu.scala 86:36] - node T_188 = mux(T_186, in1_xor_in2, UInt<1>("h00")) @[dpath_alu.scala 86:18] - node T_189 = eq(io.fn, UInt<3>("h06")) @[dpath_alu.scala 87:25] - node T_190 = eq(io.fn, UInt<3>("h07")) @[dpath_alu.scala 87:44] - node T_191 = or(T_189, T_190) @[dpath_alu.scala 87:35] - node T_192 = and(io.in1, io.in2) @[dpath_alu.scala 87:63] - node T_194 = mux(T_191, T_192, UInt<1>("h00")) @[dpath_alu.scala 87:18] - node logic = or(T_188, T_194) @[dpath_alu.scala 86:78] - node T_195 = eq(io.fn, UInt<2>("h02")) @[dpath_alu.scala 40:30] - node T_196 = eq(io.fn, UInt<2>("h03")) @[dpath_alu.scala 40:48] - node T_197 = or(T_195, T_196) @[dpath_alu.scala 40:41] - node T_198 = geq(io.fn, UInt<4>("h0c")) @[dpath_alu.scala 40:66] - node T_199 = or(T_197, T_198) @[dpath_alu.scala 40:59] - node T_200 = and(T_199, io.cmp_out) @[dpath_alu.scala 88:35] - node T_201 = or(T_200, logic) @[dpath_alu.scala 88:50] - node shift_logic = or(T_201, shout) @[dpath_alu.scala 88:58] - node T_202 = eq(io.fn, UInt<1>("h00")) @[dpath_alu.scala 89:23] - node T_203 = eq(io.fn, UInt<4>("h0a")) @[dpath_alu.scala 89:43] - node T_204 = or(T_202, T_203) @[dpath_alu.scala 89:34] - node out = mux(T_204, io.adder_out, shift_logic) @[dpath_alu.scala 89:16] - io.out <= out @[dpath_alu.scala 91:10] - node T_205 = eq(io.dw, UInt<1>("h00")) @[dpath_alu.scala 94:17] - when T_205 : @[dpath_alu.scala 94:28] - node T_206 = bits(out, 31, 31) @[dpath_alu.scala 94:56] - node T_207 = bits(T_206, 0, 0) @[Bitwise.scala 33:15] - node T_210 = mux(T_207, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_211 = bits(out, 31, 0) @[dpath_alu.scala 94:66] - node T_212 = cat(T_210, T_211) @[Cat.scala 20:58] - io.out <= T_212 @[dpath_alu.scala 94:37] - skip @[dpath_alu.scala 94:28] - - module MulDiv : + node T_7 = bits(io.fn, 3, 3) + node T_8 = not(io.in2) + node in2_inv = mux(T_7, T_8, io.in2) + node in1_xor_in2 = xor(io.in1, in2_inv) + node T_9 = add(io.in1, in2_inv) + node T_10 = tail(T_9, 1) + node T_11 = bits(io.fn, 3, 3) + node T_12 = add(T_10, T_11) + node T_13 = tail(T_12, 1) + io.adder_out <= T_13 + node T_14 = bits(io.fn, 0, 0) + node T_15 = bits(io.fn, 3, 3) + node T_17 = eq(T_15, UInt<1>("h0")) + node T_19 = eq(in1_xor_in2, UInt<1>("h0")) + node T_20 = bits(io.in1, 63, 63) + node T_21 = bits(io.in2, 63, 63) + node T_22 = eq(T_20, T_21) + node T_23 = bits(io.adder_out, 63, 63) + node T_24 = bits(io.fn, 1, 1) + node T_25 = bits(io.in2, 63, 63) + node T_26 = bits(io.in1, 63, 63) + node T_27 = mux(T_24, T_25, T_26) + node T_28 = mux(T_22, T_23, T_27) + node T_29 = mux(T_17, T_19, T_28) + node T_30 = xor(T_14, T_29) + io.cmp_out <= T_30 + node T_31 = bits(io.fn, 3, 3) + node T_32 = bits(io.in1, 31, 31) + node T_33 = and(T_31, T_32) + node T_34 = bits(T_33, 0, 0) + node T_37 = mux(T_34, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_38 = eq(io.dw, UInt<1>("h1")) + node T_39 = bits(io.in1, 63, 32) + node T_40 = mux(T_38, T_39, T_37) + node T_41 = bits(io.in2, 5, 5) + node T_42 = eq(io.dw, UInt<1>("h1")) + node T_43 = and(T_41, T_42) + node T_44 = bits(io.in2, 4, 0) + node shamt = cat(T_43, T_44) + node T_45 = bits(io.in1, 31, 0) + node shin_r = cat(T_40, T_45) + node T_46 = eq(io.fn, UInt<3>("h5")) + node T_47 = eq(io.fn, UInt<4>("hb")) + node T_48 = or(T_46, T_47) + node T_51 = shl(UInt<32>("hffffffff"), 32) + node T_52 = xor(UInt<64>("hffffffffffffffff"), T_51) + node T_53 = shr(shin_r, 32) + node T_54 = and(T_53, T_52) + node T_55 = bits(shin_r, 31, 0) + node T_56 = shl(T_55, 32) + node T_57 = not(T_52) + node T_58 = and(T_56, T_57) + node T_59 = or(T_54, T_58) + node T_60 = bits(T_52, 47, 0) + node T_61 = shl(T_60, 16) + node T_62 = xor(T_52, T_61) + node T_63 = shr(T_59, 16) + node T_64 = and(T_63, T_62) + node T_65 = bits(T_59, 47, 0) + node T_66 = shl(T_65, 16) + node T_67 = not(T_62) + node T_68 = and(T_66, T_67) + node T_69 = or(T_64, T_68) + node T_70 = bits(T_62, 55, 0) + node T_71 = shl(T_70, 8) + node T_72 = xor(T_62, T_71) + node T_73 = shr(T_69, 8) + node T_74 = and(T_73, T_72) + node T_75 = bits(T_69, 55, 0) + node T_76 = shl(T_75, 8) + node T_77 = not(T_72) + node T_78 = and(T_76, T_77) + node T_79 = or(T_74, T_78) + node T_80 = bits(T_72, 59, 0) + node T_81 = shl(T_80, 4) + node T_82 = xor(T_72, T_81) + node T_83 = shr(T_79, 4) + node T_84 = and(T_83, T_82) + node T_85 = bits(T_79, 59, 0) + node T_86 = shl(T_85, 4) + node T_87 = not(T_82) + node T_88 = and(T_86, T_87) + node T_89 = or(T_84, T_88) + node T_90 = bits(T_82, 61, 0) + node T_91 = shl(T_90, 2) + node T_92 = xor(T_82, T_91) + node T_93 = shr(T_89, 2) + node T_94 = and(T_93, T_92) + node T_95 = bits(T_89, 61, 0) + node T_96 = shl(T_95, 2) + node T_97 = not(T_92) + node T_98 = and(T_96, T_97) + node T_99 = or(T_94, T_98) + node T_100 = bits(T_92, 62, 0) + node T_101 = shl(T_100, 1) + node T_102 = xor(T_92, T_101) + node T_103 = shr(T_99, 1) + node T_104 = and(T_103, T_102) + node T_105 = bits(T_99, 62, 0) + node T_106 = shl(T_105, 1) + node T_107 = not(T_102) + node T_108 = and(T_106, T_107) + node T_109 = or(T_104, T_108) + node shin = mux(T_48, shin_r, T_109) + node T_110 = bits(io.fn, 3, 3) + node T_111 = bits(shin, 63, 63) + node T_112 = and(T_110, T_111) + node T_113 = cat(T_112, shin) + node T_114 = asSInt(T_113) + node T_115 = dshr(T_114, shamt) + node shout_r = bits(T_115, 63, 0) + node T_118 = shl(UInt<32>("hffffffff"), 32) + node T_119 = xor(UInt<64>("hffffffffffffffff"), T_118) + node T_120 = shr(shout_r, 32) + node T_121 = and(T_120, T_119) + node T_122 = bits(shout_r, 31, 0) + node T_123 = shl(T_122, 32) + node T_124 = not(T_119) + node T_125 = and(T_123, T_124) + node T_126 = or(T_121, T_125) + node T_127 = bits(T_119, 47, 0) + node T_128 = shl(T_127, 16) + node T_129 = xor(T_119, T_128) + node T_130 = shr(T_126, 16) + node T_131 = and(T_130, T_129) + node T_132 = bits(T_126, 47, 0) + node T_133 = shl(T_132, 16) + node T_134 = not(T_129) + node T_135 = and(T_133, T_134) + node T_136 = or(T_131, T_135) + node T_137 = bits(T_129, 55, 0) + node T_138 = shl(T_137, 8) + node T_139 = xor(T_129, T_138) + node T_140 = shr(T_136, 8) + node T_141 = and(T_140, T_139) + node T_142 = bits(T_136, 55, 0) + node T_143 = shl(T_142, 8) + node T_144 = not(T_139) + node T_145 = and(T_143, T_144) + node T_146 = or(T_141, T_145) + node T_147 = bits(T_139, 59, 0) + node T_148 = shl(T_147, 4) + node T_149 = xor(T_139, T_148) + node T_150 = shr(T_146, 4) + node T_151 = and(T_150, T_149) + node T_152 = bits(T_146, 59, 0) + node T_153 = shl(T_152, 4) + node T_154 = not(T_149) + node T_155 = and(T_153, T_154) + node T_156 = or(T_151, T_155) + node T_157 = bits(T_149, 61, 0) + node T_158 = shl(T_157, 2) + node T_159 = xor(T_149, T_158) + node T_160 = shr(T_156, 2) + node T_161 = and(T_160, T_159) + node T_162 = bits(T_156, 61, 0) + node T_163 = shl(T_162, 2) + node T_164 = not(T_159) + node T_165 = and(T_163, T_164) + node T_166 = or(T_161, T_165) + node T_167 = bits(T_159, 62, 0) + node T_168 = shl(T_167, 1) + node T_169 = xor(T_159, T_168) + node T_170 = shr(T_166, 1) + node T_171 = and(T_170, T_169) + node T_172 = bits(T_166, 62, 0) + node T_173 = shl(T_172, 1) + node T_174 = not(T_169) + node T_175 = and(T_173, T_174) + node shout_l = or(T_171, T_175) + node T_176 = eq(io.fn, UInt<3>("h5")) + node T_177 = eq(io.fn, UInt<4>("hb")) + node T_178 = or(T_176, T_177) + node T_180 = mux(T_178, shout_r, UInt<1>("h0")) + node T_181 = eq(io.fn, UInt<1>("h1")) + node T_183 = mux(T_181, shout_l, UInt<1>("h0")) + node shout = or(T_180, T_183) + node T_184 = eq(io.fn, UInt<3>("h4")) + node T_185 = eq(io.fn, UInt<3>("h6")) + node T_186 = or(T_184, T_185) + node T_188 = mux(T_186, in1_xor_in2, UInt<1>("h0")) + node T_189 = eq(io.fn, UInt<3>("h6")) + node T_190 = eq(io.fn, UInt<3>("h7")) + node T_191 = or(T_189, T_190) + node T_192 = and(io.in1, io.in2) + node T_194 = mux(T_191, T_192, UInt<1>("h0")) + node logic = or(T_188, T_194) + node T_195 = eq(io.fn, UInt<2>("h2")) + node T_196 = eq(io.fn, UInt<2>("h3")) + node T_197 = or(T_195, T_196) + node T_198 = geq(io.fn, UInt<4>("hc")) + node T_199 = or(T_197, T_198) + node T_200 = and(T_199, io.cmp_out) + node T_201 = or(T_200, logic) + node shift_logic = or(T_201, shout) + node T_202 = eq(io.fn, UInt<1>("h0")) + node T_203 = eq(io.fn, UInt<4>("ha")) + node T_204 = or(T_202, T_203) + node out = mux(T_204, io.adder_out, shift_logic) + io.out <= out + node T_205 = eq(io.dw, UInt<1>("h0")) + when T_205 : + node T_206 = bits(out, 31, 31) + node T_207 = bits(T_206, 0, 0) + node T_210 = mux(T_207, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_211 = bits(out, 31, 0) + node T_212 = cat(T_210, T_211) + io.out <= T_212 + + module MulDiv : input clk : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} - + output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}} + io is invalid - reg state : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk - reg count : UInt<7>, clk - reg neg_out : UInt<1>, clk - reg isMul : UInt<1>, clk - reg isHi : UInt<1>, clk - reg divisor : UInt<65>, clk - reg remainder : UInt<130>, clk - node T_62 = and(io.req.bits.fn, UInt<4>("h04")) @[decode.scala 13:65] - node T_64 = eq(T_62, UInt<4>("h00")) @[decode.scala 13:121] - node T_66 = and(io.req.bits.fn, UInt<4>("h08")) @[decode.scala 13:65] - node T_68 = eq(T_66, UInt<4>("h08")) @[decode.scala 13:121] - node T_70 = or(UInt<1>("h00"), T_64) @[decode.scala 14:30] - node T_71 = or(T_70, T_68) @[decode.scala 14:30] - node T_73 = and(io.req.bits.fn, UInt<4>("h05")) @[decode.scala 13:65] - node T_75 = eq(T_73, UInt<4>("h01")) @[decode.scala 13:121] - node T_77 = and(io.req.bits.fn, UInt<4>("h02")) @[decode.scala 13:65] - node T_79 = eq(T_77, UInt<4>("h02")) @[decode.scala 13:121] - node T_81 = or(UInt<1>("h00"), T_75) @[decode.scala 14:30] - node T_82 = or(T_81, T_79) @[decode.scala 14:30] - node T_83 = or(T_82, T_68) @[decode.scala 14:30] - node T_85 = and(io.req.bits.fn, UInt<4>("h09")) @[decode.scala 13:65] - node T_87 = eq(T_85, UInt<4>("h00")) @[decode.scala 13:121] - node T_89 = and(io.req.bits.fn, UInt<4>("h03")) @[decode.scala 13:65] - node T_91 = eq(T_89, UInt<4>("h00")) @[decode.scala 13:121] - node T_93 = or(UInt<1>("h00"), T_87) @[decode.scala 14:30] - node T_94 = or(T_93, T_64) @[decode.scala 14:30] - node T_95 = or(T_94, T_91) @[decode.scala 14:30] - node T_97 = or(UInt<1>("h00"), T_87) @[decode.scala 14:30] - node T_98 = or(T_97, T_64) @[decode.scala 14:30] - node cmdMul = bits(T_71, 0, 0) @[multiplier.scala 61:58] - node cmdHi = bits(T_83, 0, 0) @[multiplier.scala 61:58] - node lhsSigned = bits(T_95, 0, 0) @[multiplier.scala 61:58] - node rhsSigned = bits(T_98, 0, 0) @[multiplier.scala 61:58] - node T_100 = eq(io.req.bits.dw, UInt<1>("h00")) @[multiplier.scala 64:62] - node T_101 = and(UInt<1>("h01"), T_100) @[multiplier.scala 64:52] - node T_102 = bits(io.req.bits.in1, 31, 31) @[multiplier.scala 67:38] - node T_103 = bits(io.req.bits.in1, 63, 63) @[multiplier.scala 67:48] - node T_104 = mux(T_101, T_102, T_103) @[multiplier.scala 67:29] - node lhs_sign = and(lhsSigned, T_104) @[multiplier.scala 67:23] - node T_105 = bits(lhs_sign, 0, 0) @[Bitwise.scala 33:15] - node T_108 = mux(T_105, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_109 = bits(io.req.bits.in1, 63, 32) @[multiplier.scala 68:43] - node T_110 = mux(T_101, T_108, T_109) @[multiplier.scala 68:17] - node T_111 = bits(io.req.bits.in1, 31, 0) @[multiplier.scala 69:15] - node lhs_in = cat(T_110, T_111) @[Cat.scala 20:58] - node T_113 = eq(io.req.bits.dw, UInt<1>("h00")) @[multiplier.scala 64:62] - node T_114 = and(UInt<1>("h01"), T_113) @[multiplier.scala 64:52] - node T_115 = bits(io.req.bits.in2, 31, 31) @[multiplier.scala 67:38] - node T_116 = bits(io.req.bits.in2, 63, 63) @[multiplier.scala 67:48] - node T_117 = mux(T_114, T_115, T_116) @[multiplier.scala 67:29] - node rhs_sign = and(rhsSigned, T_117) @[multiplier.scala 67:23] - node T_118 = bits(rhs_sign, 0, 0) @[Bitwise.scala 33:15] - node T_121 = mux(T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_122 = bits(io.req.bits.in2, 63, 32) @[multiplier.scala 68:43] - node T_123 = mux(T_114, T_121, T_122) @[multiplier.scala 68:17] - node T_124 = bits(io.req.bits.in2, 31, 0) @[multiplier.scala 69:15] - node rhs_in = cat(T_123, T_124) @[Cat.scala 20:58] - node T_125 = bits(remainder, 128, 64) @[multiplier.scala 74:29] - node T_126 = bits(divisor, 64, 0) @[multiplier.scala 74:46] - node T_127 = sub(T_125, T_126) @[multiplier.scala 74:37] - node subtractor = tail(T_127, 1) @[multiplier.scala 74:37] - node less = bits(subtractor, 64, 64) @[multiplier.scala 75:24] - node T_128 = bits(remainder, 63, 0) @[multiplier.scala 76:37] - node T_130 = sub(UInt<1>("h00"), T_128) @[multiplier.scala 76:27] - node negated_remainder = tail(T_130, 1) @[multiplier.scala 76:27] - node T_131 = eq(state, UInt<3>("h01")) @[multiplier.scala 78:15] - when T_131 : @[multiplier.scala 78:33] - node T_132 = bits(remainder, 63, 63) @[multiplier.scala 79:20] - node T_133 = or(T_132, isMul) @[multiplier.scala 79:26] - when T_133 : @[multiplier.scala 79:36] - remainder <= negated_remainder @[multiplier.scala 80:17] - skip @[multiplier.scala 79:36] - node T_134 = bits(divisor, 63, 63) @[multiplier.scala 82:18] - node T_135 = or(T_134, isMul) @[multiplier.scala 82:24] - when T_135 : @[multiplier.scala 82:34] - divisor <= subtractor @[multiplier.scala 83:15] - skip @[multiplier.scala 82:34] - state <= UInt<3>("h02") @[multiplier.scala 85:11] - skip @[multiplier.scala 78:33] - node T_136 = eq(state, UInt<3>("h04")) @[multiplier.scala 88:15] - when T_136 : @[multiplier.scala 88:33] - remainder <= negated_remainder @[multiplier.scala 89:15] - state <= UInt<3>("h05") @[multiplier.scala 90:11] - skip @[multiplier.scala 88:33] - node T_137 = eq(state, UInt<3>("h03")) @[multiplier.scala 92:15] - when T_137 : @[multiplier.scala 92:31] - node T_138 = bits(remainder, 128, 65) @[multiplier.scala 93:27] - remainder <= T_138 @[multiplier.scala 93:15] - node T_139 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[multiplier.scala 94:17] - state <= T_139 @[multiplier.scala 94:11] - skip @[multiplier.scala 92:31] - node T_140 = eq(state, UInt<3>("h02")) @[multiplier.scala 96:15] - node T_141 = and(T_140, isMul) @[multiplier.scala 96:26] - when T_141 : @[multiplier.scala 96:36] - node T_142 = bits(remainder, 129, 65) @[multiplier.scala 97:31] - node T_143 = bits(remainder, 63, 0) @[multiplier.scala 97:55] - node T_144 = cat(T_142, T_143) @[Cat.scala 20:58] - node T_145 = bits(T_144, 63, 0) @[multiplier.scala 98:24] - node T_146 = bits(T_144, 128, 64) @[multiplier.scala 99:23] - node T_147 = asSInt(T_146) @[multiplier.scala 99:37] - node T_148 = asSInt(divisor) @[multiplier.scala 100:26] - node T_149 = bits(T_145, 7, 0) @[multiplier.scala 101:22] - node T_150 = mul(T_148, asSInt(T_149)) @[multiplier.scala 101:43] - node T_151 = add(T_150, T_147) @[multiplier.scala 101:52] - node T_152 = tail(T_151, 1) @[multiplier.scala 101:52] - node T_153 = asSInt(T_152) @[multiplier.scala 101:52] - node T_154 = bits(T_145, 63, 8) @[multiplier.scala 102:38] - node T_155 = asUInt(T_153) @[Cat.scala 20:58] - node T_156 = cat(T_155, T_154) @[Cat.scala 20:58] - node T_159 = mul(count, UInt<4>("h08")) @[multiplier.scala 104:56] - node T_160 = bits(T_159, 5, 0) @[multiplier.scala 104:72] - node T_161 = dshr(asSInt(UInt<65>("h010000000000000000")), T_160) @[multiplier.scala 104:46] - node T_162 = bits(T_161, 63, 0) @[multiplier.scala 104:91] - node T_165 = neq(count, UInt<3>("h07")) @[multiplier.scala 105:47] - node T_166 = and(UInt<1>("h01"), T_165) @[multiplier.scala 105:38] - node T_168 = neq(count, UInt<1>("h00")) @[multiplier.scala 105:81] - node T_169 = and(T_166, T_168) @[multiplier.scala 105:72] - node T_171 = eq(isHi, UInt<1>("h00")) @[multiplier.scala 106:7] - node T_172 = and(T_169, T_171) @[multiplier.scala 105:87] - node T_173 = not(T_162) @[multiplier.scala 106:26] - node T_174 = and(T_145, T_173) @[multiplier.scala 106:24] - node T_176 = eq(T_174, UInt<1>("h00")) @[multiplier.scala 106:37] - node T_177 = and(T_172, T_176) @[multiplier.scala 106:13] - node T_180 = mul(count, UInt<4>("h08")) @[multiplier.scala 107:44] - node T_181 = sub(UInt<7>("h040"), T_180) @[multiplier.scala 107:36] - node T_182 = tail(T_181, 1) @[multiplier.scala 107:36] - node T_183 = bits(T_182, 5, 0) @[multiplier.scala 107:60] - node T_184 = dshr(T_144, T_183) @[multiplier.scala 107:27] - node T_185 = bits(T_156, 128, 64) @[multiplier.scala 108:37] - node T_186 = mux(T_177, T_184, T_156) @[multiplier.scala 108:55] - node T_187 = bits(T_186, 63, 0) @[multiplier.scala 108:82] - node T_188 = cat(T_185, T_187) @[Cat.scala 20:58] - node T_189 = shr(T_188, 64) @[multiplier.scala 109:34] - node T_191 = bits(T_188, 63, 0) @[multiplier.scala 109:64] - node T_192 = cat(T_189, UInt<1>("h00")) @[Cat.scala 20:58] - node T_193 = cat(T_192, T_191) @[Cat.scala 20:58] - remainder <= T_193 @[multiplier.scala 109:15] - node T_195 = add(count, UInt<1>("h01")) @[multiplier.scala 111:20] - node T_196 = tail(T_195, 1) @[multiplier.scala 111:20] - count <= T_196 @[multiplier.scala 111:11] - node T_198 = eq(count, UInt<3>("h07")) @[multiplier.scala 112:25] - node T_199 = or(T_177, T_198) @[multiplier.scala 112:16] - when T_199 : @[multiplier.scala 112:51] - node T_200 = mux(isHi, UInt<3>("h03"), UInt<3>("h05")) @[multiplier.scala 113:19] - state <= T_200 @[multiplier.scala 113:13] - skip @[multiplier.scala 112:51] - skip @[multiplier.scala 96:36] - node T_201 = eq(state, UInt<3>("h02")) @[multiplier.scala 116:15] - node T_203 = eq(isMul, UInt<1>("h00")) @[multiplier.scala 116:29] - node T_204 = and(T_201, T_203) @[multiplier.scala 116:26] - when T_204 : @[multiplier.scala 116:37] - node T_206 = eq(count, UInt<7>("h040")) @[multiplier.scala 117:17] - when T_206 : @[multiplier.scala 117:24] - node T_207 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[multiplier.scala 118:41] - node T_208 = mux(isHi, UInt<3>("h03"), T_207) @[multiplier.scala 118:19] - state <= T_208 @[multiplier.scala 118:13] - skip @[multiplier.scala 117:24] - node T_210 = add(count, UInt<1>("h01")) @[multiplier.scala 120:20] - node T_211 = tail(T_210, 1) @[multiplier.scala 120:20] - count <= T_211 @[multiplier.scala 120:11] - node T_212 = bits(remainder, 127, 64) @[multiplier.scala 122:41] - node T_213 = bits(subtractor, 63, 0) @[multiplier.scala 122:62] - node T_214 = mux(less, T_212, T_213) @[multiplier.scala 122:25] - node T_215 = bits(remainder, 63, 0) @[multiplier.scala 122:81] - node T_217 = eq(less, UInt<1>("h00")) @[multiplier.scala 122:90] - node T_218 = cat(T_214, T_215) @[Cat.scala 20:58] - node T_219 = cat(T_218, T_217) @[Cat.scala 20:58] - remainder <= T_219 @[multiplier.scala 122:15] - node T_220 = bits(divisor, 63, 0) @[multiplier.scala 124:34] - node T_221 = bits(T_220, 63, 32) @[CircuitMath.scala 26:17] - node T_222 = bits(T_220, 31, 0) @[CircuitMath.scala 27:17] - node T_224 = neq(T_221, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_225 = bits(T_221, 31, 16) @[CircuitMath.scala 26:17] - node T_226 = bits(T_221, 15, 0) @[CircuitMath.scala 27:17] - node T_228 = neq(T_225, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_229 = bits(T_225, 15, 8) @[CircuitMath.scala 26:17] - node T_230 = bits(T_225, 7, 0) @[CircuitMath.scala 27:17] - node T_232 = neq(T_229, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_233 = bits(T_229, 7, 4) @[CircuitMath.scala 26:17] - node T_234 = bits(T_229, 3, 0) @[CircuitMath.scala 27:17] - node T_236 = neq(T_233, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_237 = bits(T_233, 3, 3) @[CircuitMath.scala 23:12] - node T_239 = bits(T_233, 2, 2) @[CircuitMath.scala 23:12] - node T_241 = bits(T_233, 1, 1) @[CircuitMath.scala 21:8] - node T_242 = shl(T_241, 0) @[CircuitMath.scala 23:10] - node T_243 = mux(T_239, UInt<2>("h02"), T_242) @[CircuitMath.scala 23:10] - node T_244 = mux(T_237, UInt<2>("h03"), T_243) @[CircuitMath.scala 23:10] - node T_245 = bits(T_234, 3, 3) @[CircuitMath.scala 23:12] - node T_247 = bits(T_234, 2, 2) @[CircuitMath.scala 23:12] - node T_249 = bits(T_234, 1, 1) @[CircuitMath.scala 21:8] - node T_250 = shl(T_249, 0) @[CircuitMath.scala 23:10] - node T_251 = mux(T_247, UInt<2>("h02"), T_250) @[CircuitMath.scala 23:10] - node T_252 = mux(T_245, UInt<2>("h03"), T_251) @[CircuitMath.scala 23:10] - node T_253 = mux(T_236, T_244, T_252) @[CircuitMath.scala 29:21] - node T_254 = cat(T_236, T_253) @[Cat.scala 20:58] - node T_255 = bits(T_230, 7, 4) @[CircuitMath.scala 26:17] - node T_256 = bits(T_230, 3, 0) @[CircuitMath.scala 27:17] - node T_258 = neq(T_255, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_259 = bits(T_255, 3, 3) @[CircuitMath.scala 23:12] - node T_261 = bits(T_255, 2, 2) @[CircuitMath.scala 23:12] - node T_263 = bits(T_255, 1, 1) @[CircuitMath.scala 21:8] - node T_264 = shl(T_263, 0) @[CircuitMath.scala 23:10] - node T_265 = mux(T_261, UInt<2>("h02"), T_264) @[CircuitMath.scala 23:10] - node T_266 = mux(T_259, UInt<2>("h03"), T_265) @[CircuitMath.scala 23:10] - node T_267 = bits(T_256, 3, 3) @[CircuitMath.scala 23:12] - node T_269 = bits(T_256, 2, 2) @[CircuitMath.scala 23:12] - node T_271 = bits(T_256, 1, 1) @[CircuitMath.scala 21:8] - node T_272 = shl(T_271, 0) @[CircuitMath.scala 23:10] - node T_273 = mux(T_269, UInt<2>("h02"), T_272) @[CircuitMath.scala 23:10] - node T_274 = mux(T_267, UInt<2>("h03"), T_273) @[CircuitMath.scala 23:10] - node T_275 = mux(T_258, T_266, T_274) @[CircuitMath.scala 29:21] - node T_276 = cat(T_258, T_275) @[Cat.scala 20:58] - node T_277 = mux(T_232, T_254, T_276) @[CircuitMath.scala 29:21] - node T_278 = cat(T_232, T_277) @[Cat.scala 20:58] - node T_279 = bits(T_226, 15, 8) @[CircuitMath.scala 26:17] - node T_280 = bits(T_226, 7, 0) @[CircuitMath.scala 27:17] - node T_282 = neq(T_279, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_283 = bits(T_279, 7, 4) @[CircuitMath.scala 26:17] - node T_284 = bits(T_279, 3, 0) @[CircuitMath.scala 27:17] - node T_286 = neq(T_283, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_287 = bits(T_283, 3, 3) @[CircuitMath.scala 23:12] - node T_289 = bits(T_283, 2, 2) @[CircuitMath.scala 23:12] - node T_291 = bits(T_283, 1, 1) @[CircuitMath.scala 21:8] - node T_292 = shl(T_291, 0) @[CircuitMath.scala 23:10] - node T_293 = mux(T_289, UInt<2>("h02"), T_292) @[CircuitMath.scala 23:10] - node T_294 = mux(T_287, UInt<2>("h03"), T_293) @[CircuitMath.scala 23:10] - node T_295 = bits(T_284, 3, 3) @[CircuitMath.scala 23:12] - node T_297 = bits(T_284, 2, 2) @[CircuitMath.scala 23:12] - node T_299 = bits(T_284, 1, 1) @[CircuitMath.scala 21:8] - node T_300 = shl(T_299, 0) @[CircuitMath.scala 23:10] - node T_301 = mux(T_297, UInt<2>("h02"), T_300) @[CircuitMath.scala 23:10] - node T_302 = mux(T_295, UInt<2>("h03"), T_301) @[CircuitMath.scala 23:10] - node T_303 = mux(T_286, T_294, T_302) @[CircuitMath.scala 29:21] - node T_304 = cat(T_286, T_303) @[Cat.scala 20:58] - node T_305 = bits(T_280, 7, 4) @[CircuitMath.scala 26:17] - node T_306 = bits(T_280, 3, 0) @[CircuitMath.scala 27:17] - node T_308 = neq(T_305, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_309 = bits(T_305, 3, 3) @[CircuitMath.scala 23:12] - node T_311 = bits(T_305, 2, 2) @[CircuitMath.scala 23:12] - node T_313 = bits(T_305, 1, 1) @[CircuitMath.scala 21:8] - node T_314 = shl(T_313, 0) @[CircuitMath.scala 23:10] - node T_315 = mux(T_311, UInt<2>("h02"), T_314) @[CircuitMath.scala 23:10] - node T_316 = mux(T_309, UInt<2>("h03"), T_315) @[CircuitMath.scala 23:10] - node T_317 = bits(T_306, 3, 3) @[CircuitMath.scala 23:12] - node T_319 = bits(T_306, 2, 2) @[CircuitMath.scala 23:12] - node T_321 = bits(T_306, 1, 1) @[CircuitMath.scala 21:8] - node T_322 = shl(T_321, 0) @[CircuitMath.scala 23:10] - node T_323 = mux(T_319, UInt<2>("h02"), T_322) @[CircuitMath.scala 23:10] - node T_324 = mux(T_317, UInt<2>("h03"), T_323) @[CircuitMath.scala 23:10] - node T_325 = mux(T_308, T_316, T_324) @[CircuitMath.scala 29:21] - node T_326 = cat(T_308, T_325) @[Cat.scala 20:58] - node T_327 = mux(T_282, T_304, T_326) @[CircuitMath.scala 29:21] - node T_328 = cat(T_282, T_327) @[Cat.scala 20:58] - node T_329 = mux(T_228, T_278, T_328) @[CircuitMath.scala 29:21] - node T_330 = cat(T_228, T_329) @[Cat.scala 20:58] - node T_331 = bits(T_222, 31, 16) @[CircuitMath.scala 26:17] - node T_332 = bits(T_222, 15, 0) @[CircuitMath.scala 27:17] - node T_334 = neq(T_331, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_335 = bits(T_331, 15, 8) @[CircuitMath.scala 26:17] - node T_336 = bits(T_331, 7, 0) @[CircuitMath.scala 27:17] - node T_338 = neq(T_335, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_339 = bits(T_335, 7, 4) @[CircuitMath.scala 26:17] - node T_340 = bits(T_335, 3, 0) @[CircuitMath.scala 27:17] - node T_342 = neq(T_339, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_343 = bits(T_339, 3, 3) @[CircuitMath.scala 23:12] - node T_345 = bits(T_339, 2, 2) @[CircuitMath.scala 23:12] - node T_347 = bits(T_339, 1, 1) @[CircuitMath.scala 21:8] - node T_348 = shl(T_347, 0) @[CircuitMath.scala 23:10] - node T_349 = mux(T_345, UInt<2>("h02"), T_348) @[CircuitMath.scala 23:10] - node T_350 = mux(T_343, UInt<2>("h03"), T_349) @[CircuitMath.scala 23:10] - node T_351 = bits(T_340, 3, 3) @[CircuitMath.scala 23:12] - node T_353 = bits(T_340, 2, 2) @[CircuitMath.scala 23:12] - node T_355 = bits(T_340, 1, 1) @[CircuitMath.scala 21:8] - node T_356 = shl(T_355, 0) @[CircuitMath.scala 23:10] - node T_357 = mux(T_353, UInt<2>("h02"), T_356) @[CircuitMath.scala 23:10] - node T_358 = mux(T_351, UInt<2>("h03"), T_357) @[CircuitMath.scala 23:10] - node T_359 = mux(T_342, T_350, T_358) @[CircuitMath.scala 29:21] - node T_360 = cat(T_342, T_359) @[Cat.scala 20:58] - node T_361 = bits(T_336, 7, 4) @[CircuitMath.scala 26:17] - node T_362 = bits(T_336, 3, 0) @[CircuitMath.scala 27:17] - node T_364 = neq(T_361, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_365 = bits(T_361, 3, 3) @[CircuitMath.scala 23:12] - node T_367 = bits(T_361, 2, 2) @[CircuitMath.scala 23:12] - node T_369 = bits(T_361, 1, 1) @[CircuitMath.scala 21:8] - node T_370 = shl(T_369, 0) @[CircuitMath.scala 23:10] - node T_371 = mux(T_367, UInt<2>("h02"), T_370) @[CircuitMath.scala 23:10] - node T_372 = mux(T_365, UInt<2>("h03"), T_371) @[CircuitMath.scala 23:10] - node T_373 = bits(T_362, 3, 3) @[CircuitMath.scala 23:12] - node T_375 = bits(T_362, 2, 2) @[CircuitMath.scala 23:12] - node T_377 = bits(T_362, 1, 1) @[CircuitMath.scala 21:8] - node T_378 = shl(T_377, 0) @[CircuitMath.scala 23:10] - node T_379 = mux(T_375, UInt<2>("h02"), T_378) @[CircuitMath.scala 23:10] - node T_380 = mux(T_373, UInt<2>("h03"), T_379) @[CircuitMath.scala 23:10] - node T_381 = mux(T_364, T_372, T_380) @[CircuitMath.scala 29:21] - node T_382 = cat(T_364, T_381) @[Cat.scala 20:58] - node T_383 = mux(T_338, T_360, T_382) @[CircuitMath.scala 29:21] - node T_384 = cat(T_338, T_383) @[Cat.scala 20:58] - node T_385 = bits(T_332, 15, 8) @[CircuitMath.scala 26:17] - node T_386 = bits(T_332, 7, 0) @[CircuitMath.scala 27:17] - node T_388 = neq(T_385, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_389 = bits(T_385, 7, 4) @[CircuitMath.scala 26:17] - node T_390 = bits(T_385, 3, 0) @[CircuitMath.scala 27:17] - node T_392 = neq(T_389, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_393 = bits(T_389, 3, 3) @[CircuitMath.scala 23:12] - node T_395 = bits(T_389, 2, 2) @[CircuitMath.scala 23:12] - node T_397 = bits(T_389, 1, 1) @[CircuitMath.scala 21:8] - node T_398 = shl(T_397, 0) @[CircuitMath.scala 23:10] - node T_399 = mux(T_395, UInt<2>("h02"), T_398) @[CircuitMath.scala 23:10] - node T_400 = mux(T_393, UInt<2>("h03"), T_399) @[CircuitMath.scala 23:10] - node T_401 = bits(T_390, 3, 3) @[CircuitMath.scala 23:12] - node T_403 = bits(T_390, 2, 2) @[CircuitMath.scala 23:12] - node T_405 = bits(T_390, 1, 1) @[CircuitMath.scala 21:8] - node T_406 = shl(T_405, 0) @[CircuitMath.scala 23:10] - node T_407 = mux(T_403, UInt<2>("h02"), T_406) @[CircuitMath.scala 23:10] - node T_408 = mux(T_401, UInt<2>("h03"), T_407) @[CircuitMath.scala 23:10] - node T_409 = mux(T_392, T_400, T_408) @[CircuitMath.scala 29:21] - node T_410 = cat(T_392, T_409) @[Cat.scala 20:58] - node T_411 = bits(T_386, 7, 4) @[CircuitMath.scala 26:17] - node T_412 = bits(T_386, 3, 0) @[CircuitMath.scala 27:17] - node T_414 = neq(T_411, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_415 = bits(T_411, 3, 3) @[CircuitMath.scala 23:12] - node T_417 = bits(T_411, 2, 2) @[CircuitMath.scala 23:12] - node T_419 = bits(T_411, 1, 1) @[CircuitMath.scala 21:8] - node T_420 = shl(T_419, 0) @[CircuitMath.scala 23:10] - node T_421 = mux(T_417, UInt<2>("h02"), T_420) @[CircuitMath.scala 23:10] - node T_422 = mux(T_415, UInt<2>("h03"), T_421) @[CircuitMath.scala 23:10] - node T_423 = bits(T_412, 3, 3) @[CircuitMath.scala 23:12] - node T_425 = bits(T_412, 2, 2) @[CircuitMath.scala 23:12] - node T_427 = bits(T_412, 1, 1) @[CircuitMath.scala 21:8] - node T_428 = shl(T_427, 0) @[CircuitMath.scala 23:10] - node T_429 = mux(T_425, UInt<2>("h02"), T_428) @[CircuitMath.scala 23:10] - node T_430 = mux(T_423, UInt<2>("h03"), T_429) @[CircuitMath.scala 23:10] - node T_431 = mux(T_414, T_422, T_430) @[CircuitMath.scala 29:21] - node T_432 = cat(T_414, T_431) @[Cat.scala 20:58] - node T_433 = mux(T_388, T_410, T_432) @[CircuitMath.scala 29:21] - node T_434 = cat(T_388, T_433) @[Cat.scala 20:58] - node T_435 = mux(T_334, T_384, T_434) @[CircuitMath.scala 29:21] - node T_436 = cat(T_334, T_435) @[Cat.scala 20:58] - node T_437 = mux(T_224, T_330, T_436) @[CircuitMath.scala 29:21] - node T_438 = cat(T_224, T_437) @[Cat.scala 20:58] - node T_439 = bits(remainder, 63, 0) @[multiplier.scala 125:37] - node T_440 = bits(T_439, 63, 32) @[CircuitMath.scala 26:17] - node T_441 = bits(T_439, 31, 0) @[CircuitMath.scala 27:17] - node T_443 = neq(T_440, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_444 = bits(T_440, 31, 16) @[CircuitMath.scala 26:17] - node T_445 = bits(T_440, 15, 0) @[CircuitMath.scala 27:17] - node T_447 = neq(T_444, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_448 = bits(T_444, 15, 8) @[CircuitMath.scala 26:17] - node T_449 = bits(T_444, 7, 0) @[CircuitMath.scala 27:17] - node T_451 = neq(T_448, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_452 = bits(T_448, 7, 4) @[CircuitMath.scala 26:17] - node T_453 = bits(T_448, 3, 0) @[CircuitMath.scala 27:17] - node T_455 = neq(T_452, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_456 = bits(T_452, 3, 3) @[CircuitMath.scala 23:12] - node T_458 = bits(T_452, 2, 2) @[CircuitMath.scala 23:12] - node T_460 = bits(T_452, 1, 1) @[CircuitMath.scala 21:8] - node T_461 = shl(T_460, 0) @[CircuitMath.scala 23:10] - node T_462 = mux(T_458, UInt<2>("h02"), T_461) @[CircuitMath.scala 23:10] - node T_463 = mux(T_456, UInt<2>("h03"), T_462) @[CircuitMath.scala 23:10] - node T_464 = bits(T_453, 3, 3) @[CircuitMath.scala 23:12] - node T_466 = bits(T_453, 2, 2) @[CircuitMath.scala 23:12] - node T_468 = bits(T_453, 1, 1) @[CircuitMath.scala 21:8] - node T_469 = shl(T_468, 0) @[CircuitMath.scala 23:10] - node T_470 = mux(T_466, UInt<2>("h02"), T_469) @[CircuitMath.scala 23:10] - node T_471 = mux(T_464, UInt<2>("h03"), T_470) @[CircuitMath.scala 23:10] - node T_472 = mux(T_455, T_463, T_471) @[CircuitMath.scala 29:21] - node T_473 = cat(T_455, T_472) @[Cat.scala 20:58] - node T_474 = bits(T_449, 7, 4) @[CircuitMath.scala 26:17] - node T_475 = bits(T_449, 3, 0) @[CircuitMath.scala 27:17] - node T_477 = neq(T_474, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_478 = bits(T_474, 3, 3) @[CircuitMath.scala 23:12] - node T_480 = bits(T_474, 2, 2) @[CircuitMath.scala 23:12] - node T_482 = bits(T_474, 1, 1) @[CircuitMath.scala 21:8] - node T_483 = shl(T_482, 0) @[CircuitMath.scala 23:10] - node T_484 = mux(T_480, UInt<2>("h02"), T_483) @[CircuitMath.scala 23:10] - node T_485 = mux(T_478, UInt<2>("h03"), T_484) @[CircuitMath.scala 23:10] - node T_486 = bits(T_475, 3, 3) @[CircuitMath.scala 23:12] - node T_488 = bits(T_475, 2, 2) @[CircuitMath.scala 23:12] - node T_490 = bits(T_475, 1, 1) @[CircuitMath.scala 21:8] - node T_491 = shl(T_490, 0) @[CircuitMath.scala 23:10] - node T_492 = mux(T_488, UInt<2>("h02"), T_491) @[CircuitMath.scala 23:10] - node T_493 = mux(T_486, UInt<2>("h03"), T_492) @[CircuitMath.scala 23:10] - node T_494 = mux(T_477, T_485, T_493) @[CircuitMath.scala 29:21] - node T_495 = cat(T_477, T_494) @[Cat.scala 20:58] - node T_496 = mux(T_451, T_473, T_495) @[CircuitMath.scala 29:21] - node T_497 = cat(T_451, T_496) @[Cat.scala 20:58] - node T_498 = bits(T_445, 15, 8) @[CircuitMath.scala 26:17] - node T_499 = bits(T_445, 7, 0) @[CircuitMath.scala 27:17] - node T_501 = neq(T_498, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_502 = bits(T_498, 7, 4) @[CircuitMath.scala 26:17] - node T_503 = bits(T_498, 3, 0) @[CircuitMath.scala 27:17] - node T_505 = neq(T_502, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_506 = bits(T_502, 3, 3) @[CircuitMath.scala 23:12] - node T_508 = bits(T_502, 2, 2) @[CircuitMath.scala 23:12] - node T_510 = bits(T_502, 1, 1) @[CircuitMath.scala 21:8] - node T_511 = shl(T_510, 0) @[CircuitMath.scala 23:10] - node T_512 = mux(T_508, UInt<2>("h02"), T_511) @[CircuitMath.scala 23:10] - node T_513 = mux(T_506, UInt<2>("h03"), T_512) @[CircuitMath.scala 23:10] - node T_514 = bits(T_503, 3, 3) @[CircuitMath.scala 23:12] - node T_516 = bits(T_503, 2, 2) @[CircuitMath.scala 23:12] - node T_518 = bits(T_503, 1, 1) @[CircuitMath.scala 21:8] - node T_519 = shl(T_518, 0) @[CircuitMath.scala 23:10] - node T_520 = mux(T_516, UInt<2>("h02"), T_519) @[CircuitMath.scala 23:10] - node T_521 = mux(T_514, UInt<2>("h03"), T_520) @[CircuitMath.scala 23:10] - node T_522 = mux(T_505, T_513, T_521) @[CircuitMath.scala 29:21] - node T_523 = cat(T_505, T_522) @[Cat.scala 20:58] - node T_524 = bits(T_499, 7, 4) @[CircuitMath.scala 26:17] - node T_525 = bits(T_499, 3, 0) @[CircuitMath.scala 27:17] - node T_527 = neq(T_524, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_528 = bits(T_524, 3, 3) @[CircuitMath.scala 23:12] - node T_530 = bits(T_524, 2, 2) @[CircuitMath.scala 23:12] - node T_532 = bits(T_524, 1, 1) @[CircuitMath.scala 21:8] - node T_533 = shl(T_532, 0) @[CircuitMath.scala 23:10] - node T_534 = mux(T_530, UInt<2>("h02"), T_533) @[CircuitMath.scala 23:10] - node T_535 = mux(T_528, UInt<2>("h03"), T_534) @[CircuitMath.scala 23:10] - node T_536 = bits(T_525, 3, 3) @[CircuitMath.scala 23:12] - node T_538 = bits(T_525, 2, 2) @[CircuitMath.scala 23:12] - node T_540 = bits(T_525, 1, 1) @[CircuitMath.scala 21:8] - node T_541 = shl(T_540, 0) @[CircuitMath.scala 23:10] - node T_542 = mux(T_538, UInt<2>("h02"), T_541) @[CircuitMath.scala 23:10] - node T_543 = mux(T_536, UInt<2>("h03"), T_542) @[CircuitMath.scala 23:10] - node T_544 = mux(T_527, T_535, T_543) @[CircuitMath.scala 29:21] - node T_545 = cat(T_527, T_544) @[Cat.scala 20:58] - node T_546 = mux(T_501, T_523, T_545) @[CircuitMath.scala 29:21] - node T_547 = cat(T_501, T_546) @[Cat.scala 20:58] - node T_548 = mux(T_447, T_497, T_547) @[CircuitMath.scala 29:21] - node T_549 = cat(T_447, T_548) @[Cat.scala 20:58] - node T_550 = bits(T_441, 31, 16) @[CircuitMath.scala 26:17] - node T_551 = bits(T_441, 15, 0) @[CircuitMath.scala 27:17] - node T_553 = neq(T_550, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_554 = bits(T_550, 15, 8) @[CircuitMath.scala 26:17] - node T_555 = bits(T_550, 7, 0) @[CircuitMath.scala 27:17] - node T_557 = neq(T_554, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_558 = bits(T_554, 7, 4) @[CircuitMath.scala 26:17] - node T_559 = bits(T_554, 3, 0) @[CircuitMath.scala 27:17] - node T_561 = neq(T_558, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_562 = bits(T_558, 3, 3) @[CircuitMath.scala 23:12] - node T_564 = bits(T_558, 2, 2) @[CircuitMath.scala 23:12] - node T_566 = bits(T_558, 1, 1) @[CircuitMath.scala 21:8] - node T_567 = shl(T_566, 0) @[CircuitMath.scala 23:10] - node T_568 = mux(T_564, UInt<2>("h02"), T_567) @[CircuitMath.scala 23:10] - node T_569 = mux(T_562, UInt<2>("h03"), T_568) @[CircuitMath.scala 23:10] - node T_570 = bits(T_559, 3, 3) @[CircuitMath.scala 23:12] - node T_572 = bits(T_559, 2, 2) @[CircuitMath.scala 23:12] - node T_574 = bits(T_559, 1, 1) @[CircuitMath.scala 21:8] - node T_575 = shl(T_574, 0) @[CircuitMath.scala 23:10] - node T_576 = mux(T_572, UInt<2>("h02"), T_575) @[CircuitMath.scala 23:10] - node T_577 = mux(T_570, UInt<2>("h03"), T_576) @[CircuitMath.scala 23:10] - node T_578 = mux(T_561, T_569, T_577) @[CircuitMath.scala 29:21] - node T_579 = cat(T_561, T_578) @[Cat.scala 20:58] - node T_580 = bits(T_555, 7, 4) @[CircuitMath.scala 26:17] - node T_581 = bits(T_555, 3, 0) @[CircuitMath.scala 27:17] - node T_583 = neq(T_580, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_584 = bits(T_580, 3, 3) @[CircuitMath.scala 23:12] - node T_586 = bits(T_580, 2, 2) @[CircuitMath.scala 23:12] - node T_588 = bits(T_580, 1, 1) @[CircuitMath.scala 21:8] - node T_589 = shl(T_588, 0) @[CircuitMath.scala 23:10] - node T_590 = mux(T_586, UInt<2>("h02"), T_589) @[CircuitMath.scala 23:10] - node T_591 = mux(T_584, UInt<2>("h03"), T_590) @[CircuitMath.scala 23:10] - node T_592 = bits(T_581, 3, 3) @[CircuitMath.scala 23:12] - node T_594 = bits(T_581, 2, 2) @[CircuitMath.scala 23:12] - node T_596 = bits(T_581, 1, 1) @[CircuitMath.scala 21:8] - node T_597 = shl(T_596, 0) @[CircuitMath.scala 23:10] - node T_598 = mux(T_594, UInt<2>("h02"), T_597) @[CircuitMath.scala 23:10] - node T_599 = mux(T_592, UInt<2>("h03"), T_598) @[CircuitMath.scala 23:10] - node T_600 = mux(T_583, T_591, T_599) @[CircuitMath.scala 29:21] - node T_601 = cat(T_583, T_600) @[Cat.scala 20:58] - node T_602 = mux(T_557, T_579, T_601) @[CircuitMath.scala 29:21] - node T_603 = cat(T_557, T_602) @[Cat.scala 20:58] - node T_604 = bits(T_551, 15, 8) @[CircuitMath.scala 26:17] - node T_605 = bits(T_551, 7, 0) @[CircuitMath.scala 27:17] - node T_607 = neq(T_604, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_608 = bits(T_604, 7, 4) @[CircuitMath.scala 26:17] - node T_609 = bits(T_604, 3, 0) @[CircuitMath.scala 27:17] - node T_611 = neq(T_608, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_612 = bits(T_608, 3, 3) @[CircuitMath.scala 23:12] - node T_614 = bits(T_608, 2, 2) @[CircuitMath.scala 23:12] - node T_616 = bits(T_608, 1, 1) @[CircuitMath.scala 21:8] - node T_617 = shl(T_616, 0) @[CircuitMath.scala 23:10] - node T_618 = mux(T_614, UInt<2>("h02"), T_617) @[CircuitMath.scala 23:10] - node T_619 = mux(T_612, UInt<2>("h03"), T_618) @[CircuitMath.scala 23:10] - node T_620 = bits(T_609, 3, 3) @[CircuitMath.scala 23:12] - node T_622 = bits(T_609, 2, 2) @[CircuitMath.scala 23:12] - node T_624 = bits(T_609, 1, 1) @[CircuitMath.scala 21:8] - node T_625 = shl(T_624, 0) @[CircuitMath.scala 23:10] - node T_626 = mux(T_622, UInt<2>("h02"), T_625) @[CircuitMath.scala 23:10] - node T_627 = mux(T_620, UInt<2>("h03"), T_626) @[CircuitMath.scala 23:10] - node T_628 = mux(T_611, T_619, T_627) @[CircuitMath.scala 29:21] - node T_629 = cat(T_611, T_628) @[Cat.scala 20:58] - node T_630 = bits(T_605, 7, 4) @[CircuitMath.scala 26:17] - node T_631 = bits(T_605, 3, 0) @[CircuitMath.scala 27:17] - node T_633 = neq(T_630, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_634 = bits(T_630, 3, 3) @[CircuitMath.scala 23:12] - node T_636 = bits(T_630, 2, 2) @[CircuitMath.scala 23:12] - node T_638 = bits(T_630, 1, 1) @[CircuitMath.scala 21:8] - node T_639 = shl(T_638, 0) @[CircuitMath.scala 23:10] - node T_640 = mux(T_636, UInt<2>("h02"), T_639) @[CircuitMath.scala 23:10] - node T_641 = mux(T_634, UInt<2>("h03"), T_640) @[CircuitMath.scala 23:10] - node T_642 = bits(T_631, 3, 3) @[CircuitMath.scala 23:12] - node T_644 = bits(T_631, 2, 2) @[CircuitMath.scala 23:12] - node T_646 = bits(T_631, 1, 1) @[CircuitMath.scala 21:8] - node T_647 = shl(T_646, 0) @[CircuitMath.scala 23:10] - node T_648 = mux(T_644, UInt<2>("h02"), T_647) @[CircuitMath.scala 23:10] - node T_649 = mux(T_642, UInt<2>("h03"), T_648) @[CircuitMath.scala 23:10] - node T_650 = mux(T_633, T_641, T_649) @[CircuitMath.scala 29:21] - node T_651 = cat(T_633, T_650) @[Cat.scala 20:58] - node T_652 = mux(T_607, T_629, T_651) @[CircuitMath.scala 29:21] - node T_653 = cat(T_607, T_652) @[Cat.scala 20:58] - node T_654 = mux(T_553, T_603, T_653) @[CircuitMath.scala 29:21] - node T_655 = cat(T_553, T_654) @[Cat.scala 20:58] - node T_656 = mux(T_443, T_549, T_655) @[CircuitMath.scala 29:21] - node T_657 = cat(T_443, T_656) @[Cat.scala 20:58] - node T_659 = add(UInt<6>("h03f"), T_438) @[multiplier.scala 126:29] - node T_660 = tail(T_659, 1) @[multiplier.scala 126:29] - node T_661 = sub(T_660, T_657) @[multiplier.scala 126:42] - node T_662 = tail(T_661, 1) @[multiplier.scala 126:42] - node T_663 = gt(T_438, T_657) @[multiplier.scala 127:31] - node T_665 = eq(count, UInt<1>("h00")) @[multiplier.scala 128:22] - node T_666 = and(T_665, less) @[multiplier.scala 128:28] - node T_668 = gt(T_662, UInt<1>("h00")) @[multiplier.scala 128:65] - node T_669 = or(T_668, T_663) @[multiplier.scala 128:69] - node T_670 = and(T_666, T_669) @[multiplier.scala 128:53] - node T_672 = and(UInt<1>("h01"), T_670) @[multiplier.scala 129:33] - when T_672 : @[multiplier.scala 129:42] - node T_674 = bits(T_662, 5, 0) @[multiplier.scala 130:51] - node T_675 = mux(T_663, UInt<6>("h03f"), T_674) @[multiplier.scala 130:22] - node T_676 = bits(remainder, 63, 0) @[multiplier.scala 131:29] - node T_677 = dshl(T_676, T_675) @[multiplier.scala 131:37] - remainder <= T_677 @[multiplier.scala 131:17] - count <= T_675 @[multiplier.scala 132:13] - skip @[multiplier.scala 129:42] - node T_679 = eq(count, UInt<1>("h00")) @[multiplier.scala 134:17] - node T_681 = eq(less, UInt<1>("h00")) @[multiplier.scala 134:26] - node T_682 = and(T_679, T_681) @[multiplier.scala 134:23] - node T_684 = eq(isHi, UInt<1>("h00")) @[multiplier.scala 134:48] - node T_685 = and(T_682, T_684) @[multiplier.scala 134:45] - when T_685 : @[multiplier.scala 134:55] - neg_out <= UInt<1>("h00") @[multiplier.scala 134:65] - skip @[multiplier.scala 134:55] - skip @[multiplier.scala 116:37] - node T_687 = and(io.resp.ready, io.resp.valid) @[Decoupled.scala 21:42] - node T_688 = or(T_687, io.kill) @[multiplier.scala 136:24] - when T_688 : @[multiplier.scala 136:36] - state <= UInt<3>("h00") @[multiplier.scala 137:11] - skip @[multiplier.scala 136:36] - node T_689 = and(io.req.ready, io.req.valid) @[Decoupled.scala 21:42] - when T_689 : @[multiplier.scala 139:24] - node T_691 = eq(cmdMul, UInt<1>("h00")) @[multiplier.scala 140:42] - node T_692 = and(rhs_sign, T_691) @[multiplier.scala 140:39] - node T_693 = or(lhs_sign, T_692) @[multiplier.scala 140:27] - node T_694 = mux(T_693, UInt<3>("h01"), UInt<3>("h02")) @[multiplier.scala 140:17] - state <= T_694 @[multiplier.scala 140:11] - isMul <= cmdMul @[multiplier.scala 141:11] - isHi <= cmdHi @[multiplier.scala 142:10] - count <= UInt<1>("h00") @[multiplier.scala 143:11] - node T_697 = eq(cmdMul, UInt<1>("h00")) @[multiplier.scala 144:16] - node T_698 = neq(lhs_sign, rhs_sign) @[multiplier.scala 144:57] - node T_699 = mux(cmdHi, lhs_sign, T_698) @[multiplier.scala 144:30] - node T_700 = and(T_697, T_699) @[multiplier.scala 144:24] - neg_out <= T_700 @[multiplier.scala 144:13] - node T_701 = cat(rhs_sign, rhs_in) @[Cat.scala 20:58] - divisor <= T_701 @[multiplier.scala 145:13] - remainder <= lhs_in @[multiplier.scala 146:15] - req <- io.req.bits @[multiplier.scala 147:9] - skip @[multiplier.scala 139:24] - io.resp.bits <- req @[multiplier.scala 150:16] - node T_703 = eq(req.dw, UInt<1>("h00")) @[multiplier.scala 64:62] - node T_704 = and(UInt<1>("h01"), T_703) @[multiplier.scala 64:52] - node T_705 = bits(remainder, 31, 31) @[multiplier.scala 151:67] - node T_706 = bits(T_705, 0, 0) @[Bitwise.scala 33:15] - node T_709 = mux(T_706, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_710 = bits(remainder, 31, 0) @[multiplier.scala 151:86] - node T_711 = cat(T_709, T_710) @[Cat.scala 20:58] - node T_712 = bits(remainder, 63, 0) @[multiplier.scala 151:107] - node T_713 = mux(T_704, T_711, T_712) @[multiplier.scala 151:27] - io.resp.bits.data <= T_713 @[multiplier.scala 151:21] - node T_714 = eq(state, UInt<3>("h05")) @[multiplier.scala 152:26] - io.resp.valid <= T_714 @[multiplier.scala 152:17] - node T_715 = eq(state, UInt<3>("h00")) @[multiplier.scala 153:25] - io.req.ready <= T_715 @[multiplier.scala 153:16] - - module Rocket : + reg state : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg req : { fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk with : + reset => (UInt<1>("h0"), req) + reg count : UInt<7>, clk with : + reset => (UInt<1>("h0"), count) + reg neg_out : UInt<1>, clk with : + reset => (UInt<1>("h0"), neg_out) + reg isMul : UInt<1>, clk with : + reset => (UInt<1>("h0"), isMul) + reg isHi : UInt<1>, clk with : + reset => (UInt<1>("h0"), isHi) + reg divisor : UInt<65>, clk with : + reset => (UInt<1>("h0"), divisor) + reg remainder : UInt<130>, clk with : + reset => (UInt<1>("h0"), remainder) + node T_62 = and(io.req.bits.fn, UInt<4>("h4")) + node T_64 = eq(T_62, UInt<4>("h0")) + node T_66 = and(io.req.bits.fn, UInt<4>("h8")) + node T_68 = eq(T_66, UInt<4>("h8")) + node T_70 = or(UInt<1>("h0"), T_64) + node T_71 = or(T_70, T_68) + node T_73 = and(io.req.bits.fn, UInt<4>("h5")) + node T_75 = eq(T_73, UInt<4>("h1")) + node T_77 = and(io.req.bits.fn, UInt<4>("h2")) + node T_79 = eq(T_77, UInt<4>("h2")) + node T_81 = or(UInt<1>("h0"), T_75) + node T_82 = or(T_81, T_79) + node T_83 = or(T_82, T_68) + node T_85 = and(io.req.bits.fn, UInt<4>("h9")) + node T_87 = eq(T_85, UInt<4>("h0")) + node T_89 = and(io.req.bits.fn, UInt<4>("h3")) + node T_91 = eq(T_89, UInt<4>("h0")) + node T_93 = or(UInt<1>("h0"), T_87) + node T_94 = or(T_93, T_64) + node T_95 = or(T_94, T_91) + node T_97 = or(UInt<1>("h0"), T_87) + node T_98 = or(T_97, T_64) + node cmdMul = bits(T_71, 0, 0) + node cmdHi = bits(T_83, 0, 0) + node lhsSigned = bits(T_95, 0, 0) + node rhsSigned = bits(T_98, 0, 0) + node T_100 = eq(io.req.bits.dw, UInt<1>("h0")) + node T_101 = and(UInt<1>("h1"), T_100) + node T_102 = bits(io.req.bits.in1, 31, 31) + node T_103 = bits(io.req.bits.in1, 63, 63) + node T_104 = mux(T_101, T_102, T_103) + node lhs_sign = and(lhsSigned, T_104) + node T_105 = bits(lhs_sign, 0, 0) + node T_108 = mux(T_105, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_109 = bits(io.req.bits.in1, 63, 32) + node T_110 = mux(T_101, T_108, T_109) + node T_111 = bits(io.req.bits.in1, 31, 0) + node lhs_in = cat(T_110, T_111) + node T_113 = eq(io.req.bits.dw, UInt<1>("h0")) + node T_114 = and(UInt<1>("h1"), T_113) + node T_115 = bits(io.req.bits.in2, 31, 31) + node T_116 = bits(io.req.bits.in2, 63, 63) + node T_117 = mux(T_114, T_115, T_116) + node rhs_sign = and(rhsSigned, T_117) + node T_118 = bits(rhs_sign, 0, 0) + node T_121 = mux(T_118, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_122 = bits(io.req.bits.in2, 63, 32) + node T_123 = mux(T_114, T_121, T_122) + node T_124 = bits(io.req.bits.in2, 31, 0) + node rhs_in = cat(T_123, T_124) + node T_125 = bits(remainder, 128, 64) + node T_126 = bits(divisor, 64, 0) + node T_127 = sub(T_125, T_126) + node subtractor = tail(T_127, 1) + node less = bits(subtractor, 64, 64) + node T_128 = bits(remainder, 63, 0) + node T_130 = sub(UInt<1>("h0"), T_128) + node negated_remainder = tail(T_130, 1) + node T_131 = eq(state, UInt<3>("h1")) + when T_131 : + node T_132 = bits(remainder, 63, 63) + node T_133 = or(T_132, isMul) + when T_133 : + remainder <= negated_remainder + node T_134 = bits(divisor, 63, 63) + node T_135 = or(T_134, isMul) + when T_135 : + divisor <= subtractor + state <= UInt<3>("h2") + node T_136 = eq(state, UInt<3>("h4")) + when T_136 : + remainder <= negated_remainder + state <= UInt<3>("h5") + node T_137 = eq(state, UInt<3>("h3")) + when T_137 : + node T_138 = bits(remainder, 128, 65) + remainder <= T_138 + node T_139 = mux(neg_out, UInt<3>("h4"), UInt<3>("h5")) + state <= T_139 + node T_140 = eq(state, UInt<3>("h2")) + node T_141 = and(T_140, isMul) + when T_141 : + node T_142 = bits(remainder, 129, 65) + node T_143 = bits(remainder, 63, 0) + node T_144 = cat(T_142, T_143) + node T_145 = bits(T_144, 63, 0) + node T_146 = bits(T_144, 128, 64) + node T_147 = asSInt(T_146) + node T_148 = asSInt(divisor) + node T_149 = bits(T_145, 7, 0) + node T_150 = mul(T_148, asSInt(T_149)) + node T_151 = add(T_150, T_147) + node T_152 = tail(T_151, 1) + node T_153 = asSInt(T_152) + node T_154 = bits(T_145, 63, 8) + node T_155 = asUInt(T_153) + node T_156 = cat(T_155, T_154) + node T_159 = mul(count, UInt<4>("h8")) + node T_160 = bits(T_159, 5, 0) + node T_161 = dshr(asSInt(UInt<65>("h10000000000000000")), T_160) + node T_162 = bits(T_161, 63, 0) + node T_165 = neq(count, UInt<3>("h7")) + node T_166 = and(UInt<1>("h1"), T_165) + node T_168 = neq(count, UInt<1>("h0")) + node T_169 = and(T_166, T_168) + node T_171 = eq(isHi, UInt<1>("h0")) + node T_172 = and(T_169, T_171) + node T_173 = not(T_162) + node T_174 = and(T_145, T_173) + node T_176 = eq(T_174, UInt<1>("h0")) + node T_177 = and(T_172, T_176) + node T_180 = mul(count, UInt<4>("h8")) + node T_181 = sub(UInt<7>("h40"), T_180) + node T_182 = tail(T_181, 1) + node T_183 = bits(T_182, 5, 0) + node T_184 = dshr(T_144, T_183) + node T_185 = bits(T_156, 128, 64) + node T_186 = mux(T_177, T_184, T_156) + node T_187 = bits(T_186, 63, 0) + node T_188 = cat(T_185, T_187) + node T_189 = shr(T_188, 64) + node T_191 = bits(T_188, 63, 0) + node T_192 = cat(T_189, UInt<1>("h0")) + node T_193 = cat(T_192, T_191) + remainder <= T_193 + node T_195 = add(count, UInt<1>("h1")) + node T_196 = tail(T_195, 1) + count <= T_196 + node T_198 = eq(count, UInt<3>("h7")) + node T_199 = or(T_177, T_198) + when T_199 : + node T_200 = mux(isHi, UInt<3>("h3"), UInt<3>("h5")) + state <= T_200 + node T_201 = eq(state, UInt<3>("h2")) + node T_203 = eq(isMul, UInt<1>("h0")) + node T_204 = and(T_201, T_203) + when T_204 : + node T_206 = eq(count, UInt<7>("h40")) + when T_206 : + node T_207 = mux(neg_out, UInt<3>("h4"), UInt<3>("h5")) + node T_208 = mux(isHi, UInt<3>("h3"), T_207) + state <= T_208 + node T_210 = add(count, UInt<1>("h1")) + node T_211 = tail(T_210, 1) + count <= T_211 + node T_212 = bits(remainder, 127, 64) + node T_213 = bits(subtractor, 63, 0) + node T_214 = mux(less, T_212, T_213) + node T_215 = bits(remainder, 63, 0) + node T_217 = eq(less, UInt<1>("h0")) + node T_218 = cat(T_214, T_215) + node T_219 = cat(T_218, T_217) + remainder <= T_219 + node T_220 = bits(divisor, 63, 0) + node T_221 = bits(T_220, 63, 32) + node T_222 = bits(T_220, 31, 0) + node T_224 = neq(T_221, UInt<1>("h0")) + node T_225 = bits(T_221, 31, 16) + node T_226 = bits(T_221, 15, 0) + node T_228 = neq(T_225, UInt<1>("h0")) + node T_229 = bits(T_225, 15, 8) + node T_230 = bits(T_225, 7, 0) + node T_232 = neq(T_229, UInt<1>("h0")) + node T_233 = bits(T_229, 7, 4) + node T_234 = bits(T_229, 3, 0) + node T_236 = neq(T_233, UInt<1>("h0")) + node T_237 = bits(T_233, 3, 3) + node T_239 = bits(T_233, 2, 2) + node T_241 = bits(T_233, 1, 1) + node T_242 = shl(T_241, 0) + node T_243 = mux(T_239, UInt<2>("h2"), T_242) + node T_244 = mux(T_237, UInt<2>("h3"), T_243) + node T_245 = bits(T_234, 3, 3) + node T_247 = bits(T_234, 2, 2) + node T_249 = bits(T_234, 1, 1) + node T_250 = shl(T_249, 0) + node T_251 = mux(T_247, UInt<2>("h2"), T_250) + node T_252 = mux(T_245, UInt<2>("h3"), T_251) + node T_253 = mux(T_236, T_244, T_252) + node T_254 = cat(T_236, T_253) + node T_255 = bits(T_230, 7, 4) + node T_256 = bits(T_230, 3, 0) + node T_258 = neq(T_255, UInt<1>("h0")) + node T_259 = bits(T_255, 3, 3) + node T_261 = bits(T_255, 2, 2) + node T_263 = bits(T_255, 1, 1) + node T_264 = shl(T_263, 0) + node T_265 = mux(T_261, UInt<2>("h2"), T_264) + node T_266 = mux(T_259, UInt<2>("h3"), T_265) + node T_267 = bits(T_256, 3, 3) + node T_269 = bits(T_256, 2, 2) + node T_271 = bits(T_256, 1, 1) + node T_272 = shl(T_271, 0) + node T_273 = mux(T_269, UInt<2>("h2"), T_272) + node T_274 = mux(T_267, UInt<2>("h3"), T_273) + node T_275 = mux(T_258, T_266, T_274) + node T_276 = cat(T_258, T_275) + node T_277 = mux(T_232, T_254, T_276) + node T_278 = cat(T_232, T_277) + node T_279 = bits(T_226, 15, 8) + node T_280 = bits(T_226, 7, 0) + node T_282 = neq(T_279, UInt<1>("h0")) + node T_283 = bits(T_279, 7, 4) + node T_284 = bits(T_279, 3, 0) + node T_286 = neq(T_283, UInt<1>("h0")) + node T_287 = bits(T_283, 3, 3) + node T_289 = bits(T_283, 2, 2) + node T_291 = bits(T_283, 1, 1) + node T_292 = shl(T_291, 0) + node T_293 = mux(T_289, UInt<2>("h2"), T_292) + node T_294 = mux(T_287, UInt<2>("h3"), T_293) + node T_295 = bits(T_284, 3, 3) + node T_297 = bits(T_284, 2, 2) + node T_299 = bits(T_284, 1, 1) + node T_300 = shl(T_299, 0) + node T_301 = mux(T_297, UInt<2>("h2"), T_300) + node T_302 = mux(T_295, UInt<2>("h3"), T_301) + node T_303 = mux(T_286, T_294, T_302) + node T_304 = cat(T_286, T_303) + node T_305 = bits(T_280, 7, 4) + node T_306 = bits(T_280, 3, 0) + node T_308 = neq(T_305, UInt<1>("h0")) + node T_309 = bits(T_305, 3, 3) + node T_311 = bits(T_305, 2, 2) + node T_313 = bits(T_305, 1, 1) + node T_314 = shl(T_313, 0) + node T_315 = mux(T_311, UInt<2>("h2"), T_314) + node T_316 = mux(T_309, UInt<2>("h3"), T_315) + node T_317 = bits(T_306, 3, 3) + node T_319 = bits(T_306, 2, 2) + node T_321 = bits(T_306, 1, 1) + node T_322 = shl(T_321, 0) + node T_323 = mux(T_319, UInt<2>("h2"), T_322) + node T_324 = mux(T_317, UInt<2>("h3"), T_323) + node T_325 = mux(T_308, T_316, T_324) + node T_326 = cat(T_308, T_325) + node T_327 = mux(T_282, T_304, T_326) + node T_328 = cat(T_282, T_327) + node T_329 = mux(T_228, T_278, T_328) + node T_330 = cat(T_228, T_329) + node T_331 = bits(T_222, 31, 16) + node T_332 = bits(T_222, 15, 0) + node T_334 = neq(T_331, UInt<1>("h0")) + node T_335 = bits(T_331, 15, 8) + node T_336 = bits(T_331, 7, 0) + node T_338 = neq(T_335, UInt<1>("h0")) + node T_339 = bits(T_335, 7, 4) + node T_340 = bits(T_335, 3, 0) + node T_342 = neq(T_339, UInt<1>("h0")) + node T_343 = bits(T_339, 3, 3) + node T_345 = bits(T_339, 2, 2) + node T_347 = bits(T_339, 1, 1) + node T_348 = shl(T_347, 0) + node T_349 = mux(T_345, UInt<2>("h2"), T_348) + node T_350 = mux(T_343, UInt<2>("h3"), T_349) + node T_351 = bits(T_340, 3, 3) + node T_353 = bits(T_340, 2, 2) + node T_355 = bits(T_340, 1, 1) + node T_356 = shl(T_355, 0) + node T_357 = mux(T_353, UInt<2>("h2"), T_356) + node T_358 = mux(T_351, UInt<2>("h3"), T_357) + node T_359 = mux(T_342, T_350, T_358) + node T_360 = cat(T_342, T_359) + node T_361 = bits(T_336, 7, 4) + node T_362 = bits(T_336, 3, 0) + node T_364 = neq(T_361, UInt<1>("h0")) + node T_365 = bits(T_361, 3, 3) + node T_367 = bits(T_361, 2, 2) + node T_369 = bits(T_361, 1, 1) + node T_370 = shl(T_369, 0) + node T_371 = mux(T_367, UInt<2>("h2"), T_370) + node T_372 = mux(T_365, UInt<2>("h3"), T_371) + node T_373 = bits(T_362, 3, 3) + node T_375 = bits(T_362, 2, 2) + node T_377 = bits(T_362, 1, 1) + node T_378 = shl(T_377, 0) + node T_379 = mux(T_375, UInt<2>("h2"), T_378) + node T_380 = mux(T_373, UInt<2>("h3"), T_379) + node T_381 = mux(T_364, T_372, T_380) + node T_382 = cat(T_364, T_381) + node T_383 = mux(T_338, T_360, T_382) + node T_384 = cat(T_338, T_383) + node T_385 = bits(T_332, 15, 8) + node T_386 = bits(T_332, 7, 0) + node T_388 = neq(T_385, UInt<1>("h0")) + node T_389 = bits(T_385, 7, 4) + node T_390 = bits(T_385, 3, 0) + node T_392 = neq(T_389, UInt<1>("h0")) + node T_393 = bits(T_389, 3, 3) + node T_395 = bits(T_389, 2, 2) + node T_397 = bits(T_389, 1, 1) + node T_398 = shl(T_397, 0) + node T_399 = mux(T_395, UInt<2>("h2"), T_398) + node T_400 = mux(T_393, UInt<2>("h3"), T_399) + node T_401 = bits(T_390, 3, 3) + node T_403 = bits(T_390, 2, 2) + node T_405 = bits(T_390, 1, 1) + node T_406 = shl(T_405, 0) + node T_407 = mux(T_403, UInt<2>("h2"), T_406) + node T_408 = mux(T_401, UInt<2>("h3"), T_407) + node T_409 = mux(T_392, T_400, T_408) + node T_410 = cat(T_392, T_409) + node T_411 = bits(T_386, 7, 4) + node T_412 = bits(T_386, 3, 0) + node T_414 = neq(T_411, UInt<1>("h0")) + node T_415 = bits(T_411, 3, 3) + node T_417 = bits(T_411, 2, 2) + node T_419 = bits(T_411, 1, 1) + node T_420 = shl(T_419, 0) + node T_421 = mux(T_417, UInt<2>("h2"), T_420) + node T_422 = mux(T_415, UInt<2>("h3"), T_421) + node T_423 = bits(T_412, 3, 3) + node T_425 = bits(T_412, 2, 2) + node T_427 = bits(T_412, 1, 1) + node T_428 = shl(T_427, 0) + node T_429 = mux(T_425, UInt<2>("h2"), T_428) + node T_430 = mux(T_423, UInt<2>("h3"), T_429) + node T_431 = mux(T_414, T_422, T_430) + node T_432 = cat(T_414, T_431) + node T_433 = mux(T_388, T_410, T_432) + node T_434 = cat(T_388, T_433) + node T_435 = mux(T_334, T_384, T_434) + node T_436 = cat(T_334, T_435) + node T_437 = mux(T_224, T_330, T_436) + node T_438 = cat(T_224, T_437) + node T_439 = bits(remainder, 63, 0) + node T_440 = bits(T_439, 63, 32) + node T_441 = bits(T_439, 31, 0) + node T_443 = neq(T_440, UInt<1>("h0")) + node T_444 = bits(T_440, 31, 16) + node T_445 = bits(T_440, 15, 0) + node T_447 = neq(T_444, UInt<1>("h0")) + node T_448 = bits(T_444, 15, 8) + node T_449 = bits(T_444, 7, 0) + node T_451 = neq(T_448, UInt<1>("h0")) + node T_452 = bits(T_448, 7, 4) + node T_453 = bits(T_448, 3, 0) + node T_455 = neq(T_452, UInt<1>("h0")) + node T_456 = bits(T_452, 3, 3) + node T_458 = bits(T_452, 2, 2) + node T_460 = bits(T_452, 1, 1) + node T_461 = shl(T_460, 0) + node T_462 = mux(T_458, UInt<2>("h2"), T_461) + node T_463 = mux(T_456, UInt<2>("h3"), T_462) + node T_464 = bits(T_453, 3, 3) + node T_466 = bits(T_453, 2, 2) + node T_468 = bits(T_453, 1, 1) + node T_469 = shl(T_468, 0) + node T_470 = mux(T_466, UInt<2>("h2"), T_469) + node T_471 = mux(T_464, UInt<2>("h3"), T_470) + node T_472 = mux(T_455, T_463, T_471) + node T_473 = cat(T_455, T_472) + node T_474 = bits(T_449, 7, 4) + node T_475 = bits(T_449, 3, 0) + node T_477 = neq(T_474, UInt<1>("h0")) + node T_478 = bits(T_474, 3, 3) + node T_480 = bits(T_474, 2, 2) + node T_482 = bits(T_474, 1, 1) + node T_483 = shl(T_482, 0) + node T_484 = mux(T_480, UInt<2>("h2"), T_483) + node T_485 = mux(T_478, UInt<2>("h3"), T_484) + node T_486 = bits(T_475, 3, 3) + node T_488 = bits(T_475, 2, 2) + node T_490 = bits(T_475, 1, 1) + node T_491 = shl(T_490, 0) + node T_492 = mux(T_488, UInt<2>("h2"), T_491) + node T_493 = mux(T_486, UInt<2>("h3"), T_492) + node T_494 = mux(T_477, T_485, T_493) + node T_495 = cat(T_477, T_494) + node T_496 = mux(T_451, T_473, T_495) + node T_497 = cat(T_451, T_496) + node T_498 = bits(T_445, 15, 8) + node T_499 = bits(T_445, 7, 0) + node T_501 = neq(T_498, UInt<1>("h0")) + node T_502 = bits(T_498, 7, 4) + node T_503 = bits(T_498, 3, 0) + node T_505 = neq(T_502, UInt<1>("h0")) + node T_506 = bits(T_502, 3, 3) + node T_508 = bits(T_502, 2, 2) + node T_510 = bits(T_502, 1, 1) + node T_511 = shl(T_510, 0) + node T_512 = mux(T_508, UInt<2>("h2"), T_511) + node T_513 = mux(T_506, UInt<2>("h3"), T_512) + node T_514 = bits(T_503, 3, 3) + node T_516 = bits(T_503, 2, 2) + node T_518 = bits(T_503, 1, 1) + node T_519 = shl(T_518, 0) + node T_520 = mux(T_516, UInt<2>("h2"), T_519) + node T_521 = mux(T_514, UInt<2>("h3"), T_520) + node T_522 = mux(T_505, T_513, T_521) + node T_523 = cat(T_505, T_522) + node T_524 = bits(T_499, 7, 4) + node T_525 = bits(T_499, 3, 0) + node T_527 = neq(T_524, UInt<1>("h0")) + node T_528 = bits(T_524, 3, 3) + node T_530 = bits(T_524, 2, 2) + node T_532 = bits(T_524, 1, 1) + node T_533 = shl(T_532, 0) + node T_534 = mux(T_530, UInt<2>("h2"), T_533) + node T_535 = mux(T_528, UInt<2>("h3"), T_534) + node T_536 = bits(T_525, 3, 3) + node T_538 = bits(T_525, 2, 2) + node T_540 = bits(T_525, 1, 1) + node T_541 = shl(T_540, 0) + node T_542 = mux(T_538, UInt<2>("h2"), T_541) + node T_543 = mux(T_536, UInt<2>("h3"), T_542) + node T_544 = mux(T_527, T_535, T_543) + node T_545 = cat(T_527, T_544) + node T_546 = mux(T_501, T_523, T_545) + node T_547 = cat(T_501, T_546) + node T_548 = mux(T_447, T_497, T_547) + node T_549 = cat(T_447, T_548) + node T_550 = bits(T_441, 31, 16) + node T_551 = bits(T_441, 15, 0) + node T_553 = neq(T_550, UInt<1>("h0")) + node T_554 = bits(T_550, 15, 8) + node T_555 = bits(T_550, 7, 0) + node T_557 = neq(T_554, UInt<1>("h0")) + node T_558 = bits(T_554, 7, 4) + node T_559 = bits(T_554, 3, 0) + node T_561 = neq(T_558, UInt<1>("h0")) + node T_562 = bits(T_558, 3, 3) + node T_564 = bits(T_558, 2, 2) + node T_566 = bits(T_558, 1, 1) + node T_567 = shl(T_566, 0) + node T_568 = mux(T_564, UInt<2>("h2"), T_567) + node T_569 = mux(T_562, UInt<2>("h3"), T_568) + node T_570 = bits(T_559, 3, 3) + node T_572 = bits(T_559, 2, 2) + node T_574 = bits(T_559, 1, 1) + node T_575 = shl(T_574, 0) + node T_576 = mux(T_572, UInt<2>("h2"), T_575) + node T_577 = mux(T_570, UInt<2>("h3"), T_576) + node T_578 = mux(T_561, T_569, T_577) + node T_579 = cat(T_561, T_578) + node T_580 = bits(T_555, 7, 4) + node T_581 = bits(T_555, 3, 0) + node T_583 = neq(T_580, UInt<1>("h0")) + node T_584 = bits(T_580, 3, 3) + node T_586 = bits(T_580, 2, 2) + node T_588 = bits(T_580, 1, 1) + node T_589 = shl(T_588, 0) + node T_590 = mux(T_586, UInt<2>("h2"), T_589) + node T_591 = mux(T_584, UInt<2>("h3"), T_590) + node T_592 = bits(T_581, 3, 3) + node T_594 = bits(T_581, 2, 2) + node T_596 = bits(T_581, 1, 1) + node T_597 = shl(T_596, 0) + node T_598 = mux(T_594, UInt<2>("h2"), T_597) + node T_599 = mux(T_592, UInt<2>("h3"), T_598) + node T_600 = mux(T_583, T_591, T_599) + node T_601 = cat(T_583, T_600) + node T_602 = mux(T_557, T_579, T_601) + node T_603 = cat(T_557, T_602) + node T_604 = bits(T_551, 15, 8) + node T_605 = bits(T_551, 7, 0) + node T_607 = neq(T_604, UInt<1>("h0")) + node T_608 = bits(T_604, 7, 4) + node T_609 = bits(T_604, 3, 0) + node T_611 = neq(T_608, UInt<1>("h0")) + node T_612 = bits(T_608, 3, 3) + node T_614 = bits(T_608, 2, 2) + node T_616 = bits(T_608, 1, 1) + node T_617 = shl(T_616, 0) + node T_618 = mux(T_614, UInt<2>("h2"), T_617) + node T_619 = mux(T_612, UInt<2>("h3"), T_618) + node T_620 = bits(T_609, 3, 3) + node T_622 = bits(T_609, 2, 2) + node T_624 = bits(T_609, 1, 1) + node T_625 = shl(T_624, 0) + node T_626 = mux(T_622, UInt<2>("h2"), T_625) + node T_627 = mux(T_620, UInt<2>("h3"), T_626) + node T_628 = mux(T_611, T_619, T_627) + node T_629 = cat(T_611, T_628) + node T_630 = bits(T_605, 7, 4) + node T_631 = bits(T_605, 3, 0) + node T_633 = neq(T_630, UInt<1>("h0")) + node T_634 = bits(T_630, 3, 3) + node T_636 = bits(T_630, 2, 2) + node T_638 = bits(T_630, 1, 1) + node T_639 = shl(T_638, 0) + node T_640 = mux(T_636, UInt<2>("h2"), T_639) + node T_641 = mux(T_634, UInt<2>("h3"), T_640) + node T_642 = bits(T_631, 3, 3) + node T_644 = bits(T_631, 2, 2) + node T_646 = bits(T_631, 1, 1) + node T_647 = shl(T_646, 0) + node T_648 = mux(T_644, UInt<2>("h2"), T_647) + node T_649 = mux(T_642, UInt<2>("h3"), T_648) + node T_650 = mux(T_633, T_641, T_649) + node T_651 = cat(T_633, T_650) + node T_652 = mux(T_607, T_629, T_651) + node T_653 = cat(T_607, T_652) + node T_654 = mux(T_553, T_603, T_653) + node T_655 = cat(T_553, T_654) + node T_656 = mux(T_443, T_549, T_655) + node T_657 = cat(T_443, T_656) + node T_659 = add(UInt<6>("h3f"), T_438) + node T_660 = tail(T_659, 1) + node T_661 = sub(T_660, T_657) + node T_662 = tail(T_661, 1) + node T_663 = gt(T_438, T_657) + node T_665 = eq(count, UInt<1>("h0")) + node T_666 = and(T_665, less) + node T_668 = gt(T_662, UInt<1>("h0")) + node T_669 = or(T_668, T_663) + node T_670 = and(T_666, T_669) + node T_672 = and(UInt<1>("h1"), T_670) + when T_672 : + node T_674 = bits(T_662, 5, 0) + node T_675 = mux(T_663, UInt<6>("h3f"), T_674) + node T_676 = bits(remainder, 63, 0) + node T_677 = dshl(T_676, T_675) + remainder <= T_677 + count <= T_675 + node T_679 = eq(count, UInt<1>("h0")) + node T_681 = eq(less, UInt<1>("h0")) + node T_682 = and(T_679, T_681) + node T_684 = eq(isHi, UInt<1>("h0")) + node T_685 = and(T_682, T_684) + when T_685 : + neg_out <= UInt<1>("h0") + node T_687 = and(io.resp.ready, io.resp.valid) + node T_688 = or(T_687, io.kill) + when T_688 : + state <= UInt<3>("h0") + node T_689 = and(io.req.ready, io.req.valid) + when T_689 : + node T_691 = eq(cmdMul, UInt<1>("h0")) + node T_692 = and(rhs_sign, T_691) + node T_693 = or(lhs_sign, T_692) + node T_694 = mux(T_693, UInt<3>("h1"), UInt<3>("h2")) + state <= T_694 + isMul <= cmdMul + isHi <= cmdHi + count <= UInt<1>("h0") + node T_697 = eq(cmdMul, UInt<1>("h0")) + node T_698 = neq(lhs_sign, rhs_sign) + node T_699 = mux(cmdHi, lhs_sign, T_698) + node T_700 = and(T_697, T_699) + neg_out <= T_700 + node T_701 = cat(rhs_sign, rhs_in) + divisor <= T_701 + remainder <= lhs_in + req <- io.req.bits + io.resp.bits <- req + node T_703 = eq(req.dw, UInt<1>("h0")) + node T_704 = and(UInt<1>("h1"), T_703) + node T_705 = bits(remainder, 31, 31) + node T_706 = bits(T_705, 0, 0) + node T_709 = mux(T_706, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_710 = bits(remainder, 31, 0) + node T_711 = cat(T_709, T_710) + node T_712 = bits(remainder, 63, 0) + node T_713 = mux(T_704, T_711, T_712) + io.resp.bits.data <= T_713 + node T_714 = eq(state, UInt<3>("h5")) + io.resp.valid <= T_714 + node T_715 = eq(state, UInt<3>("h0")) + io.req.ready <= T_715 + + module Rocket : input clk : Clock input reset : UInt<1> - output io : {flip prci : {reset : UInt<1>, id : UInt<1>, interrupts : {meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[0], fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>}} - + output io : { flip prci : { reset : UInt<1>, id : UInt<1>, interrupts : { meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}, imem : { req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : { flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip fpu : { flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, autl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, utl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[0], fpu_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>}} + io is invalid - reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk - reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk - reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk - reg ex_reg_xcpt_interrupt : UInt<1>, clk - reg ex_reg_valid : UInt<1>, clk - reg ex_reg_rvc : UInt<1>, clk - reg ex_reg_btb_hit : UInt<1>, clk - reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg ex_reg_xcpt : UInt<1>, clk - reg ex_reg_flush_pipe : UInt<1>, clk - reg ex_reg_load_use : UInt<1>, clk - reg ex_reg_cause : UInt, clk - reg ex_reg_replay : UInt<1>, clk - reg ex_reg_pc : UInt, clk - reg ex_reg_inst : UInt, clk - reg mem_reg_xcpt_interrupt : UInt<1>, clk - reg mem_reg_valid : UInt<1>, clk - reg mem_reg_rvc : UInt<1>, clk - reg mem_reg_btb_hit : UInt<1>, clk - reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg mem_reg_xcpt : UInt<1>, clk - reg mem_reg_replay : UInt<1>, clk - reg mem_reg_flush_pipe : UInt<1>, clk - reg mem_reg_cause : UInt, clk - reg mem_reg_slow_bypass : UInt<1>, clk - reg mem_reg_load : UInt<1>, clk - reg mem_reg_store : UInt<1>, clk - reg mem_reg_pc : UInt, clk - reg mem_reg_inst : UInt, clk - reg mem_reg_wdata : UInt, clk - reg mem_reg_rs2 : UInt, clk - wire take_pc_mem : UInt<1> @[rocket.scala 198:25] - take_pc_mem is invalid @[rocket.scala 198:25] - reg wb_reg_valid : UInt<1>, clk - reg wb_reg_xcpt : UInt<1>, clk - reg wb_reg_replay : UInt<1>, clk - reg wb_reg_cause : UInt, clk - reg wb_reg_pc : UInt, clk - reg wb_reg_inst : UInt, clk - reg wb_reg_wdata : UInt, clk - reg wb_reg_rs2 : UInt, clk - wire take_pc_wb : UInt<1> @[rocket.scala 208:24] - take_pc_wb is invalid @[rocket.scala 208:24] - wire take_pc_id : UInt<1> @[rocket.scala 210:24] - take_pc_id is invalid @[rocket.scala 210:24] - node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[rocket.scala 211:35] - node take_pc = or(take_pc_mem_wb, take_pc_id) @[rocket.scala 212:32] - inst ibuf of IBuf @[rocket.scala 215:20] + reg ex_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk with : + reset => (UInt<1>("h0"), ex_ctrl) + reg mem_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk with : + reset => (UInt<1>("h0"), mem_ctrl) + reg wb_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clk with : + reset => (UInt<1>("h0"), wb_ctrl) + reg ex_reg_xcpt_interrupt : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_xcpt_interrupt) + reg ex_reg_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_valid) + reg ex_reg_rvc : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_rvc) + reg ex_reg_btb_hit : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_btb_hit) + reg ex_reg_btb_resp : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : + reset => (UInt<1>("h0"), ex_reg_btb_resp) + reg ex_reg_xcpt : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_xcpt) + reg ex_reg_flush_pipe : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_flush_pipe) + reg ex_reg_load_use : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_load_use) + reg ex_reg_cause : UInt, clk with : + reset => (UInt<1>("h0"), ex_reg_cause) + reg ex_reg_replay : UInt<1>, clk with : + reset => (UInt<1>("h0"), ex_reg_replay) + reg ex_reg_pc : UInt, clk with : + reset => (UInt<1>("h0"), ex_reg_pc) + reg ex_reg_inst : UInt, clk with : + reset => (UInt<1>("h0"), ex_reg_inst) + reg mem_reg_xcpt_interrupt : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_xcpt_interrupt) + reg mem_reg_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_valid) + reg mem_reg_rvc : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_rvc) + reg mem_reg_btb_hit : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_btb_hit) + reg mem_reg_btb_resp : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : + reset => (UInt<1>("h0"), mem_reg_btb_resp) + reg mem_reg_xcpt : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_xcpt) + reg mem_reg_replay : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_replay) + reg mem_reg_flush_pipe : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_flush_pipe) + reg mem_reg_cause : UInt, clk with : + reset => (UInt<1>("h0"), mem_reg_cause) + reg mem_reg_slow_bypass : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_slow_bypass) + reg mem_reg_load : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_load) + reg mem_reg_store : UInt<1>, clk with : + reset => (UInt<1>("h0"), mem_reg_store) + reg mem_reg_pc : UInt, clk with : + reset => (UInt<1>("h0"), mem_reg_pc) + reg mem_reg_inst : UInt, clk with : + reset => (UInt<1>("h0"), mem_reg_inst) + reg mem_reg_wdata : UInt, clk with : + reset => (UInt<1>("h0"), mem_reg_wdata) + reg mem_reg_rs2 : UInt, clk with : + reset => (UInt<1>("h0"), mem_reg_rs2) + wire take_pc_mem : UInt<1> + take_pc_mem is invalid + reg wb_reg_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), wb_reg_valid) + reg wb_reg_xcpt : UInt<1>, clk with : + reset => (UInt<1>("h0"), wb_reg_xcpt) + reg wb_reg_replay : UInt<1>, clk with : + reset => (UInt<1>("h0"), wb_reg_replay) + reg wb_reg_cause : UInt, clk with : + reset => (UInt<1>("h0"), wb_reg_cause) + reg wb_reg_pc : UInt, clk with : + reset => (UInt<1>("h0"), wb_reg_pc) + reg wb_reg_inst : UInt, clk with : + reset => (UInt<1>("h0"), wb_reg_inst) + reg wb_reg_wdata : UInt, clk with : + reset => (UInt<1>("h0"), wb_reg_wdata) + reg wb_reg_rs2 : UInt, clk with : + reset => (UInt<1>("h0"), wb_reg_rs2) + wire take_pc_wb : UInt<1> + take_pc_wb is invalid + wire take_pc_id : UInt<1> + take_pc_id is invalid + node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) + node take_pc = or(take_pc_mem_wb, take_pc_id) + inst ibuf of IBuf ibuf.io is invalid ibuf.clk <= clk ibuf.reset <= reset - ibuf.io.imem <- io.imem.resp @[rocket.scala 218:16] - ibuf.io.kill <= take_pc @[rocket.scala 219:16] - wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>} @[rocket.scala 222:21] - id_ctrl is invalid @[rocket.scala 222:21] - node T_6680 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[decode.scala 13:65] - node T_6682 = eq(T_6680, UInt<32>("h03")) @[decode.scala 13:121] - node T_6684 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0106f")) @[decode.scala 13:65] - node T_6686 = eq(T_6684, UInt<32>("h03")) @[decode.scala 13:121] - node T_6688 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0607f")) @[decode.scala 13:65] - node T_6690 = eq(T_6688, UInt<32>("h0f")) @[decode.scala 13:121] - node T_6692 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07077")) @[decode.scala 13:65] - node T_6694 = eq(T_6692, UInt<32>("h013")) @[decode.scala 13:121] - node T_6696 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05f")) @[decode.scala 13:65] - node T_6698 = eq(T_6696, UInt<32>("h017")) @[decode.scala 13:121] - node T_6700 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00007f")) @[decode.scala 13:65] - node T_6702 = eq(T_6700, UInt<32>("h033")) @[decode.scala 13:121] - node T_6704 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[decode.scala 13:65] - node T_6706 = eq(T_6704, UInt<32>("h033")) @[decode.scala 13:121] - node T_6708 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000073")) @[decode.scala 13:65] - node T_6710 = eq(T_6708, UInt<32>("h043")) @[decode.scala 13:121] - node T_6712 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e400007f")) @[decode.scala 13:65] - node T_6714 = eq(T_6712, UInt<32>("h053")) @[decode.scala 13:121] - node T_6716 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707b")) @[decode.scala 13:65] - node T_6718 = eq(T_6716, UInt<32>("h063")) @[decode.scala 13:121] - node T_6720 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07f")) @[decode.scala 13:65] - node T_6722 = eq(T_6720, UInt<32>("h06f")) @[decode.scala 13:121] - node T_6724 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0ffefffff")) @[decode.scala 13:65] - node T_6726 = eq(T_6724, UInt<32>("h073")) @[decode.scala 13:121] - node T_6728 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00305f")) @[decode.scala 13:65] - node T_6730 = eq(T_6728, UInt<32>("h01013")) @[decode.scala 13:121] - node T_6732 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe00305f")) @[decode.scala 13:65] - node T_6734 = eq(T_6732, UInt<32>("h0101b")) @[decode.scala 13:121] - node T_6736 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0605b")) @[decode.scala 13:65] - node T_6738 = eq(T_6736, UInt<32>("h02003")) @[decode.scala 13:121] - node T_6740 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[decode.scala 13:65] - node T_6742 = eq(T_6740, UInt<32>("h02013")) @[decode.scala 13:121] - node T_6744 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01800607f")) @[decode.scala 13:65] - node T_6746 = eq(T_6744, UInt<32>("h0202f")) @[decode.scala 13:121] - node T_6748 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[decode.scala 13:65] - node T_6750 = eq(T_6748, UInt<32>("h02073")) @[decode.scala 13:121] - node T_6752 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0bc00707f")) @[decode.scala 13:65] - node T_6754 = eq(T_6752, UInt<32>("h05013")) @[decode.scala 13:121] - node T_6756 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be00705f")) @[decode.scala 13:65] - node T_6758 = eq(T_6756, UInt<32>("h0501b")) @[decode.scala 13:121] - node T_6760 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[decode.scala 13:65] - node T_6762 = eq(T_6760, UInt<32>("h05033")) @[decode.scala 13:121] - node T_6764 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe004077")) @[decode.scala 13:65] - node T_6766 = eq(T_6764, UInt<32>("h02004033")) @[decode.scala 13:121] - node T_6768 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e800607f")) @[decode.scala 13:65] - node T_6770 = eq(T_6768, UInt<32>("h0800202f")) @[decode.scala 13:121] - node T_6772 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f9f0607f")) @[decode.scala 13:65] - node T_6774 = eq(T_6772, UInt<32>("h01000202f")) @[decode.scala 13:121] - node T_6776 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0dfffffff")) @[decode.scala 13:65] - node T_6778 = eq(T_6776, UInt<32>("h010200073")) @[decode.scala 13:121] - node T_6780 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fff07fff")) @[decode.scala 13:65] - node T_6782 = eq(T_6780, UInt<32>("h010400073")) @[decode.scala 13:121] - node T_6784 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010500073")) @[decode.scala 13:121] - node T_6786 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f400607f")) @[decode.scala 13:65] - node T_6788 = eq(T_6786, UInt<32>("h020000053")) @[decode.scala 13:121] - node T_6790 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00607f")) @[decode.scala 13:65] - node T_6792 = eq(T_6790, UInt<32>("h020000053")) @[decode.scala 13:121] - node T_6794 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00507f")) @[decode.scala 13:65] - node T_6796 = eq(T_6794, UInt<32>("h020000053")) @[decode.scala 13:121] - node T_6798 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[decode.scala 13:65] - node T_6800 = eq(T_6798, UInt<32>("h040100053")) @[decode.scala 13:121] - node T_6802 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[decode.scala 13:65] - node T_6804 = eq(T_6802, UInt<32>("h042000053")) @[decode.scala 13:121] - node T_6806 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0007f")) @[decode.scala 13:65] - node T_6808 = eq(T_6806, UInt<32>("h058000053")) @[decode.scala 13:121] - node T_6810 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07b200073")) @[decode.scala 13:121] - node T_6812 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edc0007f")) @[decode.scala 13:65] - node T_6814 = eq(T_6812, UInt<32>("h0c0000053")) @[decode.scala 13:121] - node T_6816 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0607f")) @[decode.scala 13:65] - node T_6818 = eq(T_6816, UInt<32>("h0e0000053")) @[decode.scala 13:121] - node T_6820 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edf0707f")) @[decode.scala 13:65] - node T_6822 = eq(T_6820, UInt<32>("h0e0000053")) @[decode.scala 13:121] - node T_6824 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0603f")) @[decode.scala 13:65] - node T_6826 = eq(T_6824, UInt<32>("h023")) @[decode.scala 13:121] - node T_6828 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0306f")) @[decode.scala 13:65] - node T_6830 = eq(T_6828, UInt<32>("h01063")) @[decode.scala 13:121] - node T_6832 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0407f")) @[decode.scala 13:65] - node T_6834 = eq(T_6832, UInt<32>("h04063")) @[decode.scala 13:121] - node T_6836 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc007077")) @[decode.scala 13:65] - node T_6838 = eq(T_6836, UInt<32>("h033")) @[decode.scala 13:121] - node T_6840 = or(UInt<1>("h00"), T_6682) @[decode.scala 14:30] - node T_6841 = or(T_6840, T_6686) @[decode.scala 14:30] - node T_6842 = or(T_6841, T_6690) @[decode.scala 14:30] - node T_6843 = or(T_6842, T_6694) @[decode.scala 14:30] - node T_6844 = or(T_6843, T_6698) @[decode.scala 14:30] - node T_6845 = or(T_6844, T_6702) @[decode.scala 14:30] - node T_6846 = or(T_6845, T_6706) @[decode.scala 14:30] - node T_6847 = or(T_6846, T_6710) @[decode.scala 14:30] - node T_6848 = or(T_6847, T_6714) @[decode.scala 14:30] - node T_6849 = or(T_6848, T_6718) @[decode.scala 14:30] - node T_6850 = or(T_6849, T_6722) @[decode.scala 14:30] - node T_6851 = or(T_6850, T_6726) @[decode.scala 14:30] - node T_6852 = or(T_6851, T_6730) @[decode.scala 14:30] - node T_6853 = or(T_6852, T_6734) @[decode.scala 14:30] - node T_6854 = or(T_6853, T_6738) @[decode.scala 14:30] - node T_6855 = or(T_6854, T_6742) @[decode.scala 14:30] - node T_6856 = or(T_6855, T_6746) @[decode.scala 14:30] - node T_6857 = or(T_6856, T_6750) @[decode.scala 14:30] - node T_6858 = or(T_6857, T_6754) @[decode.scala 14:30] - node T_6859 = or(T_6858, T_6758) @[decode.scala 14:30] - node T_6860 = or(T_6859, T_6762) @[decode.scala 14:30] - node T_6861 = or(T_6860, T_6766) @[decode.scala 14:30] - node T_6862 = or(T_6861, T_6770) @[decode.scala 14:30] - node T_6863 = or(T_6862, T_6774) @[decode.scala 14:30] - node T_6864 = or(T_6863, T_6778) @[decode.scala 14:30] - node T_6865 = or(T_6864, T_6782) @[decode.scala 14:30] - node T_6866 = or(T_6865, T_6784) @[decode.scala 14:30] - node T_6867 = or(T_6866, T_6788) @[decode.scala 14:30] - node T_6868 = or(T_6867, T_6792) @[decode.scala 14:30] - node T_6869 = or(T_6868, T_6796) @[decode.scala 14:30] - node T_6870 = or(T_6869, T_6800) @[decode.scala 14:30] - node T_6871 = or(T_6870, T_6804) @[decode.scala 14:30] - node T_6872 = or(T_6871, T_6808) @[decode.scala 14:30] - node T_6873 = or(T_6872, T_6810) @[decode.scala 14:30] - node T_6874 = or(T_6873, T_6814) @[decode.scala 14:30] - node T_6875 = or(T_6874, T_6818) @[decode.scala 14:30] - node T_6876 = or(T_6875, T_6822) @[decode.scala 14:30] - node T_6877 = or(T_6876, T_6826) @[decode.scala 14:30] - node T_6878 = or(T_6877, T_6830) @[decode.scala 14:30] - node T_6879 = or(T_6878, T_6834) @[decode.scala 14:30] - node T_6880 = or(T_6879, T_6838) @[decode.scala 14:30] - node T_6882 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05c")) @[decode.scala 13:65] - node T_6884 = eq(T_6882, UInt<32>("h04")) @[decode.scala 13:121] - node T_6886 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h060")) @[decode.scala 13:65] - node T_6888 = eq(T_6886, UInt<32>("h040")) @[decode.scala 13:121] - node T_6890 = or(UInt<1>("h00"), T_6884) @[decode.scala 14:30] - node T_6891 = or(T_6890, T_6888) @[decode.scala 14:30] - node T_6894 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h074")) @[decode.scala 13:65] - node T_6896 = eq(T_6894, UInt<32>("h060")) @[decode.scala 13:121] - node T_6898 = or(UInt<1>("h00"), T_6896) @[decode.scala 14:30] - node T_6900 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h068")) @[decode.scala 13:65] - node T_6902 = eq(T_6900, UInt<32>("h068")) @[decode.scala 13:121] - node T_6904 = or(UInt<1>("h00"), T_6902) @[decode.scala 14:30] - node T_6906 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0203c")) @[decode.scala 13:65] - node T_6908 = eq(T_6906, UInt<32>("h024")) @[decode.scala 13:121] - node T_6910 = or(UInt<1>("h00"), T_6908) @[decode.scala 14:30] - node T_6912 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[decode.scala 13:65] - node T_6914 = eq(T_6912, UInt<32>("h020")) @[decode.scala 13:121] - node T_6916 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[decode.scala 13:65] - node T_6918 = eq(T_6916, UInt<32>("h020")) @[decode.scala 13:121] - node T_6920 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02048")) @[decode.scala 13:65] - node T_6922 = eq(T_6920, UInt<32>("h02008")) @[decode.scala 13:121] - node T_6924 = or(UInt<1>("h00"), T_6914) @[decode.scala 14:30] - node T_6925 = or(T_6924, T_6918) @[decode.scala 14:30] - node T_6926 = or(T_6925, T_6922) @[decode.scala 14:30] - node T_6928 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[decode.scala 13:65] - node T_6930 = eq(T_6928, UInt<32>("h00")) @[decode.scala 13:121] - node T_6932 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04024")) @[decode.scala 13:65] - node T_6934 = eq(T_6932, UInt<32>("h020")) @[decode.scala 13:121] - node T_6936 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h038")) @[decode.scala 13:65] - node T_6938 = eq(T_6936, UInt<32>("h020")) @[decode.scala 13:121] - node T_6940 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02050")) @[decode.scala 13:65] - node T_6942 = eq(T_6940, UInt<32>("h02000")) @[decode.scala 13:121] - node T_6944 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000034")) @[decode.scala 13:65] - node T_6946 = eq(T_6944, UInt<32>("h090000010")) @[decode.scala 13:121] - node T_6948 = or(UInt<1>("h00"), T_6930) @[decode.scala 14:30] - node T_6949 = or(T_6948, T_6934) @[decode.scala 14:30] - node T_6950 = or(T_6949, T_6938) @[decode.scala 14:30] - node T_6951 = or(T_6950, T_6942) @[decode.scala 14:30] - node T_6952 = or(T_6951, T_6946) @[decode.scala 14:30] - node T_6954 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h058")) @[decode.scala 13:65] - node T_6956 = eq(T_6954, UInt<32>("h00")) @[decode.scala 13:121] - node T_6958 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020")) @[decode.scala 13:65] - node T_6960 = eq(T_6958, UInt<32>("h00")) @[decode.scala 13:121] - node T_6962 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0c")) @[decode.scala 13:65] - node T_6964 = eq(T_6962, UInt<32>("h04")) @[decode.scala 13:121] - node T_6966 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[decode.scala 13:65] - node T_6968 = eq(T_6966, UInt<32>("h048")) @[decode.scala 13:121] - node T_6970 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04050")) @[decode.scala 13:65] - node T_6972 = eq(T_6970, UInt<32>("h04050")) @[decode.scala 13:121] - node T_6974 = or(UInt<1>("h00"), T_6956) @[decode.scala 14:30] - node T_6975 = or(T_6974, T_6960) @[decode.scala 14:30] - node T_6976 = or(T_6975, T_6964) @[decode.scala 14:30] - node T_6977 = or(T_6976, T_6968) @[decode.scala 14:30] - node T_6978 = or(T_6977, T_6972) @[decode.scala 14:30] - node T_6980 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[decode.scala 13:65] - node T_6982 = eq(T_6980, UInt<32>("h00")) @[decode.scala 13:121] - node T_6984 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[decode.scala 13:65] - node T_6986 = eq(T_6984, UInt<32>("h00")) @[decode.scala 13:121] - node T_6988 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04008")) @[decode.scala 13:65] - node T_6990 = eq(T_6988, UInt<32>("h04000")) @[decode.scala 13:121] - node T_6992 = or(UInt<1>("h00"), T_6982) @[decode.scala 14:30] - node T_6993 = or(T_6992, T_6930) @[decode.scala 14:30] - node T_6994 = or(T_6993, T_6986) @[decode.scala 14:30] - node T_6995 = or(T_6994, T_6990) @[decode.scala 14:30] - node T_6996 = cat(T_6995, T_6978) @[Cat.scala 20:58] - node T_6998 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04004")) @[decode.scala 13:65] - node T_7000 = eq(T_6998, UInt<32>("h00")) @[decode.scala 13:121] - node T_7002 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[decode.scala 13:65] - node T_7004 = eq(T_7002, UInt<32>("h00")) @[decode.scala 13:121] - node T_7006 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h024")) @[decode.scala 13:65] - node T_7008 = eq(T_7006, UInt<32>("h00")) @[decode.scala 13:121] - node T_7010 = or(UInt<1>("h00"), T_7000) @[decode.scala 14:30] - node T_7011 = or(T_7010, T_7004) @[decode.scala 14:30] - node T_7012 = or(T_7011, T_6930) @[decode.scala 14:30] - node T_7013 = or(T_7012, T_7008) @[decode.scala 14:30] - node T_7014 = or(T_7013, T_6986) @[decode.scala 14:30] - node T_7016 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[decode.scala 13:65] - node T_7018 = eq(T_7016, UInt<32>("h014")) @[decode.scala 13:121] - node T_7020 = or(UInt<1>("h00"), T_7018) @[decode.scala 14:30] - node T_7021 = or(T_7020, T_6968) @[decode.scala 14:30] - node T_7022 = cat(T_7021, T_7014) @[Cat.scala 20:58] - node T_7024 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[decode.scala 13:65] - node T_7026 = eq(T_7024, UInt<32>("h08")) @[decode.scala 13:121] - node T_7028 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[decode.scala 13:65] - node T_7030 = eq(T_7028, UInt<32>("h040")) @[decode.scala 13:121] - node T_7032 = or(UInt<1>("h00"), T_7026) @[decode.scala 14:30] - node T_7033 = or(T_7032, T_7030) @[decode.scala 14:30] - node T_7035 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[decode.scala 13:65] - node T_7037 = eq(T_7035, UInt<32>("h014")) @[decode.scala 13:121] - node T_7039 = or(UInt<1>("h00"), T_7026) @[decode.scala 14:30] - node T_7040 = or(T_7039, T_7037) @[decode.scala 14:30] - node T_7042 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h030")) @[decode.scala 13:65] - node T_7044 = eq(T_7042, UInt<32>("h00")) @[decode.scala 13:121] - node T_7046 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0201c")) @[decode.scala 13:65] - node T_7048 = eq(T_7046, UInt<32>("h04")) @[decode.scala 13:121] - node T_7050 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[decode.scala 13:65] - node T_7052 = eq(T_7050, UInt<32>("h010")) @[decode.scala 13:121] - node T_7054 = or(UInt<1>("h00"), T_7044) @[decode.scala 14:30] - node T_7055 = or(T_7054, T_7048) @[decode.scala 14:30] - node T_7056 = or(T_7055, T_7052) @[decode.scala 14:30] - node T_7057 = cat(T_7056, T_7040) @[Cat.scala 20:58] - node T_7058 = cat(T_7057, T_7033) @[Cat.scala 20:58] - node T_7060 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010")) @[decode.scala 13:65] - node T_7062 = eq(T_7060, UInt<32>("h00")) @[decode.scala 13:121] - node T_7064 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08")) @[decode.scala 13:65] - node T_7066 = eq(T_7064, UInt<32>("h00")) @[decode.scala 13:121] - node T_7068 = or(UInt<1>("h00"), T_7062) @[decode.scala 14:30] - node T_7069 = or(T_7068, T_7066) @[decode.scala 14:30] - node T_7071 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[decode.scala 13:65] - node T_7073 = eq(T_7071, UInt<32>("h01010")) @[decode.scala 13:121] - node T_7075 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01058")) @[decode.scala 13:65] - node T_7077 = eq(T_7075, UInt<32>("h01040")) @[decode.scala 13:121] - node T_7079 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07044")) @[decode.scala 13:65] - node T_7081 = eq(T_7079, UInt<32>("h07000")) @[decode.scala 13:121] - node T_7083 = or(UInt<1>("h00"), T_7073) @[decode.scala 14:30] - node T_7084 = or(T_7083, T_7077) @[decode.scala 14:30] - node T_7085 = or(T_7084, T_7081) @[decode.scala 14:30] - node T_7087 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04054")) @[decode.scala 13:65] - node T_7089 = eq(T_7087, UInt<32>("h040")) @[decode.scala 13:121] - node T_7091 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02058")) @[decode.scala 13:65] - node T_7093 = eq(T_7091, UInt<32>("h02040")) @[decode.scala 13:121] - node T_7095 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[decode.scala 13:65] - node T_7097 = eq(T_7095, UInt<32>("h03010")) @[decode.scala 13:121] - node T_7099 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[decode.scala 13:65] - node T_7101 = eq(T_7099, UInt<32>("h06010")) @[decode.scala 13:121] - node T_7103 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003034")) @[decode.scala 13:65] - node T_7105 = eq(T_7103, UInt<32>("h040000030")) @[decode.scala 13:121] - node T_7107 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040001054")) @[decode.scala 13:65] - node T_7109 = eq(T_7107, UInt<32>("h040001010")) @[decode.scala 13:121] - node T_7111 = or(UInt<1>("h00"), T_7089) @[decode.scala 14:30] - node T_7112 = or(T_7111, T_7093) @[decode.scala 14:30] - node T_7113 = or(T_7112, T_7097) @[decode.scala 14:30] - node T_7114 = or(T_7113, T_7101) @[decode.scala 14:30] - node T_7115 = or(T_7114, T_7105) @[decode.scala 14:30] - node T_7116 = or(T_7115, T_7109) @[decode.scala 14:30] - node T_7118 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02054")) @[decode.scala 13:65] - node T_7120 = eq(T_7118, UInt<32>("h02010")) @[decode.scala 13:121] - node T_7122 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040004054")) @[decode.scala 13:65] - node T_7124 = eq(T_7122, UInt<32>("h04010")) @[decode.scala 13:121] - node T_7126 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05054")) @[decode.scala 13:65] - node T_7128 = eq(T_7126, UInt<32>("h04010")) @[decode.scala 13:121] - node T_7130 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04058")) @[decode.scala 13:65] - node T_7132 = eq(T_7130, UInt<32>("h04040")) @[decode.scala 13:121] - node T_7134 = or(UInt<1>("h00"), T_7120) @[decode.scala 14:30] - node T_7135 = or(T_7134, T_7124) @[decode.scala 14:30] - node T_7136 = or(T_7135, T_7128) @[decode.scala 14:30] - node T_7137 = or(T_7136, T_7132) @[decode.scala 14:30] - node T_7139 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[decode.scala 13:65] - node T_7141 = eq(T_7139, UInt<32>("h02010")) @[decode.scala 13:121] - node T_7143 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003054")) @[decode.scala 13:65] - node T_7145 = eq(T_7143, UInt<32>("h040001010")) @[decode.scala 13:121] - node T_7147 = or(UInt<1>("h00"), T_7141) @[decode.scala 14:30] - node T_7148 = or(T_7147, T_7132) @[decode.scala 14:30] - node T_7149 = or(T_7148, T_7105) @[decode.scala 14:30] - node T_7150 = or(T_7149, T_7145) @[decode.scala 14:30] - node T_7151 = cat(T_7116, T_7085) @[Cat.scala 20:58] - node T_7152 = cat(T_7150, T_7137) @[Cat.scala 20:58] - node T_7153 = cat(T_7152, T_7151) @[Cat.scala 20:58] - node T_7155 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0405f")) @[decode.scala 13:65] - node T_7157 = eq(T_7155, UInt<32>("h03")) @[decode.scala 13:121] - node T_7159 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0107f")) @[decode.scala 13:65] - node T_7161 = eq(T_7159, UInt<32>("h03")) @[decode.scala 13:121] - node T_7163 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707f")) @[decode.scala 13:65] - node T_7165 = eq(T_7163, UInt<32>("h0100f")) @[decode.scala 13:121] - node T_7167 = or(UInt<1>("h00"), T_7157) @[decode.scala 14:30] - node T_7168 = or(T_7167, T_6682) @[decode.scala 14:30] - node T_7169 = or(T_7168, T_7161) @[decode.scala 14:30] - node T_7170 = or(T_7169, T_7165) @[decode.scala 14:30] - node T_7171 = or(T_7170, T_6738) @[decode.scala 14:30] - node T_7172 = or(T_7171, T_6746) @[decode.scala 14:30] - node T_7173 = or(T_7172, T_6770) @[decode.scala 14:30] - node T_7174 = or(T_7173, T_6774) @[decode.scala 14:30] - node T_7176 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02008")) @[decode.scala 13:65] - node T_7178 = eq(T_7176, UInt<32>("h08")) @[decode.scala 13:121] - node T_7180 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[decode.scala 13:65] - node T_7182 = eq(T_7180, UInt<32>("h020")) @[decode.scala 13:121] - node T_7184 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018000020")) @[decode.scala 13:65] - node T_7186 = eq(T_7184, UInt<32>("h018000020")) @[decode.scala 13:121] - node T_7188 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020000020")) @[decode.scala 13:65] - node T_7190 = eq(T_7188, UInt<32>("h020000020")) @[decode.scala 13:121] - node T_7192 = or(UInt<1>("h00"), T_7178) @[decode.scala 14:30] - node T_7193 = or(T_7192, T_7182) @[decode.scala 14:30] - node T_7194 = or(T_7193, T_7186) @[decode.scala 14:30] - node T_7195 = or(T_7194, T_7190) @[decode.scala 14:30] - node T_7197 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010002008")) @[decode.scala 13:65] - node T_7199 = eq(T_7197, UInt<32>("h010002008")) @[decode.scala 13:121] - node T_7201 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040002008")) @[decode.scala 13:65] - node T_7203 = eq(T_7201, UInt<32>("h040002008")) @[decode.scala 13:121] - node T_7205 = or(UInt<1>("h00"), T_7199) @[decode.scala 14:30] - node T_7206 = or(T_7205, T_7203) @[decode.scala 14:30] - node T_7208 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08000008")) @[decode.scala 13:65] - node T_7210 = eq(T_7208, UInt<32>("h08000008")) @[decode.scala 13:121] - node T_7212 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000008")) @[decode.scala 13:65] - node T_7214 = eq(T_7212, UInt<32>("h010000008")) @[decode.scala 13:121] - node T_7216 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000008")) @[decode.scala 13:65] - node T_7218 = eq(T_7216, UInt<32>("h080000008")) @[decode.scala 13:121] - node T_7220 = or(UInt<1>("h00"), T_7178) @[decode.scala 14:30] - node T_7221 = or(T_7220, T_7210) @[decode.scala 14:30] - node T_7222 = or(T_7221, T_7214) @[decode.scala 14:30] - node T_7223 = or(T_7222, T_7218) @[decode.scala 14:30] - node T_7225 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018002008")) @[decode.scala 13:65] - node T_7227 = eq(T_7225, UInt<32>("h02008")) @[decode.scala 13:121] - node T_7229 = or(UInt<1>("h00"), T_7227) @[decode.scala 14:30] - node T_7231 = cat(T_7206, T_7195) @[Cat.scala 20:58] - node T_7232 = cat(UInt<1>("h00"), T_7229) @[Cat.scala 20:58] - node T_7233 = cat(T_7232, T_7223) @[Cat.scala 20:58] - node T_7234 = cat(T_7233, T_7231) @[Cat.scala 20:58] - node T_7236 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01000")) @[decode.scala 13:65] - node T_7238 = eq(T_7236, UInt<32>("h01000")) @[decode.scala 13:121] - node T_7240 = or(UInt<1>("h00"), T_7238) @[decode.scala 14:30] - node T_7242 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000")) @[decode.scala 13:65] - node T_7244 = eq(T_7242, UInt<32>("h02000")) @[decode.scala 13:121] - node T_7246 = or(UInt<1>("h00"), T_7244) @[decode.scala 14:30] - node T_7248 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000")) @[decode.scala 13:65] - node T_7250 = eq(T_7248, UInt<32>("h04000")) @[decode.scala 13:121] - node T_7252 = or(UInt<1>("h00"), T_7250) @[decode.scala 14:30] - node T_7253 = cat(T_7252, T_7246) @[Cat.scala 20:58] - node T_7254 = cat(T_7253, T_7240) @[Cat.scala 20:58] - node T_7256 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000060")) @[decode.scala 13:65] - node T_7258 = eq(T_7256, UInt<32>("h040")) @[decode.scala 13:121] - node T_7260 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[decode.scala 13:65] - node T_7262 = eq(T_7260, UInt<32>("h040")) @[decode.scala 13:121] - node T_7264 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h070")) @[decode.scala 13:65] - node T_7266 = eq(T_7264, UInt<32>("h040")) @[decode.scala 13:121] - node T_7268 = or(UInt<1>("h00"), T_7258) @[decode.scala 14:30] - node T_7269 = or(T_7268, T_7262) @[decode.scala 14:30] - node T_7270 = or(T_7269, T_7266) @[decode.scala 14:30] - node T_7272 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c")) @[decode.scala 13:65] - node T_7274 = eq(T_7272, UInt<32>("h024")) @[decode.scala 13:121] - node T_7276 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040000060")) @[decode.scala 13:65] - node T_7278 = eq(T_7276, UInt<32>("h040")) @[decode.scala 13:121] - node T_7280 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000060")) @[decode.scala 13:65] - node T_7282 = eq(T_7280, UInt<32>("h010000040")) @[decode.scala 13:121] - node T_7284 = or(UInt<1>("h00"), T_7274) @[decode.scala 14:30] - node T_7285 = or(T_7284, T_7278) @[decode.scala 14:30] - node T_7286 = or(T_7285, T_7266) @[decode.scala 14:30] - node T_7287 = or(T_7286, T_7282) @[decode.scala 14:30] - node T_7289 = or(UInt<1>("h00"), T_7266) @[decode.scala 14:30] - node T_7291 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03c")) @[decode.scala 13:65] - node T_7293 = eq(T_7291, UInt<32>("h04")) @[decode.scala 13:121] - node T_7295 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[decode.scala 13:65] - node T_7297 = eq(T_7295, UInt<32>("h010000040")) @[decode.scala 13:121] - node T_7299 = or(UInt<1>("h00"), T_7293) @[decode.scala 14:30] - node T_7300 = or(T_7299, T_7258) @[decode.scala 14:30] - node T_7301 = or(T_7300, T_7266) @[decode.scala 14:30] - node T_7302 = or(T_7301, T_7297) @[decode.scala 14:30] - node T_7304 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000074")) @[decode.scala 13:65] - node T_7306 = eq(T_7304, UInt<32>("h02000030")) @[decode.scala 13:121] - node T_7308 = or(UInt<1>("h00"), T_7306) @[decode.scala 14:30] - node T_7310 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[decode.scala 13:65] - node T_7312 = eq(T_7310, UInt<32>("h00")) @[decode.scala 13:121] - node T_7314 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[decode.scala 13:65] - node T_7316 = eq(T_7314, UInt<32>("h010")) @[decode.scala 13:121] - node T_7318 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02024")) @[decode.scala 13:65] - node T_7320 = eq(T_7318, UInt<32>("h024")) @[decode.scala 13:121] - node T_7322 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[decode.scala 13:65] - node T_7324 = eq(T_7322, UInt<32>("h028")) @[decode.scala 13:121] - node T_7326 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01030")) @[decode.scala 13:65] - node T_7328 = eq(T_7326, UInt<32>("h01030")) @[decode.scala 13:121] - node T_7330 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02030")) @[decode.scala 13:65] - node T_7332 = eq(T_7330, UInt<32>("h02030")) @[decode.scala 13:121] - node T_7334 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000010")) @[decode.scala 13:65] - node T_7336 = eq(T_7334, UInt<32>("h080000010")) @[decode.scala 13:121] - node T_7338 = or(UInt<1>("h00"), T_7312) @[decode.scala 14:30] - node T_7339 = or(T_7338, T_7316) @[decode.scala 14:30] - node T_7340 = or(T_7339, T_7320) @[decode.scala 14:30] - node T_7341 = or(T_7340, T_7324) @[decode.scala 14:30] - node T_7342 = or(T_7341, T_7328) @[decode.scala 14:30] - node T_7343 = or(T_7342, T_7332) @[decode.scala 14:30] - node T_7344 = or(T_7343, T_7336) @[decode.scala 14:30] - node T_7346 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01070")) @[decode.scala 13:65] - node T_7348 = eq(T_7346, UInt<32>("h01070")) @[decode.scala 13:121] - node T_7350 = or(UInt<1>("h00"), T_7348) @[decode.scala 14:30] - node T_7352 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02070")) @[decode.scala 13:65] - node T_7354 = eq(T_7352, UInt<32>("h02070")) @[decode.scala 13:121] - node T_7356 = or(UInt<1>("h00"), T_7354) @[decode.scala 14:30] - node T_7358 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03070")) @[decode.scala 13:65] - node T_7360 = eq(T_7358, UInt<32>("h070")) @[decode.scala 13:121] - node T_7362 = or(UInt<1>("h00"), T_7360) @[decode.scala 14:30] - node T_7363 = cat(T_7362, T_7356) @[Cat.scala 20:58] - node T_7364 = cat(T_7363, T_7350) @[Cat.scala 20:58] - node T_7366 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[decode.scala 13:65] - node T_7368 = eq(T_7366, UInt<32>("h01008")) @[decode.scala 13:121] - node T_7370 = or(UInt<1>("h00"), T_7368) @[decode.scala 14:30] - node T_7372 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[decode.scala 13:65] - node T_7374 = eq(T_7372, UInt<32>("h08")) @[decode.scala 13:121] - node T_7376 = or(UInt<1>("h00"), T_7374) @[decode.scala 14:30] - node T_7378 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06048")) @[decode.scala 13:65] - node T_7380 = eq(T_7378, UInt<32>("h02008")) @[decode.scala 13:121] - node T_7382 = or(UInt<1>("h00"), T_7380) @[decode.scala 14:30] - node T_7384 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0105c")) @[decode.scala 13:65] - node T_7386 = eq(T_7384, UInt<32>("h01004")) @[decode.scala 13:121] - node T_7388 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000060")) @[decode.scala 13:65] - node T_7390 = eq(T_7388, UInt<32>("h02000040")) @[decode.scala 13:121] - node T_7392 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0d0000070")) @[decode.scala 13:65] - node T_7394 = eq(T_7392, UInt<32>("h040000050")) @[decode.scala 13:121] - node T_7396 = or(UInt<1>("h00"), T_7386) @[decode.scala 14:30] - node T_7397 = or(T_7396, T_7390) @[decode.scala 14:30] - node T_7398 = or(T_7397, T_7394) @[decode.scala 14:30] - id_ctrl.legal <= T_6880 @[idecode.scala 62:42] - id_ctrl.fp <= T_6891 @[idecode.scala 62:42] - id_ctrl.rocc <= UInt<1>("h00") @[idecode.scala 62:42] - id_ctrl.branch <= T_6898 @[idecode.scala 62:42] - id_ctrl.jal <= T_6904 @[idecode.scala 62:42] - id_ctrl.jalr <= T_6910 @[idecode.scala 62:42] - id_ctrl.rxs2 <= T_6926 @[idecode.scala 62:42] - id_ctrl.rxs1 <= T_6952 @[idecode.scala 62:42] - id_ctrl.sel_alu2 <= T_6996 @[idecode.scala 62:42] - id_ctrl.sel_alu1 <= T_7022 @[idecode.scala 62:42] - id_ctrl.sel_imm <= T_7058 @[idecode.scala 62:42] - id_ctrl.alu_dw <= T_7069 @[idecode.scala 62:42] - id_ctrl.alu_fn <= T_7153 @[idecode.scala 62:42] - id_ctrl.mem <= T_7174 @[idecode.scala 62:42] - id_ctrl.mem_cmd <= T_7234 @[idecode.scala 62:42] - id_ctrl.mem_type <= T_7254 @[idecode.scala 62:42] - id_ctrl.rfs1 <= T_7270 @[idecode.scala 62:42] - id_ctrl.rfs2 <= T_7287 @[idecode.scala 62:42] - id_ctrl.rfs3 <= T_7289 @[idecode.scala 62:42] - id_ctrl.wfd <= T_7302 @[idecode.scala 62:42] - id_ctrl.div <= T_7308 @[idecode.scala 62:42] - id_ctrl.wxd <= T_7344 @[idecode.scala 62:42] - id_ctrl.csr <= T_7364 @[idecode.scala 62:42] - id_ctrl.fence_i <= T_7370 @[idecode.scala 62:42] - id_ctrl.fence <= T_7376 @[idecode.scala 62:42] - id_ctrl.amo <= T_7382 @[idecode.scala 62:42] - id_ctrl.dp <= T_7398 @[idecode.scala 62:42] - wire id_load_use : UInt<1> @[rocket.scala 227:25] - id_load_use is invalid @[rocket.scala 227:25] - reg id_reg_fence : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - cmem T_7403 : UInt<64>[31] @[rocket.scala 103:23] - wire id_rs_0 : UInt @[rocket.scala 109:26] - id_rs_0 is invalid @[rocket.scala 109:26] - node T_7407 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[rocket.scala 110:45] - node T_7408 = and(UInt<1>("h00"), T_7407) @[rocket.scala 110:37] - node T_7410 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) @[rocket.scala 104:44] - node T_7411 = not(T_7410) @[rocket.scala 104:39] + ibuf.io.imem <- io.imem.resp + ibuf.io.kill <= take_pc + wire id_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>} + id_ctrl is invalid + node T_6680 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h207f")) + node T_6682 = eq(T_6680, UInt<32>("h3")) + node T_6684 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h106f")) + node T_6686 = eq(T_6684, UInt<32>("h3")) + node T_6688 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h607f")) + node T_6690 = eq(T_6688, UInt<32>("hf")) + node T_6692 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7077")) + node T_6694 = eq(T_6692, UInt<32>("h13")) + node T_6696 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h5f")) + node T_6698 = eq(T_6696, UInt<32>("h17")) + node T_6700 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfc00007f")) + node T_6702 = eq(T_6700, UInt<32>("h33")) + node T_6704 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hbe007077")) + node T_6706 = eq(T_6704, UInt<32>("h33")) + node T_6708 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4000073")) + node T_6710 = eq(T_6708, UInt<32>("h43")) + node T_6712 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("he400007f")) + node T_6714 = eq(T_6712, UInt<32>("h53")) + node T_6716 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h707b")) + node T_6718 = eq(T_6716, UInt<32>("h63")) + node T_6720 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7f")) + node T_6722 = eq(T_6720, UInt<32>("h6f")) + node T_6724 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hffefffff")) + node T_6726 = eq(T_6724, UInt<32>("h73")) + node T_6728 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfc00305f")) + node T_6730 = eq(T_6728, UInt<32>("h1013")) + node T_6732 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfe00305f")) + node T_6734 = eq(T_6732, UInt<32>("h101b")) + node T_6736 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h605b")) + node T_6738 = eq(T_6736, UInt<32>("h2003")) + node T_6740 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h207f")) + node T_6742 = eq(T_6740, UInt<32>("h2013")) + node T_6744 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h1800607f")) + node T_6746 = eq(T_6744, UInt<32>("h202f")) + node T_6748 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h207f")) + node T_6750 = eq(T_6748, UInt<32>("h2073")) + node T_6752 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hbc00707f")) + node T_6754 = eq(T_6752, UInt<32>("h5013")) + node T_6756 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hbe00705f")) + node T_6758 = eq(T_6756, UInt<32>("h501b")) + node T_6760 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hbe007077")) + node T_6762 = eq(T_6760, UInt<32>("h5033")) + node T_6764 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfe004077")) + node T_6766 = eq(T_6764, UInt<32>("h2004033")) + node T_6768 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("he800607f")) + node T_6770 = eq(T_6768, UInt<32>("h800202f")) + node T_6772 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hf9f0607f")) + node T_6774 = eq(T_6772, UInt<32>("h1000202f")) + node T_6776 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hdfffffff")) + node T_6778 = eq(T_6776, UInt<32>("h10200073")) + node T_6780 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfff07fff")) + node T_6782 = eq(T_6780, UInt<32>("h10400073")) + node T_6784 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10500073")) + node T_6786 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hf400607f")) + node T_6788 = eq(T_6786, UInt<32>("h20000053")) + node T_6790 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7c00607f")) + node T_6792 = eq(T_6790, UInt<32>("h20000053")) + node T_6794 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7c00507f")) + node T_6796 = eq(T_6794, UInt<32>("h20000053")) + node T_6798 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7ff0007f")) + node T_6800 = eq(T_6798, UInt<32>("h40100053")) + node T_6802 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7ff0007f")) + node T_6804 = eq(T_6802, UInt<32>("h42000053")) + node T_6806 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfdf0007f")) + node T_6808 = eq(T_6806, UInt<32>("h58000053")) + node T_6810 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7b200073")) + node T_6812 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hedc0007f")) + node T_6814 = eq(T_6812, UInt<32>("hc0000053")) + node T_6816 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfdf0607f")) + node T_6818 = eq(T_6816, UInt<32>("he0000053")) + node T_6820 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hedf0707f")) + node T_6822 = eq(T_6820, UInt<32>("he0000053")) + node T_6824 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h603f")) + node T_6826 = eq(T_6824, UInt<32>("h23")) + node T_6828 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h306f")) + node T_6830 = eq(T_6828, UInt<32>("h1063")) + node T_6832 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h407f")) + node T_6834 = eq(T_6832, UInt<32>("h4063")) + node T_6836 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hfc007077")) + node T_6838 = eq(T_6836, UInt<32>("h33")) + node T_6840 = or(UInt<1>("h0"), T_6682) + node T_6841 = or(T_6840, T_6686) + node T_6842 = or(T_6841, T_6690) + node T_6843 = or(T_6842, T_6694) + node T_6844 = or(T_6843, T_6698) + node T_6845 = or(T_6844, T_6702) + node T_6846 = or(T_6845, T_6706) + node T_6847 = or(T_6846, T_6710) + node T_6848 = or(T_6847, T_6714) + node T_6849 = or(T_6848, T_6718) + node T_6850 = or(T_6849, T_6722) + node T_6851 = or(T_6850, T_6726) + node T_6852 = or(T_6851, T_6730) + node T_6853 = or(T_6852, T_6734) + node T_6854 = or(T_6853, T_6738) + node T_6855 = or(T_6854, T_6742) + node T_6856 = or(T_6855, T_6746) + node T_6857 = or(T_6856, T_6750) + node T_6858 = or(T_6857, T_6754) + node T_6859 = or(T_6858, T_6758) + node T_6860 = or(T_6859, T_6762) + node T_6861 = or(T_6860, T_6766) + node T_6862 = or(T_6861, T_6770) + node T_6863 = or(T_6862, T_6774) + node T_6864 = or(T_6863, T_6778) + node T_6865 = or(T_6864, T_6782) + node T_6866 = or(T_6865, T_6784) + node T_6867 = or(T_6866, T_6788) + node T_6868 = or(T_6867, T_6792) + node T_6869 = or(T_6868, T_6796) + node T_6870 = or(T_6869, T_6800) + node T_6871 = or(T_6870, T_6804) + node T_6872 = or(T_6871, T_6808) + node T_6873 = or(T_6872, T_6810) + node T_6874 = or(T_6873, T_6814) + node T_6875 = or(T_6874, T_6818) + node T_6876 = or(T_6875, T_6822) + node T_6877 = or(T_6876, T_6826) + node T_6878 = or(T_6877, T_6830) + node T_6879 = or(T_6878, T_6834) + node T_6880 = or(T_6879, T_6838) + node T_6882 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h5c")) + node T_6884 = eq(T_6882, UInt<32>("h4")) + node T_6886 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h60")) + node T_6888 = eq(T_6886, UInt<32>("h40")) + node T_6890 = or(UInt<1>("h0"), T_6884) + node T_6891 = or(T_6890, T_6888) + node T_6894 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h74")) + node T_6896 = eq(T_6894, UInt<32>("h60")) + node T_6898 = or(UInt<1>("h0"), T_6896) + node T_6900 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h68")) + node T_6902 = eq(T_6900, UInt<32>("h68")) + node T_6904 = or(UInt<1>("h0"), T_6902) + node T_6906 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h203c")) + node T_6908 = eq(T_6906, UInt<32>("h24")) + node T_6910 = or(UInt<1>("h0"), T_6908) + node T_6912 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h64")) + node T_6914 = eq(T_6912, UInt<32>("h20")) + node T_6916 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h34")) + node T_6918 = eq(T_6916, UInt<32>("h20")) + node T_6920 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2048")) + node T_6922 = eq(T_6920, UInt<32>("h2008")) + node T_6924 = or(UInt<1>("h0"), T_6914) + node T_6925 = or(T_6924, T_6918) + node T_6926 = or(T_6925, T_6922) + node T_6928 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h44")) + node T_6930 = eq(T_6928, UInt<32>("h0")) + node T_6932 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4024")) + node T_6934 = eq(T_6932, UInt<32>("h20")) + node T_6936 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h38")) + node T_6938 = eq(T_6936, UInt<32>("h20")) + node T_6940 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2050")) + node T_6942 = eq(T_6940, UInt<32>("h2000")) + node T_6944 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h90000034")) + node T_6946 = eq(T_6944, UInt<32>("h90000010")) + node T_6948 = or(UInt<1>("h0"), T_6930) + node T_6949 = or(T_6948, T_6934) + node T_6950 = or(T_6949, T_6938) + node T_6951 = or(T_6950, T_6942) + node T_6952 = or(T_6951, T_6946) + node T_6954 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h58")) + node T_6956 = eq(T_6954, UInt<32>("h0")) + node T_6958 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h20")) + node T_6960 = eq(T_6958, UInt<32>("h0")) + node T_6962 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hc")) + node T_6964 = eq(T_6962, UInt<32>("h4")) + node T_6966 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h48")) + node T_6968 = eq(T_6966, UInt<32>("h48")) + node T_6970 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4050")) + node T_6972 = eq(T_6970, UInt<32>("h4050")) + node T_6974 = or(UInt<1>("h0"), T_6956) + node T_6975 = or(T_6974, T_6960) + node T_6976 = or(T_6975, T_6964) + node T_6977 = or(T_6976, T_6968) + node T_6978 = or(T_6977, T_6972) + node T_6980 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h48")) + node T_6982 = eq(T_6980, UInt<32>("h0")) + node T_6984 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h18")) + node T_6986 = eq(T_6984, UInt<32>("h0")) + node T_6988 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4008")) + node T_6990 = eq(T_6988, UInt<32>("h4000")) + node T_6992 = or(UInt<1>("h0"), T_6982) + node T_6993 = or(T_6992, T_6930) + node T_6994 = or(T_6993, T_6986) + node T_6995 = or(T_6994, T_6990) + node T_6996 = cat(T_6995, T_6978) + node T_6998 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4004")) + node T_7000 = eq(T_6998, UInt<32>("h0")) + node T_7002 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h50")) + node T_7004 = eq(T_7002, UInt<32>("h0")) + node T_7006 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h24")) + node T_7008 = eq(T_7006, UInt<32>("h0")) + node T_7010 = or(UInt<1>("h0"), T_7000) + node T_7011 = or(T_7010, T_7004) + node T_7012 = or(T_7011, T_6930) + node T_7013 = or(T_7012, T_7008) + node T_7014 = or(T_7013, T_6986) + node T_7016 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h34")) + node T_7018 = eq(T_7016, UInt<32>("h14")) + node T_7020 = or(UInt<1>("h0"), T_7018) + node T_7021 = or(T_7020, T_6968) + node T_7022 = cat(T_7021, T_7014) + node T_7024 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h18")) + node T_7026 = eq(T_7024, UInt<32>("h8")) + node T_7028 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h44")) + node T_7030 = eq(T_7028, UInt<32>("h40")) + node T_7032 = or(UInt<1>("h0"), T_7026) + node T_7033 = or(T_7032, T_7030) + node T_7035 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h14")) + node T_7037 = eq(T_7035, UInt<32>("h14")) + node T_7039 = or(UInt<1>("h0"), T_7026) + node T_7040 = or(T_7039, T_7037) + node T_7042 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h30")) + node T_7044 = eq(T_7042, UInt<32>("h0")) + node T_7046 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h201c")) + node T_7048 = eq(T_7046, UInt<32>("h4")) + node T_7050 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h14")) + node T_7052 = eq(T_7050, UInt<32>("h10")) + node T_7054 = or(UInt<1>("h0"), T_7044) + node T_7055 = or(T_7054, T_7048) + node T_7056 = or(T_7055, T_7052) + node T_7057 = cat(T_7056, T_7040) + node T_7058 = cat(T_7057, T_7033) + node T_7060 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10")) + node T_7062 = eq(T_7060, UInt<32>("h0")) + node T_7064 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h8")) + node T_7066 = eq(T_7064, UInt<32>("h0")) + node T_7068 = or(UInt<1>("h0"), T_7062) + node T_7069 = or(T_7068, T_7066) + node T_7071 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3054")) + node T_7073 = eq(T_7071, UInt<32>("h1010")) + node T_7075 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h1058")) + node T_7077 = eq(T_7075, UInt<32>("h1040")) + node T_7079 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7044")) + node T_7081 = eq(T_7079, UInt<32>("h7000")) + node T_7083 = or(UInt<1>("h0"), T_7073) + node T_7084 = or(T_7083, T_7077) + node T_7085 = or(T_7084, T_7081) + node T_7087 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4054")) + node T_7089 = eq(T_7087, UInt<32>("h40")) + node T_7091 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2058")) + node T_7093 = eq(T_7091, UInt<32>("h2040")) + node T_7095 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3054")) + node T_7097 = eq(T_7095, UInt<32>("h3010")) + node T_7099 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h6054")) + node T_7101 = eq(T_7099, UInt<32>("h6010")) + node T_7103 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40003034")) + node T_7105 = eq(T_7103, UInt<32>("h40000030")) + node T_7107 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40001054")) + node T_7109 = eq(T_7107, UInt<32>("h40001010")) + node T_7111 = or(UInt<1>("h0"), T_7089) + node T_7112 = or(T_7111, T_7093) + node T_7113 = or(T_7112, T_7097) + node T_7114 = or(T_7113, T_7101) + node T_7115 = or(T_7114, T_7105) + node T_7116 = or(T_7115, T_7109) + node T_7118 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2054")) + node T_7120 = eq(T_7118, UInt<32>("h2010")) + node T_7122 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40004054")) + node T_7124 = eq(T_7122, UInt<32>("h4010")) + node T_7126 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h5054")) + node T_7128 = eq(T_7126, UInt<32>("h4010")) + node T_7130 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4058")) + node T_7132 = eq(T_7130, UInt<32>("h4040")) + node T_7134 = or(UInt<1>("h0"), T_7120) + node T_7135 = or(T_7134, T_7124) + node T_7136 = or(T_7135, T_7128) + node T_7137 = or(T_7136, T_7132) + node T_7139 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h6054")) + node T_7141 = eq(T_7139, UInt<32>("h2010")) + node T_7143 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40003054")) + node T_7145 = eq(T_7143, UInt<32>("h40001010")) + node T_7147 = or(UInt<1>("h0"), T_7141) + node T_7148 = or(T_7147, T_7132) + node T_7149 = or(T_7148, T_7105) + node T_7150 = or(T_7149, T_7145) + node T_7151 = cat(T_7116, T_7085) + node T_7152 = cat(T_7150, T_7137) + node T_7153 = cat(T_7152, T_7151) + node T_7155 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h405f")) + node T_7157 = eq(T_7155, UInt<32>("h3")) + node T_7159 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h107f")) + node T_7161 = eq(T_7159, UInt<32>("h3")) + node T_7163 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h707f")) + node T_7165 = eq(T_7163, UInt<32>("h100f")) + node T_7167 = or(UInt<1>("h0"), T_7157) + node T_7168 = or(T_7167, T_6682) + node T_7169 = or(T_7168, T_7161) + node T_7170 = or(T_7169, T_7165) + node T_7171 = or(T_7170, T_6738) + node T_7172 = or(T_7171, T_6746) + node T_7173 = or(T_7172, T_6770) + node T_7174 = or(T_7173, T_6774) + node T_7176 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2008")) + node T_7178 = eq(T_7176, UInt<32>("h8")) + node T_7180 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h28")) + node T_7182 = eq(T_7180, UInt<32>("h20")) + node T_7184 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h18000020")) + node T_7186 = eq(T_7184, UInt<32>("h18000020")) + node T_7188 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h20000020")) + node T_7190 = eq(T_7188, UInt<32>("h20000020")) + node T_7192 = or(UInt<1>("h0"), T_7178) + node T_7193 = or(T_7192, T_7182) + node T_7194 = or(T_7193, T_7186) + node T_7195 = or(T_7194, T_7190) + node T_7197 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10002008")) + node T_7199 = eq(T_7197, UInt<32>("h10002008")) + node T_7201 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40002008")) + node T_7203 = eq(T_7201, UInt<32>("h40002008")) + node T_7205 = or(UInt<1>("h0"), T_7199) + node T_7206 = or(T_7205, T_7203) + node T_7208 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h8000008")) + node T_7210 = eq(T_7208, UInt<32>("h8000008")) + node T_7212 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10000008")) + node T_7214 = eq(T_7212, UInt<32>("h10000008")) + node T_7216 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h80000008")) + node T_7218 = eq(T_7216, UInt<32>("h80000008")) + node T_7220 = or(UInt<1>("h0"), T_7178) + node T_7221 = or(T_7220, T_7210) + node T_7222 = or(T_7221, T_7214) + node T_7223 = or(T_7222, T_7218) + node T_7225 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h18002008")) + node T_7227 = eq(T_7225, UInt<32>("h2008")) + node T_7229 = or(UInt<1>("h0"), T_7227) + node T_7231 = cat(T_7206, T_7195) + node T_7232 = cat(UInt<1>("h0"), T_7229) + node T_7233 = cat(T_7232, T_7223) + node T_7234 = cat(T_7233, T_7231) + node T_7236 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h1000")) + node T_7238 = eq(T_7236, UInt<32>("h1000")) + node T_7240 = or(UInt<1>("h0"), T_7238) + node T_7242 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2000")) + node T_7244 = eq(T_7242, UInt<32>("h2000")) + node T_7246 = or(UInt<1>("h0"), T_7244) + node T_7248 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h4000")) + node T_7250 = eq(T_7248, UInt<32>("h4000")) + node T_7252 = or(UInt<1>("h0"), T_7250) + node T_7253 = cat(T_7252, T_7246) + node T_7254 = cat(T_7253, T_7240) + node T_7256 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h80000060")) + node T_7258 = eq(T_7256, UInt<32>("h40")) + node T_7260 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10000060")) + node T_7262 = eq(T_7260, UInt<32>("h40")) + node T_7264 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h70")) + node T_7266 = eq(T_7264, UInt<32>("h40")) + node T_7268 = or(UInt<1>("h0"), T_7258) + node T_7269 = or(T_7268, T_7262) + node T_7270 = or(T_7269, T_7266) + node T_7272 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h7c")) + node T_7274 = eq(T_7272, UInt<32>("h24")) + node T_7276 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h40000060")) + node T_7278 = eq(T_7276, UInt<32>("h40")) + node T_7280 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h90000060")) + node T_7282 = eq(T_7280, UInt<32>("h10000040")) + node T_7284 = or(UInt<1>("h0"), T_7274) + node T_7285 = or(T_7284, T_7278) + node T_7286 = or(T_7285, T_7266) + node T_7287 = or(T_7286, T_7282) + node T_7289 = or(UInt<1>("h0"), T_7266) + node T_7291 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3c")) + node T_7293 = eq(T_7291, UInt<32>("h4")) + node T_7295 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h10000060")) + node T_7297 = eq(T_7295, UInt<32>("h10000040")) + node T_7299 = or(UInt<1>("h0"), T_7293) + node T_7300 = or(T_7299, T_7258) + node T_7301 = or(T_7300, T_7266) + node T_7302 = or(T_7301, T_7297) + node T_7304 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2000074")) + node T_7306 = eq(T_7304, UInt<32>("h2000030")) + node T_7308 = or(UInt<1>("h0"), T_7306) + node T_7310 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h64")) + node T_7312 = eq(T_7310, UInt<32>("h0")) + node T_7314 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h50")) + node T_7316 = eq(T_7314, UInt<32>("h10")) + node T_7318 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2024")) + node T_7320 = eq(T_7318, UInt<32>("h24")) + node T_7322 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h28")) + node T_7324 = eq(T_7322, UInt<32>("h28")) + node T_7326 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h1030")) + node T_7328 = eq(T_7326, UInt<32>("h1030")) + node T_7330 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2030")) + node T_7332 = eq(T_7330, UInt<32>("h2030")) + node T_7334 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h90000010")) + node T_7336 = eq(T_7334, UInt<32>("h80000010")) + node T_7338 = or(UInt<1>("h0"), T_7312) + node T_7339 = or(T_7338, T_7316) + node T_7340 = or(T_7339, T_7320) + node T_7341 = or(T_7340, T_7324) + node T_7342 = or(T_7341, T_7328) + node T_7343 = or(T_7342, T_7332) + node T_7344 = or(T_7343, T_7336) + node T_7346 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h1070")) + node T_7348 = eq(T_7346, UInt<32>("h1070")) + node T_7350 = or(UInt<1>("h0"), T_7348) + node T_7352 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2070")) + node T_7354 = eq(T_7352, UInt<32>("h2070")) + node T_7356 = or(UInt<1>("h0"), T_7354) + node T_7358 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3070")) + node T_7360 = eq(T_7358, UInt<32>("h70")) + node T_7362 = or(UInt<1>("h0"), T_7360) + node T_7363 = cat(T_7362, T_7356) + node T_7364 = cat(T_7363, T_7350) + node T_7366 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3058")) + node T_7368 = eq(T_7366, UInt<32>("h1008")) + node T_7370 = or(UInt<1>("h0"), T_7368) + node T_7372 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h3058")) + node T_7374 = eq(T_7372, UInt<32>("h8")) + node T_7376 = or(UInt<1>("h0"), T_7374) + node T_7378 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h6048")) + node T_7380 = eq(T_7378, UInt<32>("h2008")) + node T_7382 = or(UInt<1>("h0"), T_7380) + node T_7384 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h105c")) + node T_7386 = eq(T_7384, UInt<32>("h1004")) + node T_7388 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h2000060")) + node T_7390 = eq(T_7388, UInt<32>("h2000040")) + node T_7392 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("hd0000070")) + node T_7394 = eq(T_7392, UInt<32>("h40000050")) + node T_7396 = or(UInt<1>("h0"), T_7386) + node T_7397 = or(T_7396, T_7390) + node T_7398 = or(T_7397, T_7394) + id_ctrl.legal <= T_6880 + id_ctrl.fp <= T_6891 + id_ctrl.rocc <= UInt<1>("h0") + id_ctrl.branch <= T_6898 + id_ctrl.jal <= T_6904 + id_ctrl.jalr <= T_6910 + id_ctrl.rxs2 <= T_6926 + id_ctrl.rxs1 <= T_6952 + id_ctrl.sel_alu2 <= T_6996 + id_ctrl.sel_alu1 <= T_7022 + id_ctrl.sel_imm <= T_7058 + id_ctrl.alu_dw <= T_7069 + id_ctrl.alu_fn <= T_7153 + id_ctrl.mem <= T_7174 + id_ctrl.mem_cmd <= T_7234 + id_ctrl.mem_type <= T_7254 + id_ctrl.rfs1 <= T_7270 + id_ctrl.rfs2 <= T_7287 + id_ctrl.rfs3 <= T_7289 + id_ctrl.wfd <= T_7302 + id_ctrl.div <= T_7308 + id_ctrl.wxd <= T_7344 + id_ctrl.csr <= T_7364 + id_ctrl.fence_i <= T_7370 + id_ctrl.fence <= T_7376 + id_ctrl.amo <= T_7382 + id_ctrl.dp <= T_7398 + wire id_load_use : UInt<1> + id_load_use is invalid + reg id_reg_fence : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + cmem T_7403 : UInt<64> [31] + wire id_rs_0 : UInt + id_rs_0 is invalid + node T_7407 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h0")) + node T_7408 = and(UInt<1>("h0"), T_7407) + node T_7410 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) + node T_7411 = not(T_7410) infer mport T_7412 = T_7403[T_7411], clk - node T_7413 = mux(T_7408, UInt<1>("h00"), T_7412) @[rocket.scala 110:25] - id_rs_0 <= T_7413 @[rocket.scala 110:19] - wire id_rs_1 : UInt @[rocket.scala 109:26] - id_rs_1 is invalid @[rocket.scala 109:26] - node T_7417 = eq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[rocket.scala 110:45] - node T_7418 = and(UInt<1>("h00"), T_7417) @[rocket.scala 110:37] - node T_7420 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) @[rocket.scala 104:44] - node T_7421 = not(T_7420) @[rocket.scala 104:39] + node T_7413 = mux(T_7408, UInt<1>("h0"), T_7412) + id_rs_0 <= T_7413 + wire id_rs_1 : UInt + id_rs_1 is invalid + node T_7417 = eq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h0")) + node T_7418 = and(UInt<1>("h0"), T_7417) + node T_7420 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) + node T_7421 = not(T_7420) infer mport T_7422 = T_7403[T_7421], clk - node T_7423 = mux(T_7418, UInt<1>("h00"), T_7422) @[rocket.scala 110:25] - id_rs_1 <= T_7423 @[rocket.scala 110:19] - wire ctrl_killd : UInt<1> @[rocket.scala 233:24] - ctrl_killd is invalid @[rocket.scala 233:24] - node T_7425 = asSInt(ibuf.io.pc) @[rocket.scala 234:28] - node T_7426 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 125:24] - node T_7428 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) @[rocket.scala 125:48] - node T_7429 = asSInt(T_7428) @[rocket.scala 125:53] - node T_7430 = mux(T_7426, asSInt(UInt<1>("h00")), T_7429) @[rocket.scala 125:19] - node T_7431 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 126:26] - node T_7432 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) @[rocket.scala 126:41] - node T_7433 = asSInt(T_7432) @[rocket.scala 126:49] - node T_7434 = mux(T_7431, T_7433, T_7430) @[rocket.scala 126:21] - node T_7435 = neq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 127:26] - node T_7436 = neq(UInt<3>("h03"), UInt<3>("h03")) @[rocket.scala 127:43] - node T_7437 = and(T_7435, T_7436) @[rocket.scala 127:36] - node T_7438 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) @[rocket.scala 127:65] - node T_7439 = asSInt(T_7438) @[rocket.scala 127:73] - node T_7440 = mux(T_7437, T_7430, T_7439) @[rocket.scala 127:21] - node T_7441 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 128:23] - node T_7442 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 128:40] - node T_7443 = or(T_7441, T_7442) @[rocket.scala 128:33] - node T_7445 = eq(UInt<3>("h03"), UInt<3>("h03")) @[rocket.scala 129:23] - node T_7446 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[rocket.scala 129:39] - node T_7447 = asSInt(T_7446) @[rocket.scala 129:44] - node T_7448 = eq(UInt<3>("h03"), UInt<3>("h01")) @[rocket.scala 130:23] - node T_7449 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[rocket.scala 130:39] - node T_7450 = asSInt(T_7449) @[rocket.scala 130:43] - node T_7451 = mux(T_7448, T_7450, T_7430) @[rocket.scala 130:18] - node T_7452 = mux(T_7445, T_7447, T_7451) @[rocket.scala 129:18] - node T_7453 = mux(T_7443, asSInt(UInt<1>("h00")), T_7452) @[rocket.scala 128:18] - node T_7454 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 131:25] - node T_7455 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 131:42] - node T_7456 = or(T_7454, T_7455) @[rocket.scala 131:35] - node T_7458 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) @[rocket.scala 131:66] - node T_7459 = mux(T_7456, UInt<1>("h00"), T_7458) @[rocket.scala 131:20] - node T_7460 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 132:24] - node T_7462 = eq(UInt<3>("h03"), UInt<3>("h00")) @[rocket.scala 133:24] - node T_7463 = eq(UInt<3>("h03"), UInt<3>("h01")) @[rocket.scala 133:41] - node T_7464 = or(T_7462, T_7463) @[rocket.scala 133:34] - node T_7465 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) @[rocket.scala 133:57] - node T_7466 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 134:24] - node T_7467 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) @[rocket.scala 134:39] - node T_7468 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) @[rocket.scala 134:52] - node T_7469 = mux(T_7466, T_7467, T_7468) @[rocket.scala 134:19] - node T_7470 = mux(T_7464, T_7465, T_7469) @[rocket.scala 133:19] - node T_7471 = mux(T_7460, UInt<1>("h00"), T_7470) @[rocket.scala 132:19] - node T_7472 = eq(UInt<3>("h03"), UInt<3>("h00")) @[rocket.scala 135:22] - node T_7473 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[rocket.scala 135:37] - node T_7474 = eq(UInt<3>("h03"), UInt<3>("h04")) @[rocket.scala 136:22] - node T_7475 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[rocket.scala 136:37] - node T_7476 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 137:22] - node T_7477 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) @[rocket.scala 137:37] - node T_7479 = shl(T_7477, 0) @[rocket.scala 137:17] - node T_7480 = mux(T_7476, T_7479, UInt<1>("h00")) @[rocket.scala 137:17] - node T_7481 = shl(T_7475, 0) @[rocket.scala 136:17] - node T_7482 = mux(T_7474, T_7481, T_7480) @[rocket.scala 136:17] - node T_7483 = shl(T_7473, 0) @[rocket.scala 135:17] - node T_7484 = mux(T_7472, T_7483, T_7482) @[rocket.scala 135:17] - node T_7485 = cat(T_7459, T_7471) @[Cat.scala 20:58] - node T_7486 = cat(T_7485, T_7484) @[Cat.scala 20:58] - node T_7487 = asUInt(T_7453) @[Cat.scala 20:58] - node T_7488 = asUInt(T_7440) @[Cat.scala 20:58] - node T_7489 = cat(T_7488, T_7487) @[Cat.scala 20:58] - node T_7490 = asUInt(T_7434) @[Cat.scala 20:58] - node T_7491 = asUInt(T_7430) @[Cat.scala 20:58] - node T_7492 = cat(T_7491, T_7490) @[Cat.scala 20:58] - node T_7493 = cat(T_7492, T_7489) @[Cat.scala 20:58] - node T_7494 = cat(T_7493, T_7486) @[Cat.scala 20:58] - node T_7495 = asSInt(T_7494) @[rocket.scala 139:53] - node T_7496 = add(T_7425, T_7495) @[rocket.scala 234:35] - node T_7497 = tail(T_7496, 1) @[rocket.scala 234:35] - node T_7498 = asSInt(T_7497) @[rocket.scala 234:35] - node id_npc = asUInt(T_7498) @[rocket.scala 234:65] - node T_7501 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 235:34] - node T_7502 = and(UInt<1>("h00"), T_7501) @[rocket.scala 235:31] - node T_7503 = and(T_7502, id_ctrl.jal) @[rocket.scala 235:46] - take_pc_id <= T_7503 @[rocket.scala 235:14] - inst csr of CSRFile @[rocket.scala 237:19] + node T_7423 = mux(T_7418, UInt<1>("h0"), T_7422) + id_rs_1 <= T_7423 + wire ctrl_killd : UInt<1> + ctrl_killd is invalid + node T_7425 = asSInt(ibuf.io.pc) + node T_7426 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_7428 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) + node T_7429 = asSInt(T_7428) + node T_7430 = mux(T_7426, asSInt(UInt<1>("h0")), T_7429) + node T_7431 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_7432 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) + node T_7433 = asSInt(T_7432) + node T_7434 = mux(T_7431, T_7433, T_7430) + node T_7435 = neq(UInt<3>("h3"), UInt<3>("h2")) + node T_7436 = neq(UInt<3>("h3"), UInt<3>("h3")) + node T_7437 = and(T_7435, T_7436) + node T_7438 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) + node T_7439 = asSInt(T_7438) + node T_7440 = mux(T_7437, T_7430, T_7439) + node T_7441 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_7442 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_7443 = or(T_7441, T_7442) + node T_7445 = eq(UInt<3>("h3"), UInt<3>("h3")) + node T_7446 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) + node T_7447 = asSInt(T_7446) + node T_7448 = eq(UInt<3>("h3"), UInt<3>("h1")) + node T_7449 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) + node T_7450 = asSInt(T_7449) + node T_7451 = mux(T_7448, T_7450, T_7430) + node T_7452 = mux(T_7445, T_7447, T_7451) + node T_7453 = mux(T_7443, asSInt(UInt<1>("h0")), T_7452) + node T_7454 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_7455 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_7456 = or(T_7454, T_7455) + node T_7458 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) + node T_7459 = mux(T_7456, UInt<1>("h0"), T_7458) + node T_7460 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_7462 = eq(UInt<3>("h3"), UInt<3>("h0")) + node T_7463 = eq(UInt<3>("h3"), UInt<3>("h1")) + node T_7464 = or(T_7462, T_7463) + node T_7465 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) + node T_7466 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_7467 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) + node T_7468 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) + node T_7469 = mux(T_7466, T_7467, T_7468) + node T_7470 = mux(T_7464, T_7465, T_7469) + node T_7471 = mux(T_7460, UInt<1>("h0"), T_7470) + node T_7472 = eq(UInt<3>("h3"), UInt<3>("h0")) + node T_7473 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) + node T_7474 = eq(UInt<3>("h3"), UInt<3>("h4")) + node T_7475 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) + node T_7476 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_7477 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) + node T_7479 = shl(T_7477, 0) + node T_7480 = mux(T_7476, T_7479, UInt<1>("h0")) + node T_7481 = shl(T_7475, 0) + node T_7482 = mux(T_7474, T_7481, T_7480) + node T_7483 = shl(T_7473, 0) + node T_7484 = mux(T_7472, T_7483, T_7482) + node T_7485 = cat(T_7459, T_7471) + node T_7486 = cat(T_7485, T_7484) + node T_7487 = asUInt(T_7453) + node T_7488 = asUInt(T_7440) + node T_7489 = cat(T_7488, T_7487) + node T_7490 = asUInt(T_7434) + node T_7491 = asUInt(T_7430) + node T_7492 = cat(T_7491, T_7490) + node T_7493 = cat(T_7492, T_7489) + node T_7494 = cat(T_7493, T_7486) + node T_7495 = asSInt(T_7494) + node T_7496 = add(T_7425, T_7495) + node T_7497 = tail(T_7496, 1) + node T_7498 = asSInt(T_7497) + node id_npc = asUInt(T_7498) + node T_7501 = eq(ctrl_killd, UInt<1>("h0")) + node T_7502 = and(UInt<1>("h0"), T_7501) + node T_7503 = and(T_7502, id_ctrl.jal) + take_pc_id <= T_7503 + inst csr of CSRFile csr.io is invalid csr.clk <= clk csr.reset <= reset - node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) @[rocket.scala 238:31] - node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) @[rocket.scala 239:36] - node T_7504 = eq(id_ctrl.csr, UInt<3>("h02")) @[rocket.scala 240:33] - node T_7505 = eq(id_ctrl.csr, UInt<3>("h03")) @[rocket.scala 240:58] - node T_7506 = or(T_7504, T_7505) @[rocket.scala 240:43] - node T_7508 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[rocket.scala 240:82] - node id_csr_ren = and(T_7506, T_7508) @[rocket.scala 240:69] - node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) @[rocket.scala 241:19] - node id_csr_addr = bits(ibuf.io.inst[0].bits.inst.bits, 31, 20) @[rocket.scala 242:31] - node T_7510 = eq(id_csr_ren, UInt<1>("h00")) @[rocket.scala 246:54] - node T_7511 = and(id_csr_en, T_7510) @[rocket.scala 246:51] - node T_7641 = and(id_csr_addr, UInt<12>("h046")) @[decode.scala 13:65] - node T_7643 = eq(T_7641, UInt<12>("h040")) @[decode.scala 13:121] - node T_7645 = and(id_csr_addr, UInt<12>("h0244")) @[decode.scala 13:65] - node T_7647 = eq(T_7645, UInt<12>("h0240")) @[decode.scala 13:121] - node T_7649 = or(UInt<1>("h00"), T_7643) @[decode.scala 14:30] - node T_7650 = or(T_7649, T_7647) @[decode.scala 14:30] - node T_7651 = bits(T_7650, 0, 0) @[decode.scala 54:116] - node T_7653 = eq(T_7651, UInt<1>("h00")) @[rocket.scala 246:69] - node T_7654 = and(T_7511, T_7653) @[rocket.scala 246:66] - node id_csr_flush = or(id_system_insn, T_7654) @[rocket.scala 246:37] - node T_7656 = eq(id_ctrl.legal, UInt<1>("h00")) @[rocket.scala 248:25] - node T_7657 = bits(csr.io.status.isa, 12, 12) @[rocket.scala 249:38] - node T_7659 = eq(T_7657, UInt<1>("h00")) @[rocket.scala 249:20] - node T_7660 = and(id_ctrl.div, T_7659) @[rocket.scala 249:17] - node T_7661 = or(T_7656, T_7660) @[rocket.scala 248:40] - node T_7662 = bits(csr.io.status.isa, 0, 0) @[rocket.scala 250:38] - node T_7664 = eq(T_7662, UInt<1>("h00")) @[rocket.scala 250:20] - node T_7665 = and(id_ctrl.amo, T_7664) @[rocket.scala 250:17] - node T_7666 = or(T_7661, T_7665) @[rocket.scala 249:48] - node T_7668 = neq(csr.io.status.fs, UInt<1>("h00")) @[rocket.scala 251:38] - node T_7669 = bits(csr.io.status.isa, 5, 5) @[rocket.scala 251:62] - node T_7670 = and(T_7668, T_7669) @[rocket.scala 251:42] - node T_7672 = eq(T_7670, UInt<1>("h00")) @[rocket.scala 251:19] - node T_7673 = and(id_ctrl.fp, T_7672) @[rocket.scala 251:16] - node T_7674 = or(T_7666, T_7673) @[rocket.scala 250:48] - node T_7675 = bits(csr.io.status.isa, 3, 3) @[rocket.scala 252:37] - node T_7677 = eq(T_7675, UInt<1>("h00")) @[rocket.scala 252:19] - node T_7678 = and(id_ctrl.dp, T_7677) @[rocket.scala 252:16] - node T_7679 = or(T_7674, T_7678) @[rocket.scala 251:73] - node T_7680 = bits(csr.io.status.isa, 2, 2) @[rocket.scala 253:51] - node T_7682 = eq(T_7680, UInt<1>("h00")) @[rocket.scala 253:33] - node T_7683 = and(ibuf.io.inst[0].bits.rvc, T_7682) @[rocket.scala 253:30] - node T_7684 = or(T_7679, T_7683) @[rocket.scala 252:47] - node T_7686 = neq(csr.io.status.xs, UInt<1>("h00")) @[rocket.scala 254:40] - node T_7687 = bits(csr.io.status.isa, 23, 23) @[rocket.scala 254:64] - node T_7688 = and(T_7686, T_7687) @[rocket.scala 254:44] - node T_7690 = eq(T_7688, UInt<1>("h00")) @[rocket.scala 254:21] - node T_7691 = and(id_ctrl.rocc, T_7690) @[rocket.scala 254:18] - node id_illegal_insn = or(T_7684, T_7691) @[rocket.scala 253:61] - node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) @[rocket.scala 256:29] - node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) @[rocket.scala 257:29] - node T_7692 = and(id_ctrl.amo, id_amo_rl) @[rocket.scala 258:52] - node id_fence_next = or(id_ctrl.fence, T_7692) @[rocket.scala 258:37] - node T_7694 = eq(io.dmem.ordered, UInt<1>("h00")) @[rocket.scala 259:21] - node id_mem_busy = or(T_7694, io.dmem.req.valid) @[rocket.scala 259:38] - node T_7696 = and(ex_reg_valid, ex_ctrl.rocc) @[rocket.scala 261:35] - node T_7697 = or(io.rocc.busy, T_7696) @[rocket.scala 261:19] - node T_7698 = and(mem_reg_valid, mem_ctrl.rocc) @[rocket.scala 262:20] - node T_7699 = or(T_7697, T_7698) @[rocket.scala 261:51] - node T_7700 = and(wb_reg_valid, wb_ctrl.rocc) @[rocket.scala 262:53] - node T_7701 = or(T_7699, T_7700) @[rocket.scala 262:37] - node id_rocc_busy = and(UInt<1>("h00"), T_7701) @[rocket.scala 260:38] - node T_7702 = and(id_reg_fence, id_mem_busy) @[rocket.scala 263:49] - node T_7703 = or(id_fence_next, T_7702) @[rocket.scala 263:33] - id_reg_fence <= T_7703 @[rocket.scala 263:16] - node T_7704 = and(id_rocc_busy, id_ctrl.fence) @[rocket.scala 264:34] - node T_7705 = and(id_ctrl.amo, id_amo_aq) @[rocket.scala 265:33] - node T_7706 = or(T_7705, id_ctrl.fence_i) @[rocket.scala 265:46] - node T_7707 = or(id_ctrl.mem, id_ctrl.rocc) @[rocket.scala 265:97] - node T_7708 = and(id_reg_fence, T_7707) @[rocket.scala 265:81] - node T_7709 = or(T_7706, T_7708) @[rocket.scala 265:65] - node T_7710 = or(T_7709, id_csr_en) @[rocket.scala 265:114] - node T_7711 = and(id_mem_busy, T_7710) @[rocket.scala 265:17] - node id_do_fence = or(T_7704, T_7711) @[rocket.scala 264:51] - inst bpu of BreakpointUnit @[rocket.scala 267:19] + node id_csr_en = neq(id_ctrl.csr, UInt<3>("h0")) + node id_system_insn = eq(id_ctrl.csr, UInt<3>("h4")) + node T_7504 = eq(id_ctrl.csr, UInt<3>("h2")) + node T_7505 = eq(id_ctrl.csr, UInt<3>("h3")) + node T_7506 = or(T_7504, T_7505) + node T_7508 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h0")) + node id_csr_ren = and(T_7506, T_7508) + node id_csr = mux(id_csr_ren, UInt<3>("h5"), id_ctrl.csr) + node id_csr_addr = bits(ibuf.io.inst[0].bits.inst.bits, 31, 20) + node T_7510 = eq(id_csr_ren, UInt<1>("h0")) + node T_7511 = and(id_csr_en, T_7510) + node T_7641 = and(id_csr_addr, UInt<12>("h46")) + node T_7643 = eq(T_7641, UInt<12>("h40")) + node T_7645 = and(id_csr_addr, UInt<12>("h244")) + node T_7647 = eq(T_7645, UInt<12>("h240")) + node T_7649 = or(UInt<1>("h0"), T_7643) + node T_7650 = or(T_7649, T_7647) + node T_7651 = bits(T_7650, 0, 0) + node T_7653 = eq(T_7651, UInt<1>("h0")) + node T_7654 = and(T_7511, T_7653) + node id_csr_flush = or(id_system_insn, T_7654) + node T_7656 = eq(id_ctrl.legal, UInt<1>("h0")) + node T_7657 = bits(csr.io.status.isa, 12, 12) + node T_7659 = eq(T_7657, UInt<1>("h0")) + node T_7660 = and(id_ctrl.div, T_7659) + node T_7661 = or(T_7656, T_7660) + node T_7662 = bits(csr.io.status.isa, 0, 0) + node T_7664 = eq(T_7662, UInt<1>("h0")) + node T_7665 = and(id_ctrl.amo, T_7664) + node T_7666 = or(T_7661, T_7665) + node T_7668 = neq(csr.io.status.fs, UInt<1>("h0")) + node T_7669 = bits(csr.io.status.isa, 5, 5) + node T_7670 = and(T_7668, T_7669) + node T_7672 = eq(T_7670, UInt<1>("h0")) + node T_7673 = and(id_ctrl.fp, T_7672) + node T_7674 = or(T_7666, T_7673) + node T_7675 = bits(csr.io.status.isa, 3, 3) + node T_7677 = eq(T_7675, UInt<1>("h0")) + node T_7678 = and(id_ctrl.dp, T_7677) + node T_7679 = or(T_7674, T_7678) + node T_7680 = bits(csr.io.status.isa, 2, 2) + node T_7682 = eq(T_7680, UInt<1>("h0")) + node T_7683 = and(ibuf.io.inst[0].bits.rvc, T_7682) + node T_7684 = or(T_7679, T_7683) + node T_7686 = neq(csr.io.status.xs, UInt<1>("h0")) + node T_7687 = bits(csr.io.status.isa, 23, 23) + node T_7688 = and(T_7686, T_7687) + node T_7690 = eq(T_7688, UInt<1>("h0")) + node T_7691 = and(id_ctrl.rocc, T_7690) + node id_illegal_insn = or(T_7684, T_7691) + node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) + node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) + node T_7692 = and(id_ctrl.amo, id_amo_rl) + node id_fence_next = or(id_ctrl.fence, T_7692) + node T_7694 = eq(io.dmem.ordered, UInt<1>("h0")) + node id_mem_busy = or(T_7694, io.dmem.req.valid) + node T_7696 = and(ex_reg_valid, ex_ctrl.rocc) + node T_7697 = or(io.rocc.busy, T_7696) + node T_7698 = and(mem_reg_valid, mem_ctrl.rocc) + node T_7699 = or(T_7697, T_7698) + node T_7700 = and(wb_reg_valid, wb_ctrl.rocc) + node T_7701 = or(T_7699, T_7700) + node id_rocc_busy = and(UInt<1>("h0"), T_7701) + node T_7702 = and(id_reg_fence, id_mem_busy) + node T_7703 = or(id_fence_next, T_7702) + id_reg_fence <= T_7703 + node T_7704 = and(id_rocc_busy, id_ctrl.fence) + node T_7705 = and(id_ctrl.amo, id_amo_aq) + node T_7706 = or(T_7705, id_ctrl.fence_i) + node T_7707 = or(id_ctrl.mem, id_ctrl.rocc) + node T_7708 = and(id_reg_fence, T_7707) + node T_7709 = or(T_7706, T_7708) + node T_7710 = or(T_7709, id_csr_en) + node T_7711 = and(id_mem_busy, T_7710) + node id_do_fence = or(T_7704, T_7711) + inst bpu of BreakpointUnit bpu.io is invalid bpu.clk <= clk bpu.reset <= reset - bpu.io.status <- csr.io.status @[rocket.scala 268:17] - bpu.io.bp <= csr.io.bp @[rocket.scala 269:13] - bpu.io.pc <= ibuf.io.pc @[rocket.scala 270:13] - bpu.io.ea <= mem_reg_wdata @[rocket.scala 271:13] - node id_xcpt_if = or(ibuf.io.inst[0].bits.pf0, ibuf.io.inst[0].bits.pf1) @[rocket.scala 273:45] - node T_7716 = or(csr.io.interrupt, bpu.io.debug_if) @[rocket.scala 691:26] - node T_7717 = or(T_7716, bpu.io.xcpt_if) @[rocket.scala 691:26] - node T_7718 = or(T_7717, id_xcpt_if) @[rocket.scala 691:26] - node id_xcpt = or(T_7718, id_illegal_insn) @[rocket.scala 691:26] - node T_7719 = mux(id_xcpt_if, UInt<1>("h01"), UInt<2>("h02")) @[Mux.scala 31:69] - node T_7720 = mux(bpu.io.xcpt_if, UInt<2>("h03"), T_7719) @[Mux.scala 31:69] - node T_7721 = mux(bpu.io.debug_if, UInt<4>("h0d"), T_7720) @[Mux.scala 31:69] - node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_7721) @[Mux.scala 31:69] - node ex_waddr = bits(ex_reg_inst, 11, 7) @[rocket.scala 287:29] - node mem_waddr = bits(mem_reg_inst, 11, 7) @[rocket.scala 288:31] - node wb_waddr = bits(wb_reg_inst, 11, 7) @[rocket.scala 289:29] - node T_7725 = and(ex_reg_valid, ex_ctrl.wxd) @[rocket.scala 292:19] - node T_7726 = and(mem_reg_valid, mem_ctrl.wxd) @[rocket.scala 293:20] - node T_7728 = eq(mem_ctrl.mem, UInt<1>("h00")) @[rocket.scala 293:39] - node T_7729 = and(T_7726, T_7728) @[rocket.scala 293:36] - node T_7730 = and(mem_reg_valid, mem_ctrl.wxd) @[rocket.scala 294:20] - node T_7731 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 295:82] - node id_bypass_src_0_0 = and(UInt<1>("h01"), T_7731) @[rocket.scala 295:74] - node T_7732 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 295:82] - node id_bypass_src_0_1 = and(T_7725, T_7732) @[rocket.scala 295:74] - node T_7733 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 295:82] - node id_bypass_src_0_2 = and(T_7729, T_7733) @[rocket.scala 295:74] - node T_7734 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 295:82] - node id_bypass_src_0_3 = and(T_7730, T_7734) @[rocket.scala 295:74] - node T_7735 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 295:82] - node id_bypass_src_1_0 = and(UInt<1>("h01"), T_7735) @[rocket.scala 295:74] - node T_7736 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 295:82] - node id_bypass_src_1_1 = and(T_7725, T_7736) @[rocket.scala 295:74] - node T_7737 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 295:82] - node id_bypass_src_1_2 = and(T_7729, T_7737) @[rocket.scala 295:74] - node T_7738 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 295:82] - node id_bypass_src_1_3 = and(T_7730, T_7738) @[rocket.scala 295:74] - wire bypass_mux : UInt[4] @[rocket.scala 298:23] - bypass_mux is invalid @[rocket.scala 298:23] - bypass_mux[0] <= UInt<1>("h00") @[rocket.scala 298:23] - bypass_mux[1] <= mem_reg_wdata @[rocket.scala 298:23] - bypass_mux[2] <= wb_reg_wdata @[rocket.scala 298:23] - bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass @[rocket.scala 298:23] - reg ex_reg_rs_bypass : UInt<1>[2], clk - reg ex_reg_rs_lsb : UInt[2], clk - reg ex_reg_rs_msb : UInt[2], clk - node T_7766 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) @[Cat.scala 20:58] - node ex_rs_0 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_7766) @[rocket.scala 303:14] - node T_7767 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) @[Cat.scala 20:58] - node ex_rs_1 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_7767) @[rocket.scala 303:14] - node T_7768 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[rocket.scala 125:24] - node T_7770 = bits(ex_reg_inst, 31, 31) @[rocket.scala 125:48] - node T_7771 = asSInt(T_7770) @[rocket.scala 125:53] - node T_7772 = mux(T_7768, asSInt(UInt<1>("h00")), T_7771) @[rocket.scala 125:19] - node T_7773 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[rocket.scala 126:26] - node T_7774 = bits(ex_reg_inst, 30, 20) @[rocket.scala 126:41] - node T_7775 = asSInt(T_7774) @[rocket.scala 126:49] - node T_7776 = mux(T_7773, T_7775, T_7772) @[rocket.scala 126:21] - node T_7777 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) @[rocket.scala 127:26] - node T_7778 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) @[rocket.scala 127:43] - node T_7779 = and(T_7777, T_7778) @[rocket.scala 127:36] - node T_7780 = bits(ex_reg_inst, 19, 12) @[rocket.scala 127:65] - node T_7781 = asSInt(T_7780) @[rocket.scala 127:73] - node T_7782 = mux(T_7779, T_7772, T_7781) @[rocket.scala 127:21] - node T_7783 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[rocket.scala 128:23] - node T_7784 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[rocket.scala 128:40] - node T_7785 = or(T_7783, T_7784) @[rocket.scala 128:33] - node T_7787 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) @[rocket.scala 129:23] - node T_7788 = bits(ex_reg_inst, 20, 20) @[rocket.scala 129:39] - node T_7789 = asSInt(T_7788) @[rocket.scala 129:44] - node T_7790 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[rocket.scala 130:23] - node T_7791 = bits(ex_reg_inst, 7, 7) @[rocket.scala 130:39] - node T_7792 = asSInt(T_7791) @[rocket.scala 130:43] - node T_7793 = mux(T_7790, T_7792, T_7772) @[rocket.scala 130:18] - node T_7794 = mux(T_7787, T_7789, T_7793) @[rocket.scala 129:18] - node T_7795 = mux(T_7785, asSInt(UInt<1>("h00")), T_7794) @[rocket.scala 128:18] - node T_7796 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[rocket.scala 131:25] - node T_7797 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[rocket.scala 131:42] - node T_7798 = or(T_7796, T_7797) @[rocket.scala 131:35] - node T_7800 = bits(ex_reg_inst, 30, 25) @[rocket.scala 131:66] - node T_7801 = mux(T_7798, UInt<1>("h00"), T_7800) @[rocket.scala 131:20] - node T_7802 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[rocket.scala 132:24] - node T_7804 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[rocket.scala 133:24] - node T_7805 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[rocket.scala 133:41] - node T_7806 = or(T_7804, T_7805) @[rocket.scala 133:34] - node T_7807 = bits(ex_reg_inst, 11, 8) @[rocket.scala 133:57] - node T_7808 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[rocket.scala 134:24] - node T_7809 = bits(ex_reg_inst, 19, 16) @[rocket.scala 134:39] - node T_7810 = bits(ex_reg_inst, 24, 21) @[rocket.scala 134:52] - node T_7811 = mux(T_7808, T_7809, T_7810) @[rocket.scala 134:19] - node T_7812 = mux(T_7806, T_7807, T_7811) @[rocket.scala 133:19] - node T_7813 = mux(T_7802, UInt<1>("h00"), T_7812) @[rocket.scala 132:19] - node T_7814 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[rocket.scala 135:22] - node T_7815 = bits(ex_reg_inst, 7, 7) @[rocket.scala 135:37] - node T_7816 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) @[rocket.scala 136:22] - node T_7817 = bits(ex_reg_inst, 20, 20) @[rocket.scala 136:37] - node T_7818 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[rocket.scala 137:22] - node T_7819 = bits(ex_reg_inst, 15, 15) @[rocket.scala 137:37] - node T_7821 = shl(T_7819, 0) @[rocket.scala 137:17] - node T_7822 = mux(T_7818, T_7821, UInt<1>("h00")) @[rocket.scala 137:17] - node T_7823 = shl(T_7817, 0) @[rocket.scala 136:17] - node T_7824 = mux(T_7816, T_7823, T_7822) @[rocket.scala 136:17] - node T_7825 = shl(T_7815, 0) @[rocket.scala 135:17] - node T_7826 = mux(T_7814, T_7825, T_7824) @[rocket.scala 135:17] - node T_7827 = cat(T_7801, T_7813) @[Cat.scala 20:58] - node T_7828 = cat(T_7827, T_7826) @[Cat.scala 20:58] - node T_7829 = asUInt(T_7795) @[Cat.scala 20:58] - node T_7830 = asUInt(T_7782) @[Cat.scala 20:58] - node T_7831 = cat(T_7830, T_7829) @[Cat.scala 20:58] - node T_7832 = asUInt(T_7776) @[Cat.scala 20:58] - node T_7833 = asUInt(T_7772) @[Cat.scala 20:58] - node T_7834 = cat(T_7833, T_7832) @[Cat.scala 20:58] - node T_7835 = cat(T_7834, T_7831) @[Cat.scala 20:58] - node T_7836 = cat(T_7835, T_7828) @[Cat.scala 20:58] - node ex_imm = asSInt(T_7836) @[rocket.scala 139:53] - node T_7838 = asSInt(ex_rs_0) @[rocket.scala 306:24] - node T_7839 = asSInt(ex_reg_pc) @[rocket.scala 307:24] - node T_7840 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] - node T_7841 = mux(T_7840, T_7839, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] - node T_7842 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] - node ex_op1 = mux(T_7842, T_7838, T_7841) @[Mux.scala 46:16] - node T_7844 = asSInt(ex_rs_1) @[rocket.scala 309:24] - node T_7847 = mux(ex_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[rocket.scala 311:19] - node T_7848 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] - node T_7849 = mux(T_7848, T_7847, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] - node T_7850 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] - node T_7851 = mux(T_7850, ex_imm, T_7849) @[Mux.scala 46:16] - node T_7852 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] - node ex_op2 = mux(T_7852, T_7844, T_7851) @[Mux.scala 46:16] - inst alu of ALU @[rocket.scala 313:19] + bpu.io.status <- csr.io.status + bpu.io.bp <= csr.io.bp + bpu.io.pc <= ibuf.io.pc + bpu.io.ea <= mem_reg_wdata + node id_xcpt_if = or(ibuf.io.inst[0].bits.pf0, ibuf.io.inst[0].bits.pf1) + node T_7716 = or(csr.io.interrupt, bpu.io.debug_if) + node T_7717 = or(T_7716, bpu.io.xcpt_if) + node T_7718 = or(T_7717, id_xcpt_if) + node id_xcpt = or(T_7718, id_illegal_insn) + node T_7719 = mux(id_xcpt_if, UInt<1>("h1"), UInt<2>("h2")) + node T_7720 = mux(bpu.io.xcpt_if, UInt<2>("h3"), T_7719) + node T_7721 = mux(bpu.io.debug_if, UInt<4>("hd"), T_7720) + node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_7721) + node ex_waddr = bits(ex_reg_inst, 11, 7) + node mem_waddr = bits(mem_reg_inst, 11, 7) + node wb_waddr = bits(wb_reg_inst, 11, 7) + node T_7725 = and(ex_reg_valid, ex_ctrl.wxd) + node T_7726 = and(mem_reg_valid, mem_ctrl.wxd) + node T_7728 = eq(mem_ctrl.mem, UInt<1>("h0")) + node T_7729 = and(T_7726, T_7728) + node T_7730 = and(mem_reg_valid, mem_ctrl.wxd) + node T_7731 = eq(UInt<1>("h0"), ibuf.io.inst[0].bits.inst.rs1) + node id_bypass_src_0_0 = and(UInt<1>("h1"), T_7731) + node T_7732 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs1) + node id_bypass_src_0_1 = and(T_7725, T_7732) + node T_7733 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) + node id_bypass_src_0_2 = and(T_7729, T_7733) + node T_7734 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) + node id_bypass_src_0_3 = and(T_7730, T_7734) + node T_7735 = eq(UInt<1>("h0"), ibuf.io.inst[0].bits.inst.rs2) + node id_bypass_src_1_0 = and(UInt<1>("h1"), T_7735) + node T_7736 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs2) + node id_bypass_src_1_1 = and(T_7725, T_7736) + node T_7737 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) + node id_bypass_src_1_2 = and(T_7729, T_7737) + node T_7738 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) + node id_bypass_src_1_3 = and(T_7730, T_7738) + wire bypass_mux : UInt[4] + bypass_mux is invalid + bypass_mux[0] <= UInt<1>("h0") + bypass_mux[1] <= mem_reg_wdata + bypass_mux[2] <= wb_reg_wdata + bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass + reg ex_reg_rs_bypass : UInt<1>[2], clk with : + reset => (UInt<1>("h0"), ex_reg_rs_bypass) + reg ex_reg_rs_lsb : UInt[2], clk with : + reset => (UInt<1>("h0"), ex_reg_rs_lsb) + reg ex_reg_rs_msb : UInt[2], clk with : + reset => (UInt<1>("h0"), ex_reg_rs_msb) + node T_7766 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) + node ex_rs_0 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_7766) + node T_7767 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) + node ex_rs_1 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_7767) + node T_7768 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) + node T_7770 = bits(ex_reg_inst, 31, 31) + node T_7771 = asSInt(T_7770) + node T_7772 = mux(T_7768, asSInt(UInt<1>("h0")), T_7771) + node T_7773 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) + node T_7774 = bits(ex_reg_inst, 30, 20) + node T_7775 = asSInt(T_7774) + node T_7776 = mux(T_7773, T_7775, T_7772) + node T_7777 = neq(ex_ctrl.sel_imm, UInt<3>("h2")) + node T_7778 = neq(ex_ctrl.sel_imm, UInt<3>("h3")) + node T_7779 = and(T_7777, T_7778) + node T_7780 = bits(ex_reg_inst, 19, 12) + node T_7781 = asSInt(T_7780) + node T_7782 = mux(T_7779, T_7772, T_7781) + node T_7783 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) + node T_7784 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) + node T_7785 = or(T_7783, T_7784) + node T_7787 = eq(ex_ctrl.sel_imm, UInt<3>("h3")) + node T_7788 = bits(ex_reg_inst, 20, 20) + node T_7789 = asSInt(T_7788) + node T_7790 = eq(ex_ctrl.sel_imm, UInt<3>("h1")) + node T_7791 = bits(ex_reg_inst, 7, 7) + node T_7792 = asSInt(T_7791) + node T_7793 = mux(T_7790, T_7792, T_7772) + node T_7794 = mux(T_7787, T_7789, T_7793) + node T_7795 = mux(T_7785, asSInt(UInt<1>("h0")), T_7794) + node T_7796 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) + node T_7797 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) + node T_7798 = or(T_7796, T_7797) + node T_7800 = bits(ex_reg_inst, 30, 25) + node T_7801 = mux(T_7798, UInt<1>("h0"), T_7800) + node T_7802 = eq(ex_ctrl.sel_imm, UInt<3>("h2")) + node T_7804 = eq(ex_ctrl.sel_imm, UInt<3>("h0")) + node T_7805 = eq(ex_ctrl.sel_imm, UInt<3>("h1")) + node T_7806 = or(T_7804, T_7805) + node T_7807 = bits(ex_reg_inst, 11, 8) + node T_7808 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) + node T_7809 = bits(ex_reg_inst, 19, 16) + node T_7810 = bits(ex_reg_inst, 24, 21) + node T_7811 = mux(T_7808, T_7809, T_7810) + node T_7812 = mux(T_7806, T_7807, T_7811) + node T_7813 = mux(T_7802, UInt<1>("h0"), T_7812) + node T_7814 = eq(ex_ctrl.sel_imm, UInt<3>("h0")) + node T_7815 = bits(ex_reg_inst, 7, 7) + node T_7816 = eq(ex_ctrl.sel_imm, UInt<3>("h4")) + node T_7817 = bits(ex_reg_inst, 20, 20) + node T_7818 = eq(ex_ctrl.sel_imm, UInt<3>("h5")) + node T_7819 = bits(ex_reg_inst, 15, 15) + node T_7821 = shl(T_7819, 0) + node T_7822 = mux(T_7818, T_7821, UInt<1>("h0")) + node T_7823 = shl(T_7817, 0) + node T_7824 = mux(T_7816, T_7823, T_7822) + node T_7825 = shl(T_7815, 0) + node T_7826 = mux(T_7814, T_7825, T_7824) + node T_7827 = cat(T_7801, T_7813) + node T_7828 = cat(T_7827, T_7826) + node T_7829 = asUInt(T_7795) + node T_7830 = asUInt(T_7782) + node T_7831 = cat(T_7830, T_7829) + node T_7832 = asUInt(T_7776) + node T_7833 = asUInt(T_7772) + node T_7834 = cat(T_7833, T_7832) + node T_7835 = cat(T_7834, T_7831) + node T_7836 = cat(T_7835, T_7828) + node ex_imm = asSInt(T_7836) + node T_7838 = asSInt(ex_rs_0) + node T_7839 = asSInt(ex_reg_pc) + node T_7840 = eq(UInt<2>("h2"), ex_ctrl.sel_alu1) + node T_7841 = mux(T_7840, T_7839, asSInt(UInt<1>("h0"))) + node T_7842 = eq(UInt<2>("h1"), ex_ctrl.sel_alu1) + node ex_op1 = mux(T_7842, T_7838, T_7841) + node T_7844 = asSInt(ex_rs_1) + node T_7847 = mux(ex_reg_rvc, asSInt(UInt<3>("h2")), asSInt(UInt<4>("h4"))) + node T_7848 = eq(UInt<2>("h1"), ex_ctrl.sel_alu2) + node T_7849 = mux(T_7848, T_7847, asSInt(UInt<1>("h0"))) + node T_7850 = eq(UInt<2>("h3"), ex_ctrl.sel_alu2) + node T_7851 = mux(T_7850, ex_imm, T_7849) + node T_7852 = eq(UInt<2>("h2"), ex_ctrl.sel_alu2) + node ex_op2 = mux(T_7852, T_7844, T_7851) + inst alu of ALU alu.io is invalid alu.clk <= clk alu.reset <= reset - alu.io.dw <= ex_ctrl.alu_dw @[rocket.scala 314:13] - alu.io.fn <= ex_ctrl.alu_fn @[rocket.scala 315:13] - node T_7853 = asUInt(ex_op2) @[rocket.scala 316:24] - alu.io.in2 <= T_7853 @[rocket.scala 316:14] - node T_7854 = asUInt(ex_op1) @[rocket.scala 317:24] - alu.io.in1 <= T_7854 @[rocket.scala 317:14] - inst div of MulDiv @[rocket.scala 320:19] + alu.io.dw <= ex_ctrl.alu_dw + alu.io.fn <= ex_ctrl.alu_fn + node T_7853 = asUInt(ex_op2) + alu.io.in2 <= T_7853 + node T_7854 = asUInt(ex_op1) + alu.io.in1 <= T_7854 + inst div of MulDiv div.io is invalid div.clk <= clk div.reset <= reset - node T_7855 = and(ex_reg_valid, ex_ctrl.div) @[rocket.scala 321:36] - div.io.req.valid <= T_7855 @[rocket.scala 321:20] - div.io.req.bits.dw <= ex_ctrl.alu_dw @[rocket.scala 322:22] - div.io.req.bits.fn <= ex_ctrl.alu_fn @[rocket.scala 323:22] - div.io.req.bits.in1 <= ex_rs_0 @[rocket.scala 324:23] - div.io.req.bits.in2 <= ex_rs_1 @[rocket.scala 325:23] - div.io.req.bits.tag <= ex_waddr @[rocket.scala 326:23] - node T_7857 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 328:19] - ex_reg_valid <= T_7857 @[rocket.scala 328:16] - node T_7859 = eq(take_pc, UInt<1>("h00")) @[rocket.scala 329:20] - node T_7860 = and(T_7859, ibuf.io.inst[0].valid) @[rocket.scala 329:29] - node T_7861 = and(T_7860, ibuf.io.inst[0].bits.replay) @[rocket.scala 329:54] - ex_reg_replay <= T_7861 @[rocket.scala 329:17] - node T_7863 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 330:18] - node T_7864 = and(T_7863, id_xcpt) @[rocket.scala 330:30] - ex_reg_xcpt <= T_7864 @[rocket.scala 330:15] - node T_7866 = eq(take_pc, UInt<1>("h00")) @[rocket.scala 331:28] - node T_7867 = and(T_7866, ibuf.io.inst[0].valid) @[rocket.scala 331:37] - node T_7868 = and(T_7867, csr.io.interrupt) @[rocket.scala 331:62] - ex_reg_xcpt_interrupt <= T_7868 @[rocket.scala 331:25] - when id_xcpt : @[rocket.scala 332:18] - ex_reg_cause <= id_cause @[rocket.scala 332:33] - skip @[rocket.scala 332:18] - ex_reg_btb_hit <= ibuf.io.inst[0].bits.btb_hit @[rocket.scala 333:18] - when ibuf.io.inst[0].bits.btb_hit : @[rocket.scala 334:39] - ex_reg_btb_resp <- ibuf.io.btb_resp @[rocket.scala 334:57] - skip @[rocket.scala 334:39] - node T_7870 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 336:9] - when T_7870 : @[rocket.scala 336:22] - ex_ctrl <- id_ctrl @[rocket.scala 337:13] - ex_reg_rvc <= ibuf.io.inst[0].bits.rvc @[rocket.scala 338:16] - ex_ctrl.csr <= id_csr @[rocket.scala 339:17] - when id_xcpt : @[rocket.scala 340:20] - ex_ctrl.alu_fn <= UInt<1>("h00") @[rocket.scala 341:22] - ex_ctrl.alu_dw <= UInt<1>("h01") @[rocket.scala 342:22] - ex_ctrl.sel_alu1 <= UInt<2>("h02") @[rocket.scala 343:24] - ex_ctrl.sel_alu2 <= UInt<2>("h00") @[rocket.scala 344:24] - node T_7872 = eq(bpu.io.xcpt_if, UInt<1>("h00")) @[rocket.scala 345:13] - node T_7874 = eq(ibuf.io.inst[0].bits.pf0, UInt<1>("h00")) @[rocket.scala 345:32] - node T_7875 = and(T_7872, T_7874) @[rocket.scala 345:29] - node T_7876 = and(T_7875, ibuf.io.inst[0].bits.pf1) @[rocket.scala 345:58] - when T_7876 : @[rocket.scala 345:87] - ex_ctrl.sel_alu2 <= UInt<2>("h01") @[rocket.scala 346:26] - ex_reg_rvc <= UInt<1>("h01") @[rocket.scala 347:20] - skip @[rocket.scala 345:87] - skip @[rocket.scala 340:20] - node T_7878 = or(id_ctrl.fence_i, id_csr_flush) @[rocket.scala 350:42] - node T_7879 = or(T_7878, csr.io.singleStep) @[rocket.scala 350:58] - ex_reg_flush_pipe <= T_7879 @[rocket.scala 350:23] - ex_reg_load_use <= id_load_use @[rocket.scala 351:21] - node T_7880 = and(id_ctrl.jalr, csr.io.status.debug) @[rocket.scala 353:24] - when T_7880 : @[rocket.scala 353:48] - ex_reg_flush_pipe <= UInt<1>("h01") @[rocket.scala 354:25] - ex_ctrl.fence_i <= UInt<1>("h01") @[rocket.scala 355:23] - skip @[rocket.scala 353:48] - node T_7883 = or(id_bypass_src_0_0, id_bypass_src_0_1) @[rocket.scala 359:48] - node T_7884 = or(T_7883, id_bypass_src_0_2) @[rocket.scala 359:48] - node T_7885 = or(T_7884, id_bypass_src_0_3) @[rocket.scala 359:48] - node T_7890 = mux(id_bypass_src_0_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] - node T_7891 = mux(id_bypass_src_0_1, UInt<1>("h01"), T_7890) @[Mux.scala 31:69] - node T_7892 = mux(id_bypass_src_0_0, UInt<1>("h00"), T_7891) @[Mux.scala 31:69] - ex_reg_rs_bypass[0] <= T_7885 @[rocket.scala 361:27] - ex_reg_rs_lsb[0] <= T_7892 @[rocket.scala 362:24] - node T_7894 = eq(T_7885, UInt<1>("h00")) @[rocket.scala 363:26] - node T_7895 = and(id_ctrl.rxs1, T_7894) @[rocket.scala 363:23] - when T_7895 : @[rocket.scala 363:38] - node T_7896 = bits(id_rs_0, 1, 0) @[rocket.scala 364:37] - ex_reg_rs_lsb[0] <= T_7896 @[rocket.scala 364:26] - node T_7897 = shr(id_rs_0, 2) @[rocket.scala 365:38] - ex_reg_rs_msb[0] <= T_7897 @[rocket.scala 365:26] - skip @[rocket.scala 363:38] - node T_7898 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[rocket.scala 359:48] - node T_7899 = or(T_7898, id_bypass_src_1_2) @[rocket.scala 359:48] - node T_7900 = or(T_7899, id_bypass_src_1_3) @[rocket.scala 359:48] - node T_7905 = mux(id_bypass_src_1_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] - node T_7906 = mux(id_bypass_src_1_1, UInt<1>("h01"), T_7905) @[Mux.scala 31:69] - node T_7907 = mux(id_bypass_src_1_0, UInt<1>("h00"), T_7906) @[Mux.scala 31:69] - ex_reg_rs_bypass[1] <= T_7900 @[rocket.scala 361:27] - ex_reg_rs_lsb[1] <= T_7907 @[rocket.scala 362:24] - node T_7909 = eq(T_7900, UInt<1>("h00")) @[rocket.scala 363:26] - node T_7910 = and(id_ctrl.rxs2, T_7909) @[rocket.scala 363:23] - when T_7910 : @[rocket.scala 363:38] - node T_7911 = bits(id_rs_1, 1, 0) @[rocket.scala 364:37] - ex_reg_rs_lsb[1] <= T_7911 @[rocket.scala 364:26] - node T_7912 = shr(id_rs_1, 2) @[rocket.scala 365:38] - ex_reg_rs_msb[1] <= T_7912 @[rocket.scala 365:26] - skip @[rocket.scala 363:38] - skip @[rocket.scala 336:22] - node T_7914 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 369:9] - node T_7915 = or(T_7914, csr.io.interrupt) @[rocket.scala 369:21] - node T_7916 = or(T_7915, ibuf.io.inst[0].bits.replay) @[rocket.scala 369:41] - when T_7916 : @[rocket.scala 369:73] - ex_reg_inst <= ibuf.io.inst[0].bits.inst.bits @[rocket.scala 370:17] - ex_reg_pc <= ibuf.io.pc @[rocket.scala 371:15] - skip @[rocket.scala 369:73] - node T_7917 = or(ex_reg_valid, ex_reg_replay) @[rocket.scala 375:34] - node ex_pc_valid = or(T_7917, ex_reg_xcpt_interrupt) @[rocket.scala 375:51] - node T_7919 = eq(io.dmem.resp.valid, UInt<1>("h00")) @[rocket.scala 376:39] - node wb_dcache_miss = and(wb_ctrl.mem, T_7919) @[rocket.scala 376:36] - node T_7921 = eq(io.dmem.req.ready, UInt<1>("h00")) @[rocket.scala 377:45] - node T_7922 = and(ex_ctrl.mem, T_7921) @[rocket.scala 377:42] - node T_7924 = eq(div.io.req.ready, UInt<1>("h00")) @[rocket.scala 378:45] - node T_7925 = and(ex_ctrl.div, T_7924) @[rocket.scala 378:42] - node replay_ex_structural = or(T_7922, T_7925) @[rocket.scala 377:64] - node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[rocket.scala 379:43] - node T_7926 = or(replay_ex_structural, replay_ex_load_use) @[rocket.scala 380:75] - node T_7927 = and(ex_reg_valid, T_7926) @[rocket.scala 380:50] - node replay_ex = or(ex_reg_replay, T_7927) @[rocket.scala 380:33] - node T_7928 = or(take_pc_mem_wb, replay_ex) @[rocket.scala 381:35] - node T_7930 = eq(ex_reg_valid, UInt<1>("h00")) @[rocket.scala 381:51] - node ctrl_killx = or(T_7928, T_7930) @[rocket.scala 381:48] - node T_7931 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) @[rocket.scala 383:40] - wire T_7937 : UInt<3>[4] @[rocket.scala 383:56] - T_7937 is invalid @[rocket.scala 383:56] - T_7937[0] <= UInt<3>("h00") @[rocket.scala 383:56] - T_7937[1] <= UInt<3>("h04") @[rocket.scala 383:56] - T_7937[2] <= UInt<3>("h01") @[rocket.scala 383:56] - T_7937[3] <= UInt<3>("h05") @[rocket.scala 383:56] - node T_7939 = eq(T_7937[0], ex_ctrl.mem_type) @[rocket.scala 383:91] - node T_7940 = eq(T_7937[1], ex_ctrl.mem_type) @[rocket.scala 383:91] - node T_7941 = eq(T_7937[2], ex_ctrl.mem_type) @[rocket.scala 383:91] - node T_7942 = eq(T_7937[3], ex_ctrl.mem_type) @[rocket.scala 383:91] - node T_7944 = or(UInt<1>("h00"), T_7939) @[rocket.scala 383:91] - node T_7945 = or(T_7944, T_7940) @[rocket.scala 383:91] - node T_7946 = or(T_7945, T_7941) @[rocket.scala 383:91] - node T_7947 = or(T_7946, T_7942) @[rocket.scala 383:91] - node ex_slow_bypass = or(T_7931, T_7947) @[rocket.scala 383:50] - node T_7948 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[rocket.scala 386:28] - node T_7949 = and(ex_ctrl.fp, io.fpu.illegal_rm) @[rocket.scala 387:17] - node ex_xcpt = or(T_7948, T_7949) @[rocket.scala 691:26] - node ex_cause = mux(T_7948, ex_reg_cause, UInt<2>("h02")) @[Mux.scala 31:69] - node mem_br_taken = bits(mem_reg_wdata, 0, 0) @[rocket.scala 390:35] - node T_7951 = asSInt(mem_reg_pc) @[rocket.scala 391:34] - node T_7952 = and(mem_ctrl.branch, mem_br_taken) @[rocket.scala 392:25] - node T_7953 = eq(UInt<3>("h01"), UInt<3>("h05")) @[rocket.scala 125:24] - node T_7955 = bits(mem_reg_inst, 31, 31) @[rocket.scala 125:48] - node T_7956 = asSInt(T_7955) @[rocket.scala 125:53] - node T_7957 = mux(T_7953, asSInt(UInt<1>("h00")), T_7956) @[rocket.scala 125:19] - node T_7958 = eq(UInt<3>("h01"), UInt<3>("h02")) @[rocket.scala 126:26] - node T_7959 = bits(mem_reg_inst, 30, 20) @[rocket.scala 126:41] - node T_7960 = asSInt(T_7959) @[rocket.scala 126:49] - node T_7961 = mux(T_7958, T_7960, T_7957) @[rocket.scala 126:21] - node T_7962 = neq(UInt<3>("h01"), UInt<3>("h02")) @[rocket.scala 127:26] - node T_7963 = neq(UInt<3>("h01"), UInt<3>("h03")) @[rocket.scala 127:43] - node T_7964 = and(T_7962, T_7963) @[rocket.scala 127:36] - node T_7965 = bits(mem_reg_inst, 19, 12) @[rocket.scala 127:65] - node T_7966 = asSInt(T_7965) @[rocket.scala 127:73] - node T_7967 = mux(T_7964, T_7957, T_7966) @[rocket.scala 127:21] - node T_7968 = eq(UInt<3>("h01"), UInt<3>("h02")) @[rocket.scala 128:23] - node T_7969 = eq(UInt<3>("h01"), UInt<3>("h05")) @[rocket.scala 128:40] - node T_7970 = or(T_7968, T_7969) @[rocket.scala 128:33] - node T_7972 = eq(UInt<3>("h01"), UInt<3>("h03")) @[rocket.scala 129:23] - node T_7973 = bits(mem_reg_inst, 20, 20) @[rocket.scala 129:39] - node T_7974 = asSInt(T_7973) @[rocket.scala 129:44] - node T_7975 = eq(UInt<3>("h01"), UInt<3>("h01")) @[rocket.scala 130:23] - node T_7976 = bits(mem_reg_inst, 7, 7) @[rocket.scala 130:39] - node T_7977 = asSInt(T_7976) @[rocket.scala 130:43] - node T_7978 = mux(T_7975, T_7977, T_7957) @[rocket.scala 130:18] - node T_7979 = mux(T_7972, T_7974, T_7978) @[rocket.scala 129:18] - node T_7980 = mux(T_7970, asSInt(UInt<1>("h00")), T_7979) @[rocket.scala 128:18] - node T_7981 = eq(UInt<3>("h01"), UInt<3>("h02")) @[rocket.scala 131:25] - node T_7982 = eq(UInt<3>("h01"), UInt<3>("h05")) @[rocket.scala 131:42] - node T_7983 = or(T_7981, T_7982) @[rocket.scala 131:35] - node T_7985 = bits(mem_reg_inst, 30, 25) @[rocket.scala 131:66] - node T_7986 = mux(T_7983, UInt<1>("h00"), T_7985) @[rocket.scala 131:20] - node T_7987 = eq(UInt<3>("h01"), UInt<3>("h02")) @[rocket.scala 132:24] - node T_7989 = eq(UInt<3>("h01"), UInt<3>("h00")) @[rocket.scala 133:24] - node T_7990 = eq(UInt<3>("h01"), UInt<3>("h01")) @[rocket.scala 133:41] - node T_7991 = or(T_7989, T_7990) @[rocket.scala 133:34] - node T_7992 = bits(mem_reg_inst, 11, 8) @[rocket.scala 133:57] - node T_7993 = eq(UInt<3>("h01"), UInt<3>("h05")) @[rocket.scala 134:24] - node T_7994 = bits(mem_reg_inst, 19, 16) @[rocket.scala 134:39] - node T_7995 = bits(mem_reg_inst, 24, 21) @[rocket.scala 134:52] - node T_7996 = mux(T_7993, T_7994, T_7995) @[rocket.scala 134:19] - node T_7997 = mux(T_7991, T_7992, T_7996) @[rocket.scala 133:19] - node T_7998 = mux(T_7987, UInt<1>("h00"), T_7997) @[rocket.scala 132:19] - node T_7999 = eq(UInt<3>("h01"), UInt<3>("h00")) @[rocket.scala 135:22] - node T_8000 = bits(mem_reg_inst, 7, 7) @[rocket.scala 135:37] - node T_8001 = eq(UInt<3>("h01"), UInt<3>("h04")) @[rocket.scala 136:22] - node T_8002 = bits(mem_reg_inst, 20, 20) @[rocket.scala 136:37] - node T_8003 = eq(UInt<3>("h01"), UInt<3>("h05")) @[rocket.scala 137:22] - node T_8004 = bits(mem_reg_inst, 15, 15) @[rocket.scala 137:37] - node T_8006 = shl(T_8004, 0) @[rocket.scala 137:17] - node T_8007 = mux(T_8003, T_8006, UInt<1>("h00")) @[rocket.scala 137:17] - node T_8008 = shl(T_8002, 0) @[rocket.scala 136:17] - node T_8009 = mux(T_8001, T_8008, T_8007) @[rocket.scala 136:17] - node T_8010 = shl(T_8000, 0) @[rocket.scala 135:17] - node T_8011 = mux(T_7999, T_8010, T_8009) @[rocket.scala 135:17] - node T_8012 = cat(T_7986, T_7998) @[Cat.scala 20:58] - node T_8013 = cat(T_8012, T_8011) @[Cat.scala 20:58] - node T_8014 = asUInt(T_7980) @[Cat.scala 20:58] - node T_8015 = asUInt(T_7967) @[Cat.scala 20:58] - node T_8016 = cat(T_8015, T_8014) @[Cat.scala 20:58] - node T_8017 = asUInt(T_7961) @[Cat.scala 20:58] - node T_8018 = asUInt(T_7957) @[Cat.scala 20:58] - node T_8019 = cat(T_8018, T_8017) @[Cat.scala 20:58] - node T_8020 = cat(T_8019, T_8016) @[Cat.scala 20:58] - node T_8021 = cat(T_8020, T_8013) @[Cat.scala 20:58] - node T_8022 = asSInt(T_8021) @[rocket.scala 139:53] - node T_8024 = and(UInt<1>("h01"), mem_ctrl.jal) @[rocket.scala 393:24] - node T_8025 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 125:24] - node T_8027 = bits(mem_reg_inst, 31, 31) @[rocket.scala 125:48] - node T_8028 = asSInt(T_8027) @[rocket.scala 125:53] - node T_8029 = mux(T_8025, asSInt(UInt<1>("h00")), T_8028) @[rocket.scala 125:19] - node T_8030 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 126:26] - node T_8031 = bits(mem_reg_inst, 30, 20) @[rocket.scala 126:41] - node T_8032 = asSInt(T_8031) @[rocket.scala 126:49] - node T_8033 = mux(T_8030, T_8032, T_8029) @[rocket.scala 126:21] - node T_8034 = neq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 127:26] - node T_8035 = neq(UInt<3>("h03"), UInt<3>("h03")) @[rocket.scala 127:43] - node T_8036 = and(T_8034, T_8035) @[rocket.scala 127:36] - node T_8037 = bits(mem_reg_inst, 19, 12) @[rocket.scala 127:65] - node T_8038 = asSInt(T_8037) @[rocket.scala 127:73] - node T_8039 = mux(T_8036, T_8029, T_8038) @[rocket.scala 127:21] - node T_8040 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 128:23] - node T_8041 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 128:40] - node T_8042 = or(T_8040, T_8041) @[rocket.scala 128:33] - node T_8044 = eq(UInt<3>("h03"), UInt<3>("h03")) @[rocket.scala 129:23] - node T_8045 = bits(mem_reg_inst, 20, 20) @[rocket.scala 129:39] - node T_8046 = asSInt(T_8045) @[rocket.scala 129:44] - node T_8047 = eq(UInt<3>("h03"), UInt<3>("h01")) @[rocket.scala 130:23] - node T_8048 = bits(mem_reg_inst, 7, 7) @[rocket.scala 130:39] - node T_8049 = asSInt(T_8048) @[rocket.scala 130:43] - node T_8050 = mux(T_8047, T_8049, T_8029) @[rocket.scala 130:18] - node T_8051 = mux(T_8044, T_8046, T_8050) @[rocket.scala 129:18] - node T_8052 = mux(T_8042, asSInt(UInt<1>("h00")), T_8051) @[rocket.scala 128:18] - node T_8053 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 131:25] - node T_8054 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 131:42] - node T_8055 = or(T_8053, T_8054) @[rocket.scala 131:35] - node T_8057 = bits(mem_reg_inst, 30, 25) @[rocket.scala 131:66] - node T_8058 = mux(T_8055, UInt<1>("h00"), T_8057) @[rocket.scala 131:20] - node T_8059 = eq(UInt<3>("h03"), UInt<3>("h02")) @[rocket.scala 132:24] - node T_8061 = eq(UInt<3>("h03"), UInt<3>("h00")) @[rocket.scala 133:24] - node T_8062 = eq(UInt<3>("h03"), UInt<3>("h01")) @[rocket.scala 133:41] - node T_8063 = or(T_8061, T_8062) @[rocket.scala 133:34] - node T_8064 = bits(mem_reg_inst, 11, 8) @[rocket.scala 133:57] - node T_8065 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 134:24] - node T_8066 = bits(mem_reg_inst, 19, 16) @[rocket.scala 134:39] - node T_8067 = bits(mem_reg_inst, 24, 21) @[rocket.scala 134:52] - node T_8068 = mux(T_8065, T_8066, T_8067) @[rocket.scala 134:19] - node T_8069 = mux(T_8063, T_8064, T_8068) @[rocket.scala 133:19] - node T_8070 = mux(T_8059, UInt<1>("h00"), T_8069) @[rocket.scala 132:19] - node T_8071 = eq(UInt<3>("h03"), UInt<3>("h00")) @[rocket.scala 135:22] - node T_8072 = bits(mem_reg_inst, 7, 7) @[rocket.scala 135:37] - node T_8073 = eq(UInt<3>("h03"), UInt<3>("h04")) @[rocket.scala 136:22] - node T_8074 = bits(mem_reg_inst, 20, 20) @[rocket.scala 136:37] - node T_8075 = eq(UInt<3>("h03"), UInt<3>("h05")) @[rocket.scala 137:22] - node T_8076 = bits(mem_reg_inst, 15, 15) @[rocket.scala 137:37] - node T_8078 = shl(T_8076, 0) @[rocket.scala 137:17] - node T_8079 = mux(T_8075, T_8078, UInt<1>("h00")) @[rocket.scala 137:17] - node T_8080 = shl(T_8074, 0) @[rocket.scala 136:17] - node T_8081 = mux(T_8073, T_8080, T_8079) @[rocket.scala 136:17] - node T_8082 = shl(T_8072, 0) @[rocket.scala 135:17] - node T_8083 = mux(T_8071, T_8082, T_8081) @[rocket.scala 135:17] - node T_8084 = cat(T_8058, T_8070) @[Cat.scala 20:58] - node T_8085 = cat(T_8084, T_8083) @[Cat.scala 20:58] - node T_8086 = asUInt(T_8052) @[Cat.scala 20:58] - node T_8087 = asUInt(T_8039) @[Cat.scala 20:58] - node T_8088 = cat(T_8087, T_8086) @[Cat.scala 20:58] - node T_8089 = asUInt(T_8033) @[Cat.scala 20:58] - node T_8090 = asUInt(T_8029) @[Cat.scala 20:58] - node T_8091 = cat(T_8090, T_8089) @[Cat.scala 20:58] - node T_8092 = cat(T_8091, T_8088) @[Cat.scala 20:58] - node T_8093 = cat(T_8092, T_8085) @[Cat.scala 20:58] - node T_8094 = asSInt(T_8093) @[rocket.scala 139:53] - node T_8097 = mux(mem_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[rocket.scala 394:8] - node T_8098 = mux(T_8024, T_8094, T_8097) @[rocket.scala 393:8] - node T_8099 = mux(T_7952, T_8022, T_8098) @[rocket.scala 392:8] - node T_8100 = add(T_7951, T_8099) @[rocket.scala 391:41] - node T_8101 = tail(T_8100, 1) @[rocket.scala 391:41] - node mem_br_target = asSInt(T_8101) @[rocket.scala 391:41] - node T_8102 = shr(mem_reg_wdata, 38) @[rocket.scala 699:16] - node T_8103 = bits(mem_reg_wdata, 39, 38) @[rocket.scala 700:15] - node T_8104 = asSInt(T_8103) @[rocket.scala 700:39] - node T_8106 = eq(T_8102, UInt<1>("h00")) @[rocket.scala 702:13] - node T_8108 = eq(T_8102, UInt<1>("h01")) @[rocket.scala 702:30] - node T_8109 = or(T_8106, T_8108) @[rocket.scala 702:25] - node T_8111 = neq(T_8104, asSInt(UInt<1>("h00"))) @[rocket.scala 702:45] - node T_8112 = asSInt(T_8102) @[rocket.scala 703:13] - node T_8114 = eq(T_8112, asSInt(UInt<1>("h01"))) @[rocket.scala 703:20] - node T_8115 = asSInt(T_8102) @[rocket.scala 703:38] - node T_8117 = eq(T_8115, asSInt(UInt<2>("h02"))) @[rocket.scala 703:45] - node T_8118 = or(T_8114, T_8117) @[rocket.scala 703:33] - node T_8120 = eq(T_8104, asSInt(UInt<1>("h01"))) @[rocket.scala 703:61] - node T_8121 = bits(T_8104, 0, 0) @[rocket.scala 703:76] - node T_8122 = mux(T_8118, T_8120, T_8121) @[rocket.scala 703:10] - node T_8123 = mux(T_8109, T_8111, T_8122) @[rocket.scala 702:10] - node T_8124 = bits(mem_reg_wdata, 38, 0) @[rocket.scala 704:16] - node T_8125 = cat(T_8123, T_8124) @[Cat.scala 20:58] - node T_8126 = asSInt(T_8125) @[rocket.scala 395:88] - node T_8127 = mux(mem_ctrl.jalr, T_8126, mem_br_target) @[rocket.scala 395:21] - node T_8129 = and(T_8127, asSInt(UInt<2>("h02"))) @[rocket.scala 395:111] - node T_8130 = asSInt(T_8129) @[rocket.scala 395:111] - node mem_npc = asUInt(T_8130) @[rocket.scala 395:123] - node T_8131 = neq(mem_npc, ex_reg_pc) @[rocket.scala 396:48] - node T_8132 = neq(mem_npc, ibuf.io.pc) @[rocket.scala 396:98] - node T_8134 = mux(ibuf.io.inst[0].valid, T_8132, UInt<1>("h01")) @[rocket.scala 396:66] - node mem_wrong_npc = mux(ex_pc_valid, T_8131, T_8134) @[rocket.scala 396:26] - node T_8135 = bits(csr.io.status.isa, 2, 2) @[rocket.scala 397:46] - node T_8137 = eq(T_8135, UInt<1>("h00")) @[rocket.scala 397:28] - node T_8138 = bits(mem_npc, 1, 1) @[rocket.scala 397:66] - node mem_npc_misaligned = and(T_8137, T_8138) @[rocket.scala 397:56] - node T_8140 = eq(mem_reg_xcpt, UInt<1>("h00")) @[rocket.scala 398:27] - node T_8141 = xor(mem_ctrl.jalr, mem_npc_misaligned) @[rocket.scala 398:59] - node T_8142 = and(T_8140, T_8141) @[rocket.scala 398:41] - node T_8143 = asSInt(mem_reg_wdata) @[rocket.scala 398:111] - node T_8144 = mux(T_8142, mem_br_target, T_8143) @[rocket.scala 398:26] - node mem_int_wdata = asUInt(T_8144) @[rocket.scala 398:119] - node T_8145 = or(mem_ctrl.branch, mem_ctrl.jalr) @[rocket.scala 399:33] - node mem_cfi = or(T_8145, mem_ctrl.jal) @[rocket.scala 399:50] - node T_8146 = and(mem_ctrl.branch, mem_br_taken) @[rocket.scala 400:40] - node T_8147 = or(T_8146, mem_ctrl.jalr) @[rocket.scala 400:57] - node T_8149 = and(UInt<1>("h01"), mem_ctrl.jal) @[rocket.scala 400:93] - node mem_cfi_taken = or(T_8147, T_8149) @[rocket.scala 400:74] - node T_8150 = or(mem_wrong_npc, mem_reg_flush_pipe) @[rocket.scala 404:54] - node T_8151 = and(mem_reg_valid, T_8150) @[rocket.scala 404:32] - take_pc_mem <= T_8151 @[rocket.scala 404:15] - node T_8153 = eq(ctrl_killx, UInt<1>("h00")) @[rocket.scala 406:20] - mem_reg_valid <= T_8153 @[rocket.scala 406:17] - node T_8155 = eq(take_pc_mem_wb, UInt<1>("h00")) @[rocket.scala 407:21] - node T_8156 = and(T_8155, replay_ex) @[rocket.scala 407:37] - mem_reg_replay <= T_8156 @[rocket.scala 407:18] - node T_8158 = eq(ctrl_killx, UInt<1>("h00")) @[rocket.scala 408:19] - node T_8159 = and(T_8158, ex_xcpt) @[rocket.scala 408:31] - mem_reg_xcpt <= T_8159 @[rocket.scala 408:16] - node T_8161 = eq(take_pc_mem_wb, UInt<1>("h00")) @[rocket.scala 409:29] - node T_8162 = and(T_8161, ex_reg_xcpt_interrupt) @[rocket.scala 409:45] - mem_reg_xcpt_interrupt <= T_8162 @[rocket.scala 409:26] - when ex_xcpt : @[rocket.scala 410:18] - mem_reg_cause <= ex_cause @[rocket.scala 410:34] - skip @[rocket.scala 410:18] - when ex_pc_valid : @[rocket.scala 412:22] - mem_ctrl <- ex_ctrl @[rocket.scala 413:14] - mem_reg_rvc <= ex_reg_rvc @[rocket.scala 414:17] - node T_8163 = eq(ex_ctrl.mem_cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_8164 = eq(ex_ctrl.mem_cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_8165 = or(T_8163, T_8164) @[Consts.scala 35:41] - node T_8166 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_8167 = or(T_8165, T_8166) @[Consts.scala 35:58] - node T_8168 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] - node T_8169 = eq(ex_ctrl.mem_cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_8170 = or(T_8168, T_8169) @[Consts.scala 33:33] - node T_8171 = or(T_8167, T_8170) @[Consts.scala 35:75] - node T_8172 = and(ex_ctrl.mem, T_8171) @[rocket.scala 415:33] - mem_reg_load <= T_8172 @[rocket.scala 415:18] - node T_8173 = eq(ex_ctrl.mem_cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_8174 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_8175 = or(T_8173, T_8174) @[Consts.scala 36:42] - node T_8176 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] - node T_8177 = eq(ex_ctrl.mem_cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_8178 = or(T_8176, T_8177) @[Consts.scala 33:33] - node T_8179 = or(T_8175, T_8178) @[Consts.scala 36:59] - node T_8180 = and(ex_ctrl.mem, T_8179) @[rocket.scala 416:34] - mem_reg_store <= T_8180 @[rocket.scala 416:19] - mem_reg_btb_hit <= ex_reg_btb_hit @[rocket.scala 417:21] - when ex_reg_btb_hit : @[rocket.scala 418:27] - mem_reg_btb_resp <- ex_reg_btb_resp @[rocket.scala 418:46] - skip @[rocket.scala 418:27] - mem_reg_flush_pipe <= ex_reg_flush_pipe @[rocket.scala 419:24] - mem_reg_slow_bypass <= ex_slow_bypass @[rocket.scala 420:25] - mem_reg_inst <= ex_reg_inst @[rocket.scala 422:18] - mem_reg_pc <= ex_reg_pc @[rocket.scala 423:16] - mem_reg_wdata <= alu.io.out @[rocket.scala 424:19] - node T_8181 = or(ex_ctrl.mem, ex_ctrl.rocc) @[rocket.scala 425:40] - node T_8182 = and(ex_ctrl.rxs2, T_8181) @[rocket.scala 425:24] - when T_8182 : @[rocket.scala 425:58] - mem_reg_rs2 <= ex_rs_1 @[rocket.scala 426:19] - skip @[rocket.scala 425:58] - skip @[rocket.scala 412:22] - node T_8183 = and(mem_reg_load, bpu.io.xcpt_ld) @[rocket.scala 430:38] - node T_8184 = and(mem_reg_store, bpu.io.xcpt_st) @[rocket.scala 430:75] - node mem_breakpoint = or(T_8183, T_8184) @[rocket.scala 430:57] - node T_8185 = and(mem_reg_load, bpu.io.debug_ld) @[rocket.scala 431:44] - node T_8186 = and(mem_reg_store, bpu.io.debug_st) @[rocket.scala 431:82] - node mem_debug_breakpoint = or(T_8185, T_8186) @[rocket.scala 431:64] - node T_8190 = and(mem_ctrl.mem, io.dmem.xcpt.ma.st) @[rocket.scala 436:19] - node T_8192 = and(mem_ctrl.mem, io.dmem.xcpt.ma.ld) @[rocket.scala 437:19] - node T_8194 = and(mem_ctrl.mem, io.dmem.xcpt.pf.st) @[rocket.scala 438:19] - node T_8196 = and(mem_ctrl.mem, io.dmem.xcpt.pf.ld) @[rocket.scala 439:19] - node T_8198 = or(mem_debug_breakpoint, mem_breakpoint) @[rocket.scala 691:26] - node T_8199 = or(T_8198, mem_npc_misaligned) @[rocket.scala 691:26] - node T_8200 = or(T_8199, T_8190) @[rocket.scala 691:26] - node T_8201 = or(T_8200, T_8192) @[rocket.scala 691:26] - node T_8202 = or(T_8201, T_8194) @[rocket.scala 691:26] - node mem_new_xcpt = or(T_8202, T_8196) @[rocket.scala 691:26] - node T_8203 = mux(T_8194, UInt<3>("h07"), UInt<3>("h05")) @[Mux.scala 31:69] - node T_8204 = mux(T_8192, UInt<3>("h04"), T_8203) @[Mux.scala 31:69] - node T_8205 = mux(T_8190, UInt<3>("h06"), T_8204) @[Mux.scala 31:69] - node T_8206 = mux(mem_npc_misaligned, UInt<1>("h00"), T_8205) @[Mux.scala 31:69] - node T_8207 = mux(mem_breakpoint, UInt<2>("h03"), T_8206) @[Mux.scala 31:69] - node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("h0d"), T_8207) @[Mux.scala 31:69] - node T_8208 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[rocket.scala 442:29] - node T_8209 = and(mem_reg_valid, mem_new_xcpt) @[rocket.scala 443:20] - node mem_xcpt = or(T_8208, T_8209) @[rocket.scala 691:26] - node mem_cause = mux(T_8208, mem_reg_cause, mem_new_cause) @[Mux.scala 31:69] - node T_8210 = and(mem_reg_valid, mem_ctrl.wxd) @[rocket.scala 445:39] - node dcache_kill_mem = and(T_8210, io.dmem.replay_next) @[rocket.scala 445:55] - node T_8211 = and(mem_reg_valid, mem_ctrl.fp) @[rocket.scala 446:36] - node fpu_kill_mem = and(T_8211, io.fpu.nack_mem) @[rocket.scala 446:51] - node T_8212 = or(dcache_kill_mem, mem_reg_replay) @[rocket.scala 447:37] - node replay_mem = or(T_8212, fpu_kill_mem) @[rocket.scala 447:55] - node T_8213 = or(dcache_kill_mem, take_pc_wb) @[rocket.scala 448:38] - node T_8214 = or(T_8213, mem_reg_xcpt) @[rocket.scala 448:52] - node T_8216 = eq(mem_reg_valid, UInt<1>("h00")) @[rocket.scala 448:71] - node killm_common = or(T_8214, T_8216) @[rocket.scala 448:68] - node T_8217 = and(div.io.req.ready, div.io.req.valid) @[Decoupled.scala 21:42] - reg T_8218 : UInt<1>, clk + node T_7855 = and(ex_reg_valid, ex_ctrl.div) + div.io.req.valid <= T_7855 + div.io.req.bits.dw <= ex_ctrl.alu_dw + div.io.req.bits.fn <= ex_ctrl.alu_fn + div.io.req.bits.in1 <= ex_rs_0 + div.io.req.bits.in2 <= ex_rs_1 + div.io.req.bits.tag <= ex_waddr + node T_7857 = eq(ctrl_killd, UInt<1>("h0")) + ex_reg_valid <= T_7857 + node T_7859 = eq(take_pc, UInt<1>("h0")) + node T_7860 = and(T_7859, ibuf.io.inst[0].valid) + node T_7861 = and(T_7860, ibuf.io.inst[0].bits.replay) + ex_reg_replay <= T_7861 + node T_7863 = eq(ctrl_killd, UInt<1>("h0")) + node T_7864 = and(T_7863, id_xcpt) + ex_reg_xcpt <= T_7864 + node T_7866 = eq(take_pc, UInt<1>("h0")) + node T_7867 = and(T_7866, ibuf.io.inst[0].valid) + node T_7868 = and(T_7867, csr.io.interrupt) + ex_reg_xcpt_interrupt <= T_7868 + when id_xcpt : + ex_reg_cause <= id_cause + ex_reg_btb_hit <= ibuf.io.inst[0].bits.btb_hit + when ibuf.io.inst[0].bits.btb_hit : + ex_reg_btb_resp <- ibuf.io.btb_resp + node T_7870 = eq(ctrl_killd, UInt<1>("h0")) + when T_7870 : + ex_ctrl <- id_ctrl + ex_reg_rvc <= ibuf.io.inst[0].bits.rvc + ex_ctrl.csr <= id_csr + when id_xcpt : + ex_ctrl.alu_fn <= UInt<1>("h0") + ex_ctrl.alu_dw <= UInt<1>("h1") + ex_ctrl.sel_alu1 <= UInt<2>("h2") + ex_ctrl.sel_alu2 <= UInt<2>("h0") + node T_7872 = eq(bpu.io.xcpt_if, UInt<1>("h0")) + node T_7874 = eq(ibuf.io.inst[0].bits.pf0, UInt<1>("h0")) + node T_7875 = and(T_7872, T_7874) + node T_7876 = and(T_7875, ibuf.io.inst[0].bits.pf1) + when T_7876 : + ex_ctrl.sel_alu2 <= UInt<2>("h1") + ex_reg_rvc <= UInt<1>("h1") + node T_7878 = or(id_ctrl.fence_i, id_csr_flush) + node T_7879 = or(T_7878, csr.io.singleStep) + ex_reg_flush_pipe <= T_7879 + ex_reg_load_use <= id_load_use + node T_7880 = and(id_ctrl.jalr, csr.io.status.debug) + when T_7880 : + ex_reg_flush_pipe <= UInt<1>("h1") + ex_ctrl.fence_i <= UInt<1>("h1") + node T_7883 = or(id_bypass_src_0_0, id_bypass_src_0_1) + node T_7884 = or(T_7883, id_bypass_src_0_2) + node T_7885 = or(T_7884, id_bypass_src_0_3) + node T_7890 = mux(id_bypass_src_0_2, UInt<2>("h2"), UInt<2>("h3")) + node T_7891 = mux(id_bypass_src_0_1, UInt<1>("h1"), T_7890) + node T_7892 = mux(id_bypass_src_0_0, UInt<1>("h0"), T_7891) + ex_reg_rs_bypass[0] <= T_7885 + ex_reg_rs_lsb[0] <= T_7892 + node T_7894 = eq(T_7885, UInt<1>("h0")) + node T_7895 = and(id_ctrl.rxs1, T_7894) + when T_7895 : + node T_7896 = bits(id_rs_0, 1, 0) + ex_reg_rs_lsb[0] <= T_7896 + node T_7897 = shr(id_rs_0, 2) + ex_reg_rs_msb[0] <= T_7897 + node T_7898 = or(id_bypass_src_1_0, id_bypass_src_1_1) + node T_7899 = or(T_7898, id_bypass_src_1_2) + node T_7900 = or(T_7899, id_bypass_src_1_3) + node T_7905 = mux(id_bypass_src_1_2, UInt<2>("h2"), UInt<2>("h3")) + node T_7906 = mux(id_bypass_src_1_1, UInt<1>("h1"), T_7905) + node T_7907 = mux(id_bypass_src_1_0, UInt<1>("h0"), T_7906) + ex_reg_rs_bypass[1] <= T_7900 + ex_reg_rs_lsb[1] <= T_7907 + node T_7909 = eq(T_7900, UInt<1>("h0")) + node T_7910 = and(id_ctrl.rxs2, T_7909) + when T_7910 : + node T_7911 = bits(id_rs_1, 1, 0) + ex_reg_rs_lsb[1] <= T_7911 + node T_7912 = shr(id_rs_1, 2) + ex_reg_rs_msb[1] <= T_7912 + node T_7914 = eq(ctrl_killd, UInt<1>("h0")) + node T_7915 = or(T_7914, csr.io.interrupt) + node T_7916 = or(T_7915, ibuf.io.inst[0].bits.replay) + when T_7916 : + ex_reg_inst <= ibuf.io.inst[0].bits.inst.bits + ex_reg_pc <= ibuf.io.pc + node T_7917 = or(ex_reg_valid, ex_reg_replay) + node ex_pc_valid = or(T_7917, ex_reg_xcpt_interrupt) + node T_7919 = eq(io.dmem.resp.valid, UInt<1>("h0")) + node wb_dcache_miss = and(wb_ctrl.mem, T_7919) + node T_7921 = eq(io.dmem.req.ready, UInt<1>("h0")) + node T_7922 = and(ex_ctrl.mem, T_7921) + node T_7924 = eq(div.io.req.ready, UInt<1>("h0")) + node T_7925 = and(ex_ctrl.div, T_7924) + node replay_ex_structural = or(T_7922, T_7925) + node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) + node T_7926 = or(replay_ex_structural, replay_ex_load_use) + node T_7927 = and(ex_reg_valid, T_7926) + node replay_ex = or(ex_reg_replay, T_7927) + node T_7928 = or(take_pc_mem_wb, replay_ex) + node T_7930 = eq(ex_reg_valid, UInt<1>("h0")) + node ctrl_killx = or(T_7928, T_7930) + node T_7931 = eq(ex_ctrl.mem_cmd, UInt<5>("h7")) + wire T_7937 : UInt<3>[4] + T_7937 is invalid + T_7937[0] <= UInt<3>("h0") + T_7937[1] <= UInt<3>("h4") + T_7937[2] <= UInt<3>("h1") + T_7937[3] <= UInt<3>("h5") + node T_7939 = eq(T_7937[0], ex_ctrl.mem_type) + node T_7940 = eq(T_7937[1], ex_ctrl.mem_type) + node T_7941 = eq(T_7937[2], ex_ctrl.mem_type) + node T_7942 = eq(T_7937[3], ex_ctrl.mem_type) + node T_7944 = or(UInt<1>("h0"), T_7939) + node T_7945 = or(T_7944, T_7940) + node T_7946 = or(T_7945, T_7941) + node T_7947 = or(T_7946, T_7942) + node ex_slow_bypass = or(T_7931, T_7947) + node T_7948 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) + node T_7949 = and(ex_ctrl.fp, io.fpu.illegal_rm) + node ex_xcpt = or(T_7948, T_7949) + node ex_cause = mux(T_7948, ex_reg_cause, UInt<2>("h2")) + node mem_br_taken = bits(mem_reg_wdata, 0, 0) + node T_7951 = asSInt(mem_reg_pc) + node T_7952 = and(mem_ctrl.branch, mem_br_taken) + node T_7953 = eq(UInt<3>("h1"), UInt<3>("h5")) + node T_7955 = bits(mem_reg_inst, 31, 31) + node T_7956 = asSInt(T_7955) + node T_7957 = mux(T_7953, asSInt(UInt<1>("h0")), T_7956) + node T_7958 = eq(UInt<3>("h1"), UInt<3>("h2")) + node T_7959 = bits(mem_reg_inst, 30, 20) + node T_7960 = asSInt(T_7959) + node T_7961 = mux(T_7958, T_7960, T_7957) + node T_7962 = neq(UInt<3>("h1"), UInt<3>("h2")) + node T_7963 = neq(UInt<3>("h1"), UInt<3>("h3")) + node T_7964 = and(T_7962, T_7963) + node T_7965 = bits(mem_reg_inst, 19, 12) + node T_7966 = asSInt(T_7965) + node T_7967 = mux(T_7964, T_7957, T_7966) + node T_7968 = eq(UInt<3>("h1"), UInt<3>("h2")) + node T_7969 = eq(UInt<3>("h1"), UInt<3>("h5")) + node T_7970 = or(T_7968, T_7969) + node T_7972 = eq(UInt<3>("h1"), UInt<3>("h3")) + node T_7973 = bits(mem_reg_inst, 20, 20) + node T_7974 = asSInt(T_7973) + node T_7975 = eq(UInt<3>("h1"), UInt<3>("h1")) + node T_7976 = bits(mem_reg_inst, 7, 7) + node T_7977 = asSInt(T_7976) + node T_7978 = mux(T_7975, T_7977, T_7957) + node T_7979 = mux(T_7972, T_7974, T_7978) + node T_7980 = mux(T_7970, asSInt(UInt<1>("h0")), T_7979) + node T_7981 = eq(UInt<3>("h1"), UInt<3>("h2")) + node T_7982 = eq(UInt<3>("h1"), UInt<3>("h5")) + node T_7983 = or(T_7981, T_7982) + node T_7985 = bits(mem_reg_inst, 30, 25) + node T_7986 = mux(T_7983, UInt<1>("h0"), T_7985) + node T_7987 = eq(UInt<3>("h1"), UInt<3>("h2")) + node T_7989 = eq(UInt<3>("h1"), UInt<3>("h0")) + node T_7990 = eq(UInt<3>("h1"), UInt<3>("h1")) + node T_7991 = or(T_7989, T_7990) + node T_7992 = bits(mem_reg_inst, 11, 8) + node T_7993 = eq(UInt<3>("h1"), UInt<3>("h5")) + node T_7994 = bits(mem_reg_inst, 19, 16) + node T_7995 = bits(mem_reg_inst, 24, 21) + node T_7996 = mux(T_7993, T_7994, T_7995) + node T_7997 = mux(T_7991, T_7992, T_7996) + node T_7998 = mux(T_7987, UInt<1>("h0"), T_7997) + node T_7999 = eq(UInt<3>("h1"), UInt<3>("h0")) + node T_8000 = bits(mem_reg_inst, 7, 7) + node T_8001 = eq(UInt<3>("h1"), UInt<3>("h4")) + node T_8002 = bits(mem_reg_inst, 20, 20) + node T_8003 = eq(UInt<3>("h1"), UInt<3>("h5")) + node T_8004 = bits(mem_reg_inst, 15, 15) + node T_8006 = shl(T_8004, 0) + node T_8007 = mux(T_8003, T_8006, UInt<1>("h0")) + node T_8008 = shl(T_8002, 0) + node T_8009 = mux(T_8001, T_8008, T_8007) + node T_8010 = shl(T_8000, 0) + node T_8011 = mux(T_7999, T_8010, T_8009) + node T_8012 = cat(T_7986, T_7998) + node T_8013 = cat(T_8012, T_8011) + node T_8014 = asUInt(T_7980) + node T_8015 = asUInt(T_7967) + node T_8016 = cat(T_8015, T_8014) + node T_8017 = asUInt(T_7961) + node T_8018 = asUInt(T_7957) + node T_8019 = cat(T_8018, T_8017) + node T_8020 = cat(T_8019, T_8016) + node T_8021 = cat(T_8020, T_8013) + node T_8022 = asSInt(T_8021) + node T_8024 = and(UInt<1>("h1"), mem_ctrl.jal) + node T_8025 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_8027 = bits(mem_reg_inst, 31, 31) + node T_8028 = asSInt(T_8027) + node T_8029 = mux(T_8025, asSInt(UInt<1>("h0")), T_8028) + node T_8030 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_8031 = bits(mem_reg_inst, 30, 20) + node T_8032 = asSInt(T_8031) + node T_8033 = mux(T_8030, T_8032, T_8029) + node T_8034 = neq(UInt<3>("h3"), UInt<3>("h2")) + node T_8035 = neq(UInt<3>("h3"), UInt<3>("h3")) + node T_8036 = and(T_8034, T_8035) + node T_8037 = bits(mem_reg_inst, 19, 12) + node T_8038 = asSInt(T_8037) + node T_8039 = mux(T_8036, T_8029, T_8038) + node T_8040 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_8041 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_8042 = or(T_8040, T_8041) + node T_8044 = eq(UInt<3>("h3"), UInt<3>("h3")) + node T_8045 = bits(mem_reg_inst, 20, 20) + node T_8046 = asSInt(T_8045) + node T_8047 = eq(UInt<3>("h3"), UInt<3>("h1")) + node T_8048 = bits(mem_reg_inst, 7, 7) + node T_8049 = asSInt(T_8048) + node T_8050 = mux(T_8047, T_8049, T_8029) + node T_8051 = mux(T_8044, T_8046, T_8050) + node T_8052 = mux(T_8042, asSInt(UInt<1>("h0")), T_8051) + node T_8053 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_8054 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_8055 = or(T_8053, T_8054) + node T_8057 = bits(mem_reg_inst, 30, 25) + node T_8058 = mux(T_8055, UInt<1>("h0"), T_8057) + node T_8059 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_8061 = eq(UInt<3>("h3"), UInt<3>("h0")) + node T_8062 = eq(UInt<3>("h3"), UInt<3>("h1")) + node T_8063 = or(T_8061, T_8062) + node T_8064 = bits(mem_reg_inst, 11, 8) + node T_8065 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_8066 = bits(mem_reg_inst, 19, 16) + node T_8067 = bits(mem_reg_inst, 24, 21) + node T_8068 = mux(T_8065, T_8066, T_8067) + node T_8069 = mux(T_8063, T_8064, T_8068) + node T_8070 = mux(T_8059, UInt<1>("h0"), T_8069) + node T_8071 = eq(UInt<3>("h3"), UInt<3>("h0")) + node T_8072 = bits(mem_reg_inst, 7, 7) + node T_8073 = eq(UInt<3>("h3"), UInt<3>("h4")) + node T_8074 = bits(mem_reg_inst, 20, 20) + node T_8075 = eq(UInt<3>("h3"), UInt<3>("h5")) + node T_8076 = bits(mem_reg_inst, 15, 15) + node T_8078 = shl(T_8076, 0) + node T_8079 = mux(T_8075, T_8078, UInt<1>("h0")) + node T_8080 = shl(T_8074, 0) + node T_8081 = mux(T_8073, T_8080, T_8079) + node T_8082 = shl(T_8072, 0) + node T_8083 = mux(T_8071, T_8082, T_8081) + node T_8084 = cat(T_8058, T_8070) + node T_8085 = cat(T_8084, T_8083) + node T_8086 = asUInt(T_8052) + node T_8087 = asUInt(T_8039) + node T_8088 = cat(T_8087, T_8086) + node T_8089 = asUInt(T_8033) + node T_8090 = asUInt(T_8029) + node T_8091 = cat(T_8090, T_8089) + node T_8092 = cat(T_8091, T_8088) + node T_8093 = cat(T_8092, T_8085) + node T_8094 = asSInt(T_8093) + node T_8097 = mux(mem_reg_rvc, asSInt(UInt<3>("h2")), asSInt(UInt<4>("h4"))) + node T_8098 = mux(T_8024, T_8094, T_8097) + node T_8099 = mux(T_7952, T_8022, T_8098) + node T_8100 = add(T_7951, T_8099) + node T_8101 = tail(T_8100, 1) + node mem_br_target = asSInt(T_8101) + node T_8102 = shr(mem_reg_wdata, 38) + node T_8103 = bits(mem_reg_wdata, 39, 38) + node T_8104 = asSInt(T_8103) + node T_8106 = eq(T_8102, UInt<1>("h0")) + node T_8108 = eq(T_8102, UInt<1>("h1")) + node T_8109 = or(T_8106, T_8108) + node T_8111 = neq(T_8104, asSInt(UInt<1>("h0"))) + node T_8112 = asSInt(T_8102) + node T_8114 = eq(T_8112, asSInt(UInt<1>("h1"))) + node T_8115 = asSInt(T_8102) + node T_8117 = eq(T_8115, asSInt(UInt<2>("h2"))) + node T_8118 = or(T_8114, T_8117) + node T_8120 = eq(T_8104, asSInt(UInt<1>("h1"))) + node T_8121 = bits(T_8104, 0, 0) + node T_8122 = mux(T_8118, T_8120, T_8121) + node T_8123 = mux(T_8109, T_8111, T_8122) + node T_8124 = bits(mem_reg_wdata, 38, 0) + node T_8125 = cat(T_8123, T_8124) + node T_8126 = asSInt(T_8125) + node T_8127 = mux(mem_ctrl.jalr, T_8126, mem_br_target) + node T_8129 = and(T_8127, asSInt(UInt<2>("h2"))) + node T_8130 = asSInt(T_8129) + node mem_npc = asUInt(T_8130) + node T_8131 = neq(mem_npc, ex_reg_pc) + node T_8132 = neq(mem_npc, ibuf.io.pc) + node T_8134 = mux(ibuf.io.inst[0].valid, T_8132, UInt<1>("h1")) + node mem_wrong_npc = mux(ex_pc_valid, T_8131, T_8134) + node T_8135 = bits(csr.io.status.isa, 2, 2) + node T_8137 = eq(T_8135, UInt<1>("h0")) + node T_8138 = bits(mem_npc, 1, 1) + node mem_npc_misaligned = and(T_8137, T_8138) + node T_8140 = eq(mem_reg_xcpt, UInt<1>("h0")) + node T_8141 = xor(mem_ctrl.jalr, mem_npc_misaligned) + node T_8142 = and(T_8140, T_8141) + node T_8143 = asSInt(mem_reg_wdata) + node T_8144 = mux(T_8142, mem_br_target, T_8143) + node mem_int_wdata = asUInt(T_8144) + node T_8145 = or(mem_ctrl.branch, mem_ctrl.jalr) + node mem_cfi = or(T_8145, mem_ctrl.jal) + node T_8146 = and(mem_ctrl.branch, mem_br_taken) + node T_8147 = or(T_8146, mem_ctrl.jalr) + node T_8149 = and(UInt<1>("h1"), mem_ctrl.jal) + node mem_cfi_taken = or(T_8147, T_8149) + node T_8150 = or(mem_wrong_npc, mem_reg_flush_pipe) + node T_8151 = and(mem_reg_valid, T_8150) + take_pc_mem <= T_8151 + node T_8153 = eq(ctrl_killx, UInt<1>("h0")) + mem_reg_valid <= T_8153 + node T_8155 = eq(take_pc_mem_wb, UInt<1>("h0")) + node T_8156 = and(T_8155, replay_ex) + mem_reg_replay <= T_8156 + node T_8158 = eq(ctrl_killx, UInt<1>("h0")) + node T_8159 = and(T_8158, ex_xcpt) + mem_reg_xcpt <= T_8159 + node T_8161 = eq(take_pc_mem_wb, UInt<1>("h0")) + node T_8162 = and(T_8161, ex_reg_xcpt_interrupt) + mem_reg_xcpt_interrupt <= T_8162 + when ex_xcpt : + mem_reg_cause <= ex_cause + when ex_pc_valid : + mem_ctrl <- ex_ctrl + mem_reg_rvc <= ex_reg_rvc + node T_8163 = eq(ex_ctrl.mem_cmd, UInt<5>("h0")) + node T_8164 = eq(ex_ctrl.mem_cmd, UInt<5>("h6")) + node T_8165 = or(T_8163, T_8164) + node T_8166 = eq(ex_ctrl.mem_cmd, UInt<5>("h7")) + node T_8167 = or(T_8165, T_8166) + node T_8168 = bits(ex_ctrl.mem_cmd, 3, 3) + node T_8169 = eq(ex_ctrl.mem_cmd, UInt<5>("h4")) + node T_8170 = or(T_8168, T_8169) + node T_8171 = or(T_8167, T_8170) + node T_8172 = and(ex_ctrl.mem, T_8171) + mem_reg_load <= T_8172 + node T_8173 = eq(ex_ctrl.mem_cmd, UInt<5>("h1")) + node T_8174 = eq(ex_ctrl.mem_cmd, UInt<5>("h7")) + node T_8175 = or(T_8173, T_8174) + node T_8176 = bits(ex_ctrl.mem_cmd, 3, 3) + node T_8177 = eq(ex_ctrl.mem_cmd, UInt<5>("h4")) + node T_8178 = or(T_8176, T_8177) + node T_8179 = or(T_8175, T_8178) + node T_8180 = and(ex_ctrl.mem, T_8179) + mem_reg_store <= T_8180 + mem_reg_btb_hit <= ex_reg_btb_hit + when ex_reg_btb_hit : + mem_reg_btb_resp <- ex_reg_btb_resp + mem_reg_flush_pipe <= ex_reg_flush_pipe + mem_reg_slow_bypass <= ex_slow_bypass + mem_reg_inst <= ex_reg_inst + mem_reg_pc <= ex_reg_pc + mem_reg_wdata <= alu.io.out + node T_8181 = or(ex_ctrl.mem, ex_ctrl.rocc) + node T_8182 = and(ex_ctrl.rxs2, T_8181) + when T_8182 : + mem_reg_rs2 <= ex_rs_1 + node T_8183 = and(mem_reg_load, bpu.io.xcpt_ld) + node T_8184 = and(mem_reg_store, bpu.io.xcpt_st) + node mem_breakpoint = or(T_8183, T_8184) + node T_8185 = and(mem_reg_load, bpu.io.debug_ld) + node T_8186 = and(mem_reg_store, bpu.io.debug_st) + node mem_debug_breakpoint = or(T_8185, T_8186) + node T_8190 = and(mem_ctrl.mem, io.dmem.xcpt.ma.st) + node T_8192 = and(mem_ctrl.mem, io.dmem.xcpt.ma.ld) + node T_8194 = and(mem_ctrl.mem, io.dmem.xcpt.pf.st) + node T_8196 = and(mem_ctrl.mem, io.dmem.xcpt.pf.ld) + node T_8198 = or(mem_debug_breakpoint, mem_breakpoint) + node T_8199 = or(T_8198, mem_npc_misaligned) + node T_8200 = or(T_8199, T_8190) + node T_8201 = or(T_8200, T_8192) + node T_8202 = or(T_8201, T_8194) + node mem_new_xcpt = or(T_8202, T_8196) + node T_8203 = mux(T_8194, UInt<3>("h7"), UInt<3>("h5")) + node T_8204 = mux(T_8192, UInt<3>("h4"), T_8203) + node T_8205 = mux(T_8190, UInt<3>("h6"), T_8204) + node T_8206 = mux(mem_npc_misaligned, UInt<1>("h0"), T_8205) + node T_8207 = mux(mem_breakpoint, UInt<2>("h3"), T_8206) + node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("hd"), T_8207) + node T_8208 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) + node T_8209 = and(mem_reg_valid, mem_new_xcpt) + node mem_xcpt = or(T_8208, T_8209) + node mem_cause = mux(T_8208, mem_reg_cause, mem_new_cause) + node T_8210 = and(mem_reg_valid, mem_ctrl.wxd) + node dcache_kill_mem = and(T_8210, io.dmem.replay_next) + node T_8211 = and(mem_reg_valid, mem_ctrl.fp) + node fpu_kill_mem = and(T_8211, io.fpu.nack_mem) + node T_8212 = or(dcache_kill_mem, mem_reg_replay) + node replay_mem = or(T_8212, fpu_kill_mem) + node T_8213 = or(dcache_kill_mem, take_pc_wb) + node T_8214 = or(T_8213, mem_reg_xcpt) + node T_8216 = eq(mem_reg_valid, UInt<1>("h0")) + node killm_common = or(T_8214, T_8216) + node T_8217 = and(div.io.req.ready, div.io.req.valid) + reg T_8218 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_8218) T_8218 <= T_8217 - node T_8219 = and(killm_common, T_8218) @[rocket.scala 449:31] - div.io.kill <= T_8219 @[rocket.scala 449:15] - node T_8220 = or(killm_common, mem_xcpt) @[rocket.scala 450:33] - node ctrl_killm = or(T_8220, fpu_kill_mem) @[rocket.scala 450:45] - node T_8222 = eq(ctrl_killm, UInt<1>("h00")) @[rocket.scala 453:19] - wb_reg_valid <= T_8222 @[rocket.scala 453:16] - node T_8224 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 454:34] - node T_8225 = and(replay_mem, T_8224) @[rocket.scala 454:31] - wb_reg_replay <= T_8225 @[rocket.scala 454:17] - node T_8227 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 455:30] - node T_8228 = and(mem_xcpt, T_8227) @[rocket.scala 455:27] - wb_reg_xcpt <= T_8228 @[rocket.scala 455:15] - when mem_xcpt : @[rocket.scala 456:19] - wb_reg_cause <= mem_cause @[rocket.scala 456:34] - skip @[rocket.scala 456:19] - node T_8229 = or(mem_reg_valid, mem_reg_replay) @[rocket.scala 457:23] - node T_8230 = or(T_8229, mem_reg_xcpt_interrupt) @[rocket.scala 457:41] - when T_8230 : @[rocket.scala 457:68] - wb_ctrl <- mem_ctrl @[rocket.scala 458:13] - node T_8232 = eq(mem_reg_xcpt, UInt<1>("h00")) @[rocket.scala 459:25] - node T_8233 = and(T_8232, mem_ctrl.fp) @[rocket.scala 459:39] - node T_8234 = and(T_8233, mem_ctrl.wxd) @[rocket.scala 459:54] - node T_8235 = mux(T_8234, io.fpu.toint_data, mem_int_wdata) @[rocket.scala 459:24] - wb_reg_wdata <= T_8235 @[rocket.scala 459:18] - when mem_ctrl.rocc : @[rocket.scala 460:26] - wb_reg_rs2 <= mem_reg_rs2 @[rocket.scala 461:18] - skip @[rocket.scala 460:26] - wb_reg_inst <= mem_reg_inst @[rocket.scala 463:17] - wb_reg_pc <= mem_reg_pc @[rocket.scala 464:15] - skip @[rocket.scala 457:68] - node T_8236 = or(wb_ctrl.div, wb_dcache_miss) @[rocket.scala 467:35] - node wb_set_sboard = or(T_8236, wb_ctrl.rocc) @[rocket.scala 467:53] - node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) @[rocket.scala 468:42] - node T_8237 = and(wb_reg_valid, wb_ctrl.rocc) @[rocket.scala 469:37] - node T_8239 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[rocket.scala 469:56] - node replay_wb_rocc = and(T_8237, T_8239) @[rocket.scala 469:53] - node replay_wb = or(replay_wb_common, replay_wb_rocc) @[rocket.scala 470:36] - node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) @[rocket.scala 471:29] - node T_8240 = or(replay_wb, wb_xcpt) @[rocket.scala 472:27] - node T_8241 = or(T_8240, csr.io.eret) @[rocket.scala 472:38] - take_pc_wb <= T_8241 @[rocket.scala 472:14] - node T_8242 = bits(io.dmem.resp.bits.tag, 0, 0) @[rocket.scala 475:45] - node T_8243 = bits(T_8242, 0, 0) @[rocket.scala 475:49] - node dmem_resp_xpu = eq(T_8243, UInt<1>("h00")) @[rocket.scala 475:23] - node T_8245 = bits(io.dmem.resp.bits.tag, 0, 0) @[rocket.scala 476:45] - node dmem_resp_fpu = bits(T_8245, 0, 0) @[rocket.scala 476:49] - node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) @[rocket.scala 477:46] - node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) @[rocket.scala 478:44] - node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) @[rocket.scala 479:42] - node T_8246 = and(wb_reg_valid, wb_ctrl.wxd) @[rocket.scala 481:39] - node T_8248 = eq(T_8246, UInt<1>("h00")) @[rocket.scala 481:24] - div.io.resp.ready <= T_8248 @[rocket.scala 481:21] + node T_8219 = and(killm_common, T_8218) + div.io.kill <= T_8219 + node T_8220 = or(killm_common, mem_xcpt) + node ctrl_killm = or(T_8220, fpu_kill_mem) + node T_8222 = eq(ctrl_killm, UInt<1>("h0")) + wb_reg_valid <= T_8222 + node T_8224 = eq(take_pc_wb, UInt<1>("h0")) + node T_8225 = and(replay_mem, T_8224) + wb_reg_replay <= T_8225 + node T_8227 = eq(take_pc_wb, UInt<1>("h0")) + node T_8228 = and(mem_xcpt, T_8227) + wb_reg_xcpt <= T_8228 + when mem_xcpt : + wb_reg_cause <= mem_cause + node T_8229 = or(mem_reg_valid, mem_reg_replay) + node T_8230 = or(T_8229, mem_reg_xcpt_interrupt) + when T_8230 : + wb_ctrl <- mem_ctrl + node T_8232 = eq(mem_reg_xcpt, UInt<1>("h0")) + node T_8233 = and(T_8232, mem_ctrl.fp) + node T_8234 = and(T_8233, mem_ctrl.wxd) + node T_8235 = mux(T_8234, io.fpu.toint_data, mem_int_wdata) + wb_reg_wdata <= T_8235 + when mem_ctrl.rocc : + wb_reg_rs2 <= mem_reg_rs2 + wb_reg_inst <= mem_reg_inst + wb_reg_pc <= mem_reg_pc + node T_8236 = or(wb_ctrl.div, wb_dcache_miss) + node wb_set_sboard = or(T_8236, wb_ctrl.rocc) + node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) + node T_8237 = and(wb_reg_valid, wb_ctrl.rocc) + node T_8239 = eq(io.rocc.cmd.ready, UInt<1>("h0")) + node replay_wb_rocc = and(T_8237, T_8239) + node replay_wb = or(replay_wb_common, replay_wb_rocc) + node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) + node T_8240 = or(replay_wb, wb_xcpt) + node T_8241 = or(T_8240, csr.io.eret) + take_pc_wb <= T_8241 + node T_8242 = bits(io.dmem.resp.bits.tag, 0, 0) + node T_8243 = bits(T_8242, 0, 0) + node dmem_resp_xpu = eq(T_8243, UInt<1>("h0")) + node T_8245 = bits(io.dmem.resp.bits.tag, 0, 0) + node dmem_resp_fpu = bits(T_8245, 0, 0) + node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) + node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) + node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) + node T_8246 = and(wb_reg_valid, wb_ctrl.wxd) + node T_8248 = eq(T_8246, UInt<1>("h0")) + div.io.resp.ready <= T_8248 wire ll_wdata : UInt ll_wdata is invalid ll_wdata <= div.io.resp.bits.data wire ll_waddr : UInt ll_waddr is invalid ll_waddr <= div.io.resp.bits.tag - node T_8249 = and(div.io.resp.ready, div.io.resp.valid) @[Decoupled.scala 21:42] + node T_8249 = and(div.io.resp.ready, div.io.resp.valid) wire ll_wen : UInt<1> ll_wen is invalid ll_wen <= T_8249 - node T_8250 = and(dmem_resp_replay, dmem_resp_xpu) @[rocket.scala 494:26] - when T_8250 : @[rocket.scala 494:44] - div.io.resp.ready <= UInt<1>("h00") @[rocket.scala 495:23] - ll_waddr <= dmem_resp_waddr @[rocket.scala 498:14] - ll_wen <= UInt<1>("h01") @[rocket.scala 499:12] - skip @[rocket.scala 494:44] - node T_8254 = eq(replay_wb, UInt<1>("h00")) @[rocket.scala 502:34] - node T_8255 = and(wb_reg_valid, T_8254) @[rocket.scala 502:31] - node T_8257 = eq(wb_xcpt, UInt<1>("h00")) @[rocket.scala 502:48] - node wb_valid = and(T_8255, T_8257) @[rocket.scala 502:45] - node wb_wen = and(wb_valid, wb_ctrl.wxd) @[rocket.scala 503:25] - node rf_wen = or(wb_wen, ll_wen) @[rocket.scala 504:23] - node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[rocket.scala 505:21] - node T_8258 = and(dmem_resp_valid, dmem_resp_xpu) @[rocket.scala 506:38] - node T_8259 = neq(wb_ctrl.csr, UInt<3>("h00")) @[rocket.scala 508:34] - node T_8260 = mux(T_8259, csr.io.rw.rdata, wb_reg_wdata) @[rocket.scala 508:21] - node T_8261 = mux(ll_wen, ll_wdata, T_8260) @[rocket.scala 507:21] - node rf_wdata = mux(T_8258, io.dmem.resp.bits.data, T_8261) @[rocket.scala 506:21] - when rf_wen : @[rocket.scala 510:17] - node T_8263 = neq(rf_waddr, UInt<1>("h00")) @[rocket.scala 115:16] - when T_8263 : @[rocket.scala 115:29] - node T_8264 = bits(rf_waddr, 4, 0) @[rocket.scala 104:44] - node T_8265 = not(T_8264) @[rocket.scala 104:39] + node T_8250 = and(dmem_resp_replay, dmem_resp_xpu) + when T_8250 : + div.io.resp.ready <= UInt<1>("h0") + ll_waddr <= dmem_resp_waddr + ll_wen <= UInt<1>("h1") + node T_8254 = eq(replay_wb, UInt<1>("h0")) + node T_8255 = and(wb_reg_valid, T_8254) + node T_8257 = eq(wb_xcpt, UInt<1>("h0")) + node wb_valid = and(T_8255, T_8257) + node wb_wen = and(wb_valid, wb_ctrl.wxd) + node rf_wen = or(wb_wen, ll_wen) + node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) + node T_8258 = and(dmem_resp_valid, dmem_resp_xpu) + node T_8259 = neq(wb_ctrl.csr, UInt<3>("h0")) + node T_8260 = mux(T_8259, csr.io.rw.rdata, wb_reg_wdata) + node T_8261 = mux(ll_wen, ll_wdata, T_8260) + node rf_wdata = mux(T_8258, io.dmem.resp.bits.data, T_8261) + when rf_wen : + node T_8263 = neq(rf_waddr, UInt<1>("h0")) + when T_8263 : + node T_8264 = bits(rf_waddr, 4, 0) + node T_8265 = not(T_8264) infer mport T_8266 = T_7403[T_8265], clk - T_8266 <= rf_wdata @[rocket.scala 116:20] - node T_8267 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 118:20] - when T_8267 : @[rocket.scala 118:31] - id_rs_0 <= rf_wdata @[rocket.scala 118:39] - skip @[rocket.scala 118:31] - node T_8268 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 118:20] - when T_8268 : @[rocket.scala 118:31] - id_rs_1 <= rf_wdata @[rocket.scala 118:39] - skip @[rocket.scala 118:31] - skip @[rocket.scala 115:29] - skip @[rocket.scala 510:17] - csr.io.exception <= wb_reg_xcpt @[rocket.scala 513:20] - csr.io.cause <= wb_reg_cause @[rocket.scala 514:16] - csr.io.retire <= wb_valid @[rocket.scala 515:17] - csr.io.prci <- io.prci @[rocket.scala 516:15] - io.fpu.fcsr_rm <= csr.io.fcsr_rm @[rocket.scala 517:18] - csr.io.fcsr_flags <- io.fpu.fcsr_flags @[rocket.scala 518:21] - csr.io.rocc.interrupt <= io.rocc.interrupt @[rocket.scala 519:25] - csr.io.pc <= wb_reg_pc @[rocket.scala 520:13] - node T_8269 = shr(wb_reg_wdata, 38) @[rocket.scala 699:16] - node T_8270 = bits(wb_reg_wdata, 39, 38) @[rocket.scala 700:15] - node T_8271 = asSInt(T_8270) @[rocket.scala 700:39] - node T_8273 = eq(T_8269, UInt<1>("h00")) @[rocket.scala 702:13] - node T_8275 = eq(T_8269, UInt<1>("h01")) @[rocket.scala 702:30] - node T_8276 = or(T_8273, T_8275) @[rocket.scala 702:25] - node T_8278 = neq(T_8271, asSInt(UInt<1>("h00"))) @[rocket.scala 702:45] - node T_8279 = asSInt(T_8269) @[rocket.scala 703:13] - node T_8281 = eq(T_8279, asSInt(UInt<1>("h01"))) @[rocket.scala 703:20] - node T_8282 = asSInt(T_8269) @[rocket.scala 703:38] - node T_8284 = eq(T_8282, asSInt(UInt<2>("h02"))) @[rocket.scala 703:45] - node T_8285 = or(T_8281, T_8284) @[rocket.scala 703:33] - node T_8287 = eq(T_8271, asSInt(UInt<1>("h01"))) @[rocket.scala 703:61] - node T_8288 = bits(T_8271, 0, 0) @[rocket.scala 703:76] - node T_8289 = mux(T_8285, T_8287, T_8288) @[rocket.scala 703:10] - node T_8290 = mux(T_8276, T_8278, T_8289) @[rocket.scala 702:10] - node T_8291 = bits(wb_reg_wdata, 38, 0) @[rocket.scala 704:16] - node T_8292 = cat(T_8290, T_8291) @[Cat.scala 20:58] - csr.io.badaddr <= T_8292 @[rocket.scala 521:18] - io.ptw.ptbr <- csr.io.ptbr @[rocket.scala 522:15] - io.ptw.invalidate <= csr.io.fatc @[rocket.scala 523:21] - io.ptw.status <- csr.io.status @[rocket.scala 524:17] - node T_8293 = bits(wb_reg_inst, 31, 20) @[rocket.scala 525:32] - csr.io.rw.addr <= T_8293 @[rocket.scala 525:18] - node T_8294 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) @[rocket.scala 526:23] - csr.io.rw.cmd <= T_8294 @[rocket.scala 526:17] - csr.io.rw.wdata <= wb_reg_wdata @[rocket.scala 527:19] - node T_8296 = neq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[rocket.scala 529:55] - node T_8297 = and(id_ctrl.rxs1, T_8296) @[rocket.scala 529:42] - node T_8299 = neq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[rocket.scala 530:55] - node T_8300 = and(id_ctrl.rxs2, T_8299) @[rocket.scala 530:42] - node T_8302 = neq(ibuf.io.inst[0].bits.inst.rd, UInt<1>("h00")) @[rocket.scala 531:55] - node T_8303 = and(id_ctrl.wxd, T_8302) @[rocket.scala 531:42] - reg T_8305 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) - node T_8306 = shr(T_8305, 1) @[rocket.scala 715:35] - node T_8307 = shl(T_8306, 1) @[rocket.scala 715:40] - node T_8310 = dshl(UInt<1>("h01"), ll_waddr) @[rocket.scala 718:62] - node T_8312 = mux(ll_wen, T_8310, UInt<1>("h00")) @[rocket.scala 718:49] - node T_8313 = not(T_8312) @[rocket.scala 710:64] - node T_8314 = and(T_8307, T_8313) @[rocket.scala 710:62] - node T_8315 = or(UInt<1>("h00"), ll_wen) @[rocket.scala 721:17] - when T_8315 : @[rocket.scala 722:18] - T_8305 <= T_8314 @[rocket.scala 722:23] - skip @[rocket.scala 722:18] - node T_8316 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 711:35] - node T_8317 = bits(T_8316, 0, 0) @[rocket.scala 711:35] - node T_8318 = and(T_8297, T_8317) @[rocket.scala 694:27] - node T_8319 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 711:35] - node T_8320 = bits(T_8319, 0, 0) @[rocket.scala 711:35] - node T_8321 = and(T_8300, T_8320) @[rocket.scala 694:27] - node T_8322 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rd) @[rocket.scala 711:35] - node T_8323 = bits(T_8322, 0, 0) @[rocket.scala 711:35] - node T_8324 = and(T_8303, T_8323) @[rocket.scala 694:27] - node T_8325 = or(T_8318, T_8321) @[rocket.scala 694:50] - node id_sboard_hazard = or(T_8325, T_8324) @[rocket.scala 694:50] - node T_8326 = and(wb_set_sboard, wb_wen) @[rocket.scala 540:28] - node T_8328 = dshl(UInt<1>("h01"), wb_waddr) @[rocket.scala 718:62] - node T_8330 = mux(T_8326, T_8328, UInt<1>("h00")) @[rocket.scala 718:49] - node T_8331 = or(T_8314, T_8330) @[rocket.scala 709:60] - node T_8332 = or(T_8315, T_8326) @[rocket.scala 721:17] - when T_8332 : @[rocket.scala 722:18] - T_8305 <= T_8331 @[rocket.scala 722:23] - skip @[rocket.scala 722:18] - node T_8333 = neq(ex_ctrl.csr, UInt<3>("h00")) @[rocket.scala 543:38] - node T_8334 = or(T_8333, ex_ctrl.jalr) @[rocket.scala 543:48] - node T_8335 = or(T_8334, ex_ctrl.mem) @[rocket.scala 543:64] - node T_8336 = or(T_8335, ex_ctrl.div) @[rocket.scala 543:79] - node T_8337 = or(T_8336, ex_ctrl.fp) @[rocket.scala 543:94] - node ex_cannot_bypass = or(T_8337, ex_ctrl.rocc) @[rocket.scala 543:108] - node T_8338 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[rocket.scala 544:70] - node T_8339 = and(T_8297, T_8338) @[rocket.scala 694:27] - node T_8340 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[rocket.scala 544:70] - node T_8341 = and(T_8300, T_8340) @[rocket.scala 694:27] - node T_8342 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[rocket.scala 544:70] - node T_8343 = and(T_8303, T_8342) @[rocket.scala 694:27] - node T_8344 = or(T_8339, T_8341) @[rocket.scala 694:50] - node T_8345 = or(T_8344, T_8343) @[rocket.scala 694:50] - node data_hazard_ex = and(ex_ctrl.wxd, T_8345) @[rocket.scala 544:36] - node T_8346 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[rocket.scala 545:76] - node T_8347 = and(io.fpu.dec.ren1, T_8346) @[rocket.scala 694:27] - node T_8348 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[rocket.scala 545:76] - node T_8349 = and(io.fpu.dec.ren2, T_8348) @[rocket.scala 694:27] - node T_8350 = eq(ibuf.io.inst[0].bits.inst.rs3, ex_waddr) @[rocket.scala 545:76] - node T_8351 = and(io.fpu.dec.ren3, T_8350) @[rocket.scala 694:27] - node T_8352 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[rocket.scala 545:76] - node T_8353 = and(io.fpu.dec.wen, T_8352) @[rocket.scala 694:27] - node T_8354 = or(T_8347, T_8349) @[rocket.scala 694:50] - node T_8355 = or(T_8354, T_8351) @[rocket.scala 694:50] - node T_8356 = or(T_8355, T_8353) @[rocket.scala 694:50] - node fp_data_hazard_ex = and(ex_ctrl.wfd, T_8356) @[rocket.scala 545:39] - node T_8357 = and(data_hazard_ex, ex_cannot_bypass) @[rocket.scala 546:54] - node T_8358 = or(T_8357, fp_data_hazard_ex) @[rocket.scala 546:74] - node id_ex_hazard = and(ex_reg_valid, T_8358) @[rocket.scala 546:35] - node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) @[rocket.scala 550:43] - node T_8360 = neq(mem_ctrl.csr, UInt<3>("h00")) @[rocket.scala 552:40] - node T_8361 = and(mem_ctrl.mem, mem_mem_cmd_bh) @[rocket.scala 552:66] - node T_8362 = or(T_8360, T_8361) @[rocket.scala 552:50] - node T_8363 = or(T_8362, mem_ctrl.div) @[rocket.scala 552:84] - node T_8364 = or(T_8363, mem_ctrl.fp) @[rocket.scala 552:100] - node mem_cannot_bypass = or(T_8364, mem_ctrl.rocc) @[rocket.scala 552:115] - node T_8365 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[rocket.scala 553:72] - node T_8366 = and(T_8297, T_8365) @[rocket.scala 694:27] - node T_8367 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[rocket.scala 553:72] - node T_8368 = and(T_8300, T_8367) @[rocket.scala 694:27] - node T_8369 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[rocket.scala 553:72] - node T_8370 = and(T_8303, T_8369) @[rocket.scala 694:27] - node T_8371 = or(T_8366, T_8368) @[rocket.scala 694:50] - node T_8372 = or(T_8371, T_8370) @[rocket.scala 694:50] - node data_hazard_mem = and(mem_ctrl.wxd, T_8372) @[rocket.scala 553:38] - node T_8373 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[rocket.scala 554:78] - node T_8374 = and(io.fpu.dec.ren1, T_8373) @[rocket.scala 694:27] - node T_8375 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[rocket.scala 554:78] - node T_8376 = and(io.fpu.dec.ren2, T_8375) @[rocket.scala 694:27] - node T_8377 = eq(ibuf.io.inst[0].bits.inst.rs3, mem_waddr) @[rocket.scala 554:78] - node T_8378 = and(io.fpu.dec.ren3, T_8377) @[rocket.scala 694:27] - node T_8379 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[rocket.scala 554:78] - node T_8380 = and(io.fpu.dec.wen, T_8379) @[rocket.scala 694:27] - node T_8381 = or(T_8374, T_8376) @[rocket.scala 694:50] - node T_8382 = or(T_8381, T_8378) @[rocket.scala 694:50] - node T_8383 = or(T_8382, T_8380) @[rocket.scala 694:50] - node fp_data_hazard_mem = and(mem_ctrl.wfd, T_8383) @[rocket.scala 554:41] - node T_8384 = and(data_hazard_mem, mem_cannot_bypass) @[rocket.scala 555:57] - node T_8385 = or(T_8384, fp_data_hazard_mem) @[rocket.scala 555:78] - node id_mem_hazard = and(mem_reg_valid, T_8385) @[rocket.scala 555:37] - node T_8386 = and(mem_reg_valid, data_hazard_mem) @[rocket.scala 556:32] - node T_8387 = and(T_8386, mem_ctrl.mem) @[rocket.scala 556:51] - id_load_use <= T_8387 @[rocket.scala 556:15] - node T_8388 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[rocket.scala 559:70] - node T_8389 = and(T_8297, T_8388) @[rocket.scala 694:27] - node T_8390 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[rocket.scala 559:70] - node T_8391 = and(T_8300, T_8390) @[rocket.scala 694:27] - node T_8392 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[rocket.scala 559:70] - node T_8393 = and(T_8303, T_8392) @[rocket.scala 694:27] - node T_8394 = or(T_8389, T_8391) @[rocket.scala 694:50] - node T_8395 = or(T_8394, T_8393) @[rocket.scala 694:50] - node data_hazard_wb = and(wb_ctrl.wxd, T_8395) @[rocket.scala 559:36] - node T_8396 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[rocket.scala 560:76] - node T_8397 = and(io.fpu.dec.ren1, T_8396) @[rocket.scala 694:27] - node T_8398 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[rocket.scala 560:76] - node T_8399 = and(io.fpu.dec.ren2, T_8398) @[rocket.scala 694:27] - node T_8400 = eq(ibuf.io.inst[0].bits.inst.rs3, wb_waddr) @[rocket.scala 560:76] - node T_8401 = and(io.fpu.dec.ren3, T_8400) @[rocket.scala 694:27] - node T_8402 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[rocket.scala 560:76] - node T_8403 = and(io.fpu.dec.wen, T_8402) @[rocket.scala 694:27] - node T_8404 = or(T_8397, T_8399) @[rocket.scala 694:50] - node T_8405 = or(T_8404, T_8401) @[rocket.scala 694:50] - node T_8406 = or(T_8405, T_8403) @[rocket.scala 694:50] - node fp_data_hazard_wb = and(wb_ctrl.wfd, T_8406) @[rocket.scala 560:39] - node T_8407 = and(data_hazard_wb, wb_set_sboard) @[rocket.scala 561:54] - node T_8408 = or(T_8407, fp_data_hazard_wb) @[rocket.scala 561:71] - node id_wb_hazard = and(wb_reg_valid, T_8408) @[rocket.scala 561:35] - reg T_8410 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) - node T_8412 = and(wb_dcache_miss, wb_ctrl.wfd) @[rocket.scala 565:35] - node T_8413 = or(T_8412, io.fpu.sboard_set) @[rocket.scala 565:50] - node T_8414 = and(T_8413, wb_valid) @[rocket.scala 565:72] - node T_8416 = dshl(UInt<1>("h01"), wb_waddr) @[rocket.scala 718:62] - node T_8418 = mux(T_8414, T_8416, UInt<1>("h00")) @[rocket.scala 718:49] - node T_8419 = or(T_8410, T_8418) @[rocket.scala 709:60] - node T_8420 = or(UInt<1>("h00"), T_8414) @[rocket.scala 721:17] - when T_8420 : @[rocket.scala 722:18] - T_8410 <= T_8419 @[rocket.scala 722:23] - skip @[rocket.scala 722:18] - node T_8421 = and(dmem_resp_replay, dmem_resp_fpu) @[rocket.scala 566:38] - node T_8423 = dshl(UInt<1>("h01"), dmem_resp_waddr) @[rocket.scala 718:62] - node T_8425 = mux(T_8421, T_8423, UInt<1>("h00")) @[rocket.scala 718:49] - node T_8426 = not(T_8425) @[rocket.scala 710:64] - node T_8427 = and(T_8419, T_8426) @[rocket.scala 710:62] - node T_8428 = or(T_8420, T_8421) @[rocket.scala 721:17] - when T_8428 : @[rocket.scala 722:18] - T_8410 <= T_8427 @[rocket.scala 722:23] - skip @[rocket.scala 722:18] - node T_8430 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) @[rocket.scala 718:62] - node T_8432 = mux(io.fpu.sboard_clr, T_8430, UInt<1>("h00")) @[rocket.scala 718:49] - node T_8433 = not(T_8432) @[rocket.scala 710:64] - node T_8434 = and(T_8427, T_8433) @[rocket.scala 710:62] - node T_8435 = or(T_8428, io.fpu.sboard_clr) @[rocket.scala 721:17] - when T_8435 : @[rocket.scala 722:18] - T_8410 <= T_8434 @[rocket.scala 722:23] - skip @[rocket.scala 722:18] - node T_8437 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) @[rocket.scala 569:18] - node T_8438 = and(id_csr_en, T_8437) @[rocket.scala 569:15] - node T_8439 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs1) @[rocket.scala 711:35] - node T_8440 = bits(T_8439, 0, 0) @[rocket.scala 711:35] - node T_8441 = and(io.fpu.dec.ren1, T_8440) @[rocket.scala 694:27] - node T_8442 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs2) @[rocket.scala 711:35] - node T_8443 = bits(T_8442, 0, 0) @[rocket.scala 711:35] - node T_8444 = and(io.fpu.dec.ren2, T_8443) @[rocket.scala 694:27] - node T_8445 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs3) @[rocket.scala 711:35] - node T_8446 = bits(T_8445, 0, 0) @[rocket.scala 711:35] - node T_8447 = and(io.fpu.dec.ren3, T_8446) @[rocket.scala 694:27] - node T_8448 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rd) @[rocket.scala 711:35] - node T_8449 = bits(T_8448, 0, 0) @[rocket.scala 711:35] - node T_8450 = and(io.fpu.dec.wen, T_8449) @[rocket.scala 694:27] - node T_8451 = or(T_8441, T_8444) @[rocket.scala 694:50] - node T_8452 = or(T_8451, T_8447) @[rocket.scala 694:50] - node T_8453 = or(T_8452, T_8450) @[rocket.scala 694:50] - node id_stall_fpu = or(T_8438, T_8453) @[rocket.scala 569:35] - reg dcache_blocked : UInt<1>, clk - node T_8456 = eq(io.dmem.req.ready, UInt<1>("h00")) @[rocket.scala 573:21] - node T_8457 = or(io.dmem.req.valid, dcache_blocked) @[rocket.scala 573:62] - node T_8458 = and(T_8456, T_8457) @[rocket.scala 573:40] - dcache_blocked <= T_8458 @[rocket.scala 573:18] - reg rocc_blocked : UInt<1>, clk - node T_8461 = eq(wb_reg_xcpt, UInt<1>("h00")) @[rocket.scala 575:19] - node T_8463 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[rocket.scala 575:35] - node T_8464 = and(T_8461, T_8463) @[rocket.scala 575:32] - node T_8465 = or(io.rocc.cmd.valid, rocc_blocked) @[rocket.scala 575:76] - node T_8466 = and(T_8464, T_8465) @[rocket.scala 575:54] - rocc_blocked <= T_8466 @[rocket.scala 575:16] - node T_8467 = or(id_ex_hazard, id_mem_hazard) @[rocket.scala 578:18] - node T_8468 = or(T_8467, id_wb_hazard) @[rocket.scala 578:35] - node T_8469 = or(T_8468, id_sboard_hazard) @[rocket.scala 578:51] - node T_8470 = and(id_ctrl.fp, id_stall_fpu) @[rocket.scala 579:16] - node T_8471 = or(T_8469, T_8470) @[rocket.scala 578:71] - node T_8472 = and(id_ctrl.mem, dcache_blocked) @[rocket.scala 580:17] - node T_8473 = or(T_8471, T_8472) @[rocket.scala 579:32] - node T_8474 = and(id_ctrl.rocc, rocc_blocked) @[rocket.scala 581:18] - node T_8475 = or(T_8473, T_8474) @[rocket.scala 580:35] - node T_8476 = or(T_8475, id_do_fence) @[rocket.scala 581:34] - node ctrl_stalld = or(T_8476, csr.io.csr_stall) @[rocket.scala 582:17] - node T_8478 = eq(ibuf.io.inst[0].valid, UInt<1>("h00")) @[rocket.scala 584:17] - node T_8479 = or(T_8478, ibuf.io.inst[0].bits.replay) @[rocket.scala 584:40] - node T_8480 = or(T_8479, take_pc_mem_wb) @[rocket.scala 584:71] - node T_8481 = or(T_8480, ctrl_stalld) @[rocket.scala 584:89] - node T_8482 = or(T_8481, csr.io.interrupt) @[rocket.scala 584:104] - ctrl_killd <= T_8482 @[rocket.scala 584:14] - io.imem.req.valid <= take_pc @[rocket.scala 586:21] - node T_8484 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 587:35] - io.imem.req.bits.speculative <= T_8484 @[rocket.scala 587:32] - node T_8485 = or(wb_xcpt, csr.io.eret) @[rocket.scala 589:17] - node T_8487 = or(take_pc_mem, UInt<1>("h01")) @[rocket.scala 591:21] - node T_8488 = mux(T_8487, mem_npc, id_npc) @[rocket.scala 591:8] - node T_8489 = mux(replay_wb, wb_reg_pc, T_8488) @[rocket.scala 590:8] - node T_8490 = mux(T_8485, csr.io.evec, T_8489) @[rocket.scala 589:8] - io.imem.req.bits.pc <= T_8490 @[rocket.scala 588:23] - node T_8491 = and(wb_reg_valid, wb_ctrl.fence_i) @[rocket.scala 593:40] - node T_8493 = eq(io.dmem.s2_nack, UInt<1>("h00")) @[rocket.scala 593:62] - node T_8494 = and(T_8491, T_8493) @[rocket.scala 593:59] - io.imem.flush_icache <= T_8494 @[rocket.scala 593:24] - io.imem.flush_tlb <= csr.io.fatc @[rocket.scala 594:21] - node T_8496 = eq(ctrl_stalld, UInt<1>("h00")) @[rocket.scala 596:28] - node T_8497 = or(T_8496, csr.io.interrupt) @[rocket.scala 596:41] - ibuf.io.inst[0].ready <= T_8497 @[rocket.scala 596:25] - node T_8498 = and(mem_reg_replay, mem_reg_btb_hit) @[rocket.scala 598:47] - node T_8500 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 598:88] - node T_8501 = and(mem_reg_valid, T_8500) @[rocket.scala 598:85] - node T_8503 = eq(mem_cfi, UInt<1>("h00")) @[rocket.scala 598:123] - node T_8504 = or(mem_cfi_taken, T_8503) @[rocket.scala 598:120] - node T_8505 = and(T_8504, mem_wrong_npc) @[rocket.scala 598:133] - node T_8507 = and(UInt<1>("h00"), mem_ctrl.jal) @[rocket.scala 598:169] - node T_8509 = eq(mem_reg_btb_hit, UInt<1>("h00")) @[rocket.scala 598:188] - node T_8510 = and(T_8507, T_8509) @[rocket.scala 598:185] - node T_8511 = or(T_8505, T_8510) @[rocket.scala 598:151] - node T_8512 = and(T_8501, T_8511) @[rocket.scala 598:100] - node T_8513 = or(T_8498, T_8512) @[rocket.scala 598:67] - io.imem.btb_update.valid <= T_8513 @[rocket.scala 598:28] - node T_8515 = eq(mem_reg_replay, UInt<1>("h00")) @[rocket.scala 599:38] - node T_8516 = and(T_8515, mem_cfi) @[rocket.scala 599:54] - io.imem.btb_update.bits.isValid <= T_8516 @[rocket.scala 599:35] - node T_8517 = or(mem_ctrl.jal, mem_ctrl.jalr) @[rocket.scala 600:50] - io.imem.btb_update.bits.isJump <= T_8517 @[rocket.scala 600:34] - node T_8518 = bits(mem_reg_inst, 19, 15) @[rocket.scala 601:68] - node T_8521 = and(T_8518, UInt<5>("h019")) @[rocket.scala 601:76] - node T_8522 = eq(UInt<5>("h01"), T_8521) @[rocket.scala 601:76] - node T_8523 = and(mem_ctrl.jalr, T_8522) @[rocket.scala 601:53] - io.imem.btb_update.bits.isReturn <= T_8523 @[rocket.scala 601:36] - io.imem.btb_update.bits.target <= io.imem.req.bits.pc @[rocket.scala 602:34] - node T_8526 = mux(mem_reg_rvc, UInt<1>("h00"), UInt<2>("h02")) @[rocket.scala 603:74] - node T_8527 = add(mem_reg_pc, T_8526) @[rocket.scala 603:69] - node T_8528 = tail(T_8527, 1) @[rocket.scala 603:69] - io.imem.btb_update.bits.br_pc <= T_8528 @[rocket.scala 603:33] - node T_8529 = not(io.imem.btb_update.bits.br_pc) @[rocket.scala 604:35] - node T_8531 = or(T_8529, UInt<2>("h03")) @[rocket.scala 604:66] - node T_8532 = not(T_8531) @[rocket.scala 604:33] - io.imem.btb_update.bits.pc <= T_8532 @[rocket.scala 604:30] - io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit @[rocket.scala 605:44] - io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp @[rocket.scala 606:43] - node T_8534 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 608:48] - node T_8535 = and(mem_reg_valid, T_8534) @[rocket.scala 608:45] - node T_8536 = and(T_8535, mem_ctrl.branch) @[rocket.scala 608:60] - io.imem.bht_update.valid <= T_8536 @[rocket.scala 608:28] - io.imem.bht_update.bits.pc <= io.imem.btb_update.bits.pc @[rocket.scala 609:30] - io.imem.bht_update.bits.taken <= mem_br_taken @[rocket.scala 610:33] - io.imem.bht_update.bits.mispredict <= mem_wrong_npc @[rocket.scala 611:38] - io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction @[rocket.scala 612:38] - node T_8538 = eq(take_pc_wb, UInt<1>("h00")) @[rocket.scala 614:48] - node T_8539 = and(mem_reg_valid, T_8538) @[rocket.scala 614:45] - io.imem.ras_update.valid <= T_8539 @[rocket.scala 614:28] - io.imem.ras_update.bits.returnAddr <= mem_int_wdata @[rocket.scala 615:38] - node T_8540 = bits(mem_waddr, 0, 0) @[rocket.scala 616:80] - node T_8541 = and(io.imem.btb_update.bits.isJump, T_8540) @[rocket.scala 616:68] - io.imem.ras_update.bits.isCall <= T_8541 @[rocket.scala 616:34] - io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn @[rocket.scala 617:36] - io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction @[rocket.scala 618:38] - node T_8543 = eq(ctrl_killd, UInt<1>("h00")) @[rocket.scala 620:19] - node T_8544 = and(T_8543, id_ctrl.fp) @[rocket.scala 620:31] - io.fpu.valid <= T_8544 @[rocket.scala 620:16] - io.fpu.killx <= ctrl_killx @[rocket.scala 621:16] - io.fpu.killm <= killm_common @[rocket.scala 622:16] - io.fpu.inst <= ibuf.io.inst[0].bits.inst.bits @[rocket.scala 623:15] - io.fpu.fromint_data <= ex_rs_0 @[rocket.scala 624:23] - node T_8545 = and(dmem_resp_valid, dmem_resp_fpu) @[rocket.scala 625:43] - io.fpu.dmem_resp_val <= T_8545 @[rocket.scala 625:24] - io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass @[rocket.scala 626:25] - io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ @[rocket.scala 627:25] - io.fpu.dmem_resp_tag <= dmem_resp_waddr @[rocket.scala 628:24] - node T_8546 = and(ex_reg_valid, ex_ctrl.mem) @[rocket.scala 630:41] - io.dmem.req.valid <= T_8546 @[rocket.scala 630:25] - node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) @[Cat.scala 20:58] - io.dmem.req.bits.tag <= ex_dcache_tag @[rocket.scala 633:25] - io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd @[rocket.scala 634:25] - io.dmem.req.bits.typ <= ex_ctrl.mem_type @[rocket.scala 635:25] - io.dmem.req.bits.phys <= UInt<1>("h00") @[rocket.scala 636:25] - node T_8548 = shr(ex_rs_0, 38) @[rocket.scala 699:16] - node T_8549 = bits(alu.io.adder_out, 39, 38) @[rocket.scala 700:15] - node T_8550 = asSInt(T_8549) @[rocket.scala 700:39] - node T_8552 = eq(T_8548, UInt<1>("h00")) @[rocket.scala 702:13] - node T_8554 = eq(T_8548, UInt<1>("h01")) @[rocket.scala 702:30] - node T_8555 = or(T_8552, T_8554) @[rocket.scala 702:25] - node T_8557 = neq(T_8550, asSInt(UInt<1>("h00"))) @[rocket.scala 702:45] - node T_8558 = asSInt(T_8548) @[rocket.scala 703:13] - node T_8560 = eq(T_8558, asSInt(UInt<1>("h01"))) @[rocket.scala 703:20] - node T_8561 = asSInt(T_8548) @[rocket.scala 703:38] - node T_8563 = eq(T_8561, asSInt(UInt<2>("h02"))) @[rocket.scala 703:45] - node T_8564 = or(T_8560, T_8563) @[rocket.scala 703:33] - node T_8566 = eq(T_8550, asSInt(UInt<1>("h01"))) @[rocket.scala 703:61] - node T_8567 = bits(T_8550, 0, 0) @[rocket.scala 703:76] - node T_8568 = mux(T_8564, T_8566, T_8567) @[rocket.scala 703:10] - node T_8569 = mux(T_8555, T_8557, T_8568) @[rocket.scala 702:10] - node T_8570 = bits(alu.io.adder_out, 38, 0) @[rocket.scala 704:16] - node T_8571 = cat(T_8569, T_8570) @[Cat.scala 20:58] - io.dmem.req.bits.addr <= T_8571 @[rocket.scala 637:25] - io.dmem.invalidate_lr <= wb_xcpt @[rocket.scala 638:25] - node T_8572 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) @[rocket.scala 639:25] - io.dmem.s1_data <= T_8572 @[rocket.scala 639:19] - node T_8573 = or(killm_common, mem_breakpoint) @[rocket.scala 640:35] - io.dmem.s1_kill <= T_8573 @[rocket.scala 640:19] - node T_8574 = and(mem_ctrl.mem, mem_xcpt) @[rocket.scala 641:22] - node T_8576 = eq(io.dmem.s1_kill, UInt<1>("h00")) @[rocket.scala 641:37] - node T_8577 = and(T_8574, T_8576) @[rocket.scala 641:34] - when T_8577 : @[rocket.scala 641:55] - node T_8578 = cat(io.dmem.xcpt.pf.ld, io.dmem.xcpt.pf.st) @[rocket.scala 642:25] - node T_8579 = cat(io.dmem.xcpt.ma.ld, io.dmem.xcpt.ma.st) @[rocket.scala 642:25] - node T_8580 = cat(T_8579, T_8578) @[rocket.scala 642:25] - node T_8582 = neq(T_8580, UInt<1>("h00")) @[rocket.scala 642:32] - node T_8583 = or(T_8582, reset) @[rocket.scala 642:11] - node T_8585 = eq(T_8583, UInt<1>("h00")) @[rocket.scala 642:11] - when T_8585 : @[rocket.scala 642:11] - printf(clk, UInt<1>(1), "Assertion failed\n at rocket.scala:642 assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive\n") @[rocket.scala 642:11] - stop(clk, UInt<1>(1), 1) @[rocket.scala 642:11] - skip @[rocket.scala 642:11] - skip @[rocket.scala 641:55] - node T_8586 = and(wb_reg_valid, wb_ctrl.rocc) @[rocket.scala 645:37] - node T_8588 = eq(replay_wb_common, UInt<1>("h00")) @[rocket.scala 645:56] - node T_8589 = and(T_8586, T_8588) @[rocket.scala 645:53] - io.rocc.cmd.valid <= T_8589 @[rocket.scala 645:21] - node T_8591 = neq(csr.io.status.xs, UInt<1>("h00")) @[rocket.scala 646:52] - node T_8592 = and(wb_xcpt, T_8591) @[rocket.scala 646:32] - io.rocc.exception <= T_8592 @[rocket.scala 646:21] - io.rocc.cmd.bits.status <- csr.io.status @[rocket.scala 647:27] - wire T_8611 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} @[rocket.scala 648:58] - T_8611 is invalid @[rocket.scala 648:58] + T_8266 <= rf_wdata + node T_8267 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs1) + when T_8267 : + id_rs_0 <= rf_wdata + node T_8268 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs2) + when T_8268 : + id_rs_1 <= rf_wdata + csr.io.exception <= wb_reg_xcpt + csr.io.cause <= wb_reg_cause + csr.io.retire <= wb_valid + csr.io.prci <- io.prci + io.fpu.fcsr_rm <= csr.io.fcsr_rm + csr.io.fcsr_flags <- io.fpu.fcsr_flags + csr.io.rocc.interrupt <= io.rocc.interrupt + csr.io.pc <= wb_reg_pc + node T_8269 = shr(wb_reg_wdata, 38) + node T_8270 = bits(wb_reg_wdata, 39, 38) + node T_8271 = asSInt(T_8270) + node T_8273 = eq(T_8269, UInt<1>("h0")) + node T_8275 = eq(T_8269, UInt<1>("h1")) + node T_8276 = or(T_8273, T_8275) + node T_8278 = neq(T_8271, asSInt(UInt<1>("h0"))) + node T_8279 = asSInt(T_8269) + node T_8281 = eq(T_8279, asSInt(UInt<1>("h1"))) + node T_8282 = asSInt(T_8269) + node T_8284 = eq(T_8282, asSInt(UInt<2>("h2"))) + node T_8285 = or(T_8281, T_8284) + node T_8287 = eq(T_8271, asSInt(UInt<1>("h1"))) + node T_8288 = bits(T_8271, 0, 0) + node T_8289 = mux(T_8285, T_8287, T_8288) + node T_8290 = mux(T_8276, T_8278, T_8289) + node T_8291 = bits(wb_reg_wdata, 38, 0) + node T_8292 = cat(T_8290, T_8291) + csr.io.badaddr <= T_8292 + io.ptw.ptbr <- csr.io.ptbr + io.ptw.invalidate <= csr.io.fatc + io.ptw.status <- csr.io.status + node T_8293 = bits(wb_reg_inst, 31, 20) + csr.io.rw.addr <= T_8293 + node T_8294 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h0")) + csr.io.rw.cmd <= T_8294 + csr.io.rw.wdata <= wb_reg_wdata + node T_8296 = neq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h0")) + node T_8297 = and(id_ctrl.rxs1, T_8296) + node T_8299 = neq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h0")) + node T_8300 = and(id_ctrl.rxs2, T_8299) + node T_8302 = neq(ibuf.io.inst[0].bits.inst.rd, UInt<1>("h0")) + node T_8303 = and(id_ctrl.wxd, T_8302) + reg T_8305 : UInt<32>, clk with : + reset => (reset, UInt<32>("h0")) + node T_8306 = shr(T_8305, 1) + node T_8307 = shl(T_8306, 1) + node T_8310 = dshl(UInt<1>("h1"), ll_waddr) + node T_8312 = mux(ll_wen, T_8310, UInt<1>("h0")) + node T_8313 = not(T_8312) + node T_8314 = and(T_8307, T_8313) + node T_8315 = or(UInt<1>("h0"), ll_wen) + when T_8315 : + T_8305 <= T_8314 + node T_8316 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rs1) + node T_8317 = bits(T_8316, 0, 0) + node T_8318 = and(T_8297, T_8317) + node T_8319 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rs2) + node T_8320 = bits(T_8319, 0, 0) + node T_8321 = and(T_8300, T_8320) + node T_8322 = dshr(T_8307, ibuf.io.inst[0].bits.inst.rd) + node T_8323 = bits(T_8322, 0, 0) + node T_8324 = and(T_8303, T_8323) + node T_8325 = or(T_8318, T_8321) + node id_sboard_hazard = or(T_8325, T_8324) + node T_8326 = and(wb_set_sboard, wb_wen) + node T_8328 = dshl(UInt<1>("h1"), wb_waddr) + node T_8330 = mux(T_8326, T_8328, UInt<1>("h0")) + node T_8331 = or(T_8314, T_8330) + node T_8332 = or(T_8315, T_8326) + when T_8332 : + T_8305 <= T_8331 + node T_8333 = neq(ex_ctrl.csr, UInt<3>("h0")) + node T_8334 = or(T_8333, ex_ctrl.jalr) + node T_8335 = or(T_8334, ex_ctrl.mem) + node T_8336 = or(T_8335, ex_ctrl.div) + node T_8337 = or(T_8336, ex_ctrl.fp) + node ex_cannot_bypass = or(T_8337, ex_ctrl.rocc) + node T_8338 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) + node T_8339 = and(T_8297, T_8338) + node T_8340 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) + node T_8341 = and(T_8300, T_8340) + node T_8342 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) + node T_8343 = and(T_8303, T_8342) + node T_8344 = or(T_8339, T_8341) + node T_8345 = or(T_8344, T_8343) + node data_hazard_ex = and(ex_ctrl.wxd, T_8345) + node T_8346 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) + node T_8347 = and(io.fpu.dec.ren1, T_8346) + node T_8348 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) + node T_8349 = and(io.fpu.dec.ren2, T_8348) + node T_8350 = eq(ibuf.io.inst[0].bits.inst.rs3, ex_waddr) + node T_8351 = and(io.fpu.dec.ren3, T_8350) + node T_8352 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) + node T_8353 = and(io.fpu.dec.wen, T_8352) + node T_8354 = or(T_8347, T_8349) + node T_8355 = or(T_8354, T_8351) + node T_8356 = or(T_8355, T_8353) + node fp_data_hazard_ex = and(ex_ctrl.wfd, T_8356) + node T_8357 = and(data_hazard_ex, ex_cannot_bypass) + node T_8358 = or(T_8357, fp_data_hazard_ex) + node id_ex_hazard = and(ex_reg_valid, T_8358) + node mem_mem_cmd_bh = and(UInt<1>("h1"), mem_reg_slow_bypass) + node T_8360 = neq(mem_ctrl.csr, UInt<3>("h0")) + node T_8361 = and(mem_ctrl.mem, mem_mem_cmd_bh) + node T_8362 = or(T_8360, T_8361) + node T_8363 = or(T_8362, mem_ctrl.div) + node T_8364 = or(T_8363, mem_ctrl.fp) + node mem_cannot_bypass = or(T_8364, mem_ctrl.rocc) + node T_8365 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) + node T_8366 = and(T_8297, T_8365) + node T_8367 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) + node T_8368 = and(T_8300, T_8367) + node T_8369 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) + node T_8370 = and(T_8303, T_8369) + node T_8371 = or(T_8366, T_8368) + node T_8372 = or(T_8371, T_8370) + node data_hazard_mem = and(mem_ctrl.wxd, T_8372) + node T_8373 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) + node T_8374 = and(io.fpu.dec.ren1, T_8373) + node T_8375 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) + node T_8376 = and(io.fpu.dec.ren2, T_8375) + node T_8377 = eq(ibuf.io.inst[0].bits.inst.rs3, mem_waddr) + node T_8378 = and(io.fpu.dec.ren3, T_8377) + node T_8379 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) + node T_8380 = and(io.fpu.dec.wen, T_8379) + node T_8381 = or(T_8374, T_8376) + node T_8382 = or(T_8381, T_8378) + node T_8383 = or(T_8382, T_8380) + node fp_data_hazard_mem = and(mem_ctrl.wfd, T_8383) + node T_8384 = and(data_hazard_mem, mem_cannot_bypass) + node T_8385 = or(T_8384, fp_data_hazard_mem) + node id_mem_hazard = and(mem_reg_valid, T_8385) + node T_8386 = and(mem_reg_valid, data_hazard_mem) + node T_8387 = and(T_8386, mem_ctrl.mem) + id_load_use <= T_8387 + node T_8388 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) + node T_8389 = and(T_8297, T_8388) + node T_8390 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) + node T_8391 = and(T_8300, T_8390) + node T_8392 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) + node T_8393 = and(T_8303, T_8392) + node T_8394 = or(T_8389, T_8391) + node T_8395 = or(T_8394, T_8393) + node data_hazard_wb = and(wb_ctrl.wxd, T_8395) + node T_8396 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) + node T_8397 = and(io.fpu.dec.ren1, T_8396) + node T_8398 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) + node T_8399 = and(io.fpu.dec.ren2, T_8398) + node T_8400 = eq(ibuf.io.inst[0].bits.inst.rs3, wb_waddr) + node T_8401 = and(io.fpu.dec.ren3, T_8400) + node T_8402 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) + node T_8403 = and(io.fpu.dec.wen, T_8402) + node T_8404 = or(T_8397, T_8399) + node T_8405 = or(T_8404, T_8401) + node T_8406 = or(T_8405, T_8403) + node fp_data_hazard_wb = and(wb_ctrl.wfd, T_8406) + node T_8407 = and(data_hazard_wb, wb_set_sboard) + node T_8408 = or(T_8407, fp_data_hazard_wb) + node id_wb_hazard = and(wb_reg_valid, T_8408) + reg T_8410 : UInt<32>, clk with : + reset => (reset, UInt<32>("h0")) + node T_8412 = and(wb_dcache_miss, wb_ctrl.wfd) + node T_8413 = or(T_8412, io.fpu.sboard_set) + node T_8414 = and(T_8413, wb_valid) + node T_8416 = dshl(UInt<1>("h1"), wb_waddr) + node T_8418 = mux(T_8414, T_8416, UInt<1>("h0")) + node T_8419 = or(T_8410, T_8418) + node T_8420 = or(UInt<1>("h0"), T_8414) + when T_8420 : + T_8410 <= T_8419 + node T_8421 = and(dmem_resp_replay, dmem_resp_fpu) + node T_8423 = dshl(UInt<1>("h1"), dmem_resp_waddr) + node T_8425 = mux(T_8421, T_8423, UInt<1>("h0")) + node T_8426 = not(T_8425) + node T_8427 = and(T_8419, T_8426) + node T_8428 = or(T_8420, T_8421) + when T_8428 : + T_8410 <= T_8427 + node T_8430 = dshl(UInt<1>("h1"), io.fpu.sboard_clra) + node T_8432 = mux(io.fpu.sboard_clr, T_8430, UInt<1>("h0")) + node T_8433 = not(T_8432) + node T_8434 = and(T_8427, T_8433) + node T_8435 = or(T_8428, io.fpu.sboard_clr) + when T_8435 : + T_8410 <= T_8434 + node T_8437 = eq(io.fpu.fcsr_rdy, UInt<1>("h0")) + node T_8438 = and(id_csr_en, T_8437) + node T_8439 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs1) + node T_8440 = bits(T_8439, 0, 0) + node T_8441 = and(io.fpu.dec.ren1, T_8440) + node T_8442 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs2) + node T_8443 = bits(T_8442, 0, 0) + node T_8444 = and(io.fpu.dec.ren2, T_8443) + node T_8445 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rs3) + node T_8446 = bits(T_8445, 0, 0) + node T_8447 = and(io.fpu.dec.ren3, T_8446) + node T_8448 = dshr(T_8410, ibuf.io.inst[0].bits.inst.rd) + node T_8449 = bits(T_8448, 0, 0) + node T_8450 = and(io.fpu.dec.wen, T_8449) + node T_8451 = or(T_8441, T_8444) + node T_8452 = or(T_8451, T_8447) + node T_8453 = or(T_8452, T_8450) + node id_stall_fpu = or(T_8438, T_8453) + reg dcache_blocked : UInt<1>, clk with : + reset => (UInt<1>("h0"), dcache_blocked) + node T_8456 = eq(io.dmem.req.ready, UInt<1>("h0")) + node T_8457 = or(io.dmem.req.valid, dcache_blocked) + node T_8458 = and(T_8456, T_8457) + dcache_blocked <= T_8458 + reg rocc_blocked : UInt<1>, clk with : + reset => (UInt<1>("h0"), rocc_blocked) + node T_8461 = eq(wb_reg_xcpt, UInt<1>("h0")) + node T_8463 = eq(io.rocc.cmd.ready, UInt<1>("h0")) + node T_8464 = and(T_8461, T_8463) + node T_8465 = or(io.rocc.cmd.valid, rocc_blocked) + node T_8466 = and(T_8464, T_8465) + rocc_blocked <= T_8466 + node T_8467 = or(id_ex_hazard, id_mem_hazard) + node T_8468 = or(T_8467, id_wb_hazard) + node T_8469 = or(T_8468, id_sboard_hazard) + node T_8470 = and(id_ctrl.fp, id_stall_fpu) + node T_8471 = or(T_8469, T_8470) + node T_8472 = and(id_ctrl.mem, dcache_blocked) + node T_8473 = or(T_8471, T_8472) + node T_8474 = and(id_ctrl.rocc, rocc_blocked) + node T_8475 = or(T_8473, T_8474) + node T_8476 = or(T_8475, id_do_fence) + node ctrl_stalld = or(T_8476, csr.io.csr_stall) + node T_8478 = eq(ibuf.io.inst[0].valid, UInt<1>("h0")) + node T_8479 = or(T_8478, ibuf.io.inst[0].bits.replay) + node T_8480 = or(T_8479, take_pc_mem_wb) + node T_8481 = or(T_8480, ctrl_stalld) + node T_8482 = or(T_8481, csr.io.interrupt) + ctrl_killd <= T_8482 + io.imem.req.valid <= take_pc + node T_8484 = eq(take_pc_wb, UInt<1>("h0")) + io.imem.req.bits.speculative <= T_8484 + node T_8485 = or(wb_xcpt, csr.io.eret) + node T_8487 = or(take_pc_mem, UInt<1>("h1")) + node T_8488 = mux(T_8487, mem_npc, id_npc) + node T_8489 = mux(replay_wb, wb_reg_pc, T_8488) + node T_8490 = mux(T_8485, csr.io.evec, T_8489) + io.imem.req.bits.pc <= T_8490 + node T_8491 = and(wb_reg_valid, wb_ctrl.fence_i) + node T_8493 = eq(io.dmem.s2_nack, UInt<1>("h0")) + node T_8494 = and(T_8491, T_8493) + io.imem.flush_icache <= T_8494 + io.imem.flush_tlb <= csr.io.fatc + node T_8496 = eq(ctrl_stalld, UInt<1>("h0")) + node T_8497 = or(T_8496, csr.io.interrupt) + ibuf.io.inst[0].ready <= T_8497 + node T_8498 = and(mem_reg_replay, mem_reg_btb_hit) + node T_8500 = eq(take_pc_wb, UInt<1>("h0")) + node T_8501 = and(mem_reg_valid, T_8500) + node T_8503 = eq(mem_cfi, UInt<1>("h0")) + node T_8504 = or(mem_cfi_taken, T_8503) + node T_8505 = and(T_8504, mem_wrong_npc) + node T_8507 = and(UInt<1>("h0"), mem_ctrl.jal) + node T_8509 = eq(mem_reg_btb_hit, UInt<1>("h0")) + node T_8510 = and(T_8507, T_8509) + node T_8511 = or(T_8505, T_8510) + node T_8512 = and(T_8501, T_8511) + node T_8513 = or(T_8498, T_8512) + io.imem.btb_update.valid <= T_8513 + node T_8515 = eq(mem_reg_replay, UInt<1>("h0")) + node T_8516 = and(T_8515, mem_cfi) + io.imem.btb_update.bits.isValid <= T_8516 + node T_8517 = or(mem_ctrl.jal, mem_ctrl.jalr) + io.imem.btb_update.bits.isJump <= T_8517 + node T_8518 = bits(mem_reg_inst, 19, 15) + node T_8521 = and(T_8518, UInt<5>("h19")) + node T_8522 = eq(UInt<5>("h1"), T_8521) + node T_8523 = and(mem_ctrl.jalr, T_8522) + io.imem.btb_update.bits.isReturn <= T_8523 + io.imem.btb_update.bits.target <= io.imem.req.bits.pc + node T_8526 = mux(mem_reg_rvc, UInt<1>("h0"), UInt<2>("h2")) + node T_8527 = add(mem_reg_pc, T_8526) + node T_8528 = tail(T_8527, 1) + io.imem.btb_update.bits.br_pc <= T_8528 + node T_8529 = not(io.imem.btb_update.bits.br_pc) + node T_8531 = or(T_8529, UInt<2>("h3")) + node T_8532 = not(T_8531) + io.imem.btb_update.bits.pc <= T_8532 + io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit + io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp + node T_8534 = eq(take_pc_wb, UInt<1>("h0")) + node T_8535 = and(mem_reg_valid, T_8534) + node T_8536 = and(T_8535, mem_ctrl.branch) + io.imem.bht_update.valid <= T_8536 + io.imem.bht_update.bits.pc <= io.imem.btb_update.bits.pc + io.imem.bht_update.bits.taken <= mem_br_taken + io.imem.bht_update.bits.mispredict <= mem_wrong_npc + io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction + node T_8538 = eq(take_pc_wb, UInt<1>("h0")) + node T_8539 = and(mem_reg_valid, T_8538) + io.imem.ras_update.valid <= T_8539 + io.imem.ras_update.bits.returnAddr <= mem_int_wdata + node T_8540 = bits(mem_waddr, 0, 0) + node T_8541 = and(io.imem.btb_update.bits.isJump, T_8540) + io.imem.ras_update.bits.isCall <= T_8541 + io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn + io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction + node T_8543 = eq(ctrl_killd, UInt<1>("h0")) + node T_8544 = and(T_8543, id_ctrl.fp) + io.fpu.valid <= T_8544 + io.fpu.killx <= ctrl_killx + io.fpu.killm <= killm_common + io.fpu.inst <= ibuf.io.inst[0].bits.inst.bits + io.fpu.fromint_data <= ex_rs_0 + node T_8545 = and(dmem_resp_valid, dmem_resp_fpu) + io.fpu.dmem_resp_val <= T_8545 + io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass + io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ + io.fpu.dmem_resp_tag <= dmem_resp_waddr + node T_8546 = and(ex_reg_valid, ex_ctrl.mem) + io.dmem.req.valid <= T_8546 + node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) + io.dmem.req.bits.tag <= ex_dcache_tag + io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd + io.dmem.req.bits.typ <= ex_ctrl.mem_type + io.dmem.req.bits.phys <= UInt<1>("h0") + node T_8548 = shr(ex_rs_0, 38) + node T_8549 = bits(alu.io.adder_out, 39, 38) + node T_8550 = asSInt(T_8549) + node T_8552 = eq(T_8548, UInt<1>("h0")) + node T_8554 = eq(T_8548, UInt<1>("h1")) + node T_8555 = or(T_8552, T_8554) + node T_8557 = neq(T_8550, asSInt(UInt<1>("h0"))) + node T_8558 = asSInt(T_8548) + node T_8560 = eq(T_8558, asSInt(UInt<1>("h1"))) + node T_8561 = asSInt(T_8548) + node T_8563 = eq(T_8561, asSInt(UInt<2>("h2"))) + node T_8564 = or(T_8560, T_8563) + node T_8566 = eq(T_8550, asSInt(UInt<1>("h1"))) + node T_8567 = bits(T_8550, 0, 0) + node T_8568 = mux(T_8564, T_8566, T_8567) + node T_8569 = mux(T_8555, T_8557, T_8568) + node T_8570 = bits(alu.io.adder_out, 38, 0) + node T_8571 = cat(T_8569, T_8570) + io.dmem.req.bits.addr <= T_8571 + io.dmem.invalidate_lr <= wb_xcpt + node T_8572 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) + io.dmem.s1_data <= T_8572 + node T_8573 = or(killm_common, mem_breakpoint) + io.dmem.s1_kill <= T_8573 + node T_8574 = and(mem_ctrl.mem, mem_xcpt) + node T_8576 = eq(io.dmem.s1_kill, UInt<1>("h0")) + node T_8577 = and(T_8574, T_8576) + when T_8577 : + node T_8578 = cat(io.dmem.xcpt.pf.ld, io.dmem.xcpt.pf.st) + node T_8579 = cat(io.dmem.xcpt.ma.ld, io.dmem.xcpt.ma.st) + node T_8580 = cat(T_8579, T_8578) + node T_8582 = neq(T_8580, UInt<1>("h0")) + node T_8583 = or(T_8582, reset) + node T_8585 = eq(T_8583, UInt<1>("h0")) + when T_8585 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at rocket.scala:642 assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive\n") + stop(clk, UInt<1>("h1"), 1) + node T_8586 = and(wb_reg_valid, wb_ctrl.rocc) + node T_8588 = eq(replay_wb_common, UInt<1>("h0")) + node T_8589 = and(T_8586, T_8588) + io.rocc.cmd.valid <= T_8589 + node T_8591 = neq(csr.io.status.xs, UInt<1>("h0")) + node T_8592 = and(wb_xcpt, T_8591) + io.rocc.exception <= T_8592 + io.rocc.cmd.bits.status <- csr.io.status + wire T_8611 : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} + T_8611 is invalid wire T_8621 : UInt<32> T_8621 is invalid T_8621 <= wb_reg_inst - node T_8622 = bits(T_8621, 6, 0) @[rocket.scala 648:58] - T_8611.opcode <= T_8622 @[rocket.scala 648:58] - node T_8623 = bits(T_8621, 11, 7) @[rocket.scala 648:58] - T_8611.rd <= T_8623 @[rocket.scala 648:58] - node T_8624 = bits(T_8621, 12, 12) @[rocket.scala 648:58] - T_8611.xs2 <= T_8624 @[rocket.scala 648:58] - node T_8625 = bits(T_8621, 13, 13) @[rocket.scala 648:58] - T_8611.xs1 <= T_8625 @[rocket.scala 648:58] - node T_8626 = bits(T_8621, 14, 14) @[rocket.scala 648:58] - T_8611.xd <= T_8626 @[rocket.scala 648:58] - node T_8627 = bits(T_8621, 19, 15) @[rocket.scala 648:58] - T_8611.rs1 <= T_8627 @[rocket.scala 648:58] - node T_8628 = bits(T_8621, 24, 20) @[rocket.scala 648:58] - T_8611.rs2 <= T_8628 @[rocket.scala 648:58] - node T_8629 = bits(T_8621, 31, 25) @[rocket.scala 648:58] - T_8611.funct <= T_8629 @[rocket.scala 648:58] - io.rocc.cmd.bits.inst <- T_8611 @[rocket.scala 648:25] - io.rocc.cmd.bits.rs1 <= wb_reg_wdata @[rocket.scala 649:24] - io.rocc.cmd.bits.rs2 <= wb_reg_rs2 @[rocket.scala 650:24] - node T_8630 = bits(csr.io.time, 31, 0) @[rocket.scala 683:33] - node T_8632 = mux(rf_wen, rf_waddr, UInt<1>("h00")) @[rocket.scala 684:13] - node T_8633 = bits(wb_reg_inst, 19, 15) @[rocket.scala 685:21] - reg T_8634 : UInt, clk + node T_8622 = bits(T_8621, 6, 0) + T_8611.opcode <= T_8622 + node T_8623 = bits(T_8621, 11, 7) + T_8611.rd <= T_8623 + node T_8624 = bits(T_8621, 12, 12) + T_8611.xs2 <= T_8624 + node T_8625 = bits(T_8621, 13, 13) + T_8611.xs1 <= T_8625 + node T_8626 = bits(T_8621, 14, 14) + T_8611.xd <= T_8626 + node T_8627 = bits(T_8621, 19, 15) + T_8611.rs1 <= T_8627 + node T_8628 = bits(T_8621, 24, 20) + T_8611.rs2 <= T_8628 + node T_8629 = bits(T_8621, 31, 25) + T_8611.funct <= T_8629 + io.rocc.cmd.bits.inst <- T_8611 + io.rocc.cmd.bits.rs1 <= wb_reg_wdata + io.rocc.cmd.bits.rs2 <= wb_reg_rs2 + node T_8630 = bits(csr.io.time, 31, 0) + node T_8632 = mux(rf_wen, rf_waddr, UInt<1>("h0")) + node T_8633 = bits(wb_reg_inst, 19, 15) + reg T_8634 : UInt, clk with : + reset => (UInt<1>("h0"), T_8634) T_8634 <= ex_rs_0 - reg T_8635 : UInt, clk + reg T_8635 : UInt, clk with : + reset => (UInt<1>("h0"), T_8635) T_8635 <= T_8634 - node T_8636 = bits(wb_reg_inst, 24, 20) @[rocket.scala 686:21] - reg T_8637 : UInt, clk + node T_8636 = bits(wb_reg_inst, 24, 20) + reg T_8637 : UInt, clk with : + reset => (UInt<1>("h0"), T_8637) T_8637 <= ex_rs_1 - reg T_8638 : UInt, clk + reg T_8638 : UInt, clk with : + reset => (UInt<1>("h0"), T_8638) T_8638 <= T_8637 - node T_8640 = eq(reset, UInt<1>("h00")) @[rocket.scala 682:11] - when T_8640 : @[rocket.scala 682:11] - printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.prci.id, T_8630, wb_valid, wb_reg_pc, T_8632, rf_wdata, rf_wen, T_8633, T_8635, T_8636, T_8638, wb_reg_inst, wb_reg_inst) @[rocket.scala 682:11] - skip @[rocket.scala 682:11] - - module FlowThroughSerializer : + node T_8640 = eq(reset, UInt<1>("h0")) + when T_8640 : + printf(clk, UInt<1>("h1"), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.prci.id, T_8630, wb_valid, wb_reg_pc, T_8632, rf_wdata, rf_wen, T_8633, T_8635, T_8636, T_8638, wb_reg_inst, wb_reg_inst) + + module FlowThroughSerializer : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, cnt : UInt<1>, done : UInt<1>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, cnt : UInt<1>, done : UInt<1>} + io is invalid - io.out <- io.in @[Serializer.scala 19:12] - io.cnt <= UInt<1>("h00") @[Serializer.scala 20:12] - io.done <= UInt<1>("h01") @[Serializer.scala 21:13] - - module ICache : + io.out <- io.in + io.cnt <= UInt<1>("h0") + io.done <= UInt<1>("h1") + + module ICache : input clk : Clock input reset : UInt<1> - output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, flip s1_ppn : UInt<20>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<16>, datablock : UInt<64>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_ppn : UInt<20>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<16>, datablock : UInt<64>}}, flip invalidate : UInt<1>, mem : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - reg state : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg invalidated : UInt<1>, clk - node stall = eq(io.resp.ready, UInt<1>("h00")) @[icache.scala 44:15] - wire rdy : UInt<1> @[icache.scala 45:17] - rdy is invalid @[icache.scala 45:17] - reg refill_addr : UInt<32>, clk - wire s1_any_tag_hit : UInt<1> @[icache.scala 48:28] - s1_any_tag_hit is invalid @[icache.scala 48:28] - reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s1_vaddr : UInt, clk - node T_827 = bits(s1_vaddr, 11, 0) @[icache.scala 52:41] - node s1_paddr = cat(io.s1_ppn, T_827) @[Cat.scala 20:58] - node s1_tag = bits(s1_paddr, 31, 12) @[icache.scala 53:24] - node T_828 = and(s1_valid, stall) @[icache.scala 55:43] - node s0_valid = or(io.req.valid, T_828) @[icache.scala 55:31] - node T_829 = and(s1_valid, stall) @[icache.scala 56:31] - node s0_vaddr = mux(T_829, s1_vaddr, io.req.bits.addr) @[icache.scala 56:21] - node T_830 = and(io.req.valid, rdy) @[icache.scala 58:28] - node T_831 = and(s1_valid, stall) @[icache.scala 58:47] - node T_833 = eq(io.s1_kill, UInt<1>("h00")) @[icache.scala 58:59] - node T_834 = and(T_831, T_833) @[icache.scala 58:56] - node T_835 = or(T_830, T_834) @[icache.scala 58:35] - s1_valid <= T_835 @[icache.scala 58:12] - node T_836 = and(io.req.valid, rdy) @[icache.scala 59:22] - when T_836 : @[icache.scala 59:30] - s1_vaddr <= io.req.bits.addr @[icache.scala 60:14] - skip @[icache.scala 59:30] - node T_838 = eq(io.s1_kill, UInt<1>("h00")) @[icache.scala 63:31] - node T_839 = and(s1_valid, T_838) @[icache.scala 63:28] - node T_840 = eq(state, UInt<2>("h00")) @[icache.scala 63:52] - node out_valid = and(T_839, T_840) @[icache.scala 63:43] - node s1_idx = bits(s1_vaddr, 11, 6) @[icache.scala 64:24] - node s1_hit = and(out_valid, s1_any_tag_hit) @[icache.scala 65:26] - node T_842 = eq(s1_any_tag_hit, UInt<1>("h00")) @[icache.scala 66:30] - node s1_miss = and(out_valid, T_842) @[icache.scala 66:27] - node T_843 = eq(state, UInt<2>("h00")) @[icache.scala 67:16] - node T_845 = eq(s1_miss, UInt<1>("h00")) @[icache.scala 67:31] - node T_846 = and(T_843, T_845) @[icache.scala 67:28] - rdy <= T_846 @[icache.scala 67:7] - node T_847 = eq(state, UInt<2>("h00")) @[icache.scala 69:26] - node T_848 = and(s1_miss, T_847) @[icache.scala 69:17] - when T_848 : @[icache.scala 69:39] - refill_addr <= s1_paddr @[icache.scala 70:17] - skip @[icache.scala 69:39] - node refill_tag = bits(refill_addr, 31, 12) @[icache.scala 72:31] - inst FlowThroughSerializer_1 of FlowThroughSerializer @[Serializer.scala 63:20] + reg state : UInt<2>, clk with : + reset => (reset, UInt<2>("h0")) + reg invalidated : UInt<1>, clk with : + reset => (UInt<1>("h0"), invalidated) + node stall = eq(io.resp.ready, UInt<1>("h0")) + wire rdy : UInt<1> + rdy is invalid + reg refill_addr : UInt<32>, clk with : + reset => (UInt<1>("h0"), refill_addr) + wire s1_any_tag_hit : UInt<1> + s1_any_tag_hit is invalid + reg s1_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg s1_vaddr : UInt, clk with : + reset => (UInt<1>("h0"), s1_vaddr) + node T_827 = bits(s1_vaddr, 11, 0) + node s1_paddr = cat(io.s1_ppn, T_827) + node s1_tag = bits(s1_paddr, 31, 12) + node T_828 = and(s1_valid, stall) + node s0_valid = or(io.req.valid, T_828) + node T_829 = and(s1_valid, stall) + node s0_vaddr = mux(T_829, s1_vaddr, io.req.bits.addr) + node T_830 = and(io.req.valid, rdy) + node T_831 = and(s1_valid, stall) + node T_833 = eq(io.s1_kill, UInt<1>("h0")) + node T_834 = and(T_831, T_833) + node T_835 = or(T_830, T_834) + s1_valid <= T_835 + node T_836 = and(io.req.valid, rdy) + when T_836 : + s1_vaddr <= io.req.bits.addr + node T_838 = eq(io.s1_kill, UInt<1>("h0")) + node T_839 = and(s1_valid, T_838) + node T_840 = eq(state, UInt<2>("h0")) + node out_valid = and(T_839, T_840) + node s1_idx = bits(s1_vaddr, 11, 6) + node s1_hit = and(out_valid, s1_any_tag_hit) + node T_842 = eq(s1_any_tag_hit, UInt<1>("h0")) + node s1_miss = and(out_valid, T_842) + node T_843 = eq(state, UInt<2>("h0")) + node T_845 = eq(s1_miss, UInt<1>("h0")) + node T_846 = and(T_843, T_845) + rdy <= T_846 + node T_847 = eq(state, UInt<2>("h0")) + node T_848 = and(s1_miss, T_847) + when T_848 : + refill_addr <= s1_paddr + node refill_tag = bits(refill_addr, 31, 12) + inst FlowThroughSerializer_1 of FlowThroughSerializer FlowThroughSerializer_1.io is invalid FlowThroughSerializer_1.clk <= clk FlowThroughSerializer_1.reset <= reset - FlowThroughSerializer_1.io.in.valid <= io.mem.grant.valid @[Serializer.scala 64:20] - FlowThroughSerializer_1.io.in.bits <- io.mem.grant.bits @[Serializer.scala 65:19] - io.mem.grant.ready <= FlowThroughSerializer_1.io.in.ready @[Serializer.scala 66:14] - node T_849 = and(FlowThroughSerializer_1.io.out.ready, FlowThroughSerializer_1.io.out.valid) @[Decoupled.scala 21:42] - reg refill_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_849 : @[Counter.scala 43:17] - node T_852 = eq(refill_cnt, UInt<3>("h07")) @[Counter.scala 20:24] - node T_854 = add(refill_cnt, UInt<1>("h01")) @[Counter.scala 21:22] - node T_855 = tail(T_854, 1) @[Counter.scala 21:22] - refill_cnt <= T_855 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node refill_wrap = and(T_849, T_852) @[Counter.scala 44:20] - node T_856 = eq(state, UInt<2>("h03")) @[icache.scala 76:27] - node refill_done = and(T_856, refill_wrap) @[icache.scala 76:40] - FlowThroughSerializer_1.io.out.ready <= UInt<1>("h01") @[icache.scala 77:22] - reg T_859 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) - when s1_miss : @[LFSR.scala 19:22] - node T_860 = bits(T_859, 0, 0) @[LFSR.scala 19:40] - node T_861 = bits(T_859, 2, 2) @[LFSR.scala 19:48] - node T_862 = xor(T_860, T_861) @[LFSR.scala 19:43] - node T_863 = bits(T_859, 3, 3) @[LFSR.scala 19:56] - node T_864 = xor(T_862, T_863) @[LFSR.scala 19:51] - node T_865 = bits(T_859, 5, 5) @[LFSR.scala 19:64] - node T_866 = xor(T_864, T_865) @[LFSR.scala 19:59] - node T_867 = bits(T_859, 15, 1) @[LFSR.scala 19:73] - node T_868 = cat(T_866, T_867) @[Cat.scala 20:58] - T_859 <= T_868 @[LFSR.scala 19:29] - skip @[LFSR.scala 19:22] - node repl_way = bits(T_859, 1, 0) @[icache.scala 79:56] - smem tag_array : UInt<20>[4][64] @[icache.scala 81:25] - node T_877 = bits(s0_vaddr, 11, 6) @[icache.scala 82:42] - node T_879 = eq(refill_done, UInt<1>("h00")) @[icache.scala 82:70] - node T_880 = and(T_879, s0_valid) @[icache.scala 82:83] + FlowThroughSerializer_1.io.in.valid <= io.mem.grant.valid + FlowThroughSerializer_1.io.in.bits <- io.mem.grant.bits + io.mem.grant.ready <= FlowThroughSerializer_1.io.in.ready + node T_849 = and(FlowThroughSerializer_1.io.out.ready, FlowThroughSerializer_1.io.out.valid) + reg refill_cnt : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + wire T_852 : UInt<1> + T_852 is invalid + when T_849 : + T_852 <= eq(refill_cnt, UInt<3>("h7")) + node T_854 = add(refill_cnt, UInt<1>("h1")) + node T_855 = tail(T_854, 1) + refill_cnt <= T_855 + node refill_wrap = and(T_849, T_852) + node T_856 = eq(state, UInt<2>("h3")) + node refill_done = and(T_856, refill_wrap) + FlowThroughSerializer_1.io.out.ready <= UInt<1>("h1") + reg T_859 : UInt<16>, clk with : + reset => (reset, UInt<16>("h1")) + when s1_miss : + node T_860 = bits(T_859, 0, 0) + node T_861 = bits(T_859, 2, 2) + node T_862 = xor(T_860, T_861) + node T_863 = bits(T_859, 3, 3) + node T_864 = xor(T_862, T_863) + node T_865 = bits(T_859, 5, 5) + node T_866 = xor(T_864, T_865) + node T_867 = bits(T_859, 15, 1) + node T_868 = cat(T_866, T_867) + T_859 <= T_868 + node repl_way = bits(T_859, 1, 0) + smem tag_array : UInt<20>[4] [64] + node T_877 = bits(s0_vaddr, 11, 6) + node T_879 = eq(refill_done, UInt<1>("h0")) + node T_880 = and(T_879, s0_valid) wire T_882 : UInt T_882 is invalid when T_880 : T_882 <= T_877 - skip read mport tag_rdata = tag_array[T_882], clk - when refill_done : @[icache.scala 83:22] - wire T_891 : UInt<20>[4] @[icache.scala 85:44] - T_891 is invalid @[icache.scala 85:44] - T_891[0] <= refill_tag @[icache.scala 85:44] - T_891[1] <= refill_tag @[icache.scala 85:44] - T_891[2] <= refill_tag @[icache.scala 85:44] - T_891[3] <= refill_tag @[icache.scala 85:44] - node T_894 = eq(repl_way, UInt<1>("h00")) @[icache.scala 85:80] - node T_896 = eq(repl_way, UInt<1>("h01")) @[icache.scala 85:80] - node T_898 = eq(repl_way, UInt<2>("h02")) @[icache.scala 85:80] - node T_900 = eq(repl_way, UInt<2>("h03")) @[icache.scala 85:80] - wire T_906 : UInt<1>[4] @[icache.scala 85:70] - T_906 is invalid @[icache.scala 85:70] - T_906[0] <= T_894 @[icache.scala 85:70] - T_906[1] <= T_896 @[icache.scala 85:70] - T_906[2] <= T_898 @[icache.scala 85:70] - T_906[3] <= T_900 @[icache.scala 85:70] + when refill_done : + wire T_891 : UInt<20>[4] + T_891 is invalid + T_891[0] <= refill_tag + T_891[1] <= refill_tag + T_891[2] <= refill_tag + T_891[3] <= refill_tag + node T_894 = eq(repl_way, UInt<1>("h0")) + node T_896 = eq(repl_way, UInt<1>("h1")) + node T_898 = eq(repl_way, UInt<2>("h2")) + node T_900 = eq(repl_way, UInt<2>("h3")) + wire T_906 : UInt<1>[4] + T_906 is invalid + T_906[0] <= T_894 + T_906[1] <= T_896 + T_906[2] <= T_898 + T_906[3] <= T_900 write mport T_910 = tag_array[s1_idx], clk when T_906[0] : T_910[0] <= T_891[0] - skip when T_906[1] : T_910[1] <= T_891[1] - skip when T_906[2] : T_910[2] <= T_891[2] - skip when T_906[3] : T_910[3] <= T_891[3] - skip - skip @[icache.scala 83:22] - reg vb_array : UInt<256>, clk with : (reset => (reset, UInt<256>("h00"))) - node T_914 = eq(invalidated, UInt<1>("h00")) @[icache.scala 89:24] - node T_915 = and(refill_done, T_914) @[icache.scala 89:21] - when T_915 : @[icache.scala 89:38] - node T_916 = cat(repl_way, s1_idx) @[Cat.scala 20:58] - node T_919 = dshl(UInt<1>("h01"), T_916) @[icache.scala 90:32] - node T_920 = or(vb_array, T_919) @[icache.scala 90:32] - node T_921 = not(vb_array) @[icache.scala 90:32] - node T_922 = or(T_921, T_919) @[icache.scala 90:32] - node T_923 = not(T_922) @[icache.scala 90:32] - node T_924 = mux(UInt<1>("h01"), T_920, T_923) @[icache.scala 90:32] - vb_array <= T_924 @[icache.scala 90:14] - skip @[icache.scala 89:38] - when io.invalidate : @[icache.scala 92:24] - vb_array <= UInt<1>("h00") @[icache.scala 93:14] - invalidated <= UInt<1>("h01") @[icache.scala 94:17] - skip @[icache.scala 92:24] - wire s1_disparity : UInt<1>[4] @[icache.scala 96:26] - s1_disparity is invalid @[icache.scala 96:26] - node T_934 = and(s1_valid, s1_disparity[0]) @[icache.scala 98:20] - when T_934 : @[icache.scala 98:40] - node T_936 = cat(UInt<1>("h00"), s1_idx) @[Cat.scala 20:58] - node T_939 = dshl(UInt<1>("h01"), T_936) @[icache.scala 98:69] - node T_940 = or(vb_array, T_939) @[icache.scala 98:69] - node T_941 = not(vb_array) @[icache.scala 98:69] - node T_942 = or(T_941, T_939) @[icache.scala 98:69] - node T_943 = not(T_942) @[icache.scala 98:69] - node T_944 = mux(UInt<1>("h00"), T_940, T_943) @[icache.scala 98:69] - vb_array <= T_944 @[icache.scala 98:51] - skip @[icache.scala 98:40] - node T_945 = and(s1_valid, s1_disparity[1]) @[icache.scala 98:20] - when T_945 : @[icache.scala 98:40] - node T_947 = cat(UInt<1>("h01"), s1_idx) @[Cat.scala 20:58] - node T_950 = dshl(UInt<1>("h01"), T_947) @[icache.scala 98:69] - node T_951 = or(vb_array, T_950) @[icache.scala 98:69] - node T_952 = not(vb_array) @[icache.scala 98:69] - node T_953 = or(T_952, T_950) @[icache.scala 98:69] - node T_954 = not(T_953) @[icache.scala 98:69] - node T_955 = mux(UInt<1>("h00"), T_951, T_954) @[icache.scala 98:69] - vb_array <= T_955 @[icache.scala 98:51] - skip @[icache.scala 98:40] - node T_956 = and(s1_valid, s1_disparity[2]) @[icache.scala 98:20] - when T_956 : @[icache.scala 98:40] - node T_958 = cat(UInt<2>("h02"), s1_idx) @[Cat.scala 20:58] - node T_961 = dshl(UInt<1>("h01"), T_958) @[icache.scala 98:69] - node T_962 = or(vb_array, T_961) @[icache.scala 98:69] - node T_963 = not(vb_array) @[icache.scala 98:69] - node T_964 = or(T_963, T_961) @[icache.scala 98:69] - node T_965 = not(T_964) @[icache.scala 98:69] - node T_966 = mux(UInt<1>("h00"), T_962, T_965) @[icache.scala 98:69] - vb_array <= T_966 @[icache.scala 98:51] - skip @[icache.scala 98:40] - node T_967 = and(s1_valid, s1_disparity[3]) @[icache.scala 98:20] - when T_967 : @[icache.scala 98:40] - node T_969 = cat(UInt<2>("h03"), s1_idx) @[Cat.scala 20:58] - node T_972 = dshl(UInt<1>("h01"), T_969) @[icache.scala 98:69] - node T_973 = or(vb_array, T_972) @[icache.scala 98:69] - node T_974 = not(vb_array) @[icache.scala 98:69] - node T_975 = or(T_974, T_972) @[icache.scala 98:69] - node T_976 = not(T_975) @[icache.scala 98:69] - node T_977 = mux(UInt<1>("h00"), T_973, T_976) @[icache.scala 98:69] - vb_array <= T_977 @[icache.scala 98:51] - skip @[icache.scala 98:40] - wire s1_tag_match : UInt<1>[4] @[icache.scala 100:26] - s1_tag_match is invalid @[icache.scala 100:26] - wire s1_tag_hit : UInt<1>[4] @[icache.scala 101:24] - s1_tag_hit is invalid @[icache.scala 101:24] - wire s1_dout : UInt<64>[4] @[icache.scala 102:21] - s1_dout is invalid @[icache.scala 102:21] - node T_1000 = eq(io.invalidate, UInt<1>("h00")) @[icache.scala 105:17] - node T_1002 = bits(s1_vaddr, 11, 6) @[icache.scala 105:65] - node T_1003 = cat(UInt<1>("h00"), T_1002) @[Cat.scala 20:58] - node T_1004 = dshr(vb_array, T_1003) @[icache.scala 105:43] - node T_1005 = bits(T_1004, 0, 0) @[icache.scala 105:43] - node T_1006 = bits(T_1005, 0, 0) @[icache.scala 105:94] - node T_1007 = and(T_1000, T_1006) @[icache.scala 105:32] - node T_1010 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1011 = bits(tag_rdata[0], 19, 0) @[icache.scala 108:31] - node T_1012 = eq(T_1011, s1_tag) @[icache.scala 108:45] - s1_tag_match[0] <= T_1012 @[icache.scala 108:21] - node T_1013 = and(T_1007, s1_tag_match[0]) @[icache.scala 109:28] - s1_tag_hit[0] <= T_1013 @[icache.scala 109:19] - node T_1016 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1017 = or(T_1010, T_1016) @[icache.scala 110:51] - node T_1018 = and(T_1007, T_1017) @[icache.scala 110:30] - s1_disparity[0] <= T_1018 @[icache.scala 110:21] - node T_1020 = eq(io.invalidate, UInt<1>("h00")) @[icache.scala 105:17] - node T_1022 = bits(s1_vaddr, 11, 6) @[icache.scala 105:65] - node T_1023 = cat(UInt<1>("h01"), T_1022) @[Cat.scala 20:58] - node T_1024 = dshr(vb_array, T_1023) @[icache.scala 105:43] - node T_1025 = bits(T_1024, 0, 0) @[icache.scala 105:43] - node T_1026 = bits(T_1025, 0, 0) @[icache.scala 105:94] - node T_1027 = and(T_1020, T_1026) @[icache.scala 105:32] - node T_1030 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1031 = bits(tag_rdata[1], 19, 0) @[icache.scala 108:31] - node T_1032 = eq(T_1031, s1_tag) @[icache.scala 108:45] - s1_tag_match[1] <= T_1032 @[icache.scala 108:21] - node T_1033 = and(T_1027, s1_tag_match[1]) @[icache.scala 109:28] - s1_tag_hit[1] <= T_1033 @[icache.scala 109:19] - node T_1036 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1037 = or(T_1030, T_1036) @[icache.scala 110:51] - node T_1038 = and(T_1027, T_1037) @[icache.scala 110:30] - s1_disparity[1] <= T_1038 @[icache.scala 110:21] - node T_1040 = eq(io.invalidate, UInt<1>("h00")) @[icache.scala 105:17] - node T_1042 = bits(s1_vaddr, 11, 6) @[icache.scala 105:65] - node T_1043 = cat(UInt<2>("h02"), T_1042) @[Cat.scala 20:58] - node T_1044 = dshr(vb_array, T_1043) @[icache.scala 105:43] - node T_1045 = bits(T_1044, 0, 0) @[icache.scala 105:43] - node T_1046 = bits(T_1045, 0, 0) @[icache.scala 105:94] - node T_1047 = and(T_1040, T_1046) @[icache.scala 105:32] - node T_1050 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1051 = bits(tag_rdata[2], 19, 0) @[icache.scala 108:31] - node T_1052 = eq(T_1051, s1_tag) @[icache.scala 108:45] - s1_tag_match[2] <= T_1052 @[icache.scala 108:21] - node T_1053 = and(T_1047, s1_tag_match[2]) @[icache.scala 109:28] - s1_tag_hit[2] <= T_1053 @[icache.scala 109:19] - node T_1056 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1057 = or(T_1050, T_1056) @[icache.scala 110:51] - node T_1058 = and(T_1047, T_1057) @[icache.scala 110:30] - s1_disparity[2] <= T_1058 @[icache.scala 110:21] - node T_1060 = eq(io.invalidate, UInt<1>("h00")) @[icache.scala 105:17] - node T_1062 = bits(s1_vaddr, 11, 6) @[icache.scala 105:65] - node T_1063 = cat(UInt<2>("h03"), T_1062) @[Cat.scala 20:58] - node T_1064 = dshr(vb_array, T_1063) @[icache.scala 105:43] - node T_1065 = bits(T_1064, 0, 0) @[icache.scala 105:43] - node T_1066 = bits(T_1065, 0, 0) @[icache.scala 105:94] - node T_1067 = and(T_1060, T_1066) @[icache.scala 105:32] - node T_1070 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1071 = bits(tag_rdata[3], 19, 0) @[icache.scala 108:31] - node T_1072 = eq(T_1071, s1_tag) @[icache.scala 108:45] - s1_tag_match[3] <= T_1072 @[icache.scala 108:21] - node T_1073 = and(T_1067, s1_tag_match[3]) @[icache.scala 109:28] - s1_tag_hit[3] <= T_1073 @[icache.scala 109:19] - node T_1076 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] - node T_1077 = or(T_1070, T_1076) @[icache.scala 110:51] - node T_1078 = and(T_1067, T_1077) @[icache.scala 110:30] - s1_disparity[3] <= T_1078 @[icache.scala 110:21] - node T_1079 = or(s1_tag_hit[0], s1_tag_hit[1]) @[icache.scala 112:44] - node T_1080 = or(T_1079, s1_tag_hit[2]) @[icache.scala 112:44] - node T_1081 = or(T_1080, s1_tag_hit[3]) @[icache.scala 112:44] - node T_1082 = or(s1_disparity[0], s1_disparity[1]) @[icache.scala 112:78] - node T_1083 = or(T_1082, s1_disparity[2]) @[icache.scala 112:78] - node T_1084 = or(T_1083, s1_disparity[3]) @[icache.scala 112:78] - node T_1086 = eq(T_1084, UInt<1>("h00")) @[icache.scala 112:52] - node T_1087 = and(T_1081, T_1086) @[icache.scala 112:49] - s1_any_tag_hit <= T_1087 @[icache.scala 112:18] - smem T_1090 : UInt<64>[512] @[icache.scala 115:28] - node T_1092 = eq(repl_way, UInt<1>("h00")) @[icache.scala 116:46] - node T_1093 = and(FlowThroughSerializer_1.io.out.valid, T_1092) @[icache.scala 116:34] - when T_1093 : @[icache.scala 117:16] - node T_1094 = shl(s1_idx, 3) @[icache.scala 119:32] - node T_1095 = or(T_1094, refill_cnt) @[icache.scala 119:59] + reg vb_array : UInt<256>, clk with : + reset => (reset, UInt<256>("h0")) + node T_914 = eq(invalidated, UInt<1>("h0")) + node T_915 = and(refill_done, T_914) + when T_915 : + node T_916 = cat(repl_way, s1_idx) + node T_919 = dshl(UInt<1>("h1"), T_916) + node T_920 = or(vb_array, T_919) + node T_921 = not(vb_array) + node T_922 = or(T_921, T_919) + node T_923 = not(T_922) + node T_924 = mux(UInt<1>("h1"), T_920, T_923) + vb_array <= T_924 + when io.invalidate : + vb_array <= UInt<1>("h0") + invalidated <= UInt<1>("h1") + wire s1_disparity : UInt<1>[4] + s1_disparity is invalid + node T_934 = and(s1_valid, s1_disparity[0]) + when T_934 : + node T_936 = cat(UInt<1>("h0"), s1_idx) + node T_939 = dshl(UInt<1>("h1"), T_936) + node T_940 = or(vb_array, T_939) + node T_941 = not(vb_array) + node T_942 = or(T_941, T_939) + node T_943 = not(T_942) + node T_944 = mux(UInt<1>("h0"), T_940, T_943) + vb_array <= T_944 + node T_945 = and(s1_valid, s1_disparity[1]) + when T_945 : + node T_947 = cat(UInt<1>("h1"), s1_idx) + node T_950 = dshl(UInt<1>("h1"), T_947) + node T_951 = or(vb_array, T_950) + node T_952 = not(vb_array) + node T_953 = or(T_952, T_950) + node T_954 = not(T_953) + node T_955 = mux(UInt<1>("h0"), T_951, T_954) + vb_array <= T_955 + node T_956 = and(s1_valid, s1_disparity[2]) + when T_956 : + node T_958 = cat(UInt<2>("h2"), s1_idx) + node T_961 = dshl(UInt<1>("h1"), T_958) + node T_962 = or(vb_array, T_961) + node T_963 = not(vb_array) + node T_964 = or(T_963, T_961) + node T_965 = not(T_964) + node T_966 = mux(UInt<1>("h0"), T_962, T_965) + vb_array <= T_966 + node T_967 = and(s1_valid, s1_disparity[3]) + when T_967 : + node T_969 = cat(UInt<2>("h3"), s1_idx) + node T_972 = dshl(UInt<1>("h1"), T_969) + node T_973 = or(vb_array, T_972) + node T_974 = not(vb_array) + node T_975 = or(T_974, T_972) + node T_976 = not(T_975) + node T_977 = mux(UInt<1>("h0"), T_973, T_976) + vb_array <= T_977 + wire s1_tag_match : UInt<1>[4] + s1_tag_match is invalid + wire s1_tag_hit : UInt<1>[4] + s1_tag_hit is invalid + wire s1_dout : UInt<64>[4] + s1_dout is invalid + node T_1000 = eq(io.invalidate, UInt<1>("h0")) + node T_1002 = bits(s1_vaddr, 11, 6) + node T_1003 = cat(UInt<1>("h0"), T_1002) + node T_1004 = dshr(vb_array, T_1003) + node T_1005 = bits(T_1004, 0, 0) + node T_1006 = bits(T_1005, 0, 0) + node T_1007 = and(T_1000, T_1006) + node T_1010 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1011 = bits(tag_rdata[0], 19, 0) + node T_1012 = eq(T_1011, s1_tag) + s1_tag_match[0] <= T_1012 + node T_1013 = and(T_1007, s1_tag_match[0]) + s1_tag_hit[0] <= T_1013 + node T_1016 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1017 = or(T_1010, T_1016) + node T_1018 = and(T_1007, T_1017) + s1_disparity[0] <= T_1018 + node T_1020 = eq(io.invalidate, UInt<1>("h0")) + node T_1022 = bits(s1_vaddr, 11, 6) + node T_1023 = cat(UInt<1>("h1"), T_1022) + node T_1024 = dshr(vb_array, T_1023) + node T_1025 = bits(T_1024, 0, 0) + node T_1026 = bits(T_1025, 0, 0) + node T_1027 = and(T_1020, T_1026) + node T_1030 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1031 = bits(tag_rdata[1], 19, 0) + node T_1032 = eq(T_1031, s1_tag) + s1_tag_match[1] <= T_1032 + node T_1033 = and(T_1027, s1_tag_match[1]) + s1_tag_hit[1] <= T_1033 + node T_1036 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1037 = or(T_1030, T_1036) + node T_1038 = and(T_1027, T_1037) + s1_disparity[1] <= T_1038 + node T_1040 = eq(io.invalidate, UInt<1>("h0")) + node T_1042 = bits(s1_vaddr, 11, 6) + node T_1043 = cat(UInt<2>("h2"), T_1042) + node T_1044 = dshr(vb_array, T_1043) + node T_1045 = bits(T_1044, 0, 0) + node T_1046 = bits(T_1045, 0, 0) + node T_1047 = and(T_1040, T_1046) + node T_1050 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1051 = bits(tag_rdata[2], 19, 0) + node T_1052 = eq(T_1051, s1_tag) + s1_tag_match[2] <= T_1052 + node T_1053 = and(T_1047, s1_tag_match[2]) + s1_tag_hit[2] <= T_1053 + node T_1056 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1057 = or(T_1050, T_1056) + node T_1058 = and(T_1047, T_1057) + s1_disparity[2] <= T_1058 + node T_1060 = eq(io.invalidate, UInt<1>("h0")) + node T_1062 = bits(s1_vaddr, 11, 6) + node T_1063 = cat(UInt<2>("h3"), T_1062) + node T_1064 = dshr(vb_array, T_1063) + node T_1065 = bits(T_1064, 0, 0) + node T_1066 = bits(T_1065, 0, 0) + node T_1067 = and(T_1060, T_1066) + node T_1070 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1071 = bits(tag_rdata[3], 19, 0) + node T_1072 = eq(T_1071, s1_tag) + s1_tag_match[3] <= T_1072 + node T_1073 = and(T_1067, s1_tag_match[3]) + s1_tag_hit[3] <= T_1073 + node T_1076 = or(UInt<1>("h0"), UInt<1>("h0")) + node T_1077 = or(T_1070, T_1076) + node T_1078 = and(T_1067, T_1077) + s1_disparity[3] <= T_1078 + node T_1079 = or(s1_tag_hit[0], s1_tag_hit[1]) + node T_1080 = or(T_1079, s1_tag_hit[2]) + node T_1081 = or(T_1080, s1_tag_hit[3]) + node T_1082 = or(s1_disparity[0], s1_disparity[1]) + node T_1083 = or(T_1082, s1_disparity[2]) + node T_1084 = or(T_1083, s1_disparity[3]) + node T_1086 = eq(T_1084, UInt<1>("h0")) + node T_1087 = and(T_1081, T_1086) + s1_any_tag_hit <= T_1087 + smem T_1090 : UInt<64> [512] + node T_1092 = eq(repl_way, UInt<1>("h0")) + node T_1093 = and(FlowThroughSerializer_1.io.out.valid, T_1092) + when T_1093 : + node T_1094 = shl(s1_idx, 3) + node T_1095 = or(T_1094, refill_cnt) write mport T_1096 = T_1090[T_1095], clk T_1096 <= FlowThroughSerializer_1.io.out.bits.data - skip @[icache.scala 117:16] - node T_1097 = bits(s0_vaddr, 11, 3) @[icache.scala 121:28] - node T_1099 = eq(T_1093, UInt<1>("h00")) @[icache.scala 122:45] - node T_1100 = and(T_1099, s0_valid) @[icache.scala 122:50] + node T_1097 = bits(s0_vaddr, 11, 3) + node T_1099 = eq(T_1093, UInt<1>("h0")) + node T_1100 = and(T_1099, s0_valid) wire T_1102 : UInt T_1102 is invalid when T_1100 : T_1102 <= T_1097 - skip read mport T_1103 = T_1090[T_1102], clk - s1_dout[0] <= T_1103 @[icache.scala 122:16] - smem T_1106 : UInt<64>[512] @[icache.scala 115:28] - node T_1108 = eq(repl_way, UInt<1>("h01")) @[icache.scala 116:46] - node T_1109 = and(FlowThroughSerializer_1.io.out.valid, T_1108) @[icache.scala 116:34] - when T_1109 : @[icache.scala 117:16] - node T_1110 = shl(s1_idx, 3) @[icache.scala 119:32] - node T_1111 = or(T_1110, refill_cnt) @[icache.scala 119:59] + s1_dout[0] <= T_1103 + smem T_1106 : UInt<64> [512] + node T_1108 = eq(repl_way, UInt<1>("h1")) + node T_1109 = and(FlowThroughSerializer_1.io.out.valid, T_1108) + when T_1109 : + node T_1110 = shl(s1_idx, 3) + node T_1111 = or(T_1110, refill_cnt) write mport T_1112 = T_1106[T_1111], clk T_1112 <= FlowThroughSerializer_1.io.out.bits.data - skip @[icache.scala 117:16] - node T_1113 = bits(s0_vaddr, 11, 3) @[icache.scala 121:28] - node T_1115 = eq(T_1109, UInt<1>("h00")) @[icache.scala 122:45] - node T_1116 = and(T_1115, s0_valid) @[icache.scala 122:50] + node T_1113 = bits(s0_vaddr, 11, 3) + node T_1115 = eq(T_1109, UInt<1>("h0")) + node T_1116 = and(T_1115, s0_valid) wire T_1118 : UInt T_1118 is invalid when T_1116 : T_1118 <= T_1113 - skip read mport T_1119 = T_1106[T_1118], clk - s1_dout[1] <= T_1119 @[icache.scala 122:16] - smem T_1122 : UInt<64>[512] @[icache.scala 115:28] - node T_1124 = eq(repl_way, UInt<2>("h02")) @[icache.scala 116:46] - node T_1125 = and(FlowThroughSerializer_1.io.out.valid, T_1124) @[icache.scala 116:34] - when T_1125 : @[icache.scala 117:16] - node T_1126 = shl(s1_idx, 3) @[icache.scala 119:32] - node T_1127 = or(T_1126, refill_cnt) @[icache.scala 119:59] + s1_dout[1] <= T_1119 + smem T_1122 : UInt<64> [512] + node T_1124 = eq(repl_way, UInt<2>("h2")) + node T_1125 = and(FlowThroughSerializer_1.io.out.valid, T_1124) + when T_1125 : + node T_1126 = shl(s1_idx, 3) + node T_1127 = or(T_1126, refill_cnt) write mport T_1128 = T_1122[T_1127], clk T_1128 <= FlowThroughSerializer_1.io.out.bits.data - skip @[icache.scala 117:16] - node T_1129 = bits(s0_vaddr, 11, 3) @[icache.scala 121:28] - node T_1131 = eq(T_1125, UInt<1>("h00")) @[icache.scala 122:45] - node T_1132 = and(T_1131, s0_valid) @[icache.scala 122:50] + node T_1129 = bits(s0_vaddr, 11, 3) + node T_1131 = eq(T_1125, UInt<1>("h0")) + node T_1132 = and(T_1131, s0_valid) wire T_1134 : UInt T_1134 is invalid when T_1132 : T_1134 <= T_1129 - skip read mport T_1135 = T_1122[T_1134], clk - s1_dout[2] <= T_1135 @[icache.scala 122:16] - smem T_1138 : UInt<64>[512] @[icache.scala 115:28] - node T_1140 = eq(repl_way, UInt<2>("h03")) @[icache.scala 116:46] - node T_1141 = and(FlowThroughSerializer_1.io.out.valid, T_1140) @[icache.scala 116:34] - when T_1141 : @[icache.scala 117:16] - node T_1142 = shl(s1_idx, 3) @[icache.scala 119:32] - node T_1143 = or(T_1142, refill_cnt) @[icache.scala 119:59] + s1_dout[2] <= T_1135 + smem T_1138 : UInt<64> [512] + node T_1140 = eq(repl_way, UInt<2>("h3")) + node T_1141 = and(FlowThroughSerializer_1.io.out.valid, T_1140) + when T_1141 : + node T_1142 = shl(s1_idx, 3) + node T_1143 = or(T_1142, refill_cnt) write mport T_1144 = T_1138[T_1143], clk T_1144 <= FlowThroughSerializer_1.io.out.bits.data - skip @[icache.scala 117:16] - node T_1145 = bits(s0_vaddr, 11, 3) @[icache.scala 121:28] - node T_1147 = eq(T_1141, UInt<1>("h00")) @[icache.scala 122:45] - node T_1148 = and(T_1147, s0_valid) @[icache.scala 122:50] + node T_1145 = bits(s0_vaddr, 11, 3) + node T_1147 = eq(T_1141, UInt<1>("h0")) + node T_1148 = and(T_1147, s0_valid) wire T_1150 : UInt T_1150 is invalid when T_1148 : T_1150 <= T_1145 - skip read mport T_1151 = T_1138[T_1150], clk - s1_dout[3] <= T_1151 @[icache.scala 122:16] - node T_1153 = eq(stall, UInt<1>("h00")) @[icache.scala 131:38] - reg T_1154 : UInt<1>, clk - when T_1153 : @[Reg.scala 29:19] - T_1154 <= s1_hit @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_1156 = eq(stall, UInt<1>("h00")) @[icache.scala 132:46] - reg T_1159 : UInt<1>[4], clk - when T_1156 : @[Reg.scala 29:19] - T_1159 <= s1_tag_hit @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_1162 = eq(stall, UInt<1>("h00")) @[icache.scala 133:40] - reg T_1165 : UInt<64>[4], clk - when T_1162 : @[Reg.scala 29:19] - T_1165 <= s1_dout @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_1168 = mux(T_1159[0], T_1165[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1170 = mux(T_1159[1], T_1165[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1172 = mux(T_1159[2], T_1165[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1174 = mux(T_1159[3], T_1165[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1176 = or(T_1168, T_1170) @[Mux.scala 18:72] - node T_1177 = or(T_1176, T_1172) @[Mux.scala 18:72] - node T_1178 = or(T_1177, T_1174) @[Mux.scala 18:72] + s1_dout[3] <= T_1151 + node T_1153 = eq(stall, UInt<1>("h0")) + reg T_1154 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_1154) + when T_1153 : + T_1154 <= s1_hit + node T_1156 = eq(stall, UInt<1>("h0")) + reg T_1159 : UInt<1>[4], clk with : + reset => (UInt<1>("h0"), T_1159) + when T_1156 : + T_1159 <= s1_tag_hit + node T_1162 = eq(stall, UInt<1>("h0")) + reg T_1165 : UInt<64>[4], clk with : + reset => (UInt<1>("h0"), T_1165) + when T_1162 : + T_1165 <= s1_dout + node T_1168 = mux(T_1159[0], T_1165[0], UInt<1>("h0")) + node T_1170 = mux(T_1159[1], T_1165[1], UInt<1>("h0")) + node T_1172 = mux(T_1159[2], T_1165[2], UInt<1>("h0")) + node T_1174 = mux(T_1159[3], T_1165[3], UInt<1>("h0")) + node T_1176 = or(T_1168, T_1170) + node T_1177 = or(T_1176, T_1172) + node T_1178 = or(T_1177, T_1174) wire T_1179 : UInt<64> T_1179 is invalid - T_1179 <= T_1178 @[Mux.scala 18:72] - io.resp.bits.datablock <= T_1179 @[icache.scala 134:30] - io.resp.valid <= T_1154 @[icache.scala 135:21] - node T_1180 = eq(state, UInt<2>("h01")) @[icache.scala 137:33] - node T_1182 = eq(io.s2_kill, UInt<1>("h00")) @[icache.scala 137:50] - node T_1183 = and(T_1180, T_1182) @[icache.scala 137:47] - io.mem.acquire.valid <= T_1183 @[icache.scala 137:24] - node T_1184 = shr(refill_addr, 6) @[icache.scala 138:60] - node T_1235 = or(UInt<3>("h00"), UInt<1>("h00")) @[Definitions.scala 386:49] - node T_1236 = bits(T_1235, 2, 0) @[Definitions.scala 386:61] - node T_1238 = or(UInt<2>("h00"), UInt<2>("h03")) @[Definitions.scala 387:61] - node T_1239 = bits(T_1238, 1, 0) @[Definitions.scala 387:76] - node T_1241 = or(UInt<5>("h00"), UInt<5>("h00")) @[Definitions.scala 388:36] - node T_1242 = bits(T_1241, 4, 0) @[Definitions.scala 388:45] - node T_1244 = or(UInt<8>("h00"), UInt<1>("h00")) @[Definitions.scala 389:46] - node T_1245 = bits(T_1244, 7, 0) @[Definitions.scala 389:54] - node T_1248 = cat(T_1242, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1249 = cat(T_1236, T_1239) @[Cat.scala 20:58] - node T_1250 = cat(T_1249, T_1248) @[Cat.scala 20:58] - node T_1252 = cat(T_1239, T_1242) @[Cat.scala 20:58] - node T_1253 = cat(T_1252, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1255 = cat(T_1245, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1257 = cat(T_1245, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1259 = cat(T_1242, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1260 = cat(T_1236, T_1239) @[Cat.scala 20:58] - node T_1261 = cat(T_1260, T_1259) @[Cat.scala 20:58] - node T_1263 = cat(UInt<5>("h00"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_1265 = cat(UInt<5>("h01"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_1266 = eq(UInt<3>("h06"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1267 = mux(T_1266, T_1265, UInt<1>("h00")) @[Mux.scala 46:16] - node T_1268 = eq(UInt<3>("h05"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1269 = mux(T_1268, T_1263, T_1267) @[Mux.scala 46:16] - node T_1270 = eq(UInt<3>("h04"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1271 = mux(T_1270, T_1261, T_1269) @[Mux.scala 46:16] - node T_1272 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1273 = mux(T_1272, T_1257, T_1271) @[Mux.scala 46:16] - node T_1274 = eq(UInt<3>("h02"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1275 = mux(T_1274, T_1255, T_1273) @[Mux.scala 46:16] - node T_1276 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1277 = mux(T_1276, T_1253, T_1275) @[Mux.scala 46:16] - node T_1278 = eq(UInt<3>("h00"), UInt<3>("h01")) @[Mux.scala 46:19] - node T_1279 = mux(T_1278, T_1250, T_1277) @[Mux.scala 46:16] - wire T_1308 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_1308 is invalid @[Definitions.scala 417:19] - T_1308.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_1308.a_type <= UInt<3>("h01") @[Definitions.scala 419:16] - T_1308.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_1308.addr_block <= T_1184 @[Definitions.scala 421:20] - T_1308.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_1308.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_1308.union <= T_1279 @[Definitions.scala 424:15] - io.mem.acquire.bits <- T_1308 @[icache.scala 138:23] - node T_1336 = eq(UInt<2>("h00"), state) @[Conditional.scala 24:42] - when T_1336 : @[Conditional.scala 24:73] - when s1_miss : @[icache.scala 143:22] - state <= UInt<2>("h01") @[icache.scala 143:30] - skip @[icache.scala 143:22] - invalidated <= UInt<1>("h00") @[icache.scala 144:19] - skip @[Conditional.scala 24:73] - node T_1338 = eq(UInt<2>("h01"), state) @[Conditional.scala 24:42] - when T_1338 : @[Conditional.scala 24:73] - when io.mem.acquire.ready : @[icache.scala 147:35] - state <= UInt<2>("h02") @[icache.scala 147:43] - skip @[icache.scala 147:35] - when io.s2_kill : @[icache.scala 148:25] - state <= UInt<2>("h00") @[icache.scala 148:33] - skip @[icache.scala 148:25] - skip @[Conditional.scala 24:73] - node T_1339 = eq(UInt<2>("h02"), state) @[Conditional.scala 24:42] - when T_1339 : @[Conditional.scala 24:73] - when io.mem.grant.valid : @[icache.scala 151:33] - state <= UInt<2>("h03") @[icache.scala 151:41] - skip @[icache.scala 151:33] - skip @[Conditional.scala 24:73] - node T_1340 = eq(UInt<2>("h03"), state) @[Conditional.scala 24:42] - when T_1340 : @[Conditional.scala 24:73] - when refill_done : @[icache.scala 154:26] - state <= UInt<2>("h00") @[icache.scala 154:34] - skip @[icache.scala 154:26] - skip @[Conditional.scala 24:73] - - module TLB : + T_1179 <= T_1178 + io.resp.bits.datablock <= T_1179 + io.resp.valid <= T_1154 + node T_1180 = eq(state, UInt<2>("h1")) + node T_1182 = eq(io.s2_kill, UInt<1>("h0")) + node T_1183 = and(T_1180, T_1182) + io.mem.acquire.valid <= T_1183 + node T_1184 = shr(refill_addr, 6) + node T_1235 = or(UInt<3>("h0"), UInt<1>("h0")) + node T_1236 = bits(T_1235, 2, 0) + node T_1238 = or(UInt<2>("h0"), UInt<2>("h3")) + node T_1239 = bits(T_1238, 1, 0) + node T_1241 = or(UInt<5>("h0"), UInt<5>("h0")) + node T_1242 = bits(T_1241, 4, 0) + node T_1244 = or(UInt<8>("h0"), UInt<1>("h0")) + node T_1245 = bits(T_1244, 7, 0) + node T_1248 = cat(T_1242, UInt<1>("h1")) + node T_1249 = cat(T_1236, T_1239) + node T_1250 = cat(T_1249, T_1248) + node T_1252 = cat(T_1239, T_1242) + node T_1253 = cat(T_1252, UInt<1>("h1")) + node T_1255 = cat(T_1245, UInt<1>("h1")) + node T_1257 = cat(T_1245, UInt<1>("h1")) + node T_1259 = cat(T_1242, UInt<1>("h1")) + node T_1260 = cat(T_1236, T_1239) + node T_1261 = cat(T_1260, T_1259) + node T_1263 = cat(UInt<5>("h0"), UInt<1>("h1")) + node T_1265 = cat(UInt<5>("h1"), UInt<1>("h1")) + node T_1266 = eq(UInt<3>("h6"), UInt<3>("h1")) + node T_1267 = mux(T_1266, T_1265, UInt<1>("h0")) + node T_1268 = eq(UInt<3>("h5"), UInt<3>("h1")) + node T_1269 = mux(T_1268, T_1263, T_1267) + node T_1270 = eq(UInt<3>("h4"), UInt<3>("h1")) + node T_1271 = mux(T_1270, T_1261, T_1269) + node T_1272 = eq(UInt<3>("h3"), UInt<3>("h1")) + node T_1273 = mux(T_1272, T_1257, T_1271) + node T_1274 = eq(UInt<3>("h2"), UInt<3>("h1")) + node T_1275 = mux(T_1274, T_1255, T_1273) + node T_1276 = eq(UInt<3>("h1"), UInt<3>("h1")) + node T_1277 = mux(T_1276, T_1253, T_1275) + node T_1278 = eq(UInt<3>("h0"), UInt<3>("h1")) + node T_1279 = mux(T_1278, T_1250, T_1277) + wire T_1308 : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_1308 is invalid + T_1308.is_builtin_type <= UInt<1>("h1") + T_1308.a_type <= UInt<3>("h1") + T_1308.client_xact_id <= UInt<1>("h0") + T_1308.addr_block <= T_1184 + T_1308.addr_beat <= UInt<1>("h0") + T_1308.data <= UInt<1>("h0") + T_1308.union <= T_1279 + io.mem.acquire.bits <- T_1308 + node T_1336 = eq(UInt<2>("h0"), state) + when T_1336 : + when s1_miss : + state <= UInt<2>("h1") + invalidated <= UInt<1>("h0") + node T_1338 = eq(UInt<2>("h1"), state) + when T_1338 : + when io.mem.acquire.ready : + state <= UInt<2>("h2") + when io.s2_kill : + state <= UInt<2>("h0") + node T_1339 = eq(UInt<2>("h2"), state) + when T_1339 : + when io.mem.grant.valid : + state <= UInt<2>("h3") + node T_1340 = eq(UInt<2>("h3"), state) + when T_1340 : + when refill_done : + state <= UInt<2>("h0") + + module TLB : input clk : Clock input reset : UInt<1> - output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, cacheable : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} - + output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : { miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, cacheable : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} + io is invalid - reg valid : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg ppns : UInt<20>[8], clk - reg tags : UInt<34>[8], clk - reg state : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) - reg r_refill_tag : UInt<34>, clk - reg r_refill_waddr : UInt<3>, clk - reg r_req : {vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk - node T_219 = eq(io.req.bits.instruction, UInt<1>("h00")) @[tlb.scala 58:39] - node do_mprv = and(io.ptw.status.mprv, T_219) @[tlb.scala 58:36] - node priv = mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv) @[tlb.scala 59:17] - node priv_s = eq(priv, UInt<1>("h01")) @[tlb.scala 60:21] - node T_222 = leq(priv, UInt<1>("h01")) @[tlb.scala 61:27] - node T_224 = eq(io.ptw.status.debug, UInt<1>("h00")) @[tlb.scala 61:39] - node priv_uses_vm = and(T_222, T_224) @[tlb.scala 61:36] - node passthrough_ppn = bits(io.req.bits.vpn, 19, 0) @[tlb.scala 64:40] - node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) @[tlb.scala 65:44] - node do_refill = and(UInt<1>("h01"), io.ptw.resp.valid) @[tlb.scala 66:33] - node mpu_ppn = mux(do_refill, refill_ppn, passthrough_ppn) @[tlb.scala 67:20] - node T_226 = shl(mpu_ppn, 12) @[tlb.scala 68:38] - node T_228 = leq(UInt<1>("h00"), T_226) @[addrmap.scala 26:46] - node T_230 = lt(T_226, UInt<13>("h01000")) @[addrmap.scala 26:56] - node T_231 = and(T_228, T_230) @[addrmap.scala 26:51] - node T_234 = mux(T_231, UInt<3>("h07"), UInt<1>("h00")) @[addrmap.scala 150:10] - node T_236 = leq(UInt<13>("h01000"), T_226) @[addrmap.scala 26:46] - node T_238 = lt(T_226, UInt<14>("h02000")) @[addrmap.scala 26:56] - node T_239 = and(T_236, T_238) @[addrmap.scala 26:51] - node T_242 = mux(T_239, UInt<3>("h05"), UInt<1>("h00")) @[addrmap.scala 150:10] - node T_244 = leq(UInt<31>("h040000000"), T_226) @[addrmap.scala 26:46] - node T_246 = lt(T_226, UInt<31>("h044000000")) @[addrmap.scala 26:56] - node T_247 = and(T_244, T_246) @[addrmap.scala 26:51] - node T_250 = mux(T_247, UInt<3>("h03"), UInt<1>("h00")) @[addrmap.scala 150:10] - node T_252 = leq(UInt<31>("h044000000"), T_226) @[addrmap.scala 26:46] - node T_254 = lt(T_226, UInt<31>("h048000000")) @[addrmap.scala 26:56] - node T_255 = and(T_252, T_254) @[addrmap.scala 26:51] - node T_258 = mux(T_255, UInt<3>("h03"), UInt<1>("h00")) @[addrmap.scala 150:10] - node T_260 = leq(UInt<32>("h080000000"), T_226) @[addrmap.scala 26:46] - node T_262 = lt(T_226, UInt<32>("h090000000")) @[addrmap.scala 26:56] - node T_263 = and(T_260, T_262) @[addrmap.scala 26:51] - node T_266 = mux(T_263, UInt<3>("h07"), UInt<1>("h00")) @[addrmap.scala 150:10] - node T_271 = or(T_234, T_242) @[addrmap.scala 153:54] - node T_272 = or(T_271, T_250) @[addrmap.scala 153:54] - node T_273 = or(T_272, T_258) @[addrmap.scala 153:54] - node T_274 = or(T_273, T_266) @[addrmap.scala 153:54] - wire prot : {x : UInt<1>, w : UInt<1>, r : UInt<1>} @[addrmap.scala 153:31] - prot is invalid @[addrmap.scala 153:31] - node T_282 = bits(T_274, 0, 0) @[addrmap.scala 153:31] - prot.r <= T_282 @[addrmap.scala 153:31] - node T_283 = bits(T_274, 1, 1) @[addrmap.scala 153:31] - prot.w <= T_283 @[addrmap.scala 153:31] - node T_284 = bits(T_274, 2, 2) @[addrmap.scala 153:31] - prot.x <= T_284 @[addrmap.scala 153:31] - node T_285 = shl(mpu_ppn, 12) @[tlb.scala 69:47] - node T_287 = leq(UInt<32>("h080000000"), T_285) @[addrmap.scala 26:46] - node T_289 = lt(T_285, UInt<32>("h090000000")) @[addrmap.scala 26:56] - node T_290 = and(T_287, T_289) @[addrmap.scala 26:51] - node cacheable = or(UInt<1>("h00"), T_290) @[addrmap.scala 141:31] - node T_292 = bits(io.req.bits.vpn, 26, 0) @[tlb.scala 77:57] - node lookup_tag = cat(io.ptw.ptbr.asid, T_292) @[Cat.scala 20:58] - node T_294 = bits(io.ptw.status.vm, 3, 3) @[tlb.scala 78:53] - node T_295 = and(UInt<1>("h01"), T_294) @[tlb.scala 78:34] - node T_296 = and(T_295, priv_uses_vm) @[tlb.scala 78:57] - node T_298 = eq(io.req.bits.passthrough, UInt<1>("h00")) @[tlb.scala 78:76] - node vm_enabled = and(T_296, T_298) @[tlb.scala 78:73] - node T_299 = bits(valid, 0, 0) @[tlb.scala 79:49] - node T_300 = and(T_299, vm_enabled) @[tlb.scala 79:53] - node T_301 = eq(tags[0], lookup_tag) @[tlb.scala 79:78] - node hitsVec_0 = and(T_300, T_301) @[tlb.scala 79:67] - node T_302 = bits(valid, 1, 1) @[tlb.scala 79:49] - node T_303 = and(T_302, vm_enabled) @[tlb.scala 79:53] - node T_304 = eq(tags[1], lookup_tag) @[tlb.scala 79:78] - node hitsVec_1 = and(T_303, T_304) @[tlb.scala 79:67] - node T_305 = bits(valid, 2, 2) @[tlb.scala 79:49] - node T_306 = and(T_305, vm_enabled) @[tlb.scala 79:53] - node T_307 = eq(tags[2], lookup_tag) @[tlb.scala 79:78] - node hitsVec_2 = and(T_306, T_307) @[tlb.scala 79:67] - node T_308 = bits(valid, 3, 3) @[tlb.scala 79:49] - node T_309 = and(T_308, vm_enabled) @[tlb.scala 79:53] - node T_310 = eq(tags[3], lookup_tag) @[tlb.scala 79:78] - node hitsVec_3 = and(T_309, T_310) @[tlb.scala 79:67] - node T_311 = bits(valid, 4, 4) @[tlb.scala 79:49] - node T_312 = and(T_311, vm_enabled) @[tlb.scala 79:53] - node T_313 = eq(tags[4], lookup_tag) @[tlb.scala 79:78] - node hitsVec_4 = and(T_312, T_313) @[tlb.scala 79:67] - node T_314 = bits(valid, 5, 5) @[tlb.scala 79:49] - node T_315 = and(T_314, vm_enabled) @[tlb.scala 79:53] - node T_316 = eq(tags[5], lookup_tag) @[tlb.scala 79:78] - node hitsVec_5 = and(T_315, T_316) @[tlb.scala 79:67] - node T_317 = bits(valid, 6, 6) @[tlb.scala 79:49] - node T_318 = and(T_317, vm_enabled) @[tlb.scala 79:53] - node T_319 = eq(tags[6], lookup_tag) @[tlb.scala 79:78] - node hitsVec_6 = and(T_318, T_319) @[tlb.scala 79:67] - node T_320 = bits(valid, 7, 7) @[tlb.scala 79:49] - node T_321 = and(T_320, vm_enabled) @[tlb.scala 79:53] - node T_322 = eq(tags[7], lookup_tag) @[tlb.scala 79:78] - node hitsVec_7 = and(T_321, T_322) @[tlb.scala 79:67] - node hitsVec_8 = eq(vm_enabled, UInt<1>("h00")) @[tlb.scala 79:97] - node T_324 = cat(hitsVec_1, hitsVec_0) @[Cat.scala 20:58] - node T_325 = cat(hitsVec_3, hitsVec_2) @[Cat.scala 20:58] - node T_326 = cat(T_325, T_324) @[Cat.scala 20:58] - node T_327 = cat(hitsVec_5, hitsVec_4) @[Cat.scala 20:58] - node T_328 = cat(hitsVec_8, hitsVec_7) @[Cat.scala 20:58] - node T_329 = cat(T_328, hitsVec_6) @[Cat.scala 20:58] - node T_330 = cat(T_329, T_327) @[Cat.scala 20:58] - node hits = cat(T_330, T_326) @[Cat.scala 20:58] - reg pte_array : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clk - reg u_array : UInt<8>, clk - reg sw_array : UInt<8>, clk - reg sx_array : UInt<8>, clk - reg sr_array : UInt<8>, clk - reg xr_array : UInt<8>, clk - reg cash_array : UInt<8>, clk - reg dirty_array : UInt<8>, clk - when do_refill : @[tlb.scala 91:20] - ppns[r_refill_waddr] <= io.ptw.resp.bits.pte.ppn @[tlb.scala 93:26] - tags[r_refill_waddr] <= r_refill_tag @[tlb.scala 94:26] - node T_362 = dshl(UInt<1>("h01"), r_refill_waddr) @[OneHot.scala 44:15] - node T_363 = or(valid, T_362) @[tlb.scala 97:20] - valid <= T_363 @[tlb.scala 97:11] - node T_364 = or(u_array, T_362) @[tlb.scala 98:35] - node T_365 = not(T_362) @[tlb.scala 98:53] - node T_366 = and(u_array, T_365) @[tlb.scala 98:51] - node T_367 = mux(io.ptw.resp.bits.pte.u, T_364, T_366) @[tlb.scala 98:19] - u_array <= T_367 @[tlb.scala 98:13] - node T_369 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[ptw.scala 53:47] - node T_370 = and(io.ptw.resp.bits.pte.x, T_369) @[ptw.scala 53:44] - node T_371 = or(io.ptw.resp.bits.pte.r, T_370) @[ptw.scala 53:38] - node T_372 = and(io.ptw.resp.bits.pte.v, T_371) @[ptw.scala 53:32] - node T_373 = and(T_372, io.ptw.resp.bits.pte.w) @[ptw.scala 58:35] - node T_374 = and(T_373, prot.w) @[tlb.scala 99:30] - node T_375 = or(sw_array, T_362) @[tlb.scala 99:50] - node T_376 = not(T_362) @[tlb.scala 99:69] - node T_377 = and(sw_array, T_376) @[tlb.scala 99:67] - node T_378 = mux(T_374, T_375, T_377) @[tlb.scala 99:20] - sw_array <= T_378 @[tlb.scala 99:14] - node T_380 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[ptw.scala 53:47] - node T_381 = and(io.ptw.resp.bits.pte.x, T_380) @[ptw.scala 53:44] - node T_382 = or(io.ptw.resp.bits.pte.r, T_381) @[ptw.scala 53:38] - node T_383 = and(io.ptw.resp.bits.pte.v, T_382) @[ptw.scala 53:32] - node T_384 = and(T_383, io.ptw.resp.bits.pte.x) @[ptw.scala 59:35] - node T_385 = and(T_384, prot.x) @[tlb.scala 100:30] - node T_386 = or(sx_array, T_362) @[tlb.scala 100:50] - node T_387 = not(T_362) @[tlb.scala 100:69] - node T_388 = and(sx_array, T_387) @[tlb.scala 100:67] - node T_389 = mux(T_385, T_386, T_388) @[tlb.scala 100:20] - sx_array <= T_389 @[tlb.scala 100:14] - node T_391 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[ptw.scala 53:47] - node T_392 = and(io.ptw.resp.bits.pte.x, T_391) @[ptw.scala 53:44] - node T_393 = or(io.ptw.resp.bits.pte.r, T_392) @[ptw.scala 53:38] - node T_394 = and(io.ptw.resp.bits.pte.v, T_393) @[ptw.scala 53:32] - node T_395 = and(T_394, io.ptw.resp.bits.pte.r) @[ptw.scala 57:35] - node T_396 = and(T_395, prot.r) @[tlb.scala 101:30] - node T_397 = or(sr_array, T_362) @[tlb.scala 101:50] - node T_398 = not(T_362) @[tlb.scala 101:69] - node T_399 = and(sr_array, T_398) @[tlb.scala 101:67] - node T_400 = mux(T_396, T_397, T_399) @[tlb.scala 101:20] - sr_array <= T_400 @[tlb.scala 101:14] - node T_402 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h00")) @[ptw.scala 53:47] - node T_403 = and(io.ptw.resp.bits.pte.x, T_402) @[ptw.scala 53:44] - node T_404 = or(io.ptw.resp.bits.pte.r, T_403) @[ptw.scala 53:38] - node T_405 = and(io.ptw.resp.bits.pte.v, T_404) @[ptw.scala 53:32] - node T_406 = and(T_405, io.ptw.resp.bits.pte.x) @[ptw.scala 59:35] - node T_407 = and(T_406, prot.r) @[tlb.scala 102:30] - node T_408 = or(xr_array, T_362) @[tlb.scala 102:50] - node T_409 = not(T_362) @[tlb.scala 102:69] - node T_410 = and(xr_array, T_409) @[tlb.scala 102:67] - node T_411 = mux(T_407, T_408, T_410) @[tlb.scala 102:20] - xr_array <= T_411 @[tlb.scala 102:14] - node T_412 = or(cash_array, T_362) @[tlb.scala 103:45] - node T_413 = not(T_362) @[tlb.scala 103:66] - node T_414 = and(cash_array, T_413) @[tlb.scala 103:64] - node T_415 = mux(cacheable, T_412, T_414) @[tlb.scala 103:22] - cash_array <= T_415 @[tlb.scala 103:16] - node T_416 = or(dirty_array, T_362) @[tlb.scala 104:43] - node T_417 = not(T_362) @[tlb.scala 104:65] - node T_418 = and(dirty_array, T_417) @[tlb.scala 104:63] - node T_419 = mux(io.ptw.resp.bits.pte.d, T_416, T_418) @[tlb.scala 104:23] - dirty_array <= T_419 @[tlb.scala 104:17] - skip @[tlb.scala 91:20] - reg T_421 : UInt<8>, clk - node T_422 = not(valid) @[tlb.scala 108:31] - node T_424 = eq(T_422, UInt<1>("h00")) @[tlb.scala 108:31] - node T_426 = eq(T_424, UInt<1>("h00")) @[tlb.scala 108:24] - node T_427 = not(valid) @[tlb.scala 108:53] - node T_428 = bits(T_427, 0, 0) @[OneHot.scala 35:40] - node T_429 = bits(T_427, 1, 1) @[OneHot.scala 35:40] - node T_430 = bits(T_427, 2, 2) @[OneHot.scala 35:40] - node T_431 = bits(T_427, 3, 3) @[OneHot.scala 35:40] - node T_432 = bits(T_427, 4, 4) @[OneHot.scala 35:40] - node T_433 = bits(T_427, 5, 5) @[OneHot.scala 35:40] - node T_434 = bits(T_427, 6, 6) @[OneHot.scala 35:40] - node T_435 = bits(T_427, 7, 7) @[OneHot.scala 35:40] - node T_444 = mux(T_434, UInt<3>("h06"), UInt<3>("h07")) @[Mux.scala 31:69] - node T_445 = mux(T_433, UInt<3>("h05"), T_444) @[Mux.scala 31:69] - node T_446 = mux(T_432, UInt<3>("h04"), T_445) @[Mux.scala 31:69] - node T_447 = mux(T_431, UInt<2>("h03"), T_446) @[Mux.scala 31:69] - node T_448 = mux(T_430, UInt<2>("h02"), T_447) @[Mux.scala 31:69] - node T_449 = mux(T_429, UInt<1>("h01"), T_448) @[Mux.scala 31:69] - node T_450 = mux(T_428, UInt<1>("h00"), T_449) @[Mux.scala 31:69] - node T_452 = dshr(T_421, UInt<1>("h01")) @[Cache.scala 104:27] - node T_453 = bits(T_452, 0, 0) @[Cache.scala 104:27] - node T_454 = cat(UInt<1>("h01"), T_453) @[Cat.scala 20:58] - node T_455 = dshr(T_421, T_454) @[Cache.scala 104:27] - node T_456 = bits(T_455, 0, 0) @[Cache.scala 104:27] - node T_457 = cat(T_454, T_456) @[Cat.scala 20:58] - node T_458 = dshr(T_421, T_457) @[Cache.scala 104:27] - node T_459 = bits(T_458, 0, 0) @[Cache.scala 104:27] - node T_460 = cat(T_457, T_459) @[Cat.scala 20:58] - node T_461 = bits(T_460, 2, 0) @[Cache.scala 105:8] - node repl_waddr = mux(T_426, T_450, T_461) @[tlb.scala 108:23] - node T_463 = mux(io.ptw.status.pum, u_array, UInt<1>("h00")) @[tlb.scala 110:33] - node T_464 = not(T_463) @[tlb.scala 110:29] - node priv_ok = mux(priv_s, T_464, u_array) @[tlb.scala 110:20] - node T_465 = and(priv_ok, sw_array) @[tlb.scala 111:37] - node w_array = cat(prot.w, T_465) @[Cat.scala 20:58] - node T_466 = and(priv_ok, sx_array) @[tlb.scala 112:37] - node x_array = cat(prot.x, T_466) @[Cat.scala 20:58] - node T_468 = mux(io.ptw.status.mxr, xr_array, UInt<1>("h00")) @[tlb.scala 113:54] - node T_469 = or(sr_array, T_468) @[tlb.scala 113:49] - node T_470 = and(priv_ok, T_469) @[tlb.scala 113:37] - node r_array = cat(prot.r, T_470) @[Cat.scala 20:58] - node c_array = cat(cacheable, cash_array) @[Cat.scala 20:58] - node T_471 = bits(io.req.bits.vpn, 27, 27) @[tlb.scala 118:25] - node T_472 = bits(io.req.bits.vpn, 26, 26) @[tlb.scala 118:54] - node bad_va = neq(T_471, T_472) @[tlb.scala 118:35] - node T_473 = bits(hits, 7, 0) @[tlb.scala 120:22] - node T_475 = mux(io.req.bits.store, w_array, UInt<1>("h00")) @[tlb.scala 120:58] - node T_476 = not(T_475) @[tlb.scala 120:54] - node T_477 = or(dirty_array, T_476) @[tlb.scala 120:52] - node tlb_hits = and(T_473, T_477) @[tlb.scala 120:37] - node tlb_hit = neq(tlb_hits, UInt<1>("h00")) @[tlb.scala 121:26] - node T_480 = eq(bad_va, UInt<1>("h00")) @[tlb.scala 122:32] - node T_481 = and(vm_enabled, T_480) @[tlb.scala 122:29] - node T_483 = eq(tlb_hit, UInt<1>("h00")) @[tlb.scala 122:43] - node tlb_miss = and(T_481, T_483) @[tlb.scala 122:40] - node T_485 = eq(tlb_miss, UInt<1>("h00")) @[tlb.scala 124:25] - node T_486 = and(io.req.valid, T_485) @[tlb.scala 124:22] - when T_486 : @[tlb.scala 124:36] - node T_487 = bits(hits, 7, 0) @[tlb.scala 125:30] - node T_488 = bits(T_487, 7, 4) @[OneHot.scala 22:18] - node T_489 = bits(T_487, 3, 0) @[OneHot.scala 23:18] - node T_491 = neq(T_488, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_492 = or(T_488, T_489) @[OneHot.scala 24:28] - node T_493 = bits(T_492, 3, 2) @[OneHot.scala 22:18] - node T_494 = bits(T_492, 1, 0) @[OneHot.scala 23:18] - node T_496 = neq(T_493, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_497 = or(T_493, T_494) @[OneHot.scala 24:28] - node T_498 = bits(T_497, 1, 1) @[CircuitMath.scala 21:8] - node T_499 = cat(T_496, T_498) @[Cat.scala 20:58] - node T_500 = cat(T_491, T_499) @[Cat.scala 20:58] - node T_502 = bits(T_500, 2, 2) @[Cache.scala 94:20] - node T_504 = eq(T_502, UInt<1>("h00")) @[Cache.scala 95:43] - node T_506 = dshl(UInt<1>("h01"), UInt<1>("h01")) @[Cache.scala 95:37] - node T_507 = or(T_421, T_506) @[Cache.scala 95:37] - node T_508 = not(T_421) @[Cache.scala 95:37] - node T_509 = or(T_508, T_506) @[Cache.scala 95:37] - node T_510 = not(T_509) @[Cache.scala 95:37] - node T_511 = mux(T_504, T_507, T_510) @[Cache.scala 95:37] - node T_512 = cat(UInt<1>("h01"), T_502) @[Cat.scala 20:58] - node T_513 = bits(T_500, 1, 1) @[Cache.scala 94:20] - node T_515 = eq(T_513, UInt<1>("h00")) @[Cache.scala 95:43] - node T_517 = dshl(UInt<1>("h01"), T_512) @[Cache.scala 95:37] - node T_518 = or(T_511, T_517) @[Cache.scala 95:37] - node T_519 = not(T_511) @[Cache.scala 95:37] - node T_520 = or(T_519, T_517) @[Cache.scala 95:37] - node T_521 = not(T_520) @[Cache.scala 95:37] - node T_522 = mux(T_515, T_518, T_521) @[Cache.scala 95:37] - node T_523 = cat(T_512, T_513) @[Cat.scala 20:58] - node T_524 = bits(T_500, 0, 0) @[Cache.scala 94:20] - node T_526 = eq(T_524, UInt<1>("h00")) @[Cache.scala 95:43] - node T_528 = dshl(UInt<1>("h01"), T_523) @[Cache.scala 95:37] - node T_529 = or(T_522, T_528) @[Cache.scala 95:37] - node T_530 = not(T_522) @[Cache.scala 95:37] - node T_531 = or(T_530, T_528) @[Cache.scala 95:37] - node T_532 = not(T_531) @[Cache.scala 95:37] - node T_533 = mux(T_526, T_529, T_532) @[Cache.scala 95:37] - node T_534 = cat(T_523, T_524) @[Cat.scala 20:58] - T_421 <= T_533 @[Cache.scala 88:15] - skip @[tlb.scala 124:36] - node T_535 = eq(state, UInt<2>("h00")) @[tlb.scala 128:25] - io.req.ready <= T_535 @[tlb.scala 128:16] - node T_536 = not(r_array) @[tlb.scala 129:33] - node T_537 = and(T_536, hits) @[tlb.scala 129:42] - node T_539 = neq(T_537, UInt<1>("h00")) @[tlb.scala 129:50] - node T_540 = or(bad_va, T_539) @[tlb.scala 129:29] - io.resp.xcpt_ld <= T_540 @[tlb.scala 129:19] - node T_541 = not(w_array) @[tlb.scala 130:33] - node T_542 = and(T_541, hits) @[tlb.scala 130:42] - node T_544 = neq(T_542, UInt<1>("h00")) @[tlb.scala 130:50] - node T_545 = or(bad_va, T_544) @[tlb.scala 130:29] - io.resp.xcpt_st <= T_545 @[tlb.scala 130:19] - node T_546 = not(x_array) @[tlb.scala 131:33] - node T_547 = and(T_546, hits) @[tlb.scala 131:42] - node T_549 = neq(T_547, UInt<1>("h00")) @[tlb.scala 131:50] - node T_550 = or(bad_va, T_549) @[tlb.scala 131:29] - io.resp.xcpt_if <= T_550 @[tlb.scala 131:19] - node T_551 = and(c_array, hits) @[tlb.scala 132:33] - node T_553 = neq(T_551, UInt<1>("h00")) @[tlb.scala 132:41] - io.resp.cacheable <= T_553 @[tlb.scala 132:21] - node T_554 = or(do_refill, tlb_miss) @[tlb.scala 133:29] - io.resp.miss <= T_554 @[tlb.scala 133:16] - node T_556 = mux(hitsVec_0, ppns[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_558 = mux(hitsVec_1, ppns[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_560 = mux(hitsVec_2, ppns[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_562 = mux(hitsVec_3, ppns[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_564 = mux(hitsVec_4, ppns[4], UInt<1>("h00")) @[Mux.scala 18:72] - node T_566 = mux(hitsVec_5, ppns[5], UInt<1>("h00")) @[Mux.scala 18:72] - node T_568 = mux(hitsVec_6, ppns[6], UInt<1>("h00")) @[Mux.scala 18:72] - node T_570 = mux(hitsVec_7, ppns[7], UInt<1>("h00")) @[Mux.scala 18:72] - node T_572 = mux(hitsVec_8, passthrough_ppn, UInt<1>("h00")) @[Mux.scala 18:72] - node T_574 = or(T_556, T_558) @[Mux.scala 18:72] - node T_575 = or(T_574, T_560) @[Mux.scala 18:72] - node T_576 = or(T_575, T_562) @[Mux.scala 18:72] - node T_577 = or(T_576, T_564) @[Mux.scala 18:72] - node T_578 = or(T_577, T_566) @[Mux.scala 18:72] - node T_579 = or(T_578, T_568) @[Mux.scala 18:72] - node T_580 = or(T_579, T_570) @[Mux.scala 18:72] - node T_581 = or(T_580, T_572) @[Mux.scala 18:72] + reg valid : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg ppns : UInt<20>[8], clk with : + reset => (UInt<1>("h0"), ppns) + reg tags : UInt<34>[8], clk with : + reset => (UInt<1>("h0"), tags) + reg state : UInt<2>, clk with : + reset => (reset, UInt<2>("h0")) + reg r_refill_tag : UInt<34>, clk with : + reset => (UInt<1>("h0"), r_refill_tag) + reg r_refill_waddr : UInt<3>, clk with : + reset => (UInt<1>("h0"), r_refill_waddr) + reg r_req : { vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk with : + reset => (UInt<1>("h0"), r_req) + node T_219 = eq(io.req.bits.instruction, UInt<1>("h0")) + node do_mprv = and(io.ptw.status.mprv, T_219) + node priv = mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv) + node priv_s = eq(priv, UInt<1>("h1")) + node T_222 = leq(priv, UInt<1>("h1")) + node T_224 = eq(io.ptw.status.debug, UInt<1>("h0")) + node priv_uses_vm = and(T_222, T_224) + node passthrough_ppn = bits(io.req.bits.vpn, 19, 0) + node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) + node do_refill = and(UInt<1>("h1"), io.ptw.resp.valid) + node mpu_ppn = mux(do_refill, refill_ppn, passthrough_ppn) + node T_226 = shl(mpu_ppn, 12) + node T_228 = leq(UInt<1>("h0"), T_226) + node T_230 = lt(T_226, UInt<13>("h1000")) + node T_231 = and(T_228, T_230) + node T_234 = mux(T_231, UInt<3>("h7"), UInt<1>("h0")) + node T_236 = leq(UInt<13>("h1000"), T_226) + node T_238 = lt(T_226, UInt<14>("h2000")) + node T_239 = and(T_236, T_238) + node T_242 = mux(T_239, UInt<3>("h5"), UInt<1>("h0")) + node T_244 = leq(UInt<31>("h40000000"), T_226) + node T_246 = lt(T_226, UInt<31>("h44000000")) + node T_247 = and(T_244, T_246) + node T_250 = mux(T_247, UInt<3>("h3"), UInt<1>("h0")) + node T_252 = leq(UInt<31>("h44000000"), T_226) + node T_254 = lt(T_226, UInt<31>("h48000000")) + node T_255 = and(T_252, T_254) + node T_258 = mux(T_255, UInt<3>("h3"), UInt<1>("h0")) + node T_260 = leq(UInt<32>("h80000000"), T_226) + node T_262 = lt(T_226, UInt<32>("h90000000")) + node T_263 = and(T_260, T_262) + node T_266 = mux(T_263, UInt<3>("h7"), UInt<1>("h0")) + node T_271 = or(T_234, T_242) + node T_272 = or(T_271, T_250) + node T_273 = or(T_272, T_258) + node T_274 = or(T_273, T_266) + wire prot : { x : UInt<1>, w : UInt<1>, r : UInt<1>} + prot is invalid + node T_282 = bits(T_274, 0, 0) + prot.r <= T_282 + node T_283 = bits(T_274, 1, 1) + prot.w <= T_283 + node T_284 = bits(T_274, 2, 2) + prot.x <= T_284 + node T_285 = shl(mpu_ppn, 12) + node T_287 = leq(UInt<32>("h80000000"), T_285) + node T_289 = lt(T_285, UInt<32>("h90000000")) + node T_290 = and(T_287, T_289) + node cacheable = or(UInt<1>("h0"), T_290) + node T_292 = bits(io.req.bits.vpn, 26, 0) + node lookup_tag = cat(io.ptw.ptbr.asid, T_292) + node T_294 = bits(io.ptw.status.vm, 3, 3) + node T_295 = and(UInt<1>("h1"), T_294) + node T_296 = and(T_295, priv_uses_vm) + node T_298 = eq(io.req.bits.passthrough, UInt<1>("h0")) + node vm_enabled = and(T_296, T_298) + node T_299 = bits(valid, 0, 0) + node T_300 = and(T_299, vm_enabled) + node T_301 = eq(tags[0], lookup_tag) + node hitsVec_0 = and(T_300, T_301) + node T_302 = bits(valid, 1, 1) + node T_303 = and(T_302, vm_enabled) + node T_304 = eq(tags[1], lookup_tag) + node hitsVec_1 = and(T_303, T_304) + node T_305 = bits(valid, 2, 2) + node T_306 = and(T_305, vm_enabled) + node T_307 = eq(tags[2], lookup_tag) + node hitsVec_2 = and(T_306, T_307) + node T_308 = bits(valid, 3, 3) + node T_309 = and(T_308, vm_enabled) + node T_310 = eq(tags[3], lookup_tag) + node hitsVec_3 = and(T_309, T_310) + node T_311 = bits(valid, 4, 4) + node T_312 = and(T_311, vm_enabled) + node T_313 = eq(tags[4], lookup_tag) + node hitsVec_4 = and(T_312, T_313) + node T_314 = bits(valid, 5, 5) + node T_315 = and(T_314, vm_enabled) + node T_316 = eq(tags[5], lookup_tag) + node hitsVec_5 = and(T_315, T_316) + node T_317 = bits(valid, 6, 6) + node T_318 = and(T_317, vm_enabled) + node T_319 = eq(tags[6], lookup_tag) + node hitsVec_6 = and(T_318, T_319) + node T_320 = bits(valid, 7, 7) + node T_321 = and(T_320, vm_enabled) + node T_322 = eq(tags[7], lookup_tag) + node hitsVec_7 = and(T_321, T_322) + node hitsVec_8 = eq(vm_enabled, UInt<1>("h0")) + node T_324 = cat(hitsVec_1, hitsVec_0) + node T_325 = cat(hitsVec_3, hitsVec_2) + node T_326 = cat(T_325, T_324) + node T_327 = cat(hitsVec_5, hitsVec_4) + node T_328 = cat(hitsVec_8, hitsVec_7) + node T_329 = cat(T_328, hitsVec_6) + node T_330 = cat(T_329, T_327) + node hits = cat(T_330, T_326) + reg pte_array : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clk with : + reset => (UInt<1>("h0"), pte_array) + reg u_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), u_array) + reg sw_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), sw_array) + reg sx_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), sx_array) + reg sr_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), sr_array) + reg xr_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), xr_array) + reg cash_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), cash_array) + reg dirty_array : UInt<8>, clk with : + reset => (UInt<1>("h0"), dirty_array) + when do_refill : + ppns[r_refill_waddr] <= io.ptw.resp.bits.pte.ppn + tags[r_refill_waddr] <= r_refill_tag + node T_362 = dshl(UInt<1>("h1"), r_refill_waddr) + node T_363 = or(valid, T_362) + valid <= T_363 + node T_364 = or(u_array, T_362) + node T_365 = not(T_362) + node T_366 = and(u_array, T_365) + node T_367 = mux(io.ptw.resp.bits.pte.u, T_364, T_366) + u_array <= T_367 + node T_369 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h0")) + node T_370 = and(io.ptw.resp.bits.pte.x, T_369) + node T_371 = or(io.ptw.resp.bits.pte.r, T_370) + node T_372 = and(io.ptw.resp.bits.pte.v, T_371) + node T_373 = and(T_372, io.ptw.resp.bits.pte.w) + node T_374 = and(T_373, prot.w) + node T_375 = or(sw_array, T_362) + node T_376 = not(T_362) + node T_377 = and(sw_array, T_376) + node T_378 = mux(T_374, T_375, T_377) + sw_array <= T_378 + node T_380 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h0")) + node T_381 = and(io.ptw.resp.bits.pte.x, T_380) + node T_382 = or(io.ptw.resp.bits.pte.r, T_381) + node T_383 = and(io.ptw.resp.bits.pte.v, T_382) + node T_384 = and(T_383, io.ptw.resp.bits.pte.x) + node T_385 = and(T_384, prot.x) + node T_386 = or(sx_array, T_362) + node T_387 = not(T_362) + node T_388 = and(sx_array, T_387) + node T_389 = mux(T_385, T_386, T_388) + sx_array <= T_389 + node T_391 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h0")) + node T_392 = and(io.ptw.resp.bits.pte.x, T_391) + node T_393 = or(io.ptw.resp.bits.pte.r, T_392) + node T_394 = and(io.ptw.resp.bits.pte.v, T_393) + node T_395 = and(T_394, io.ptw.resp.bits.pte.r) + node T_396 = and(T_395, prot.r) + node T_397 = or(sr_array, T_362) + node T_398 = not(T_362) + node T_399 = and(sr_array, T_398) + node T_400 = mux(T_396, T_397, T_399) + sr_array <= T_400 + node T_402 = eq(io.ptw.resp.bits.pte.w, UInt<1>("h0")) + node T_403 = and(io.ptw.resp.bits.pte.x, T_402) + node T_404 = or(io.ptw.resp.bits.pte.r, T_403) + node T_405 = and(io.ptw.resp.bits.pte.v, T_404) + node T_406 = and(T_405, io.ptw.resp.bits.pte.x) + node T_407 = and(T_406, prot.r) + node T_408 = or(xr_array, T_362) + node T_409 = not(T_362) + node T_410 = and(xr_array, T_409) + node T_411 = mux(T_407, T_408, T_410) + xr_array <= T_411 + node T_412 = or(cash_array, T_362) + node T_413 = not(T_362) + node T_414 = and(cash_array, T_413) + node T_415 = mux(cacheable, T_412, T_414) + cash_array <= T_415 + node T_416 = or(dirty_array, T_362) + node T_417 = not(T_362) + node T_418 = and(dirty_array, T_417) + node T_419 = mux(io.ptw.resp.bits.pte.d, T_416, T_418) + dirty_array <= T_419 + reg T_421 : UInt<8>, clk with : + reset => (UInt<1>("h0"), T_421) + node T_422 = not(valid) + node T_424 = eq(T_422, UInt<1>("h0")) + node T_426 = eq(T_424, UInt<1>("h0")) + node T_427 = not(valid) + node T_428 = bits(T_427, 0, 0) + node T_429 = bits(T_427, 1, 1) + node T_430 = bits(T_427, 2, 2) + node T_431 = bits(T_427, 3, 3) + node T_432 = bits(T_427, 4, 4) + node T_433 = bits(T_427, 5, 5) + node T_434 = bits(T_427, 6, 6) + node T_435 = bits(T_427, 7, 7) + node T_444 = mux(T_434, UInt<3>("h6"), UInt<3>("h7")) + node T_445 = mux(T_433, UInt<3>("h5"), T_444) + node T_446 = mux(T_432, UInt<3>("h4"), T_445) + node T_447 = mux(T_431, UInt<2>("h3"), T_446) + node T_448 = mux(T_430, UInt<2>("h2"), T_447) + node T_449 = mux(T_429, UInt<1>("h1"), T_448) + node T_450 = mux(T_428, UInt<1>("h0"), T_449) + node T_452 = dshr(T_421, UInt<1>("h1")) + node T_453 = bits(T_452, 0, 0) + node T_454 = cat(UInt<1>("h1"), T_453) + node T_455 = dshr(T_421, T_454) + node T_456 = bits(T_455, 0, 0) + node T_457 = cat(T_454, T_456) + node T_458 = dshr(T_421, T_457) + node T_459 = bits(T_458, 0, 0) + node T_460 = cat(T_457, T_459) + node T_461 = bits(T_460, 2, 0) + node repl_waddr = mux(T_426, T_450, T_461) + node T_463 = mux(io.ptw.status.pum, u_array, UInt<1>("h0")) + node T_464 = not(T_463) + node priv_ok = mux(priv_s, T_464, u_array) + node T_465 = and(priv_ok, sw_array) + node w_array = cat(prot.w, T_465) + node T_466 = and(priv_ok, sx_array) + node x_array = cat(prot.x, T_466) + node T_468 = mux(io.ptw.status.mxr, xr_array, UInt<1>("h0")) + node T_469 = or(sr_array, T_468) + node T_470 = and(priv_ok, T_469) + node r_array = cat(prot.r, T_470) + node c_array = cat(cacheable, cash_array) + node T_471 = bits(io.req.bits.vpn, 27, 27) + node T_472 = bits(io.req.bits.vpn, 26, 26) + node bad_va = neq(T_471, T_472) + node T_473 = bits(hits, 7, 0) + node T_475 = mux(io.req.bits.store, w_array, UInt<1>("h0")) + node T_476 = not(T_475) + node T_477 = or(dirty_array, T_476) + node tlb_hits = and(T_473, T_477) + node tlb_hit = neq(tlb_hits, UInt<1>("h0")) + node T_480 = eq(bad_va, UInt<1>("h0")) + node T_481 = and(vm_enabled, T_480) + node T_483 = eq(tlb_hit, UInt<1>("h0")) + node tlb_miss = and(T_481, T_483) + node T_485 = eq(tlb_miss, UInt<1>("h0")) + node T_486 = and(io.req.valid, T_485) + when T_486 : + node T_487 = bits(hits, 7, 0) + node T_488 = bits(T_487, 7, 4) + node T_489 = bits(T_487, 3, 0) + node T_491 = neq(T_488, UInt<1>("h0")) + node T_492 = or(T_488, T_489) + node T_493 = bits(T_492, 3, 2) + node T_494 = bits(T_492, 1, 0) + node T_496 = neq(T_493, UInt<1>("h0")) + node T_497 = or(T_493, T_494) + node T_498 = bits(T_497, 1, 1) + node T_499 = cat(T_496, T_498) + node T_500 = cat(T_491, T_499) + node T_502 = bits(T_500, 2, 2) + node T_504 = eq(T_502, UInt<1>("h0")) + node T_506 = dshl(UInt<1>("h1"), UInt<1>("h1")) + node T_507 = or(T_421, T_506) + node T_508 = not(T_421) + node T_509 = or(T_508, T_506) + node T_510 = not(T_509) + node T_511 = mux(T_504, T_507, T_510) + node T_512 = cat(UInt<1>("h1"), T_502) + node T_513 = bits(T_500, 1, 1) + node T_515 = eq(T_513, UInt<1>("h0")) + node T_517 = dshl(UInt<1>("h1"), T_512) + node T_518 = or(T_511, T_517) + node T_519 = not(T_511) + node T_520 = or(T_519, T_517) + node T_521 = not(T_520) + node T_522 = mux(T_515, T_518, T_521) + node T_523 = cat(T_512, T_513) + node T_524 = bits(T_500, 0, 0) + node T_526 = eq(T_524, UInt<1>("h0")) + node T_528 = dshl(UInt<1>("h1"), T_523) + node T_529 = or(T_522, T_528) + node T_530 = not(T_522) + node T_531 = or(T_530, T_528) + node T_532 = not(T_531) + node T_533 = mux(T_526, T_529, T_532) + node T_534 = cat(T_523, T_524) + T_421 <= T_533 + node T_535 = eq(state, UInt<2>("h0")) + io.req.ready <= T_535 + node T_536 = not(r_array) + node T_537 = and(T_536, hits) + node T_539 = neq(T_537, UInt<1>("h0")) + node T_540 = or(bad_va, T_539) + io.resp.xcpt_ld <= T_540 + node T_541 = not(w_array) + node T_542 = and(T_541, hits) + node T_544 = neq(T_542, UInt<1>("h0")) + node T_545 = or(bad_va, T_544) + io.resp.xcpt_st <= T_545 + node T_546 = not(x_array) + node T_547 = and(T_546, hits) + node T_549 = neq(T_547, UInt<1>("h0")) + node T_550 = or(bad_va, T_549) + io.resp.xcpt_if <= T_550 + node T_551 = and(c_array, hits) + node T_553 = neq(T_551, UInt<1>("h0")) + io.resp.cacheable <= T_553 + node T_554 = or(do_refill, tlb_miss) + io.resp.miss <= T_554 + node T_556 = mux(hitsVec_0, ppns[0], UInt<1>("h0")) + node T_558 = mux(hitsVec_1, ppns[1], UInt<1>("h0")) + node T_560 = mux(hitsVec_2, ppns[2], UInt<1>("h0")) + node T_562 = mux(hitsVec_3, ppns[3], UInt<1>("h0")) + node T_564 = mux(hitsVec_4, ppns[4], UInt<1>("h0")) + node T_566 = mux(hitsVec_5, ppns[5], UInt<1>("h0")) + node T_568 = mux(hitsVec_6, ppns[6], UInt<1>("h0")) + node T_570 = mux(hitsVec_7, ppns[7], UInt<1>("h0")) + node T_572 = mux(hitsVec_8, passthrough_ppn, UInt<1>("h0")) + node T_574 = or(T_556, T_558) + node T_575 = or(T_574, T_560) + node T_576 = or(T_575, T_562) + node T_577 = or(T_576, T_564) + node T_578 = or(T_577, T_566) + node T_579 = or(T_578, T_568) + node T_580 = or(T_579, T_570) + node T_581 = or(T_580, T_572) wire T_582 : UInt<20> T_582 is invalid - T_582 <= T_581 @[Mux.scala 18:72] - io.resp.ppn <= T_582 @[tlb.scala 134:15] - node T_583 = eq(state, UInt<2>("h01")) @[tlb.scala 136:29] - io.ptw.req.valid <= T_583 @[tlb.scala 136:20] - io.ptw.req.bits <- io.ptw.status @[tlb.scala 137:19] - io.ptw.req.bits.addr <= r_refill_tag @[tlb.scala 138:24] - io.ptw.req.bits.store <= r_req.store @[tlb.scala 139:25] - io.ptw.req.bits.fetch <= r_req.instruction @[tlb.scala 140:25] - node T_584 = and(io.req.ready, io.req.valid) @[Decoupled.scala 21:42] - node T_585 = and(T_584, tlb_miss) @[tlb.scala 143:25] - when T_585 : @[tlb.scala 143:38] - state <= UInt<2>("h01") @[tlb.scala 144:13] - r_refill_tag <= lookup_tag @[tlb.scala 145:20] - r_refill_waddr <= repl_waddr @[tlb.scala 146:22] - r_req <- io.req.bits @[tlb.scala 147:13] - skip @[tlb.scala 143:38] - node T_586 = eq(state, UInt<2>("h01")) @[tlb.scala 149:17] - when T_586 : @[tlb.scala 149:32] - when io.ptw.invalidate : @[tlb.scala 150:32] - state <= UInt<2>("h00") @[tlb.scala 151:15] - skip @[tlb.scala 150:32] - when io.ptw.req.ready : @[tlb.scala 153:31] - state <= UInt<2>("h02") @[tlb.scala 154:15] - when io.ptw.invalidate : @[tlb.scala 155:34] - state <= UInt<2>("h03") @[tlb.scala 155:42] - skip @[tlb.scala 155:34] - skip @[tlb.scala 153:31] - skip @[tlb.scala 149:32] - node T_587 = eq(state, UInt<2>("h02")) @[tlb.scala 158:17] - node T_588 = and(T_587, io.ptw.invalidate) @[tlb.scala 158:28] - when T_588 : @[tlb.scala 158:50] - state <= UInt<2>("h03") @[tlb.scala 159:13] - skip @[tlb.scala 158:50] - when io.ptw.resp.valid : @[tlb.scala 161:30] - state <= UInt<2>("h00") @[tlb.scala 162:13] - skip @[tlb.scala 161:30] - when io.ptw.invalidate : @[tlb.scala 165:30] - valid <= UInt<1>("h00") @[tlb.scala 166:13] - skip @[tlb.scala 165:30] - - module BTB : + T_582 <= T_581 + io.resp.ppn <= T_582 + node T_583 = eq(state, UInt<2>("h1")) + io.ptw.req.valid <= T_583 + io.ptw.req.bits <- io.ptw.status + io.ptw.req.bits.addr <= r_refill_tag + io.ptw.req.bits.store <= r_req.store + io.ptw.req.bits.fetch <= r_req.instruction + node T_584 = and(io.req.ready, io.req.valid) + node T_585 = and(T_584, tlb_miss) + when T_585 : + state <= UInt<2>("h1") + r_refill_tag <= lookup_tag + r_refill_waddr <= repl_waddr + r_req <- io.req.bits + node T_586 = eq(state, UInt<2>("h1")) + when T_586 : + when io.ptw.invalidate : + state <= UInt<2>("h0") + when io.ptw.req.ready : + state <= UInt<2>("h2") + when io.ptw.invalidate : + state <= UInt<2>("h3") + node T_587 = eq(state, UInt<2>("h2")) + node T_588 = and(T_587, io.ptw.invalidate) + when T_588 : + state <= UInt<2>("h3") + when io.ptw.resp.valid : + state <= UInt<2>("h0") + when io.ptw.invalidate : + valid <= UInt<1>("h0") + + module BTB : input clk : Clock input reset : UInt<1> - output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}} - + output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<39>}}, resp : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, flip btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}} + + wire T_1551 : UInt<1> + T_1551 is invalid io is invalid - reg idxs : UInt<11>[40], clk - reg idxPages : UInt<3>[40], clk - reg tgts : UInt<11>[40], clk - reg tgtPages : UInt<3>[40], clk - reg pages : UInt<27>[6], clk - reg pageValid : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - node T_606 = dshl(UInt<1>("h01"), idxPages[0]) @[OneHot.scala 44:15] - node idxPagesOH_0 = bits(T_606, 5, 0) @[btb.scala 154:44] - node T_608 = dshl(UInt<1>("h01"), idxPages[1]) @[OneHot.scala 44:15] - node idxPagesOH_1 = bits(T_608, 5, 0) @[btb.scala 154:44] - node T_610 = dshl(UInt<1>("h01"), idxPages[2]) @[OneHot.scala 44:15] - node idxPagesOH_2 = bits(T_610, 5, 0) @[btb.scala 154:44] - node T_612 = dshl(UInt<1>("h01"), idxPages[3]) @[OneHot.scala 44:15] - node idxPagesOH_3 = bits(T_612, 5, 0) @[btb.scala 154:44] - node T_614 = dshl(UInt<1>("h01"), idxPages[4]) @[OneHot.scala 44:15] - node idxPagesOH_4 = bits(T_614, 5, 0) @[btb.scala 154:44] - node T_616 = dshl(UInt<1>("h01"), idxPages[5]) @[OneHot.scala 44:15] - node idxPagesOH_5 = bits(T_616, 5, 0) @[btb.scala 154:44] - node T_618 = dshl(UInt<1>("h01"), idxPages[6]) @[OneHot.scala 44:15] - node idxPagesOH_6 = bits(T_618, 5, 0) @[btb.scala 154:44] - node T_620 = dshl(UInt<1>("h01"), idxPages[7]) @[OneHot.scala 44:15] - node idxPagesOH_7 = bits(T_620, 5, 0) @[btb.scala 154:44] - node T_622 = dshl(UInt<1>("h01"), idxPages[8]) @[OneHot.scala 44:15] - node idxPagesOH_8 = bits(T_622, 5, 0) @[btb.scala 154:44] - node T_624 = dshl(UInt<1>("h01"), idxPages[9]) @[OneHot.scala 44:15] - node idxPagesOH_9 = bits(T_624, 5, 0) @[btb.scala 154:44] - node T_626 = dshl(UInt<1>("h01"), idxPages[10]) @[OneHot.scala 44:15] - node idxPagesOH_10 = bits(T_626, 5, 0) @[btb.scala 154:44] - node T_628 = dshl(UInt<1>("h01"), idxPages[11]) @[OneHot.scala 44:15] - node idxPagesOH_11 = bits(T_628, 5, 0) @[btb.scala 154:44] - node T_630 = dshl(UInt<1>("h01"), idxPages[12]) @[OneHot.scala 44:15] - node idxPagesOH_12 = bits(T_630, 5, 0) @[btb.scala 154:44] - node T_632 = dshl(UInt<1>("h01"), idxPages[13]) @[OneHot.scala 44:15] - node idxPagesOH_13 = bits(T_632, 5, 0) @[btb.scala 154:44] - node T_634 = dshl(UInt<1>("h01"), idxPages[14]) @[OneHot.scala 44:15] - node idxPagesOH_14 = bits(T_634, 5, 0) @[btb.scala 154:44] - node T_636 = dshl(UInt<1>("h01"), idxPages[15]) @[OneHot.scala 44:15] - node idxPagesOH_15 = bits(T_636, 5, 0) @[btb.scala 154:44] - node T_638 = dshl(UInt<1>("h01"), idxPages[16]) @[OneHot.scala 44:15] - node idxPagesOH_16 = bits(T_638, 5, 0) @[btb.scala 154:44] - node T_640 = dshl(UInt<1>("h01"), idxPages[17]) @[OneHot.scala 44:15] - node idxPagesOH_17 = bits(T_640, 5, 0) @[btb.scala 154:44] - node T_642 = dshl(UInt<1>("h01"), idxPages[18]) @[OneHot.scala 44:15] - node idxPagesOH_18 = bits(T_642, 5, 0) @[btb.scala 154:44] - node T_644 = dshl(UInt<1>("h01"), idxPages[19]) @[OneHot.scala 44:15] - node idxPagesOH_19 = bits(T_644, 5, 0) @[btb.scala 154:44] - node T_646 = dshl(UInt<1>("h01"), idxPages[20]) @[OneHot.scala 44:15] - node idxPagesOH_20 = bits(T_646, 5, 0) @[btb.scala 154:44] - node T_648 = dshl(UInt<1>("h01"), idxPages[21]) @[OneHot.scala 44:15] - node idxPagesOH_21 = bits(T_648, 5, 0) @[btb.scala 154:44] - node T_650 = dshl(UInt<1>("h01"), idxPages[22]) @[OneHot.scala 44:15] - node idxPagesOH_22 = bits(T_650, 5, 0) @[btb.scala 154:44] - node T_652 = dshl(UInt<1>("h01"), idxPages[23]) @[OneHot.scala 44:15] - node idxPagesOH_23 = bits(T_652, 5, 0) @[btb.scala 154:44] - node T_654 = dshl(UInt<1>("h01"), idxPages[24]) @[OneHot.scala 44:15] - node idxPagesOH_24 = bits(T_654, 5, 0) @[btb.scala 154:44] - node T_656 = dshl(UInt<1>("h01"), idxPages[25]) @[OneHot.scala 44:15] - node idxPagesOH_25 = bits(T_656, 5, 0) @[btb.scala 154:44] - node T_658 = dshl(UInt<1>("h01"), idxPages[26]) @[OneHot.scala 44:15] - node idxPagesOH_26 = bits(T_658, 5, 0) @[btb.scala 154:44] - node T_660 = dshl(UInt<1>("h01"), idxPages[27]) @[OneHot.scala 44:15] - node idxPagesOH_27 = bits(T_660, 5, 0) @[btb.scala 154:44] - node T_662 = dshl(UInt<1>("h01"), idxPages[28]) @[OneHot.scala 44:15] - node idxPagesOH_28 = bits(T_662, 5, 0) @[btb.scala 154:44] - node T_664 = dshl(UInt<1>("h01"), idxPages[29]) @[OneHot.scala 44:15] - node idxPagesOH_29 = bits(T_664, 5, 0) @[btb.scala 154:44] - node T_666 = dshl(UInt<1>("h01"), idxPages[30]) @[OneHot.scala 44:15] - node idxPagesOH_30 = bits(T_666, 5, 0) @[btb.scala 154:44] - node T_668 = dshl(UInt<1>("h01"), idxPages[31]) @[OneHot.scala 44:15] - node idxPagesOH_31 = bits(T_668, 5, 0) @[btb.scala 154:44] - node T_670 = dshl(UInt<1>("h01"), idxPages[32]) @[OneHot.scala 44:15] - node idxPagesOH_32 = bits(T_670, 5, 0) @[btb.scala 154:44] - node T_672 = dshl(UInt<1>("h01"), idxPages[33]) @[OneHot.scala 44:15] - node idxPagesOH_33 = bits(T_672, 5, 0) @[btb.scala 154:44] - node T_674 = dshl(UInt<1>("h01"), idxPages[34]) @[OneHot.scala 44:15] - node idxPagesOH_34 = bits(T_674, 5, 0) @[btb.scala 154:44] - node T_676 = dshl(UInt<1>("h01"), idxPages[35]) @[OneHot.scala 44:15] - node idxPagesOH_35 = bits(T_676, 5, 0) @[btb.scala 154:44] - node T_678 = dshl(UInt<1>("h01"), idxPages[36]) @[OneHot.scala 44:15] - node idxPagesOH_36 = bits(T_678, 5, 0) @[btb.scala 154:44] - node T_680 = dshl(UInt<1>("h01"), idxPages[37]) @[OneHot.scala 44:15] - node idxPagesOH_37 = bits(T_680, 5, 0) @[btb.scala 154:44] - node T_682 = dshl(UInt<1>("h01"), idxPages[38]) @[OneHot.scala 44:15] - node idxPagesOH_38 = bits(T_682, 5, 0) @[btb.scala 154:44] - node T_684 = dshl(UInt<1>("h01"), idxPages[39]) @[OneHot.scala 44:15] - node idxPagesOH_39 = bits(T_684, 5, 0) @[btb.scala 154:44] - node T_686 = dshl(UInt<1>("h01"), tgtPages[0]) @[OneHot.scala 44:15] - node tgtPagesOH_0 = bits(T_686, 5, 0) @[btb.scala 155:44] - node T_688 = dshl(UInt<1>("h01"), tgtPages[1]) @[OneHot.scala 44:15] - node tgtPagesOH_1 = bits(T_688, 5, 0) @[btb.scala 155:44] - node T_690 = dshl(UInt<1>("h01"), tgtPages[2]) @[OneHot.scala 44:15] - node tgtPagesOH_2 = bits(T_690, 5, 0) @[btb.scala 155:44] - node T_692 = dshl(UInt<1>("h01"), tgtPages[3]) @[OneHot.scala 44:15] - node tgtPagesOH_3 = bits(T_692, 5, 0) @[btb.scala 155:44] - node T_694 = dshl(UInt<1>("h01"), tgtPages[4]) @[OneHot.scala 44:15] - node tgtPagesOH_4 = bits(T_694, 5, 0) @[btb.scala 155:44] - node T_696 = dshl(UInt<1>("h01"), tgtPages[5]) @[OneHot.scala 44:15] - node tgtPagesOH_5 = bits(T_696, 5, 0) @[btb.scala 155:44] - node T_698 = dshl(UInt<1>("h01"), tgtPages[6]) @[OneHot.scala 44:15] - node tgtPagesOH_6 = bits(T_698, 5, 0) @[btb.scala 155:44] - node T_700 = dshl(UInt<1>("h01"), tgtPages[7]) @[OneHot.scala 44:15] - node tgtPagesOH_7 = bits(T_700, 5, 0) @[btb.scala 155:44] - node T_702 = dshl(UInt<1>("h01"), tgtPages[8]) @[OneHot.scala 44:15] - node tgtPagesOH_8 = bits(T_702, 5, 0) @[btb.scala 155:44] - node T_704 = dshl(UInt<1>("h01"), tgtPages[9]) @[OneHot.scala 44:15] - node tgtPagesOH_9 = bits(T_704, 5, 0) @[btb.scala 155:44] - node T_706 = dshl(UInt<1>("h01"), tgtPages[10]) @[OneHot.scala 44:15] - node tgtPagesOH_10 = bits(T_706, 5, 0) @[btb.scala 155:44] - node T_708 = dshl(UInt<1>("h01"), tgtPages[11]) @[OneHot.scala 44:15] - node tgtPagesOH_11 = bits(T_708, 5, 0) @[btb.scala 155:44] - node T_710 = dshl(UInt<1>("h01"), tgtPages[12]) @[OneHot.scala 44:15] - node tgtPagesOH_12 = bits(T_710, 5, 0) @[btb.scala 155:44] - node T_712 = dshl(UInt<1>("h01"), tgtPages[13]) @[OneHot.scala 44:15] - node tgtPagesOH_13 = bits(T_712, 5, 0) @[btb.scala 155:44] - node T_714 = dshl(UInt<1>("h01"), tgtPages[14]) @[OneHot.scala 44:15] - node tgtPagesOH_14 = bits(T_714, 5, 0) @[btb.scala 155:44] - node T_716 = dshl(UInt<1>("h01"), tgtPages[15]) @[OneHot.scala 44:15] - node tgtPagesOH_15 = bits(T_716, 5, 0) @[btb.scala 155:44] - node T_718 = dshl(UInt<1>("h01"), tgtPages[16]) @[OneHot.scala 44:15] - node tgtPagesOH_16 = bits(T_718, 5, 0) @[btb.scala 155:44] - node T_720 = dshl(UInt<1>("h01"), tgtPages[17]) @[OneHot.scala 44:15] - node tgtPagesOH_17 = bits(T_720, 5, 0) @[btb.scala 155:44] - node T_722 = dshl(UInt<1>("h01"), tgtPages[18]) @[OneHot.scala 44:15] - node tgtPagesOH_18 = bits(T_722, 5, 0) @[btb.scala 155:44] - node T_724 = dshl(UInt<1>("h01"), tgtPages[19]) @[OneHot.scala 44:15] - node tgtPagesOH_19 = bits(T_724, 5, 0) @[btb.scala 155:44] - node T_726 = dshl(UInt<1>("h01"), tgtPages[20]) @[OneHot.scala 44:15] - node tgtPagesOH_20 = bits(T_726, 5, 0) @[btb.scala 155:44] - node T_728 = dshl(UInt<1>("h01"), tgtPages[21]) @[OneHot.scala 44:15] - node tgtPagesOH_21 = bits(T_728, 5, 0) @[btb.scala 155:44] - node T_730 = dshl(UInt<1>("h01"), tgtPages[22]) @[OneHot.scala 44:15] - node tgtPagesOH_22 = bits(T_730, 5, 0) @[btb.scala 155:44] - node T_732 = dshl(UInt<1>("h01"), tgtPages[23]) @[OneHot.scala 44:15] - node tgtPagesOH_23 = bits(T_732, 5, 0) @[btb.scala 155:44] - node T_734 = dshl(UInt<1>("h01"), tgtPages[24]) @[OneHot.scala 44:15] - node tgtPagesOH_24 = bits(T_734, 5, 0) @[btb.scala 155:44] - node T_736 = dshl(UInt<1>("h01"), tgtPages[25]) @[OneHot.scala 44:15] - node tgtPagesOH_25 = bits(T_736, 5, 0) @[btb.scala 155:44] - node T_738 = dshl(UInt<1>("h01"), tgtPages[26]) @[OneHot.scala 44:15] - node tgtPagesOH_26 = bits(T_738, 5, 0) @[btb.scala 155:44] - node T_740 = dshl(UInt<1>("h01"), tgtPages[27]) @[OneHot.scala 44:15] - node tgtPagesOH_27 = bits(T_740, 5, 0) @[btb.scala 155:44] - node T_742 = dshl(UInt<1>("h01"), tgtPages[28]) @[OneHot.scala 44:15] - node tgtPagesOH_28 = bits(T_742, 5, 0) @[btb.scala 155:44] - node T_744 = dshl(UInt<1>("h01"), tgtPages[29]) @[OneHot.scala 44:15] - node tgtPagesOH_29 = bits(T_744, 5, 0) @[btb.scala 155:44] - node T_746 = dshl(UInt<1>("h01"), tgtPages[30]) @[OneHot.scala 44:15] - node tgtPagesOH_30 = bits(T_746, 5, 0) @[btb.scala 155:44] - node T_748 = dshl(UInt<1>("h01"), tgtPages[31]) @[OneHot.scala 44:15] - node tgtPagesOH_31 = bits(T_748, 5, 0) @[btb.scala 155:44] - node T_750 = dshl(UInt<1>("h01"), tgtPages[32]) @[OneHot.scala 44:15] - node tgtPagesOH_32 = bits(T_750, 5, 0) @[btb.scala 155:44] - node T_752 = dshl(UInt<1>("h01"), tgtPages[33]) @[OneHot.scala 44:15] - node tgtPagesOH_33 = bits(T_752, 5, 0) @[btb.scala 155:44] - node T_754 = dshl(UInt<1>("h01"), tgtPages[34]) @[OneHot.scala 44:15] - node tgtPagesOH_34 = bits(T_754, 5, 0) @[btb.scala 155:44] - node T_756 = dshl(UInt<1>("h01"), tgtPages[35]) @[OneHot.scala 44:15] - node tgtPagesOH_35 = bits(T_756, 5, 0) @[btb.scala 155:44] - node T_758 = dshl(UInt<1>("h01"), tgtPages[36]) @[OneHot.scala 44:15] - node tgtPagesOH_36 = bits(T_758, 5, 0) @[btb.scala 155:44] - node T_760 = dshl(UInt<1>("h01"), tgtPages[37]) @[OneHot.scala 44:15] - node tgtPagesOH_37 = bits(T_760, 5, 0) @[btb.scala 155:44] - node T_762 = dshl(UInt<1>("h01"), tgtPages[38]) @[OneHot.scala 44:15] - node tgtPagesOH_38 = bits(T_762, 5, 0) @[btb.scala 155:44] - node T_764 = dshl(UInt<1>("h01"), tgtPages[39]) @[OneHot.scala 44:15] - node tgtPagesOH_39 = bits(T_764, 5, 0) @[btb.scala 155:44] - reg isValid : UInt<40>, clk with : (reset => (reset, UInt<40>("h00"))) - reg isReturn : UInt<40>, clk - reg isJump : UInt<40>, clk - reg brIdx : UInt<1>[40], clk - reg T_777 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg idxs : UInt<11>[40], clk with : + reset => (UInt<1>("h0"), idxs) + reg idxPages : UInt<3>[40], clk with : + reset => (UInt<1>("h0"), idxPages) + reg tgts : UInt<11>[40], clk with : + reset => (UInt<1>("h0"), tgts) + reg tgtPages : UInt<3>[40], clk with : + reset => (UInt<1>("h0"), tgtPages) + reg pages : UInt<27>[6], clk with : + reset => (UInt<1>("h0"), pages) + reg pageValid : UInt<6>, clk with : + reset => (reset, UInt<6>("h0")) + node T_606 = dshl(UInt<1>("h1"), idxPages[0]) + node idxPagesOH_0 = bits(T_606, 5, 0) + node T_608 = dshl(UInt<1>("h1"), idxPages[1]) + node idxPagesOH_1 = bits(T_608, 5, 0) + node T_610 = dshl(UInt<1>("h1"), idxPages[2]) + node idxPagesOH_2 = bits(T_610, 5, 0) + node T_612 = dshl(UInt<1>("h1"), idxPages[3]) + node idxPagesOH_3 = bits(T_612, 5, 0) + node T_614 = dshl(UInt<1>("h1"), idxPages[4]) + node idxPagesOH_4 = bits(T_614, 5, 0) + node T_616 = dshl(UInt<1>("h1"), idxPages[5]) + node idxPagesOH_5 = bits(T_616, 5, 0) + node T_618 = dshl(UInt<1>("h1"), idxPages[6]) + node idxPagesOH_6 = bits(T_618, 5, 0) + node T_620 = dshl(UInt<1>("h1"), idxPages[7]) + node idxPagesOH_7 = bits(T_620, 5, 0) + node T_622 = dshl(UInt<1>("h1"), idxPages[8]) + node idxPagesOH_8 = bits(T_622, 5, 0) + node T_624 = dshl(UInt<1>("h1"), idxPages[9]) + node idxPagesOH_9 = bits(T_624, 5, 0) + node T_626 = dshl(UInt<1>("h1"), idxPages[10]) + node idxPagesOH_10 = bits(T_626, 5, 0) + node T_628 = dshl(UInt<1>("h1"), idxPages[11]) + node idxPagesOH_11 = bits(T_628, 5, 0) + node T_630 = dshl(UInt<1>("h1"), idxPages[12]) + node idxPagesOH_12 = bits(T_630, 5, 0) + node T_632 = dshl(UInt<1>("h1"), idxPages[13]) + node idxPagesOH_13 = bits(T_632, 5, 0) + node T_634 = dshl(UInt<1>("h1"), idxPages[14]) + node idxPagesOH_14 = bits(T_634, 5, 0) + node T_636 = dshl(UInt<1>("h1"), idxPages[15]) + node idxPagesOH_15 = bits(T_636, 5, 0) + node T_638 = dshl(UInt<1>("h1"), idxPages[16]) + node idxPagesOH_16 = bits(T_638, 5, 0) + node T_640 = dshl(UInt<1>("h1"), idxPages[17]) + node idxPagesOH_17 = bits(T_640, 5, 0) + node T_642 = dshl(UInt<1>("h1"), idxPages[18]) + node idxPagesOH_18 = bits(T_642, 5, 0) + node T_644 = dshl(UInt<1>("h1"), idxPages[19]) + node idxPagesOH_19 = bits(T_644, 5, 0) + node T_646 = dshl(UInt<1>("h1"), idxPages[20]) + node idxPagesOH_20 = bits(T_646, 5, 0) + node T_648 = dshl(UInt<1>("h1"), idxPages[21]) + node idxPagesOH_21 = bits(T_648, 5, 0) + node T_650 = dshl(UInt<1>("h1"), idxPages[22]) + node idxPagesOH_22 = bits(T_650, 5, 0) + node T_652 = dshl(UInt<1>("h1"), idxPages[23]) + node idxPagesOH_23 = bits(T_652, 5, 0) + node T_654 = dshl(UInt<1>("h1"), idxPages[24]) + node idxPagesOH_24 = bits(T_654, 5, 0) + node T_656 = dshl(UInt<1>("h1"), idxPages[25]) + node idxPagesOH_25 = bits(T_656, 5, 0) + node T_658 = dshl(UInt<1>("h1"), idxPages[26]) + node idxPagesOH_26 = bits(T_658, 5, 0) + node T_660 = dshl(UInt<1>("h1"), idxPages[27]) + node idxPagesOH_27 = bits(T_660, 5, 0) + node T_662 = dshl(UInt<1>("h1"), idxPages[28]) + node idxPagesOH_28 = bits(T_662, 5, 0) + node T_664 = dshl(UInt<1>("h1"), idxPages[29]) + node idxPagesOH_29 = bits(T_664, 5, 0) + node T_666 = dshl(UInt<1>("h1"), idxPages[30]) + node idxPagesOH_30 = bits(T_666, 5, 0) + node T_668 = dshl(UInt<1>("h1"), idxPages[31]) + node idxPagesOH_31 = bits(T_668, 5, 0) + node T_670 = dshl(UInt<1>("h1"), idxPages[32]) + node idxPagesOH_32 = bits(T_670, 5, 0) + node T_672 = dshl(UInt<1>("h1"), idxPages[33]) + node idxPagesOH_33 = bits(T_672, 5, 0) + node T_674 = dshl(UInt<1>("h1"), idxPages[34]) + node idxPagesOH_34 = bits(T_674, 5, 0) + node T_676 = dshl(UInt<1>("h1"), idxPages[35]) + node idxPagesOH_35 = bits(T_676, 5, 0) + node T_678 = dshl(UInt<1>("h1"), idxPages[36]) + node idxPagesOH_36 = bits(T_678, 5, 0) + node T_680 = dshl(UInt<1>("h1"), idxPages[37]) + node idxPagesOH_37 = bits(T_680, 5, 0) + node T_682 = dshl(UInt<1>("h1"), idxPages[38]) + node idxPagesOH_38 = bits(T_682, 5, 0) + node T_684 = dshl(UInt<1>("h1"), idxPages[39]) + node idxPagesOH_39 = bits(T_684, 5, 0) + node T_686 = dshl(UInt<1>("h1"), tgtPages[0]) + node tgtPagesOH_0 = bits(T_686, 5, 0) + node T_688 = dshl(UInt<1>("h1"), tgtPages[1]) + node tgtPagesOH_1 = bits(T_688, 5, 0) + node T_690 = dshl(UInt<1>("h1"), tgtPages[2]) + node tgtPagesOH_2 = bits(T_690, 5, 0) + node T_692 = dshl(UInt<1>("h1"), tgtPages[3]) + node tgtPagesOH_3 = bits(T_692, 5, 0) + node T_694 = dshl(UInt<1>("h1"), tgtPages[4]) + node tgtPagesOH_4 = bits(T_694, 5, 0) + node T_696 = dshl(UInt<1>("h1"), tgtPages[5]) + node tgtPagesOH_5 = bits(T_696, 5, 0) + node T_698 = dshl(UInt<1>("h1"), tgtPages[6]) + node tgtPagesOH_6 = bits(T_698, 5, 0) + node T_700 = dshl(UInt<1>("h1"), tgtPages[7]) + node tgtPagesOH_7 = bits(T_700, 5, 0) + node T_702 = dshl(UInt<1>("h1"), tgtPages[8]) + node tgtPagesOH_8 = bits(T_702, 5, 0) + node T_704 = dshl(UInt<1>("h1"), tgtPages[9]) + node tgtPagesOH_9 = bits(T_704, 5, 0) + node T_706 = dshl(UInt<1>("h1"), tgtPages[10]) + node tgtPagesOH_10 = bits(T_706, 5, 0) + node T_708 = dshl(UInt<1>("h1"), tgtPages[11]) + node tgtPagesOH_11 = bits(T_708, 5, 0) + node T_710 = dshl(UInt<1>("h1"), tgtPages[12]) + node tgtPagesOH_12 = bits(T_710, 5, 0) + node T_712 = dshl(UInt<1>("h1"), tgtPages[13]) + node tgtPagesOH_13 = bits(T_712, 5, 0) + node T_714 = dshl(UInt<1>("h1"), tgtPages[14]) + node tgtPagesOH_14 = bits(T_714, 5, 0) + node T_716 = dshl(UInt<1>("h1"), tgtPages[15]) + node tgtPagesOH_15 = bits(T_716, 5, 0) + node T_718 = dshl(UInt<1>("h1"), tgtPages[16]) + node tgtPagesOH_16 = bits(T_718, 5, 0) + node T_720 = dshl(UInt<1>("h1"), tgtPages[17]) + node tgtPagesOH_17 = bits(T_720, 5, 0) + node T_722 = dshl(UInt<1>("h1"), tgtPages[18]) + node tgtPagesOH_18 = bits(T_722, 5, 0) + node T_724 = dshl(UInt<1>("h1"), tgtPages[19]) + node tgtPagesOH_19 = bits(T_724, 5, 0) + node T_726 = dshl(UInt<1>("h1"), tgtPages[20]) + node tgtPagesOH_20 = bits(T_726, 5, 0) + node T_728 = dshl(UInt<1>("h1"), tgtPages[21]) + node tgtPagesOH_21 = bits(T_728, 5, 0) + node T_730 = dshl(UInt<1>("h1"), tgtPages[22]) + node tgtPagesOH_22 = bits(T_730, 5, 0) + node T_732 = dshl(UInt<1>("h1"), tgtPages[23]) + node tgtPagesOH_23 = bits(T_732, 5, 0) + node T_734 = dshl(UInt<1>("h1"), tgtPages[24]) + node tgtPagesOH_24 = bits(T_734, 5, 0) + node T_736 = dshl(UInt<1>("h1"), tgtPages[25]) + node tgtPagesOH_25 = bits(T_736, 5, 0) + node T_738 = dshl(UInt<1>("h1"), tgtPages[26]) + node tgtPagesOH_26 = bits(T_738, 5, 0) + node T_740 = dshl(UInt<1>("h1"), tgtPages[27]) + node tgtPagesOH_27 = bits(T_740, 5, 0) + node T_742 = dshl(UInt<1>("h1"), tgtPages[28]) + node tgtPagesOH_28 = bits(T_742, 5, 0) + node T_744 = dshl(UInt<1>("h1"), tgtPages[29]) + node tgtPagesOH_29 = bits(T_744, 5, 0) + node T_746 = dshl(UInt<1>("h1"), tgtPages[30]) + node tgtPagesOH_30 = bits(T_746, 5, 0) + node T_748 = dshl(UInt<1>("h1"), tgtPages[31]) + node tgtPagesOH_31 = bits(T_748, 5, 0) + node T_750 = dshl(UInt<1>("h1"), tgtPages[32]) + node tgtPagesOH_32 = bits(T_750, 5, 0) + node T_752 = dshl(UInt<1>("h1"), tgtPages[33]) + node tgtPagesOH_33 = bits(T_752, 5, 0) + node T_754 = dshl(UInt<1>("h1"), tgtPages[34]) + node tgtPagesOH_34 = bits(T_754, 5, 0) + node T_756 = dshl(UInt<1>("h1"), tgtPages[35]) + node tgtPagesOH_35 = bits(T_756, 5, 0) + node T_758 = dshl(UInt<1>("h1"), tgtPages[36]) + node tgtPagesOH_36 = bits(T_758, 5, 0) + node T_760 = dshl(UInt<1>("h1"), tgtPages[37]) + node tgtPagesOH_37 = bits(T_760, 5, 0) + node T_762 = dshl(UInt<1>("h1"), tgtPages[38]) + node tgtPagesOH_38 = bits(T_762, 5, 0) + node T_764 = dshl(UInt<1>("h1"), tgtPages[39]) + node tgtPagesOH_39 = bits(T_764, 5, 0) + reg isValid : UInt<40>, clk with : + reset => (reset, UInt<40>("h0")) + reg isReturn : UInt<40>, clk with : + reset => (UInt<1>("h0"), isReturn) + reg isJump : UInt<40>, clk with : + reset => (UInt<1>("h0"), isJump) + reg brIdx : UInt<1>[40], clk with : + reset => (UInt<1>("h0"), brIdx) + reg T_777 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_777 <= io.btb_update.valid - reg T_778 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk - when io.btb_update.valid : @[Reg.scala 29:19] - T_778 <- io.btb_update.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} @[Valid.scala 39:21] - r_btb_update is invalid @[Valid.scala 39:21] - r_btb_update.valid <= T_777 @[Valid.scala 40:17] - r_btb_update.bits <- T_778 @[Valid.scala 41:16] - node T_964 = shr(io.req.bits.addr, 12) @[btb.scala 162:39] - node T_965 = eq(pages[0], T_964) @[btb.scala 165:29] - node T_966 = eq(pages[1], T_964) @[btb.scala 165:29] - node T_967 = eq(pages[2], T_964) @[btb.scala 165:29] - node T_968 = eq(pages[3], T_964) @[btb.scala 165:29] - node T_969 = eq(pages[4], T_964) @[btb.scala 165:29] - node T_970 = eq(pages[5], T_964) @[btb.scala 165:29] - node T_971 = cat(T_967, T_966) @[Cat.scala 20:58] - node T_972 = cat(T_971, T_965) @[Cat.scala 20:58] - node T_973 = cat(T_970, T_969) @[Cat.scala 20:58] - node T_974 = cat(T_973, T_968) @[Cat.scala 20:58] - node T_975 = cat(T_974, T_972) @[Cat.scala 20:58] - node pageHit = and(pageValid, T_975) @[btb.scala 165:15] - node T_976 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_977 = eq(idxs[0], T_976) @[btb.scala 168:31] - node T_978 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_979 = eq(idxs[1], T_978) @[btb.scala 168:31] - node T_980 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_981 = eq(idxs[2], T_980) @[btb.scala 168:31] - node T_982 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_983 = eq(idxs[3], T_982) @[btb.scala 168:31] - node T_984 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_985 = eq(idxs[4], T_984) @[btb.scala 168:31] - node T_986 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_987 = eq(idxs[5], T_986) @[btb.scala 168:31] - node T_988 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_989 = eq(idxs[6], T_988) @[btb.scala 168:31] - node T_990 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_991 = eq(idxs[7], T_990) @[btb.scala 168:31] - node T_992 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_993 = eq(idxs[8], T_992) @[btb.scala 168:31] - node T_994 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_995 = eq(idxs[9], T_994) @[btb.scala 168:31] - node T_996 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_997 = eq(idxs[10], T_996) @[btb.scala 168:31] - node T_998 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_999 = eq(idxs[11], T_998) @[btb.scala 168:31] - node T_1000 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1001 = eq(idxs[12], T_1000) @[btb.scala 168:31] - node T_1002 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1003 = eq(idxs[13], T_1002) @[btb.scala 168:31] - node T_1004 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1005 = eq(idxs[14], T_1004) @[btb.scala 168:31] - node T_1006 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1007 = eq(idxs[15], T_1006) @[btb.scala 168:31] - node T_1008 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1009 = eq(idxs[16], T_1008) @[btb.scala 168:31] - node T_1010 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1011 = eq(idxs[17], T_1010) @[btb.scala 168:31] - node T_1012 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1013 = eq(idxs[18], T_1012) @[btb.scala 168:31] - node T_1014 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1015 = eq(idxs[19], T_1014) @[btb.scala 168:31] - node T_1016 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1017 = eq(idxs[20], T_1016) @[btb.scala 168:31] - node T_1018 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1019 = eq(idxs[21], T_1018) @[btb.scala 168:31] - node T_1020 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1021 = eq(idxs[22], T_1020) @[btb.scala 168:31] - node T_1022 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1023 = eq(idxs[23], T_1022) @[btb.scala 168:31] - node T_1024 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1025 = eq(idxs[24], T_1024) @[btb.scala 168:31] - node T_1026 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1027 = eq(idxs[25], T_1026) @[btb.scala 168:31] - node T_1028 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1029 = eq(idxs[26], T_1028) @[btb.scala 168:31] - node T_1030 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1031 = eq(idxs[27], T_1030) @[btb.scala 168:31] - node T_1032 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1033 = eq(idxs[28], T_1032) @[btb.scala 168:31] - node T_1034 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1035 = eq(idxs[29], T_1034) @[btb.scala 168:31] - node T_1036 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1037 = eq(idxs[30], T_1036) @[btb.scala 168:31] - node T_1038 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1039 = eq(idxs[31], T_1038) @[btb.scala 168:31] - node T_1040 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1041 = eq(idxs[32], T_1040) @[btb.scala 168:31] - node T_1042 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1043 = eq(idxs[33], T_1042) @[btb.scala 168:31] - node T_1044 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1045 = eq(idxs[34], T_1044) @[btb.scala 168:31] - node T_1046 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1047 = eq(idxs[35], T_1046) @[btb.scala 168:31] - node T_1048 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1049 = eq(idxs[36], T_1048) @[btb.scala 168:31] - node T_1050 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1051 = eq(idxs[37], T_1050) @[btb.scala 168:31] - node T_1052 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1053 = eq(idxs[38], T_1052) @[btb.scala 168:31] - node T_1054 = bits(io.req.bits.addr, 11, 1) @[btb.scala 168:39] - node T_1055 = eq(idxs[39], T_1054) @[btb.scala 168:31] - node T_1056 = cat(T_979, T_977) @[Cat.scala 20:58] - node T_1057 = cat(T_985, T_983) @[Cat.scala 20:58] - node T_1058 = cat(T_1057, T_981) @[Cat.scala 20:58] - node T_1059 = cat(T_1058, T_1056) @[Cat.scala 20:58] - node T_1060 = cat(T_989, T_987) @[Cat.scala 20:58] - node T_1061 = cat(T_995, T_993) @[Cat.scala 20:58] - node T_1062 = cat(T_1061, T_991) @[Cat.scala 20:58] - node T_1063 = cat(T_1062, T_1060) @[Cat.scala 20:58] - node T_1064 = cat(T_1063, T_1059) @[Cat.scala 20:58] - node T_1065 = cat(T_999, T_997) @[Cat.scala 20:58] - node T_1066 = cat(T_1005, T_1003) @[Cat.scala 20:58] - node T_1067 = cat(T_1066, T_1001) @[Cat.scala 20:58] - node T_1068 = cat(T_1067, T_1065) @[Cat.scala 20:58] - node T_1069 = cat(T_1009, T_1007) @[Cat.scala 20:58] - node T_1070 = cat(T_1015, T_1013) @[Cat.scala 20:58] - node T_1071 = cat(T_1070, T_1011) @[Cat.scala 20:58] - node T_1072 = cat(T_1071, T_1069) @[Cat.scala 20:58] - node T_1073 = cat(T_1072, T_1068) @[Cat.scala 20:58] - node T_1074 = cat(T_1073, T_1064) @[Cat.scala 20:58] - node T_1075 = cat(T_1019, T_1017) @[Cat.scala 20:58] - node T_1076 = cat(T_1025, T_1023) @[Cat.scala 20:58] - node T_1077 = cat(T_1076, T_1021) @[Cat.scala 20:58] - node T_1078 = cat(T_1077, T_1075) @[Cat.scala 20:58] - node T_1079 = cat(T_1029, T_1027) @[Cat.scala 20:58] - node T_1080 = cat(T_1035, T_1033) @[Cat.scala 20:58] - node T_1081 = cat(T_1080, T_1031) @[Cat.scala 20:58] - node T_1082 = cat(T_1081, T_1079) @[Cat.scala 20:58] - node T_1083 = cat(T_1082, T_1078) @[Cat.scala 20:58] - node T_1084 = cat(T_1039, T_1037) @[Cat.scala 20:58] - node T_1085 = cat(T_1045, T_1043) @[Cat.scala 20:58] - node T_1086 = cat(T_1085, T_1041) @[Cat.scala 20:58] - node T_1087 = cat(T_1086, T_1084) @[Cat.scala 20:58] - node T_1088 = cat(T_1049, T_1047) @[Cat.scala 20:58] - node T_1089 = cat(T_1055, T_1053) @[Cat.scala 20:58] - node T_1090 = cat(T_1089, T_1051) @[Cat.scala 20:58] - node T_1091 = cat(T_1090, T_1088) @[Cat.scala 20:58] - node T_1092 = cat(T_1091, T_1087) @[Cat.scala 20:58] - node T_1093 = cat(T_1092, T_1083) @[Cat.scala 20:58] - node T_1094 = cat(T_1093, T_1074) @[Cat.scala 20:58] - node T_1095 = and(idxPagesOH_0, pageHit) @[btb.scala 169:41] - node T_1096 = and(idxPagesOH_1, pageHit) @[btb.scala 169:41] - node T_1097 = and(idxPagesOH_2, pageHit) @[btb.scala 169:41] - node T_1098 = and(idxPagesOH_3, pageHit) @[btb.scala 169:41] - node T_1099 = and(idxPagesOH_4, pageHit) @[btb.scala 169:41] - node T_1100 = and(idxPagesOH_5, pageHit) @[btb.scala 169:41] - node T_1101 = and(idxPagesOH_6, pageHit) @[btb.scala 169:41] - node T_1102 = and(idxPagesOH_7, pageHit) @[btb.scala 169:41] - node T_1103 = and(idxPagesOH_8, pageHit) @[btb.scala 169:41] - node T_1104 = and(idxPagesOH_9, pageHit) @[btb.scala 169:41] - node T_1105 = and(idxPagesOH_10, pageHit) @[btb.scala 169:41] - node T_1106 = and(idxPagesOH_11, pageHit) @[btb.scala 169:41] - node T_1107 = and(idxPagesOH_12, pageHit) @[btb.scala 169:41] - node T_1108 = and(idxPagesOH_13, pageHit) @[btb.scala 169:41] - node T_1109 = and(idxPagesOH_14, pageHit) @[btb.scala 169:41] - node T_1110 = and(idxPagesOH_15, pageHit) @[btb.scala 169:41] - node T_1111 = and(idxPagesOH_16, pageHit) @[btb.scala 169:41] - node T_1112 = and(idxPagesOH_17, pageHit) @[btb.scala 169:41] - node T_1113 = and(idxPagesOH_18, pageHit) @[btb.scala 169:41] - node T_1114 = and(idxPagesOH_19, pageHit) @[btb.scala 169:41] - node T_1115 = and(idxPagesOH_20, pageHit) @[btb.scala 169:41] - node T_1116 = and(idxPagesOH_21, pageHit) @[btb.scala 169:41] - node T_1117 = and(idxPagesOH_22, pageHit) @[btb.scala 169:41] - node T_1118 = and(idxPagesOH_23, pageHit) @[btb.scala 169:41] - node T_1119 = and(idxPagesOH_24, pageHit) @[btb.scala 169:41] - node T_1120 = and(idxPagesOH_25, pageHit) @[btb.scala 169:41] - node T_1121 = and(idxPagesOH_26, pageHit) @[btb.scala 169:41] - node T_1122 = and(idxPagesOH_27, pageHit) @[btb.scala 169:41] - node T_1123 = and(idxPagesOH_28, pageHit) @[btb.scala 169:41] - node T_1124 = and(idxPagesOH_29, pageHit) @[btb.scala 169:41] - node T_1125 = and(idxPagesOH_30, pageHit) @[btb.scala 169:41] - node T_1126 = and(idxPagesOH_31, pageHit) @[btb.scala 169:41] - node T_1127 = and(idxPagesOH_32, pageHit) @[btb.scala 169:41] - node T_1128 = and(idxPagesOH_33, pageHit) @[btb.scala 169:41] - node T_1129 = and(idxPagesOH_34, pageHit) @[btb.scala 169:41] - node T_1130 = and(idxPagesOH_35, pageHit) @[btb.scala 169:41] - node T_1131 = and(idxPagesOH_36, pageHit) @[btb.scala 169:41] - node T_1132 = and(idxPagesOH_37, pageHit) @[btb.scala 169:41] - node T_1133 = and(idxPagesOH_38, pageHit) @[btb.scala 169:41] - node T_1134 = and(idxPagesOH_39, pageHit) @[btb.scala 169:41] - node T_1136 = neq(T_1095, UInt<1>("h00")) @[btb.scala 169:58] - node T_1138 = neq(T_1096, UInt<1>("h00")) @[btb.scala 169:58] - node T_1140 = neq(T_1097, UInt<1>("h00")) @[btb.scala 169:58] - node T_1142 = neq(T_1098, UInt<1>("h00")) @[btb.scala 169:58] - node T_1144 = neq(T_1099, UInt<1>("h00")) @[btb.scala 169:58] - node T_1146 = neq(T_1100, UInt<1>("h00")) @[btb.scala 169:58] - node T_1148 = neq(T_1101, UInt<1>("h00")) @[btb.scala 169:58] - node T_1150 = neq(T_1102, UInt<1>("h00")) @[btb.scala 169:58] - node T_1152 = neq(T_1103, UInt<1>("h00")) @[btb.scala 169:58] - node T_1154 = neq(T_1104, UInt<1>("h00")) @[btb.scala 169:58] - node T_1156 = neq(T_1105, UInt<1>("h00")) @[btb.scala 169:58] - node T_1158 = neq(T_1106, UInt<1>("h00")) @[btb.scala 169:58] - node T_1160 = neq(T_1107, UInt<1>("h00")) @[btb.scala 169:58] - node T_1162 = neq(T_1108, UInt<1>("h00")) @[btb.scala 169:58] - node T_1164 = neq(T_1109, UInt<1>("h00")) @[btb.scala 169:58] - node T_1166 = neq(T_1110, UInt<1>("h00")) @[btb.scala 169:58] - node T_1168 = neq(T_1111, UInt<1>("h00")) @[btb.scala 169:58] - node T_1170 = neq(T_1112, UInt<1>("h00")) @[btb.scala 169:58] - node T_1172 = neq(T_1113, UInt<1>("h00")) @[btb.scala 169:58] - node T_1174 = neq(T_1114, UInt<1>("h00")) @[btb.scala 169:58] - node T_1176 = neq(T_1115, UInt<1>("h00")) @[btb.scala 169:58] - node T_1178 = neq(T_1116, UInt<1>("h00")) @[btb.scala 169:58] - node T_1180 = neq(T_1117, UInt<1>("h00")) @[btb.scala 169:58] - node T_1182 = neq(T_1118, UInt<1>("h00")) @[btb.scala 169:58] - node T_1184 = neq(T_1119, UInt<1>("h00")) @[btb.scala 169:58] - node T_1186 = neq(T_1120, UInt<1>("h00")) @[btb.scala 169:58] - node T_1188 = neq(T_1121, UInt<1>("h00")) @[btb.scala 169:58] - node T_1190 = neq(T_1122, UInt<1>("h00")) @[btb.scala 169:58] - node T_1192 = neq(T_1123, UInt<1>("h00")) @[btb.scala 169:58] - node T_1194 = neq(T_1124, UInt<1>("h00")) @[btb.scala 169:58] - node T_1196 = neq(T_1125, UInt<1>("h00")) @[btb.scala 169:58] - node T_1198 = neq(T_1126, UInt<1>("h00")) @[btb.scala 169:58] - node T_1200 = neq(T_1127, UInt<1>("h00")) @[btb.scala 169:58] - node T_1202 = neq(T_1128, UInt<1>("h00")) @[btb.scala 169:58] - node T_1204 = neq(T_1129, UInt<1>("h00")) @[btb.scala 169:58] - node T_1206 = neq(T_1130, UInt<1>("h00")) @[btb.scala 169:58] - node T_1208 = neq(T_1131, UInt<1>("h00")) @[btb.scala 169:58] - node T_1210 = neq(T_1132, UInt<1>("h00")) @[btb.scala 169:58] - node T_1212 = neq(T_1133, UInt<1>("h00")) @[btb.scala 169:58] - node T_1214 = neq(T_1134, UInt<1>("h00")) @[btb.scala 169:58] - node T_1215 = cat(T_1138, T_1136) @[Cat.scala 20:58] - node T_1216 = cat(T_1144, T_1142) @[Cat.scala 20:58] - node T_1217 = cat(T_1216, T_1140) @[Cat.scala 20:58] - node T_1218 = cat(T_1217, T_1215) @[Cat.scala 20:58] - node T_1219 = cat(T_1148, T_1146) @[Cat.scala 20:58] - node T_1220 = cat(T_1154, T_1152) @[Cat.scala 20:58] - node T_1221 = cat(T_1220, T_1150) @[Cat.scala 20:58] - node T_1222 = cat(T_1221, T_1219) @[Cat.scala 20:58] - node T_1223 = cat(T_1222, T_1218) @[Cat.scala 20:58] - node T_1224 = cat(T_1158, T_1156) @[Cat.scala 20:58] - node T_1225 = cat(T_1164, T_1162) @[Cat.scala 20:58] - node T_1226 = cat(T_1225, T_1160) @[Cat.scala 20:58] - node T_1227 = cat(T_1226, T_1224) @[Cat.scala 20:58] - node T_1228 = cat(T_1168, T_1166) @[Cat.scala 20:58] - node T_1229 = cat(T_1174, T_1172) @[Cat.scala 20:58] - node T_1230 = cat(T_1229, T_1170) @[Cat.scala 20:58] - node T_1231 = cat(T_1230, T_1228) @[Cat.scala 20:58] - node T_1232 = cat(T_1231, T_1227) @[Cat.scala 20:58] - node T_1233 = cat(T_1232, T_1223) @[Cat.scala 20:58] - node T_1234 = cat(T_1178, T_1176) @[Cat.scala 20:58] - node T_1235 = cat(T_1184, T_1182) @[Cat.scala 20:58] - node T_1236 = cat(T_1235, T_1180) @[Cat.scala 20:58] - node T_1237 = cat(T_1236, T_1234) @[Cat.scala 20:58] - node T_1238 = cat(T_1188, T_1186) @[Cat.scala 20:58] - node T_1239 = cat(T_1194, T_1192) @[Cat.scala 20:58] - node T_1240 = cat(T_1239, T_1190) @[Cat.scala 20:58] - node T_1241 = cat(T_1240, T_1238) @[Cat.scala 20:58] - node T_1242 = cat(T_1241, T_1237) @[Cat.scala 20:58] - node T_1243 = cat(T_1198, T_1196) @[Cat.scala 20:58] - node T_1244 = cat(T_1204, T_1202) @[Cat.scala 20:58] - node T_1245 = cat(T_1244, T_1200) @[Cat.scala 20:58] - node T_1246 = cat(T_1245, T_1243) @[Cat.scala 20:58] - node T_1247 = cat(T_1208, T_1206) @[Cat.scala 20:58] - node T_1248 = cat(T_1214, T_1212) @[Cat.scala 20:58] - node T_1249 = cat(T_1248, T_1210) @[Cat.scala 20:58] - node T_1250 = cat(T_1249, T_1247) @[Cat.scala 20:58] - node T_1251 = cat(T_1250, T_1246) @[Cat.scala 20:58] - node T_1252 = cat(T_1251, T_1242) @[Cat.scala 20:58] - node T_1253 = cat(T_1252, T_1233) @[Cat.scala 20:58] - node T_1254 = and(T_1094, T_1253) @[btb.scala 170:14] - node hitsVec = and(T_1254, isValid) @[btb.scala 170:29] - node T_1255 = shr(r_btb_update.bits.pc, 12) @[btb.scala 162:39] - node T_1256 = eq(pages[0], T_1255) @[btb.scala 165:29] - node T_1257 = eq(pages[1], T_1255) @[btb.scala 165:29] - node T_1258 = eq(pages[2], T_1255) @[btb.scala 165:29] - node T_1259 = eq(pages[3], T_1255) @[btb.scala 165:29] - node T_1260 = eq(pages[4], T_1255) @[btb.scala 165:29] - node T_1261 = eq(pages[5], T_1255) @[btb.scala 165:29] - node T_1262 = cat(T_1258, T_1257) @[Cat.scala 20:58] - node T_1263 = cat(T_1262, T_1256) @[Cat.scala 20:58] - node T_1264 = cat(T_1261, T_1260) @[Cat.scala 20:58] - node T_1265 = cat(T_1264, T_1259) @[Cat.scala 20:58] - node T_1266 = cat(T_1265, T_1263) @[Cat.scala 20:58] - node updatePageHit = and(pageValid, T_1266) @[btb.scala 165:15] - node T_1267 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1268 = eq(idxs[0], T_1267) @[btb.scala 168:31] - node T_1269 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1270 = eq(idxs[1], T_1269) @[btb.scala 168:31] - node T_1271 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1272 = eq(idxs[2], T_1271) @[btb.scala 168:31] - node T_1273 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1274 = eq(idxs[3], T_1273) @[btb.scala 168:31] - node T_1275 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1276 = eq(idxs[4], T_1275) @[btb.scala 168:31] - node T_1277 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1278 = eq(idxs[5], T_1277) @[btb.scala 168:31] - node T_1279 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1280 = eq(idxs[6], T_1279) @[btb.scala 168:31] - node T_1281 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1282 = eq(idxs[7], T_1281) @[btb.scala 168:31] - node T_1283 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1284 = eq(idxs[8], T_1283) @[btb.scala 168:31] - node T_1285 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1286 = eq(idxs[9], T_1285) @[btb.scala 168:31] - node T_1287 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1288 = eq(idxs[10], T_1287) @[btb.scala 168:31] - node T_1289 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1290 = eq(idxs[11], T_1289) @[btb.scala 168:31] - node T_1291 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1292 = eq(idxs[12], T_1291) @[btb.scala 168:31] - node T_1293 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1294 = eq(idxs[13], T_1293) @[btb.scala 168:31] - node T_1295 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1296 = eq(idxs[14], T_1295) @[btb.scala 168:31] - node T_1297 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1298 = eq(idxs[15], T_1297) @[btb.scala 168:31] - node T_1299 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1300 = eq(idxs[16], T_1299) @[btb.scala 168:31] - node T_1301 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1302 = eq(idxs[17], T_1301) @[btb.scala 168:31] - node T_1303 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1304 = eq(idxs[18], T_1303) @[btb.scala 168:31] - node T_1305 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1306 = eq(idxs[19], T_1305) @[btb.scala 168:31] - node T_1307 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1308 = eq(idxs[20], T_1307) @[btb.scala 168:31] - node T_1309 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1310 = eq(idxs[21], T_1309) @[btb.scala 168:31] - node T_1311 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1312 = eq(idxs[22], T_1311) @[btb.scala 168:31] - node T_1313 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1314 = eq(idxs[23], T_1313) @[btb.scala 168:31] - node T_1315 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1316 = eq(idxs[24], T_1315) @[btb.scala 168:31] - node T_1317 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1318 = eq(idxs[25], T_1317) @[btb.scala 168:31] - node T_1319 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1320 = eq(idxs[26], T_1319) @[btb.scala 168:31] - node T_1321 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1322 = eq(idxs[27], T_1321) @[btb.scala 168:31] - node T_1323 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1324 = eq(idxs[28], T_1323) @[btb.scala 168:31] - node T_1325 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1326 = eq(idxs[29], T_1325) @[btb.scala 168:31] - node T_1327 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1328 = eq(idxs[30], T_1327) @[btb.scala 168:31] - node T_1329 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1330 = eq(idxs[31], T_1329) @[btb.scala 168:31] - node T_1331 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1332 = eq(idxs[32], T_1331) @[btb.scala 168:31] - node T_1333 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1334 = eq(idxs[33], T_1333) @[btb.scala 168:31] - node T_1335 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1336 = eq(idxs[34], T_1335) @[btb.scala 168:31] - node T_1337 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1338 = eq(idxs[35], T_1337) @[btb.scala 168:31] - node T_1339 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1340 = eq(idxs[36], T_1339) @[btb.scala 168:31] - node T_1341 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1342 = eq(idxs[37], T_1341) @[btb.scala 168:31] - node T_1343 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1344 = eq(idxs[38], T_1343) @[btb.scala 168:31] - node T_1345 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 168:39] - node T_1346 = eq(idxs[39], T_1345) @[btb.scala 168:31] - node T_1347 = cat(T_1270, T_1268) @[Cat.scala 20:58] - node T_1348 = cat(T_1276, T_1274) @[Cat.scala 20:58] - node T_1349 = cat(T_1348, T_1272) @[Cat.scala 20:58] - node T_1350 = cat(T_1349, T_1347) @[Cat.scala 20:58] - node T_1351 = cat(T_1280, T_1278) @[Cat.scala 20:58] - node T_1352 = cat(T_1286, T_1284) @[Cat.scala 20:58] - node T_1353 = cat(T_1352, T_1282) @[Cat.scala 20:58] - node T_1354 = cat(T_1353, T_1351) @[Cat.scala 20:58] - node T_1355 = cat(T_1354, T_1350) @[Cat.scala 20:58] - node T_1356 = cat(T_1290, T_1288) @[Cat.scala 20:58] - node T_1357 = cat(T_1296, T_1294) @[Cat.scala 20:58] - node T_1358 = cat(T_1357, T_1292) @[Cat.scala 20:58] - node T_1359 = cat(T_1358, T_1356) @[Cat.scala 20:58] - node T_1360 = cat(T_1300, T_1298) @[Cat.scala 20:58] - node T_1361 = cat(T_1306, T_1304) @[Cat.scala 20:58] - node T_1362 = cat(T_1361, T_1302) @[Cat.scala 20:58] - node T_1363 = cat(T_1362, T_1360) @[Cat.scala 20:58] - node T_1364 = cat(T_1363, T_1359) @[Cat.scala 20:58] - node T_1365 = cat(T_1364, T_1355) @[Cat.scala 20:58] - node T_1366 = cat(T_1310, T_1308) @[Cat.scala 20:58] - node T_1367 = cat(T_1316, T_1314) @[Cat.scala 20:58] - node T_1368 = cat(T_1367, T_1312) @[Cat.scala 20:58] - node T_1369 = cat(T_1368, T_1366) @[Cat.scala 20:58] - node T_1370 = cat(T_1320, T_1318) @[Cat.scala 20:58] - node T_1371 = cat(T_1326, T_1324) @[Cat.scala 20:58] - node T_1372 = cat(T_1371, T_1322) @[Cat.scala 20:58] - node T_1373 = cat(T_1372, T_1370) @[Cat.scala 20:58] - node T_1374 = cat(T_1373, T_1369) @[Cat.scala 20:58] - node T_1375 = cat(T_1330, T_1328) @[Cat.scala 20:58] - node T_1376 = cat(T_1336, T_1334) @[Cat.scala 20:58] - node T_1377 = cat(T_1376, T_1332) @[Cat.scala 20:58] - node T_1378 = cat(T_1377, T_1375) @[Cat.scala 20:58] - node T_1379 = cat(T_1340, T_1338) @[Cat.scala 20:58] - node T_1380 = cat(T_1346, T_1344) @[Cat.scala 20:58] - node T_1381 = cat(T_1380, T_1342) @[Cat.scala 20:58] - node T_1382 = cat(T_1381, T_1379) @[Cat.scala 20:58] - node T_1383 = cat(T_1382, T_1378) @[Cat.scala 20:58] - node T_1384 = cat(T_1383, T_1374) @[Cat.scala 20:58] - node T_1385 = cat(T_1384, T_1365) @[Cat.scala 20:58] - node T_1386 = and(idxPagesOH_0, updatePageHit) @[btb.scala 169:41] - node T_1387 = and(idxPagesOH_1, updatePageHit) @[btb.scala 169:41] - node T_1388 = and(idxPagesOH_2, updatePageHit) @[btb.scala 169:41] - node T_1389 = and(idxPagesOH_3, updatePageHit) @[btb.scala 169:41] - node T_1390 = and(idxPagesOH_4, updatePageHit) @[btb.scala 169:41] - node T_1391 = and(idxPagesOH_5, updatePageHit) @[btb.scala 169:41] - node T_1392 = and(idxPagesOH_6, updatePageHit) @[btb.scala 169:41] - node T_1393 = and(idxPagesOH_7, updatePageHit) @[btb.scala 169:41] - node T_1394 = and(idxPagesOH_8, updatePageHit) @[btb.scala 169:41] - node T_1395 = and(idxPagesOH_9, updatePageHit) @[btb.scala 169:41] - node T_1396 = and(idxPagesOH_10, updatePageHit) @[btb.scala 169:41] - node T_1397 = and(idxPagesOH_11, updatePageHit) @[btb.scala 169:41] - node T_1398 = and(idxPagesOH_12, updatePageHit) @[btb.scala 169:41] - node T_1399 = and(idxPagesOH_13, updatePageHit) @[btb.scala 169:41] - node T_1400 = and(idxPagesOH_14, updatePageHit) @[btb.scala 169:41] - node T_1401 = and(idxPagesOH_15, updatePageHit) @[btb.scala 169:41] - node T_1402 = and(idxPagesOH_16, updatePageHit) @[btb.scala 169:41] - node T_1403 = and(idxPagesOH_17, updatePageHit) @[btb.scala 169:41] - node T_1404 = and(idxPagesOH_18, updatePageHit) @[btb.scala 169:41] - node T_1405 = and(idxPagesOH_19, updatePageHit) @[btb.scala 169:41] - node T_1406 = and(idxPagesOH_20, updatePageHit) @[btb.scala 169:41] - node T_1407 = and(idxPagesOH_21, updatePageHit) @[btb.scala 169:41] - node T_1408 = and(idxPagesOH_22, updatePageHit) @[btb.scala 169:41] - node T_1409 = and(idxPagesOH_23, updatePageHit) @[btb.scala 169:41] - node T_1410 = and(idxPagesOH_24, updatePageHit) @[btb.scala 169:41] - node T_1411 = and(idxPagesOH_25, updatePageHit) @[btb.scala 169:41] - node T_1412 = and(idxPagesOH_26, updatePageHit) @[btb.scala 169:41] - node T_1413 = and(idxPagesOH_27, updatePageHit) @[btb.scala 169:41] - node T_1414 = and(idxPagesOH_28, updatePageHit) @[btb.scala 169:41] - node T_1415 = and(idxPagesOH_29, updatePageHit) @[btb.scala 169:41] - node T_1416 = and(idxPagesOH_30, updatePageHit) @[btb.scala 169:41] - node T_1417 = and(idxPagesOH_31, updatePageHit) @[btb.scala 169:41] - node T_1418 = and(idxPagesOH_32, updatePageHit) @[btb.scala 169:41] - node T_1419 = and(idxPagesOH_33, updatePageHit) @[btb.scala 169:41] - node T_1420 = and(idxPagesOH_34, updatePageHit) @[btb.scala 169:41] - node T_1421 = and(idxPagesOH_35, updatePageHit) @[btb.scala 169:41] - node T_1422 = and(idxPagesOH_36, updatePageHit) @[btb.scala 169:41] - node T_1423 = and(idxPagesOH_37, updatePageHit) @[btb.scala 169:41] - node T_1424 = and(idxPagesOH_38, updatePageHit) @[btb.scala 169:41] - node T_1425 = and(idxPagesOH_39, updatePageHit) @[btb.scala 169:41] - node T_1427 = neq(T_1386, UInt<1>("h00")) @[btb.scala 169:58] - node T_1429 = neq(T_1387, UInt<1>("h00")) @[btb.scala 169:58] - node T_1431 = neq(T_1388, UInt<1>("h00")) @[btb.scala 169:58] - node T_1433 = neq(T_1389, UInt<1>("h00")) @[btb.scala 169:58] - node T_1435 = neq(T_1390, UInt<1>("h00")) @[btb.scala 169:58] - node T_1437 = neq(T_1391, UInt<1>("h00")) @[btb.scala 169:58] - node T_1439 = neq(T_1392, UInt<1>("h00")) @[btb.scala 169:58] - node T_1441 = neq(T_1393, UInt<1>("h00")) @[btb.scala 169:58] - node T_1443 = neq(T_1394, UInt<1>("h00")) @[btb.scala 169:58] - node T_1445 = neq(T_1395, UInt<1>("h00")) @[btb.scala 169:58] - node T_1447 = neq(T_1396, UInt<1>("h00")) @[btb.scala 169:58] - node T_1449 = neq(T_1397, UInt<1>("h00")) @[btb.scala 169:58] - node T_1451 = neq(T_1398, UInt<1>("h00")) @[btb.scala 169:58] - node T_1453 = neq(T_1399, UInt<1>("h00")) @[btb.scala 169:58] - node T_1455 = neq(T_1400, UInt<1>("h00")) @[btb.scala 169:58] - node T_1457 = neq(T_1401, UInt<1>("h00")) @[btb.scala 169:58] - node T_1459 = neq(T_1402, UInt<1>("h00")) @[btb.scala 169:58] - node T_1461 = neq(T_1403, UInt<1>("h00")) @[btb.scala 169:58] - node T_1463 = neq(T_1404, UInt<1>("h00")) @[btb.scala 169:58] - node T_1465 = neq(T_1405, UInt<1>("h00")) @[btb.scala 169:58] - node T_1467 = neq(T_1406, UInt<1>("h00")) @[btb.scala 169:58] - node T_1469 = neq(T_1407, UInt<1>("h00")) @[btb.scala 169:58] - node T_1471 = neq(T_1408, UInt<1>("h00")) @[btb.scala 169:58] - node T_1473 = neq(T_1409, UInt<1>("h00")) @[btb.scala 169:58] - node T_1475 = neq(T_1410, UInt<1>("h00")) @[btb.scala 169:58] - node T_1477 = neq(T_1411, UInt<1>("h00")) @[btb.scala 169:58] - node T_1479 = neq(T_1412, UInt<1>("h00")) @[btb.scala 169:58] - node T_1481 = neq(T_1413, UInt<1>("h00")) @[btb.scala 169:58] - node T_1483 = neq(T_1414, UInt<1>("h00")) @[btb.scala 169:58] - node T_1485 = neq(T_1415, UInt<1>("h00")) @[btb.scala 169:58] - node T_1487 = neq(T_1416, UInt<1>("h00")) @[btb.scala 169:58] - node T_1489 = neq(T_1417, UInt<1>("h00")) @[btb.scala 169:58] - node T_1491 = neq(T_1418, UInt<1>("h00")) @[btb.scala 169:58] - node T_1493 = neq(T_1419, UInt<1>("h00")) @[btb.scala 169:58] - node T_1495 = neq(T_1420, UInt<1>("h00")) @[btb.scala 169:58] - node T_1497 = neq(T_1421, UInt<1>("h00")) @[btb.scala 169:58] - node T_1499 = neq(T_1422, UInt<1>("h00")) @[btb.scala 169:58] - node T_1501 = neq(T_1423, UInt<1>("h00")) @[btb.scala 169:58] - node T_1503 = neq(T_1424, UInt<1>("h00")) @[btb.scala 169:58] - node T_1505 = neq(T_1425, UInt<1>("h00")) @[btb.scala 169:58] - node T_1506 = cat(T_1429, T_1427) @[Cat.scala 20:58] - node T_1507 = cat(T_1435, T_1433) @[Cat.scala 20:58] - node T_1508 = cat(T_1507, T_1431) @[Cat.scala 20:58] - node T_1509 = cat(T_1508, T_1506) @[Cat.scala 20:58] - node T_1510 = cat(T_1439, T_1437) @[Cat.scala 20:58] - node T_1511 = cat(T_1445, T_1443) @[Cat.scala 20:58] - node T_1512 = cat(T_1511, T_1441) @[Cat.scala 20:58] - node T_1513 = cat(T_1512, T_1510) @[Cat.scala 20:58] - node T_1514 = cat(T_1513, T_1509) @[Cat.scala 20:58] - node T_1515 = cat(T_1449, T_1447) @[Cat.scala 20:58] - node T_1516 = cat(T_1455, T_1453) @[Cat.scala 20:58] - node T_1517 = cat(T_1516, T_1451) @[Cat.scala 20:58] - node T_1518 = cat(T_1517, T_1515) @[Cat.scala 20:58] - node T_1519 = cat(T_1459, T_1457) @[Cat.scala 20:58] - node T_1520 = cat(T_1465, T_1463) @[Cat.scala 20:58] - node T_1521 = cat(T_1520, T_1461) @[Cat.scala 20:58] - node T_1522 = cat(T_1521, T_1519) @[Cat.scala 20:58] - node T_1523 = cat(T_1522, T_1518) @[Cat.scala 20:58] - node T_1524 = cat(T_1523, T_1514) @[Cat.scala 20:58] - node T_1525 = cat(T_1469, T_1467) @[Cat.scala 20:58] - node T_1526 = cat(T_1475, T_1473) @[Cat.scala 20:58] - node T_1527 = cat(T_1526, T_1471) @[Cat.scala 20:58] - node T_1528 = cat(T_1527, T_1525) @[Cat.scala 20:58] - node T_1529 = cat(T_1479, T_1477) @[Cat.scala 20:58] - node T_1530 = cat(T_1485, T_1483) @[Cat.scala 20:58] - node T_1531 = cat(T_1530, T_1481) @[Cat.scala 20:58] - node T_1532 = cat(T_1531, T_1529) @[Cat.scala 20:58] - node T_1533 = cat(T_1532, T_1528) @[Cat.scala 20:58] - node T_1534 = cat(T_1489, T_1487) @[Cat.scala 20:58] - node T_1535 = cat(T_1495, T_1493) @[Cat.scala 20:58] - node T_1536 = cat(T_1535, T_1491) @[Cat.scala 20:58] - node T_1537 = cat(T_1536, T_1534) @[Cat.scala 20:58] - node T_1538 = cat(T_1499, T_1497) @[Cat.scala 20:58] - node T_1539 = cat(T_1505, T_1503) @[Cat.scala 20:58] - node T_1540 = cat(T_1539, T_1501) @[Cat.scala 20:58] - node T_1541 = cat(T_1540, T_1538) @[Cat.scala 20:58] - node T_1542 = cat(T_1541, T_1537) @[Cat.scala 20:58] - node T_1543 = cat(T_1542, T_1533) @[Cat.scala 20:58] - node T_1544 = cat(T_1543, T_1524) @[Cat.scala 20:58] - node T_1545 = and(T_1385, T_1544) @[btb.scala 170:14] - node updateHits = and(T_1545, isValid) @[btb.scala 170:29] - node T_1547 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) @[btb.scala 188:37] - node T_1548 = and(r_btb_update.valid, T_1547) @[btb.scala 188:34] - reg nextRepl : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) - when T_1548 : @[Counter.scala 43:17] - node T_1551 = eq(nextRepl, UInt<6>("h027")) @[Counter.scala 20:24] - node T_1553 = add(nextRepl, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1554 = tail(T_1553, 1) @[Counter.scala 21:22] - nextRepl <= T_1554 @[Counter.scala 21:13] - when T_1551 : @[Counter.scala 23:21] - nextRepl <= UInt<1>("h00") @[Counter.scala 23:29] - skip @[Counter.scala 23:21] - skip @[Counter.scala 43:17] - node T_1556 = and(T_1548, T_1551) @[Counter.scala 44:20] - node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) @[btb.scala 195:40] - node usePageHit = neq(pageHit, UInt<1>("h00")) @[btb.scala 196:28] - node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) @[btb.scala 197:23] - reg nextPageRepl : UInt<3>, clk - node T_1561 = bits(pageHit, 4, 0) @[btb.scala 199:48] - node T_1562 = bits(pageHit, 5, 5) @[btb.scala 199:69] - node T_1563 = cat(T_1561, T_1562) @[Cat.scala 20:58] - node T_1565 = dshl(UInt<1>("h01"), nextPageRepl) @[OneHot.scala 44:15] - node idxPageRepl = mux(usePageHit, T_1563, T_1565) @[btb.scala 199:24] - node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) @[btb.scala 200:28] - node T_1566 = bits(idxPageUpdateOH, 7, 4) @[OneHot.scala 22:18] - node T_1567 = bits(idxPageUpdateOH, 3, 0) @[OneHot.scala 23:18] - node T_1569 = neq(T_1566, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_1570 = or(T_1566, T_1567) @[OneHot.scala 24:28] - node T_1571 = bits(T_1570, 3, 2) @[OneHot.scala 22:18] - node T_1572 = bits(T_1570, 1, 0) @[OneHot.scala 23:18] - node T_1574 = neq(T_1571, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_1575 = or(T_1571, T_1572) @[OneHot.scala 24:28] - node T_1576 = bits(T_1575, 1, 1) @[CircuitMath.scala 21:8] - node T_1577 = cat(T_1574, T_1576) @[Cat.scala 20:58] - node idxPageUpdate = cat(T_1569, T_1577) @[Cat.scala 20:58] - node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) @[btb.scala 202:26] - node T_1579 = shr(r_btb_update.bits.pc, 12) @[btb.scala 162:39] - node T_1580 = shr(io.req.bits.addr, 12) @[btb.scala 162:39] - node samePage = eq(T_1579, T_1580) @[btb.scala 204:45] - node T_1582 = eq(samePage, UInt<1>("h00")) @[btb.scala 205:23] - node T_1584 = eq(usePageHit, UInt<1>("h00")) @[btb.scala 205:36] - node doTgtPageRepl = and(T_1582, T_1584) @[btb.scala 205:33] - node T_1585 = bits(idxPageUpdateOH, 4, 0) @[btb.scala 206:71] - node T_1586 = bits(idxPageUpdateOH, 5, 5) @[btb.scala 206:100] - node T_1587 = cat(T_1585, T_1586) @[Cat.scala 20:58] - node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_1587) @[btb.scala 206:24] - node T_1588 = mux(usePageHit, pageHit, tgtPageRepl) @[btb.scala 207:35] - node T_1589 = bits(T_1588, 7, 4) @[OneHot.scala 22:18] - node T_1590 = bits(T_1588, 3, 0) @[OneHot.scala 23:18] - node T_1592 = neq(T_1589, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_1593 = or(T_1589, T_1590) @[OneHot.scala 24:28] - node T_1594 = bits(T_1593, 3, 2) @[OneHot.scala 22:18] - node T_1595 = bits(T_1593, 1, 0) @[OneHot.scala 23:18] - node T_1597 = neq(T_1594, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_1598 = or(T_1594, T_1595) @[OneHot.scala 24:28] - node T_1599 = bits(T_1598, 1, 1) @[CircuitMath.scala 21:8] - node T_1600 = cat(T_1597, T_1599) @[Cat.scala 20:58] - node tgtPageUpdate = cat(T_1592, T_1600) @[Cat.scala 20:58] - node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) @[btb.scala 208:26] - node T_1602 = or(doIdxPageRepl, doTgtPageRepl) @[btb.scala 210:46] - node T_1603 = and(r_btb_update.valid, T_1602) @[btb.scala 210:28] - when T_1603 : @[btb.scala 210:65] - node T_1604 = and(doIdxPageRepl, doTgtPageRepl) @[btb.scala 211:30] - node T_1607 = mux(T_1604, UInt<2>("h02"), UInt<1>("h01")) @[btb.scala 212:40] - node T_1608 = add(nextPageRepl, T_1607) @[btb.scala 212:29] - node T_1609 = tail(T_1608, 1) @[btb.scala 212:29] - node T_1611 = geq(T_1609, UInt<3>("h06")) @[btb.scala 213:30] - node T_1612 = bits(T_1609, 0, 0) @[btb.scala 213:45] - node T_1613 = shl(T_1612, 0) @[btb.scala 213:24] - node T_1614 = mux(T_1611, T_1613, T_1609) @[btb.scala 213:24] - nextPageRepl <= T_1614 @[btb.scala 213:18] - skip @[btb.scala 210:65] - when r_btb_update.valid : @[btb.scala 216:29] - node T_1615 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) @[btb.scala 217:20] - node T_1617 = dshl(UInt<1>("h01"), T_1615) @[OneHot.scala 44:15] - node T_1618 = bits(r_btb_update.bits.pc, 11, 1) @[btb.scala 219:40] - idxs[T_1615] <= T_1618 @[btb.scala 219:17] - node T_1619 = bits(io.req.bits.addr, 11, 1) @[btb.scala 220:33] - tgts[T_1615] <= T_1619 @[btb.scala 220:17] - idxPages[T_1615] <= idxPageUpdate @[btb.scala 221:21] - tgtPages[T_1615] <= tgtPageUpdate @[btb.scala 222:21] - node T_1620 = or(isValid, T_1617) @[btb.scala 223:55] - node T_1621 = not(T_1617) @[btb.scala 223:73] - node T_1622 = and(isValid, T_1621) @[btb.scala 223:71] - node T_1623 = mux(r_btb_update.bits.isValid, T_1620, T_1622) @[btb.scala 223:19] - isValid <= T_1623 @[btb.scala 223:13] - node T_1624 = or(isReturn, T_1617) @[btb.scala 224:58] - node T_1625 = not(T_1617) @[btb.scala 224:77] - node T_1626 = and(isReturn, T_1625) @[btb.scala 224:75] - node T_1627 = mux(r_btb_update.bits.isReturn, T_1624, T_1626) @[btb.scala 224:20] - isReturn <= T_1627 @[btb.scala 224:14] - node T_1628 = or(isJump, T_1617) @[btb.scala 225:52] - node T_1629 = not(T_1617) @[btb.scala 225:69] - node T_1630 = and(isJump, T_1629) @[btb.scala 225:67] - node T_1631 = mux(r_btb_update.bits.isJump, T_1628, T_1630) @[btb.scala 225:18] - isJump <= T_1631 @[btb.scala 225:12] - node T_1632 = shr(r_btb_update.bits.br_pc, 1) @[btb.scala 227:47] - brIdx[T_1615] <= T_1632 @[btb.scala 227:20] - node T_1633 = bits(idxPageUpdate, 0, 0) @[btb.scala 230:39] - node T_1635 = eq(T_1633, UInt<1>("h00")) @[btb.scala 230:25] - node T_1636 = mux(T_1635, idxPageReplEn, tgtPageReplEn) @[btb.scala 236:24] - node T_1637 = shr(r_btb_update.bits.pc, 12) @[btb.scala 162:39] - node T_1638 = shr(io.req.bits.addr, 12) @[btb.scala 162:39] - node T_1639 = mux(T_1635, T_1637, T_1638) @[btb.scala 237:10] - node T_1640 = bits(T_1636, 0, 0) @[btb.scala 234:17] - when T_1640 : @[btb.scala 234:22] - pages[0] <= T_1639 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1641 = bits(T_1636, 2, 2) @[btb.scala 234:17] - when T_1641 : @[btb.scala 234:22] - pages[2] <= T_1639 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1642 = bits(T_1636, 4, 4) @[btb.scala 234:17] - when T_1642 : @[btb.scala 234:22] - pages[4] <= T_1639 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1643 = mux(T_1635, tgtPageReplEn, idxPageReplEn) @[btb.scala 238:24] - node T_1644 = shr(io.req.bits.addr, 12) @[btb.scala 162:39] - node T_1645 = shr(r_btb_update.bits.pc, 12) @[btb.scala 162:39] - node T_1646 = mux(T_1635, T_1644, T_1645) @[btb.scala 239:10] - node T_1647 = bits(T_1643, 1, 1) @[btb.scala 234:17] - when T_1647 : @[btb.scala 234:22] - pages[1] <= T_1646 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1648 = bits(T_1643, 3, 3) @[btb.scala 234:17] - when T_1648 : @[btb.scala 234:22] - pages[3] <= T_1646 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1649 = bits(T_1643, 5, 5) @[btb.scala 234:17] - when T_1649 : @[btb.scala 234:22] - pages[5] <= T_1646 @[btb.scala 234:33] - skip @[btb.scala 234:22] - node T_1650 = or(pageValid, tgtPageReplEn) @[btb.scala 240:28] - node T_1651 = or(T_1650, idxPageReplEn) @[btb.scala 240:44] - pageValid <= T_1651 @[btb.scala 240:15] - skip @[btb.scala 216:29] - node T_1653 = neq(hitsVec, UInt<1>("h00")) @[btb.scala 243:25] - io.resp.valid <= T_1653 @[btb.scala 243:17] - io.resp.bits.taken <= UInt<1>("h01") @[btb.scala 244:22] - node T_1655 = bits(hitsVec, 0, 0) @[Mux.scala 20:36] - node T_1656 = bits(hitsVec, 1, 1) @[Mux.scala 20:36] - node T_1657 = bits(hitsVec, 2, 2) @[Mux.scala 20:36] - node T_1658 = bits(hitsVec, 3, 3) @[Mux.scala 20:36] - node T_1659 = bits(hitsVec, 4, 4) @[Mux.scala 20:36] - node T_1660 = bits(hitsVec, 5, 5) @[Mux.scala 20:36] - node T_1661 = bits(hitsVec, 6, 6) @[Mux.scala 20:36] - node T_1662 = bits(hitsVec, 7, 7) @[Mux.scala 20:36] - node T_1663 = bits(hitsVec, 8, 8) @[Mux.scala 20:36] - node T_1664 = bits(hitsVec, 9, 9) @[Mux.scala 20:36] - node T_1665 = bits(hitsVec, 10, 10) @[Mux.scala 20:36] - node T_1666 = bits(hitsVec, 11, 11) @[Mux.scala 20:36] - node T_1667 = bits(hitsVec, 12, 12) @[Mux.scala 20:36] - node T_1668 = bits(hitsVec, 13, 13) @[Mux.scala 20:36] - node T_1669 = bits(hitsVec, 14, 14) @[Mux.scala 20:36] - node T_1670 = bits(hitsVec, 15, 15) @[Mux.scala 20:36] - node T_1671 = bits(hitsVec, 16, 16) @[Mux.scala 20:36] - node T_1672 = bits(hitsVec, 17, 17) @[Mux.scala 20:36] - node T_1673 = bits(hitsVec, 18, 18) @[Mux.scala 20:36] - node T_1674 = bits(hitsVec, 19, 19) @[Mux.scala 20:36] - node T_1675 = bits(hitsVec, 20, 20) @[Mux.scala 20:36] - node T_1676 = bits(hitsVec, 21, 21) @[Mux.scala 20:36] - node T_1677 = bits(hitsVec, 22, 22) @[Mux.scala 20:36] - node T_1678 = bits(hitsVec, 23, 23) @[Mux.scala 20:36] - node T_1679 = bits(hitsVec, 24, 24) @[Mux.scala 20:36] - node T_1680 = bits(hitsVec, 25, 25) @[Mux.scala 20:36] - node T_1681 = bits(hitsVec, 26, 26) @[Mux.scala 20:36] - node T_1682 = bits(hitsVec, 27, 27) @[Mux.scala 20:36] - node T_1683 = bits(hitsVec, 28, 28) @[Mux.scala 20:36] - node T_1684 = bits(hitsVec, 29, 29) @[Mux.scala 20:36] - node T_1685 = bits(hitsVec, 30, 30) @[Mux.scala 20:36] - node T_1686 = bits(hitsVec, 31, 31) @[Mux.scala 20:36] - node T_1687 = bits(hitsVec, 32, 32) @[Mux.scala 20:36] - node T_1688 = bits(hitsVec, 33, 33) @[Mux.scala 20:36] - node T_1689 = bits(hitsVec, 34, 34) @[Mux.scala 20:36] - node T_1690 = bits(hitsVec, 35, 35) @[Mux.scala 20:36] - node T_1691 = bits(hitsVec, 36, 36) @[Mux.scala 20:36] - node T_1692 = bits(hitsVec, 37, 37) @[Mux.scala 20:36] - node T_1693 = bits(hitsVec, 38, 38) @[Mux.scala 20:36] - node T_1694 = bits(hitsVec, 39, 39) @[Mux.scala 20:36] - node T_1696 = mux(T_1655, tgtPagesOH_0, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1698 = mux(T_1656, tgtPagesOH_1, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1700 = mux(T_1657, tgtPagesOH_2, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1702 = mux(T_1658, tgtPagesOH_3, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1704 = mux(T_1659, tgtPagesOH_4, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1706 = mux(T_1660, tgtPagesOH_5, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1708 = mux(T_1661, tgtPagesOH_6, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1710 = mux(T_1662, tgtPagesOH_7, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1712 = mux(T_1663, tgtPagesOH_8, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1714 = mux(T_1664, tgtPagesOH_9, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1716 = mux(T_1665, tgtPagesOH_10, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1718 = mux(T_1666, tgtPagesOH_11, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1720 = mux(T_1667, tgtPagesOH_12, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1722 = mux(T_1668, tgtPagesOH_13, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1724 = mux(T_1669, tgtPagesOH_14, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1726 = mux(T_1670, tgtPagesOH_15, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1728 = mux(T_1671, tgtPagesOH_16, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1730 = mux(T_1672, tgtPagesOH_17, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1732 = mux(T_1673, tgtPagesOH_18, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1734 = mux(T_1674, tgtPagesOH_19, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1736 = mux(T_1675, tgtPagesOH_20, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1738 = mux(T_1676, tgtPagesOH_21, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1740 = mux(T_1677, tgtPagesOH_22, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1742 = mux(T_1678, tgtPagesOH_23, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1744 = mux(T_1679, tgtPagesOH_24, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1746 = mux(T_1680, tgtPagesOH_25, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1748 = mux(T_1681, tgtPagesOH_26, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1750 = mux(T_1682, tgtPagesOH_27, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1752 = mux(T_1683, tgtPagesOH_28, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1754 = mux(T_1684, tgtPagesOH_29, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1756 = mux(T_1685, tgtPagesOH_30, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1758 = mux(T_1686, tgtPagesOH_31, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1760 = mux(T_1687, tgtPagesOH_32, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1762 = mux(T_1688, tgtPagesOH_33, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1764 = mux(T_1689, tgtPagesOH_34, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1766 = mux(T_1690, tgtPagesOH_35, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1768 = mux(T_1691, tgtPagesOH_36, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1770 = mux(T_1692, tgtPagesOH_37, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1772 = mux(T_1693, tgtPagesOH_38, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1774 = mux(T_1694, tgtPagesOH_39, UInt<1>("h00")) @[Mux.scala 18:72] - node T_1776 = or(T_1696, T_1698) @[Mux.scala 18:72] - node T_1777 = or(T_1776, T_1700) @[Mux.scala 18:72] - node T_1778 = or(T_1777, T_1702) @[Mux.scala 18:72] - node T_1779 = or(T_1778, T_1704) @[Mux.scala 18:72] - node T_1780 = or(T_1779, T_1706) @[Mux.scala 18:72] - node T_1781 = or(T_1780, T_1708) @[Mux.scala 18:72] - node T_1782 = or(T_1781, T_1710) @[Mux.scala 18:72] - node T_1783 = or(T_1782, T_1712) @[Mux.scala 18:72] - node T_1784 = or(T_1783, T_1714) @[Mux.scala 18:72] - node T_1785 = or(T_1784, T_1716) @[Mux.scala 18:72] - node T_1786 = or(T_1785, T_1718) @[Mux.scala 18:72] - node T_1787 = or(T_1786, T_1720) @[Mux.scala 18:72] - node T_1788 = or(T_1787, T_1722) @[Mux.scala 18:72] - node T_1789 = or(T_1788, T_1724) @[Mux.scala 18:72] - node T_1790 = or(T_1789, T_1726) @[Mux.scala 18:72] - node T_1791 = or(T_1790, T_1728) @[Mux.scala 18:72] - node T_1792 = or(T_1791, T_1730) @[Mux.scala 18:72] - node T_1793 = or(T_1792, T_1732) @[Mux.scala 18:72] - node T_1794 = or(T_1793, T_1734) @[Mux.scala 18:72] - node T_1795 = or(T_1794, T_1736) @[Mux.scala 18:72] - node T_1796 = or(T_1795, T_1738) @[Mux.scala 18:72] - node T_1797 = or(T_1796, T_1740) @[Mux.scala 18:72] - node T_1798 = or(T_1797, T_1742) @[Mux.scala 18:72] - node T_1799 = or(T_1798, T_1744) @[Mux.scala 18:72] - node T_1800 = or(T_1799, T_1746) @[Mux.scala 18:72] - node T_1801 = or(T_1800, T_1748) @[Mux.scala 18:72] - node T_1802 = or(T_1801, T_1750) @[Mux.scala 18:72] - node T_1803 = or(T_1802, T_1752) @[Mux.scala 18:72] - node T_1804 = or(T_1803, T_1754) @[Mux.scala 18:72] - node T_1805 = or(T_1804, T_1756) @[Mux.scala 18:72] - node T_1806 = or(T_1805, T_1758) @[Mux.scala 18:72] - node T_1807 = or(T_1806, T_1760) @[Mux.scala 18:72] - node T_1808 = or(T_1807, T_1762) @[Mux.scala 18:72] - node T_1809 = or(T_1808, T_1764) @[Mux.scala 18:72] - node T_1810 = or(T_1809, T_1766) @[Mux.scala 18:72] - node T_1811 = or(T_1810, T_1768) @[Mux.scala 18:72] - node T_1812 = or(T_1811, T_1770) @[Mux.scala 18:72] - node T_1813 = or(T_1812, T_1772) @[Mux.scala 18:72] - node T_1814 = or(T_1813, T_1774) @[Mux.scala 18:72] + reg T_778 : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk with : + reset => (UInt<1>("h0"), T_778) + when io.btb_update.valid : + T_778 <- io.btb_update.bits + wire r_btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} + r_btb_update is invalid + r_btb_update.valid <= T_777 + r_btb_update.bits <- T_778 + node T_964 = shr(io.req.bits.addr, 12) + node T_965 = eq(pages[0], T_964) + node T_966 = eq(pages[1], T_964) + node T_967 = eq(pages[2], T_964) + node T_968 = eq(pages[3], T_964) + node T_969 = eq(pages[4], T_964) + node T_970 = eq(pages[5], T_964) + node T_971 = cat(T_967, T_966) + node T_972 = cat(T_971, T_965) + node T_973 = cat(T_970, T_969) + node T_974 = cat(T_973, T_968) + node T_975 = cat(T_974, T_972) + node pageHit = and(pageValid, T_975) + node T_976 = bits(io.req.bits.addr, 11, 1) + node T_977 = eq(idxs[0], T_976) + node T_978 = bits(io.req.bits.addr, 11, 1) + node T_979 = eq(idxs[1], T_978) + node T_980 = bits(io.req.bits.addr, 11, 1) + node T_981 = eq(idxs[2], T_980) + node T_982 = bits(io.req.bits.addr, 11, 1) + node T_983 = eq(idxs[3], T_982) + node T_984 = bits(io.req.bits.addr, 11, 1) + node T_985 = eq(idxs[4], T_984) + node T_986 = bits(io.req.bits.addr, 11, 1) + node T_987 = eq(idxs[5], T_986) + node T_988 = bits(io.req.bits.addr, 11, 1) + node T_989 = eq(idxs[6], T_988) + node T_990 = bits(io.req.bits.addr, 11, 1) + node T_991 = eq(idxs[7], T_990) + node T_992 = bits(io.req.bits.addr, 11, 1) + node T_993 = eq(idxs[8], T_992) + node T_994 = bits(io.req.bits.addr, 11, 1) + node T_995 = eq(idxs[9], T_994) + node T_996 = bits(io.req.bits.addr, 11, 1) + node T_997 = eq(idxs[10], T_996) + node T_998 = bits(io.req.bits.addr, 11, 1) + node T_999 = eq(idxs[11], T_998) + node T_1000 = bits(io.req.bits.addr, 11, 1) + node T_1001 = eq(idxs[12], T_1000) + node T_1002 = bits(io.req.bits.addr, 11, 1) + node T_1003 = eq(idxs[13], T_1002) + node T_1004 = bits(io.req.bits.addr, 11, 1) + node T_1005 = eq(idxs[14], T_1004) + node T_1006 = bits(io.req.bits.addr, 11, 1) + node T_1007 = eq(idxs[15], T_1006) + node T_1008 = bits(io.req.bits.addr, 11, 1) + node T_1009 = eq(idxs[16], T_1008) + node T_1010 = bits(io.req.bits.addr, 11, 1) + node T_1011 = eq(idxs[17], T_1010) + node T_1012 = bits(io.req.bits.addr, 11, 1) + node T_1013 = eq(idxs[18], T_1012) + node T_1014 = bits(io.req.bits.addr, 11, 1) + node T_1015 = eq(idxs[19], T_1014) + node T_1016 = bits(io.req.bits.addr, 11, 1) + node T_1017 = eq(idxs[20], T_1016) + node T_1018 = bits(io.req.bits.addr, 11, 1) + node T_1019 = eq(idxs[21], T_1018) + node T_1020 = bits(io.req.bits.addr, 11, 1) + node T_1021 = eq(idxs[22], T_1020) + node T_1022 = bits(io.req.bits.addr, 11, 1) + node T_1023 = eq(idxs[23], T_1022) + node T_1024 = bits(io.req.bits.addr, 11, 1) + node T_1025 = eq(idxs[24], T_1024) + node T_1026 = bits(io.req.bits.addr, 11, 1) + node T_1027 = eq(idxs[25], T_1026) + node T_1028 = bits(io.req.bits.addr, 11, 1) + node T_1029 = eq(idxs[26], T_1028) + node T_1030 = bits(io.req.bits.addr, 11, 1) + node T_1031 = eq(idxs[27], T_1030) + node T_1032 = bits(io.req.bits.addr, 11, 1) + node T_1033 = eq(idxs[28], T_1032) + node T_1034 = bits(io.req.bits.addr, 11, 1) + node T_1035 = eq(idxs[29], T_1034) + node T_1036 = bits(io.req.bits.addr, 11, 1) + node T_1037 = eq(idxs[30], T_1036) + node T_1038 = bits(io.req.bits.addr, 11, 1) + node T_1039 = eq(idxs[31], T_1038) + node T_1040 = bits(io.req.bits.addr, 11, 1) + node T_1041 = eq(idxs[32], T_1040) + node T_1042 = bits(io.req.bits.addr, 11, 1) + node T_1043 = eq(idxs[33], T_1042) + node T_1044 = bits(io.req.bits.addr, 11, 1) + node T_1045 = eq(idxs[34], T_1044) + node T_1046 = bits(io.req.bits.addr, 11, 1) + node T_1047 = eq(idxs[35], T_1046) + node T_1048 = bits(io.req.bits.addr, 11, 1) + node T_1049 = eq(idxs[36], T_1048) + node T_1050 = bits(io.req.bits.addr, 11, 1) + node T_1051 = eq(idxs[37], T_1050) + node T_1052 = bits(io.req.bits.addr, 11, 1) + node T_1053 = eq(idxs[38], T_1052) + node T_1054 = bits(io.req.bits.addr, 11, 1) + node T_1055 = eq(idxs[39], T_1054) + node T_1056 = cat(T_979, T_977) + node T_1057 = cat(T_985, T_983) + node T_1058 = cat(T_1057, T_981) + node T_1059 = cat(T_1058, T_1056) + node T_1060 = cat(T_989, T_987) + node T_1061 = cat(T_995, T_993) + node T_1062 = cat(T_1061, T_991) + node T_1063 = cat(T_1062, T_1060) + node T_1064 = cat(T_1063, T_1059) + node T_1065 = cat(T_999, T_997) + node T_1066 = cat(T_1005, T_1003) + node T_1067 = cat(T_1066, T_1001) + node T_1068 = cat(T_1067, T_1065) + node T_1069 = cat(T_1009, T_1007) + node T_1070 = cat(T_1015, T_1013) + node T_1071 = cat(T_1070, T_1011) + node T_1072 = cat(T_1071, T_1069) + node T_1073 = cat(T_1072, T_1068) + node T_1074 = cat(T_1073, T_1064) + node T_1075 = cat(T_1019, T_1017) + node T_1076 = cat(T_1025, T_1023) + node T_1077 = cat(T_1076, T_1021) + node T_1078 = cat(T_1077, T_1075) + node T_1079 = cat(T_1029, T_1027) + node T_1080 = cat(T_1035, T_1033) + node T_1081 = cat(T_1080, T_1031) + node T_1082 = cat(T_1081, T_1079) + node T_1083 = cat(T_1082, T_1078) + node T_1084 = cat(T_1039, T_1037) + node T_1085 = cat(T_1045, T_1043) + node T_1086 = cat(T_1085, T_1041) + node T_1087 = cat(T_1086, T_1084) + node T_1088 = cat(T_1049, T_1047) + node T_1089 = cat(T_1055, T_1053) + node T_1090 = cat(T_1089, T_1051) + node T_1091 = cat(T_1090, T_1088) + node T_1092 = cat(T_1091, T_1087) + node T_1093 = cat(T_1092, T_1083) + node T_1094 = cat(T_1093, T_1074) + node T_1095 = and(idxPagesOH_0, pageHit) + node T_1096 = and(idxPagesOH_1, pageHit) + node T_1097 = and(idxPagesOH_2, pageHit) + node T_1098 = and(idxPagesOH_3, pageHit) + node T_1099 = and(idxPagesOH_4, pageHit) + node T_1100 = and(idxPagesOH_5, pageHit) + node T_1101 = and(idxPagesOH_6, pageHit) + node T_1102 = and(idxPagesOH_7, pageHit) + node T_1103 = and(idxPagesOH_8, pageHit) + node T_1104 = and(idxPagesOH_9, pageHit) + node T_1105 = and(idxPagesOH_10, pageHit) + node T_1106 = and(idxPagesOH_11, pageHit) + node T_1107 = and(idxPagesOH_12, pageHit) + node T_1108 = and(idxPagesOH_13, pageHit) + node T_1109 = and(idxPagesOH_14, pageHit) + node T_1110 = and(idxPagesOH_15, pageHit) + node T_1111 = and(idxPagesOH_16, pageHit) + node T_1112 = and(idxPagesOH_17, pageHit) + node T_1113 = and(idxPagesOH_18, pageHit) + node T_1114 = and(idxPagesOH_19, pageHit) + node T_1115 = and(idxPagesOH_20, pageHit) + node T_1116 = and(idxPagesOH_21, pageHit) + node T_1117 = and(idxPagesOH_22, pageHit) + node T_1118 = and(idxPagesOH_23, pageHit) + node T_1119 = and(idxPagesOH_24, pageHit) + node T_1120 = and(idxPagesOH_25, pageHit) + node T_1121 = and(idxPagesOH_26, pageHit) + node T_1122 = and(idxPagesOH_27, pageHit) + node T_1123 = and(idxPagesOH_28, pageHit) + node T_1124 = and(idxPagesOH_29, pageHit) + node T_1125 = and(idxPagesOH_30, pageHit) + node T_1126 = and(idxPagesOH_31, pageHit) + node T_1127 = and(idxPagesOH_32, pageHit) + node T_1128 = and(idxPagesOH_33, pageHit) + node T_1129 = and(idxPagesOH_34, pageHit) + node T_1130 = and(idxPagesOH_35, pageHit) + node T_1131 = and(idxPagesOH_36, pageHit) + node T_1132 = and(idxPagesOH_37, pageHit) + node T_1133 = and(idxPagesOH_38, pageHit) + node T_1134 = and(idxPagesOH_39, pageHit) + node T_1136 = neq(T_1095, UInt<1>("h0")) + node T_1138 = neq(T_1096, UInt<1>("h0")) + node T_1140 = neq(T_1097, UInt<1>("h0")) + node T_1142 = neq(T_1098, UInt<1>("h0")) + node T_1144 = neq(T_1099, UInt<1>("h0")) + node T_1146 = neq(T_1100, UInt<1>("h0")) + node T_1148 = neq(T_1101, UInt<1>("h0")) + node T_1150 = neq(T_1102, UInt<1>("h0")) + node T_1152 = neq(T_1103, UInt<1>("h0")) + node T_1154 = neq(T_1104, UInt<1>("h0")) + node T_1156 = neq(T_1105, UInt<1>("h0")) + node T_1158 = neq(T_1106, UInt<1>("h0")) + node T_1160 = neq(T_1107, UInt<1>("h0")) + node T_1162 = neq(T_1108, UInt<1>("h0")) + node T_1164 = neq(T_1109, UInt<1>("h0")) + node T_1166 = neq(T_1110, UInt<1>("h0")) + node T_1168 = neq(T_1111, UInt<1>("h0")) + node T_1170 = neq(T_1112, UInt<1>("h0")) + node T_1172 = neq(T_1113, UInt<1>("h0")) + node T_1174 = neq(T_1114, UInt<1>("h0")) + node T_1176 = neq(T_1115, UInt<1>("h0")) + node T_1178 = neq(T_1116, UInt<1>("h0")) + node T_1180 = neq(T_1117, UInt<1>("h0")) + node T_1182 = neq(T_1118, UInt<1>("h0")) + node T_1184 = neq(T_1119, UInt<1>("h0")) + node T_1186 = neq(T_1120, UInt<1>("h0")) + node T_1188 = neq(T_1121, UInt<1>("h0")) + node T_1190 = neq(T_1122, UInt<1>("h0")) + node T_1192 = neq(T_1123, UInt<1>("h0")) + node T_1194 = neq(T_1124, UInt<1>("h0")) + node T_1196 = neq(T_1125, UInt<1>("h0")) + node T_1198 = neq(T_1126, UInt<1>("h0")) + node T_1200 = neq(T_1127, UInt<1>("h0")) + node T_1202 = neq(T_1128, UInt<1>("h0")) + node T_1204 = neq(T_1129, UInt<1>("h0")) + node T_1206 = neq(T_1130, UInt<1>("h0")) + node T_1208 = neq(T_1131, UInt<1>("h0")) + node T_1210 = neq(T_1132, UInt<1>("h0")) + node T_1212 = neq(T_1133, UInt<1>("h0")) + node T_1214 = neq(T_1134, UInt<1>("h0")) + node T_1215 = cat(T_1138, T_1136) + node T_1216 = cat(T_1144, T_1142) + node T_1217 = cat(T_1216, T_1140) + node T_1218 = cat(T_1217, T_1215) + node T_1219 = cat(T_1148, T_1146) + node T_1220 = cat(T_1154, T_1152) + node T_1221 = cat(T_1220, T_1150) + node T_1222 = cat(T_1221, T_1219) + node T_1223 = cat(T_1222, T_1218) + node T_1224 = cat(T_1158, T_1156) + node T_1225 = cat(T_1164, T_1162) + node T_1226 = cat(T_1225, T_1160) + node T_1227 = cat(T_1226, T_1224) + node T_1228 = cat(T_1168, T_1166) + node T_1229 = cat(T_1174, T_1172) + node T_1230 = cat(T_1229, T_1170) + node T_1231 = cat(T_1230, T_1228) + node T_1232 = cat(T_1231, T_1227) + node T_1233 = cat(T_1232, T_1223) + node T_1234 = cat(T_1178, T_1176) + node T_1235 = cat(T_1184, T_1182) + node T_1236 = cat(T_1235, T_1180) + node T_1237 = cat(T_1236, T_1234) + node T_1238 = cat(T_1188, T_1186) + node T_1239 = cat(T_1194, T_1192) + node T_1240 = cat(T_1239, T_1190) + node T_1241 = cat(T_1240, T_1238) + node T_1242 = cat(T_1241, T_1237) + node T_1243 = cat(T_1198, T_1196) + node T_1244 = cat(T_1204, T_1202) + node T_1245 = cat(T_1244, T_1200) + node T_1246 = cat(T_1245, T_1243) + node T_1247 = cat(T_1208, T_1206) + node T_1248 = cat(T_1214, T_1212) + node T_1249 = cat(T_1248, T_1210) + node T_1250 = cat(T_1249, T_1247) + node T_1251 = cat(T_1250, T_1246) + node T_1252 = cat(T_1251, T_1242) + node T_1253 = cat(T_1252, T_1233) + node T_1254 = and(T_1094, T_1253) + node hitsVec = and(T_1254, isValid) + node T_1255 = shr(r_btb_update.bits.pc, 12) + node T_1256 = eq(pages[0], T_1255) + node T_1257 = eq(pages[1], T_1255) + node T_1258 = eq(pages[2], T_1255) + node T_1259 = eq(pages[3], T_1255) + node T_1260 = eq(pages[4], T_1255) + node T_1261 = eq(pages[5], T_1255) + node T_1262 = cat(T_1258, T_1257) + node T_1263 = cat(T_1262, T_1256) + node T_1264 = cat(T_1261, T_1260) + node T_1265 = cat(T_1264, T_1259) + node T_1266 = cat(T_1265, T_1263) + node updatePageHit = and(pageValid, T_1266) + node T_1267 = bits(r_btb_update.bits.pc, 11, 1) + node T_1268 = eq(idxs[0], T_1267) + node T_1269 = bits(r_btb_update.bits.pc, 11, 1) + node T_1270 = eq(idxs[1], T_1269) + node T_1271 = bits(r_btb_update.bits.pc, 11, 1) + node T_1272 = eq(idxs[2], T_1271) + node T_1273 = bits(r_btb_update.bits.pc, 11, 1) + node T_1274 = eq(idxs[3], T_1273) + node T_1275 = bits(r_btb_update.bits.pc, 11, 1) + node T_1276 = eq(idxs[4], T_1275) + node T_1277 = bits(r_btb_update.bits.pc, 11, 1) + node T_1278 = eq(idxs[5], T_1277) + node T_1279 = bits(r_btb_update.bits.pc, 11, 1) + node T_1280 = eq(idxs[6], T_1279) + node T_1281 = bits(r_btb_update.bits.pc, 11, 1) + node T_1282 = eq(idxs[7], T_1281) + node T_1283 = bits(r_btb_update.bits.pc, 11, 1) + node T_1284 = eq(idxs[8], T_1283) + node T_1285 = bits(r_btb_update.bits.pc, 11, 1) + node T_1286 = eq(idxs[9], T_1285) + node T_1287 = bits(r_btb_update.bits.pc, 11, 1) + node T_1288 = eq(idxs[10], T_1287) + node T_1289 = bits(r_btb_update.bits.pc, 11, 1) + node T_1290 = eq(idxs[11], T_1289) + node T_1291 = bits(r_btb_update.bits.pc, 11, 1) + node T_1292 = eq(idxs[12], T_1291) + node T_1293 = bits(r_btb_update.bits.pc, 11, 1) + node T_1294 = eq(idxs[13], T_1293) + node T_1295 = bits(r_btb_update.bits.pc, 11, 1) + node T_1296 = eq(idxs[14], T_1295) + node T_1297 = bits(r_btb_update.bits.pc, 11, 1) + node T_1298 = eq(idxs[15], T_1297) + node T_1299 = bits(r_btb_update.bits.pc, 11, 1) + node T_1300 = eq(idxs[16], T_1299) + node T_1301 = bits(r_btb_update.bits.pc, 11, 1) + node T_1302 = eq(idxs[17], T_1301) + node T_1303 = bits(r_btb_update.bits.pc, 11, 1) + node T_1304 = eq(idxs[18], T_1303) + node T_1305 = bits(r_btb_update.bits.pc, 11, 1) + node T_1306 = eq(idxs[19], T_1305) + node T_1307 = bits(r_btb_update.bits.pc, 11, 1) + node T_1308 = eq(idxs[20], T_1307) + node T_1309 = bits(r_btb_update.bits.pc, 11, 1) + node T_1310 = eq(idxs[21], T_1309) + node T_1311 = bits(r_btb_update.bits.pc, 11, 1) + node T_1312 = eq(idxs[22], T_1311) + node T_1313 = bits(r_btb_update.bits.pc, 11, 1) + node T_1314 = eq(idxs[23], T_1313) + node T_1315 = bits(r_btb_update.bits.pc, 11, 1) + node T_1316 = eq(idxs[24], T_1315) + node T_1317 = bits(r_btb_update.bits.pc, 11, 1) + node T_1318 = eq(idxs[25], T_1317) + node T_1319 = bits(r_btb_update.bits.pc, 11, 1) + node T_1320 = eq(idxs[26], T_1319) + node T_1321 = bits(r_btb_update.bits.pc, 11, 1) + node T_1322 = eq(idxs[27], T_1321) + node T_1323 = bits(r_btb_update.bits.pc, 11, 1) + node T_1324 = eq(idxs[28], T_1323) + node T_1325 = bits(r_btb_update.bits.pc, 11, 1) + node T_1326 = eq(idxs[29], T_1325) + node T_1327 = bits(r_btb_update.bits.pc, 11, 1) + node T_1328 = eq(idxs[30], T_1327) + node T_1329 = bits(r_btb_update.bits.pc, 11, 1) + node T_1330 = eq(idxs[31], T_1329) + node T_1331 = bits(r_btb_update.bits.pc, 11, 1) + node T_1332 = eq(idxs[32], T_1331) + node T_1333 = bits(r_btb_update.bits.pc, 11, 1) + node T_1334 = eq(idxs[33], T_1333) + node T_1335 = bits(r_btb_update.bits.pc, 11, 1) + node T_1336 = eq(idxs[34], T_1335) + node T_1337 = bits(r_btb_update.bits.pc, 11, 1) + node T_1338 = eq(idxs[35], T_1337) + node T_1339 = bits(r_btb_update.bits.pc, 11, 1) + node T_1340 = eq(idxs[36], T_1339) + node T_1341 = bits(r_btb_update.bits.pc, 11, 1) + node T_1342 = eq(idxs[37], T_1341) + node T_1343 = bits(r_btb_update.bits.pc, 11, 1) + node T_1344 = eq(idxs[38], T_1343) + node T_1345 = bits(r_btb_update.bits.pc, 11, 1) + node T_1346 = eq(idxs[39], T_1345) + node T_1347 = cat(T_1270, T_1268) + node T_1348 = cat(T_1276, T_1274) + node T_1349 = cat(T_1348, T_1272) + node T_1350 = cat(T_1349, T_1347) + node T_1351 = cat(T_1280, T_1278) + node T_1352 = cat(T_1286, T_1284) + node T_1353 = cat(T_1352, T_1282) + node T_1354 = cat(T_1353, T_1351) + node T_1355 = cat(T_1354, T_1350) + node T_1356 = cat(T_1290, T_1288) + node T_1357 = cat(T_1296, T_1294) + node T_1358 = cat(T_1357, T_1292) + node T_1359 = cat(T_1358, T_1356) + node T_1360 = cat(T_1300, T_1298) + node T_1361 = cat(T_1306, T_1304) + node T_1362 = cat(T_1361, T_1302) + node T_1363 = cat(T_1362, T_1360) + node T_1364 = cat(T_1363, T_1359) + node T_1365 = cat(T_1364, T_1355) + node T_1366 = cat(T_1310, T_1308) + node T_1367 = cat(T_1316, T_1314) + node T_1368 = cat(T_1367, T_1312) + node T_1369 = cat(T_1368, T_1366) + node T_1370 = cat(T_1320, T_1318) + node T_1371 = cat(T_1326, T_1324) + node T_1372 = cat(T_1371, T_1322) + node T_1373 = cat(T_1372, T_1370) + node T_1374 = cat(T_1373, T_1369) + node T_1375 = cat(T_1330, T_1328) + node T_1376 = cat(T_1336, T_1334) + node T_1377 = cat(T_1376, T_1332) + node T_1378 = cat(T_1377, T_1375) + node T_1379 = cat(T_1340, T_1338) + node T_1380 = cat(T_1346, T_1344) + node T_1381 = cat(T_1380, T_1342) + node T_1382 = cat(T_1381, T_1379) + node T_1383 = cat(T_1382, T_1378) + node T_1384 = cat(T_1383, T_1374) + node T_1385 = cat(T_1384, T_1365) + node T_1386 = and(idxPagesOH_0, updatePageHit) + node T_1387 = and(idxPagesOH_1, updatePageHit) + node T_1388 = and(idxPagesOH_2, updatePageHit) + node T_1389 = and(idxPagesOH_3, updatePageHit) + node T_1390 = and(idxPagesOH_4, updatePageHit) + node T_1391 = and(idxPagesOH_5, updatePageHit) + node T_1392 = and(idxPagesOH_6, updatePageHit) + node T_1393 = and(idxPagesOH_7, updatePageHit) + node T_1394 = and(idxPagesOH_8, updatePageHit) + node T_1395 = and(idxPagesOH_9, updatePageHit) + node T_1396 = and(idxPagesOH_10, updatePageHit) + node T_1397 = and(idxPagesOH_11, updatePageHit) + node T_1398 = and(idxPagesOH_12, updatePageHit) + node T_1399 = and(idxPagesOH_13, updatePageHit) + node T_1400 = and(idxPagesOH_14, updatePageHit) + node T_1401 = and(idxPagesOH_15, updatePageHit) + node T_1402 = and(idxPagesOH_16, updatePageHit) + node T_1403 = and(idxPagesOH_17, updatePageHit) + node T_1404 = and(idxPagesOH_18, updatePageHit) + node T_1405 = and(idxPagesOH_19, updatePageHit) + node T_1406 = and(idxPagesOH_20, updatePageHit) + node T_1407 = and(idxPagesOH_21, updatePageHit) + node T_1408 = and(idxPagesOH_22, updatePageHit) + node T_1409 = and(idxPagesOH_23, updatePageHit) + node T_1410 = and(idxPagesOH_24, updatePageHit) + node T_1411 = and(idxPagesOH_25, updatePageHit) + node T_1412 = and(idxPagesOH_26, updatePageHit) + node T_1413 = and(idxPagesOH_27, updatePageHit) + node T_1414 = and(idxPagesOH_28, updatePageHit) + node T_1415 = and(idxPagesOH_29, updatePageHit) + node T_1416 = and(idxPagesOH_30, updatePageHit) + node T_1417 = and(idxPagesOH_31, updatePageHit) + node T_1418 = and(idxPagesOH_32, updatePageHit) + node T_1419 = and(idxPagesOH_33, updatePageHit) + node T_1420 = and(idxPagesOH_34, updatePageHit) + node T_1421 = and(idxPagesOH_35, updatePageHit) + node T_1422 = and(idxPagesOH_36, updatePageHit) + node T_1423 = and(idxPagesOH_37, updatePageHit) + node T_1424 = and(idxPagesOH_38, updatePageHit) + node T_1425 = and(idxPagesOH_39, updatePageHit) + node T_1427 = neq(T_1386, UInt<1>("h0")) + node T_1429 = neq(T_1387, UInt<1>("h0")) + node T_1431 = neq(T_1388, UInt<1>("h0")) + node T_1433 = neq(T_1389, UInt<1>("h0")) + node T_1435 = neq(T_1390, UInt<1>("h0")) + node T_1437 = neq(T_1391, UInt<1>("h0")) + node T_1439 = neq(T_1392, UInt<1>("h0")) + node T_1441 = neq(T_1393, UInt<1>("h0")) + node T_1443 = neq(T_1394, UInt<1>("h0")) + node T_1445 = neq(T_1395, UInt<1>("h0")) + node T_1447 = neq(T_1396, UInt<1>("h0")) + node T_1449 = neq(T_1397, UInt<1>("h0")) + node T_1451 = neq(T_1398, UInt<1>("h0")) + node T_1453 = neq(T_1399, UInt<1>("h0")) + node T_1455 = neq(T_1400, UInt<1>("h0")) + node T_1457 = neq(T_1401, UInt<1>("h0")) + node T_1459 = neq(T_1402, UInt<1>("h0")) + node T_1461 = neq(T_1403, UInt<1>("h0")) + node T_1463 = neq(T_1404, UInt<1>("h0")) + node T_1465 = neq(T_1405, UInt<1>("h0")) + node T_1467 = neq(T_1406, UInt<1>("h0")) + node T_1469 = neq(T_1407, UInt<1>("h0")) + node T_1471 = neq(T_1408, UInt<1>("h0")) + node T_1473 = neq(T_1409, UInt<1>("h0")) + node T_1475 = neq(T_1410, UInt<1>("h0")) + node T_1477 = neq(T_1411, UInt<1>("h0")) + node T_1479 = neq(T_1412, UInt<1>("h0")) + node T_1481 = neq(T_1413, UInt<1>("h0")) + node T_1483 = neq(T_1414, UInt<1>("h0")) + node T_1485 = neq(T_1415, UInt<1>("h0")) + node T_1487 = neq(T_1416, UInt<1>("h0")) + node T_1489 = neq(T_1417, UInt<1>("h0")) + node T_1491 = neq(T_1418, UInt<1>("h0")) + node T_1493 = neq(T_1419, UInt<1>("h0")) + node T_1495 = neq(T_1420, UInt<1>("h0")) + node T_1497 = neq(T_1421, UInt<1>("h0")) + node T_1499 = neq(T_1422, UInt<1>("h0")) + node T_1501 = neq(T_1423, UInt<1>("h0")) + node T_1503 = neq(T_1424, UInt<1>("h0")) + node T_1505 = neq(T_1425, UInt<1>("h0")) + node T_1506 = cat(T_1429, T_1427) + node T_1507 = cat(T_1435, T_1433) + node T_1508 = cat(T_1507, T_1431) + node T_1509 = cat(T_1508, T_1506) + node T_1510 = cat(T_1439, T_1437) + node T_1511 = cat(T_1445, T_1443) + node T_1512 = cat(T_1511, T_1441) + node T_1513 = cat(T_1512, T_1510) + node T_1514 = cat(T_1513, T_1509) + node T_1515 = cat(T_1449, T_1447) + node T_1516 = cat(T_1455, T_1453) + node T_1517 = cat(T_1516, T_1451) + node T_1518 = cat(T_1517, T_1515) + node T_1519 = cat(T_1459, T_1457) + node T_1520 = cat(T_1465, T_1463) + node T_1521 = cat(T_1520, T_1461) + node T_1522 = cat(T_1521, T_1519) + node T_1523 = cat(T_1522, T_1518) + node T_1524 = cat(T_1523, T_1514) + node T_1525 = cat(T_1469, T_1467) + node T_1526 = cat(T_1475, T_1473) + node T_1527 = cat(T_1526, T_1471) + node T_1528 = cat(T_1527, T_1525) + node T_1529 = cat(T_1479, T_1477) + node T_1530 = cat(T_1485, T_1483) + node T_1531 = cat(T_1530, T_1481) + node T_1532 = cat(T_1531, T_1529) + node T_1533 = cat(T_1532, T_1528) + node T_1534 = cat(T_1489, T_1487) + node T_1535 = cat(T_1495, T_1493) + node T_1536 = cat(T_1535, T_1491) + node T_1537 = cat(T_1536, T_1534) + node T_1538 = cat(T_1499, T_1497) + node T_1539 = cat(T_1505, T_1503) + node T_1540 = cat(T_1539, T_1501) + node T_1541 = cat(T_1540, T_1538) + node T_1542 = cat(T_1541, T_1537) + node T_1543 = cat(T_1542, T_1533) + node T_1544 = cat(T_1543, T_1524) + node T_1545 = and(T_1385, T_1544) + node updateHits = and(T_1545, isValid) + node T_1547 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h0")) + node T_1548 = and(r_btb_update.valid, T_1547) + reg nextRepl : UInt<6>, clk with : + reset => (reset, UInt<6>("h0")) + when T_1548 : + T_1551 <= eq(nextRepl, UInt<6>("h27")) + node T_1553 = add(nextRepl, UInt<1>("h1")) + node T_1554 = tail(T_1553, 1) + nextRepl <= T_1554 + when T_1551 : + nextRepl <= UInt<1>("h0") + node T_1556 = and(T_1548, T_1551) + node useUpdatePageHit = neq(updatePageHit, UInt<1>("h0")) + node usePageHit = neq(pageHit, UInt<1>("h0")) + node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h0")) + reg nextPageRepl : UInt<3>, clk with : + reset => (UInt<1>("h0"), nextPageRepl) + node T_1561 = bits(pageHit, 4, 0) + node T_1562 = bits(pageHit, 5, 5) + node T_1563 = cat(T_1561, T_1562) + node T_1565 = dshl(UInt<1>("h1"), nextPageRepl) + node idxPageRepl = mux(usePageHit, T_1563, T_1565) + node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) + node T_1566 = bits(idxPageUpdateOH, 7, 4) + node T_1567 = bits(idxPageUpdateOH, 3, 0) + node T_1569 = neq(T_1566, UInt<1>("h0")) + node T_1570 = or(T_1566, T_1567) + node T_1571 = bits(T_1570, 3, 2) + node T_1572 = bits(T_1570, 1, 0) + node T_1574 = neq(T_1571, UInt<1>("h0")) + node T_1575 = or(T_1571, T_1572) + node T_1576 = bits(T_1575, 1, 1) + node T_1577 = cat(T_1574, T_1576) + node idxPageUpdate = cat(T_1569, T_1577) + node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h0")) + node T_1579 = shr(r_btb_update.bits.pc, 12) + node T_1580 = shr(io.req.bits.addr, 12) + node samePage = eq(T_1579, T_1580) + node T_1582 = eq(samePage, UInt<1>("h0")) + node T_1584 = eq(usePageHit, UInt<1>("h0")) + node doTgtPageRepl = and(T_1582, T_1584) + node T_1585 = bits(idxPageUpdateOH, 4, 0) + node T_1586 = bits(idxPageUpdateOH, 5, 5) + node T_1587 = cat(T_1585, T_1586) + node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_1587) + node T_1588 = mux(usePageHit, pageHit, tgtPageRepl) + node T_1589 = bits(T_1588, 7, 4) + node T_1590 = bits(T_1588, 3, 0) + node T_1592 = neq(T_1589, UInt<1>("h0")) + node T_1593 = or(T_1589, T_1590) + node T_1594 = bits(T_1593, 3, 2) + node T_1595 = bits(T_1593, 1, 0) + node T_1597 = neq(T_1594, UInt<1>("h0")) + node T_1598 = or(T_1594, T_1595) + node T_1599 = bits(T_1598, 1, 1) + node T_1600 = cat(T_1597, T_1599) + node tgtPageUpdate = cat(T_1592, T_1600) + node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h0")) + node T_1602 = or(doIdxPageRepl, doTgtPageRepl) + node T_1603 = and(r_btb_update.valid, T_1602) + when T_1603 : + node T_1604 = and(doIdxPageRepl, doTgtPageRepl) + node T_1607 = mux(T_1604, UInt<2>("h2"), UInt<1>("h1")) + node T_1608 = add(nextPageRepl, T_1607) + node T_1609 = tail(T_1608, 1) + node T_1611 = geq(T_1609, UInt<3>("h6")) + node T_1612 = bits(T_1609, 0, 0) + node T_1613 = shl(T_1612, 0) + node T_1614 = mux(T_1611, T_1613, T_1609) + nextPageRepl <= T_1614 + when r_btb_update.valid : + node T_1615 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) + node T_1617 = dshl(UInt<1>("h1"), T_1615) + node T_1618 = bits(r_btb_update.bits.pc, 11, 1) + idxs[T_1615] <= T_1618 + node T_1619 = bits(io.req.bits.addr, 11, 1) + tgts[T_1615] <= T_1619 + idxPages[T_1615] <= idxPageUpdate + tgtPages[T_1615] <= tgtPageUpdate + node T_1620 = or(isValid, T_1617) + node T_1621 = not(T_1617) + node T_1622 = and(isValid, T_1621) + node T_1623 = mux(r_btb_update.bits.isValid, T_1620, T_1622) + isValid <= T_1623 + node T_1624 = or(isReturn, T_1617) + node T_1625 = not(T_1617) + node T_1626 = and(isReturn, T_1625) + node T_1627 = mux(r_btb_update.bits.isReturn, T_1624, T_1626) + isReturn <= T_1627 + node T_1628 = or(isJump, T_1617) + node T_1629 = not(T_1617) + node T_1630 = and(isJump, T_1629) + node T_1631 = mux(r_btb_update.bits.isJump, T_1628, T_1630) + isJump <= T_1631 + node T_1632 = shr(r_btb_update.bits.br_pc, 1) + brIdx[T_1615] <= T_1632 + node T_1633 = bits(idxPageUpdate, 0, 0) + node T_1635 = eq(T_1633, UInt<1>("h0")) + node T_1636 = mux(T_1635, idxPageReplEn, tgtPageReplEn) + node T_1637 = shr(r_btb_update.bits.pc, 12) + node T_1638 = shr(io.req.bits.addr, 12) + node T_1639 = mux(T_1635, T_1637, T_1638) + node T_1640 = bits(T_1636, 0, 0) + when T_1640 : + pages[0] <= T_1639 + node T_1641 = bits(T_1636, 2, 2) + when T_1641 : + pages[2] <= T_1639 + node T_1642 = bits(T_1636, 4, 4) + when T_1642 : + pages[4] <= T_1639 + node T_1643 = mux(T_1635, tgtPageReplEn, idxPageReplEn) + node T_1644 = shr(io.req.bits.addr, 12) + node T_1645 = shr(r_btb_update.bits.pc, 12) + node T_1646 = mux(T_1635, T_1644, T_1645) + node T_1647 = bits(T_1643, 1, 1) + when T_1647 : + pages[1] <= T_1646 + node T_1648 = bits(T_1643, 3, 3) + when T_1648 : + pages[3] <= T_1646 + node T_1649 = bits(T_1643, 5, 5) + when T_1649 : + pages[5] <= T_1646 + node T_1650 = or(pageValid, tgtPageReplEn) + node T_1651 = or(T_1650, idxPageReplEn) + pageValid <= T_1651 + node T_1653 = neq(hitsVec, UInt<1>("h0")) + io.resp.valid <= T_1653 + io.resp.bits.taken <= UInt<1>("h1") + node T_1655 = bits(hitsVec, 0, 0) + node T_1656 = bits(hitsVec, 1, 1) + node T_1657 = bits(hitsVec, 2, 2) + node T_1658 = bits(hitsVec, 3, 3) + node T_1659 = bits(hitsVec, 4, 4) + node T_1660 = bits(hitsVec, 5, 5) + node T_1661 = bits(hitsVec, 6, 6) + node T_1662 = bits(hitsVec, 7, 7) + node T_1663 = bits(hitsVec, 8, 8) + node T_1664 = bits(hitsVec, 9, 9) + node T_1665 = bits(hitsVec, 10, 10) + node T_1666 = bits(hitsVec, 11, 11) + node T_1667 = bits(hitsVec, 12, 12) + node T_1668 = bits(hitsVec, 13, 13) + node T_1669 = bits(hitsVec, 14, 14) + node T_1670 = bits(hitsVec, 15, 15) + node T_1671 = bits(hitsVec, 16, 16) + node T_1672 = bits(hitsVec, 17, 17) + node T_1673 = bits(hitsVec, 18, 18) + node T_1674 = bits(hitsVec, 19, 19) + node T_1675 = bits(hitsVec, 20, 20) + node T_1676 = bits(hitsVec, 21, 21) + node T_1677 = bits(hitsVec, 22, 22) + node T_1678 = bits(hitsVec, 23, 23) + node T_1679 = bits(hitsVec, 24, 24) + node T_1680 = bits(hitsVec, 25, 25) + node T_1681 = bits(hitsVec, 26, 26) + node T_1682 = bits(hitsVec, 27, 27) + node T_1683 = bits(hitsVec, 28, 28) + node T_1684 = bits(hitsVec, 29, 29) + node T_1685 = bits(hitsVec, 30, 30) + node T_1686 = bits(hitsVec, 31, 31) + node T_1687 = bits(hitsVec, 32, 32) + node T_1688 = bits(hitsVec, 33, 33) + node T_1689 = bits(hitsVec, 34, 34) + node T_1690 = bits(hitsVec, 35, 35) + node T_1691 = bits(hitsVec, 36, 36) + node T_1692 = bits(hitsVec, 37, 37) + node T_1693 = bits(hitsVec, 38, 38) + node T_1694 = bits(hitsVec, 39, 39) + node T_1696 = mux(T_1655, tgtPagesOH_0, UInt<1>("h0")) + node T_1698 = mux(T_1656, tgtPagesOH_1, UInt<1>("h0")) + node T_1700 = mux(T_1657, tgtPagesOH_2, UInt<1>("h0")) + node T_1702 = mux(T_1658, tgtPagesOH_3, UInt<1>("h0")) + node T_1704 = mux(T_1659, tgtPagesOH_4, UInt<1>("h0")) + node T_1706 = mux(T_1660, tgtPagesOH_5, UInt<1>("h0")) + node T_1708 = mux(T_1661, tgtPagesOH_6, UInt<1>("h0")) + node T_1710 = mux(T_1662, tgtPagesOH_7, UInt<1>("h0")) + node T_1712 = mux(T_1663, tgtPagesOH_8, UInt<1>("h0")) + node T_1714 = mux(T_1664, tgtPagesOH_9, UInt<1>("h0")) + node T_1716 = mux(T_1665, tgtPagesOH_10, UInt<1>("h0")) + node T_1718 = mux(T_1666, tgtPagesOH_11, UInt<1>("h0")) + node T_1720 = mux(T_1667, tgtPagesOH_12, UInt<1>("h0")) + node T_1722 = mux(T_1668, tgtPagesOH_13, UInt<1>("h0")) + node T_1724 = mux(T_1669, tgtPagesOH_14, UInt<1>("h0")) + node T_1726 = mux(T_1670, tgtPagesOH_15, UInt<1>("h0")) + node T_1728 = mux(T_1671, tgtPagesOH_16, UInt<1>("h0")) + node T_1730 = mux(T_1672, tgtPagesOH_17, UInt<1>("h0")) + node T_1732 = mux(T_1673, tgtPagesOH_18, UInt<1>("h0")) + node T_1734 = mux(T_1674, tgtPagesOH_19, UInt<1>("h0")) + node T_1736 = mux(T_1675, tgtPagesOH_20, UInt<1>("h0")) + node T_1738 = mux(T_1676, tgtPagesOH_21, UInt<1>("h0")) + node T_1740 = mux(T_1677, tgtPagesOH_22, UInt<1>("h0")) + node T_1742 = mux(T_1678, tgtPagesOH_23, UInt<1>("h0")) + node T_1744 = mux(T_1679, tgtPagesOH_24, UInt<1>("h0")) + node T_1746 = mux(T_1680, tgtPagesOH_25, UInt<1>("h0")) + node T_1748 = mux(T_1681, tgtPagesOH_26, UInt<1>("h0")) + node T_1750 = mux(T_1682, tgtPagesOH_27, UInt<1>("h0")) + node T_1752 = mux(T_1683, tgtPagesOH_28, UInt<1>("h0")) + node T_1754 = mux(T_1684, tgtPagesOH_29, UInt<1>("h0")) + node T_1756 = mux(T_1685, tgtPagesOH_30, UInt<1>("h0")) + node T_1758 = mux(T_1686, tgtPagesOH_31, UInt<1>("h0")) + node T_1760 = mux(T_1687, tgtPagesOH_32, UInt<1>("h0")) + node T_1762 = mux(T_1688, tgtPagesOH_33, UInt<1>("h0")) + node T_1764 = mux(T_1689, tgtPagesOH_34, UInt<1>("h0")) + node T_1766 = mux(T_1690, tgtPagesOH_35, UInt<1>("h0")) + node T_1768 = mux(T_1691, tgtPagesOH_36, UInt<1>("h0")) + node T_1770 = mux(T_1692, tgtPagesOH_37, UInt<1>("h0")) + node T_1772 = mux(T_1693, tgtPagesOH_38, UInt<1>("h0")) + node T_1774 = mux(T_1694, tgtPagesOH_39, UInt<1>("h0")) + node T_1776 = or(T_1696, T_1698) + node T_1777 = or(T_1776, T_1700) + node T_1778 = or(T_1777, T_1702) + node T_1779 = or(T_1778, T_1704) + node T_1780 = or(T_1779, T_1706) + node T_1781 = or(T_1780, T_1708) + node T_1782 = or(T_1781, T_1710) + node T_1783 = or(T_1782, T_1712) + node T_1784 = or(T_1783, T_1714) + node T_1785 = or(T_1784, T_1716) + node T_1786 = or(T_1785, T_1718) + node T_1787 = or(T_1786, T_1720) + node T_1788 = or(T_1787, T_1722) + node T_1789 = or(T_1788, T_1724) + node T_1790 = or(T_1789, T_1726) + node T_1791 = or(T_1790, T_1728) + node T_1792 = or(T_1791, T_1730) + node T_1793 = or(T_1792, T_1732) + node T_1794 = or(T_1793, T_1734) + node T_1795 = or(T_1794, T_1736) + node T_1796 = or(T_1795, T_1738) + node T_1797 = or(T_1796, T_1740) + node T_1798 = or(T_1797, T_1742) + node T_1799 = or(T_1798, T_1744) + node T_1800 = or(T_1799, T_1746) + node T_1801 = or(T_1800, T_1748) + node T_1802 = or(T_1801, T_1750) + node T_1803 = or(T_1802, T_1752) + node T_1804 = or(T_1803, T_1754) + node T_1805 = or(T_1804, T_1756) + node T_1806 = or(T_1805, T_1758) + node T_1807 = or(T_1806, T_1760) + node T_1808 = or(T_1807, T_1762) + node T_1809 = or(T_1808, T_1764) + node T_1810 = or(T_1809, T_1766) + node T_1811 = or(T_1810, T_1768) + node T_1812 = or(T_1811, T_1770) + node T_1813 = or(T_1812, T_1772) + node T_1814 = or(T_1813, T_1774) wire T_1815 : UInt<6> T_1815 is invalid - T_1815 <= T_1814 @[Mux.scala 18:72] - node T_1816 = bits(T_1815, 0, 0) @[Mux.scala 20:36] - node T_1817 = bits(T_1815, 1, 1) @[Mux.scala 20:36] - node T_1818 = bits(T_1815, 2, 2) @[Mux.scala 20:36] - node T_1819 = bits(T_1815, 3, 3) @[Mux.scala 20:36] - node T_1820 = bits(T_1815, 4, 4) @[Mux.scala 20:36] - node T_1821 = bits(T_1815, 5, 5) @[Mux.scala 20:36] - node T_1823 = mux(T_1816, pages[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1825 = mux(T_1817, pages[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1827 = mux(T_1818, pages[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1829 = mux(T_1819, pages[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1831 = mux(T_1820, pages[4], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1833 = mux(T_1821, pages[5], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1835 = or(T_1823, T_1825) @[Mux.scala 18:72] - node T_1836 = or(T_1835, T_1827) @[Mux.scala 18:72] - node T_1837 = or(T_1836, T_1829) @[Mux.scala 18:72] - node T_1838 = or(T_1837, T_1831) @[Mux.scala 18:72] - node T_1839 = or(T_1838, T_1833) @[Mux.scala 18:72] + T_1815 <= T_1814 + node T_1816 = bits(T_1815, 0, 0) + node T_1817 = bits(T_1815, 1, 1) + node T_1818 = bits(T_1815, 2, 2) + node T_1819 = bits(T_1815, 3, 3) + node T_1820 = bits(T_1815, 4, 4) + node T_1821 = bits(T_1815, 5, 5) + node T_1823 = mux(T_1816, pages[0], UInt<1>("h0")) + node T_1825 = mux(T_1817, pages[1], UInt<1>("h0")) + node T_1827 = mux(T_1818, pages[2], UInt<1>("h0")) + node T_1829 = mux(T_1819, pages[3], UInt<1>("h0")) + node T_1831 = mux(T_1820, pages[4], UInt<1>("h0")) + node T_1833 = mux(T_1821, pages[5], UInt<1>("h0")) + node T_1835 = or(T_1823, T_1825) + node T_1836 = or(T_1835, T_1827) + node T_1837 = or(T_1836, T_1829) + node T_1838 = or(T_1837, T_1831) + node T_1839 = or(T_1838, T_1833) wire T_1840 : UInt<27> T_1840 is invalid - T_1840 <= T_1839 @[Mux.scala 18:72] - node T_1841 = bits(hitsVec, 0, 0) @[Mux.scala 20:36] - node T_1842 = bits(hitsVec, 1, 1) @[Mux.scala 20:36] - node T_1843 = bits(hitsVec, 2, 2) @[Mux.scala 20:36] - node T_1844 = bits(hitsVec, 3, 3) @[Mux.scala 20:36] - node T_1845 = bits(hitsVec, 4, 4) @[Mux.scala 20:36] - node T_1846 = bits(hitsVec, 5, 5) @[Mux.scala 20:36] - node T_1847 = bits(hitsVec, 6, 6) @[Mux.scala 20:36] - node T_1848 = bits(hitsVec, 7, 7) @[Mux.scala 20:36] - node T_1849 = bits(hitsVec, 8, 8) @[Mux.scala 20:36] - node T_1850 = bits(hitsVec, 9, 9) @[Mux.scala 20:36] - node T_1851 = bits(hitsVec, 10, 10) @[Mux.scala 20:36] - node T_1852 = bits(hitsVec, 11, 11) @[Mux.scala 20:36] - node T_1853 = bits(hitsVec, 12, 12) @[Mux.scala 20:36] - node T_1854 = bits(hitsVec, 13, 13) @[Mux.scala 20:36] - node T_1855 = bits(hitsVec, 14, 14) @[Mux.scala 20:36] - node T_1856 = bits(hitsVec, 15, 15) @[Mux.scala 20:36] - node T_1857 = bits(hitsVec, 16, 16) @[Mux.scala 20:36] - node T_1858 = bits(hitsVec, 17, 17) @[Mux.scala 20:36] - node T_1859 = bits(hitsVec, 18, 18) @[Mux.scala 20:36] - node T_1860 = bits(hitsVec, 19, 19) @[Mux.scala 20:36] - node T_1861 = bits(hitsVec, 20, 20) @[Mux.scala 20:36] - node T_1862 = bits(hitsVec, 21, 21) @[Mux.scala 20:36] - node T_1863 = bits(hitsVec, 22, 22) @[Mux.scala 20:36] - node T_1864 = bits(hitsVec, 23, 23) @[Mux.scala 20:36] - node T_1865 = bits(hitsVec, 24, 24) @[Mux.scala 20:36] - node T_1866 = bits(hitsVec, 25, 25) @[Mux.scala 20:36] - node T_1867 = bits(hitsVec, 26, 26) @[Mux.scala 20:36] - node T_1868 = bits(hitsVec, 27, 27) @[Mux.scala 20:36] - node T_1869 = bits(hitsVec, 28, 28) @[Mux.scala 20:36] - node T_1870 = bits(hitsVec, 29, 29) @[Mux.scala 20:36] - node T_1871 = bits(hitsVec, 30, 30) @[Mux.scala 20:36] - node T_1872 = bits(hitsVec, 31, 31) @[Mux.scala 20:36] - node T_1873 = bits(hitsVec, 32, 32) @[Mux.scala 20:36] - node T_1874 = bits(hitsVec, 33, 33) @[Mux.scala 20:36] - node T_1875 = bits(hitsVec, 34, 34) @[Mux.scala 20:36] - node T_1876 = bits(hitsVec, 35, 35) @[Mux.scala 20:36] - node T_1877 = bits(hitsVec, 36, 36) @[Mux.scala 20:36] - node T_1878 = bits(hitsVec, 37, 37) @[Mux.scala 20:36] - node T_1879 = bits(hitsVec, 38, 38) @[Mux.scala 20:36] - node T_1880 = bits(hitsVec, 39, 39) @[Mux.scala 20:36] - node T_1882 = mux(T_1841, tgts[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1884 = mux(T_1842, tgts[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1886 = mux(T_1843, tgts[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1888 = mux(T_1844, tgts[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1890 = mux(T_1845, tgts[4], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1892 = mux(T_1846, tgts[5], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1894 = mux(T_1847, tgts[6], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1896 = mux(T_1848, tgts[7], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1898 = mux(T_1849, tgts[8], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1900 = mux(T_1850, tgts[9], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1902 = mux(T_1851, tgts[10], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1904 = mux(T_1852, tgts[11], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1906 = mux(T_1853, tgts[12], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1908 = mux(T_1854, tgts[13], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1910 = mux(T_1855, tgts[14], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1912 = mux(T_1856, tgts[15], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1914 = mux(T_1857, tgts[16], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1916 = mux(T_1858, tgts[17], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1918 = mux(T_1859, tgts[18], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1920 = mux(T_1860, tgts[19], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1922 = mux(T_1861, tgts[20], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1924 = mux(T_1862, tgts[21], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1926 = mux(T_1863, tgts[22], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1928 = mux(T_1864, tgts[23], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1930 = mux(T_1865, tgts[24], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1932 = mux(T_1866, tgts[25], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1934 = mux(T_1867, tgts[26], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1936 = mux(T_1868, tgts[27], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1938 = mux(T_1869, tgts[28], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1940 = mux(T_1870, tgts[29], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1942 = mux(T_1871, tgts[30], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1944 = mux(T_1872, tgts[31], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1946 = mux(T_1873, tgts[32], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1948 = mux(T_1874, tgts[33], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1950 = mux(T_1875, tgts[34], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1952 = mux(T_1876, tgts[35], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1954 = mux(T_1877, tgts[36], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1956 = mux(T_1878, tgts[37], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1958 = mux(T_1879, tgts[38], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1960 = mux(T_1880, tgts[39], UInt<1>("h00")) @[Mux.scala 18:72] - node T_1962 = or(T_1882, T_1884) @[Mux.scala 18:72] - node T_1963 = or(T_1962, T_1886) @[Mux.scala 18:72] - node T_1964 = or(T_1963, T_1888) @[Mux.scala 18:72] - node T_1965 = or(T_1964, T_1890) @[Mux.scala 18:72] - node T_1966 = or(T_1965, T_1892) @[Mux.scala 18:72] - node T_1967 = or(T_1966, T_1894) @[Mux.scala 18:72] - node T_1968 = or(T_1967, T_1896) @[Mux.scala 18:72] - node T_1969 = or(T_1968, T_1898) @[Mux.scala 18:72] - node T_1970 = or(T_1969, T_1900) @[Mux.scala 18:72] - node T_1971 = or(T_1970, T_1902) @[Mux.scala 18:72] - node T_1972 = or(T_1971, T_1904) @[Mux.scala 18:72] - node T_1973 = or(T_1972, T_1906) @[Mux.scala 18:72] - node T_1974 = or(T_1973, T_1908) @[Mux.scala 18:72] - node T_1975 = or(T_1974, T_1910) @[Mux.scala 18:72] - node T_1976 = or(T_1975, T_1912) @[Mux.scala 18:72] - node T_1977 = or(T_1976, T_1914) @[Mux.scala 18:72] - node T_1978 = or(T_1977, T_1916) @[Mux.scala 18:72] - node T_1979 = or(T_1978, T_1918) @[Mux.scala 18:72] - node T_1980 = or(T_1979, T_1920) @[Mux.scala 18:72] - node T_1981 = or(T_1980, T_1922) @[Mux.scala 18:72] - node T_1982 = or(T_1981, T_1924) @[Mux.scala 18:72] - node T_1983 = or(T_1982, T_1926) @[Mux.scala 18:72] - node T_1984 = or(T_1983, T_1928) @[Mux.scala 18:72] - node T_1985 = or(T_1984, T_1930) @[Mux.scala 18:72] - node T_1986 = or(T_1985, T_1932) @[Mux.scala 18:72] - node T_1987 = or(T_1986, T_1934) @[Mux.scala 18:72] - node T_1988 = or(T_1987, T_1936) @[Mux.scala 18:72] - node T_1989 = or(T_1988, T_1938) @[Mux.scala 18:72] - node T_1990 = or(T_1989, T_1940) @[Mux.scala 18:72] - node T_1991 = or(T_1990, T_1942) @[Mux.scala 18:72] - node T_1992 = or(T_1991, T_1944) @[Mux.scala 18:72] - node T_1993 = or(T_1992, T_1946) @[Mux.scala 18:72] - node T_1994 = or(T_1993, T_1948) @[Mux.scala 18:72] - node T_1995 = or(T_1994, T_1950) @[Mux.scala 18:72] - node T_1996 = or(T_1995, T_1952) @[Mux.scala 18:72] - node T_1997 = or(T_1996, T_1954) @[Mux.scala 18:72] - node T_1998 = or(T_1997, T_1956) @[Mux.scala 18:72] - node T_1999 = or(T_1998, T_1958) @[Mux.scala 18:72] - node T_2000 = or(T_1999, T_1960) @[Mux.scala 18:72] + T_1840 <= T_1839 + node T_1841 = bits(hitsVec, 0, 0) + node T_1842 = bits(hitsVec, 1, 1) + node T_1843 = bits(hitsVec, 2, 2) + node T_1844 = bits(hitsVec, 3, 3) + node T_1845 = bits(hitsVec, 4, 4) + node T_1846 = bits(hitsVec, 5, 5) + node T_1847 = bits(hitsVec, 6, 6) + node T_1848 = bits(hitsVec, 7, 7) + node T_1849 = bits(hitsVec, 8, 8) + node T_1850 = bits(hitsVec, 9, 9) + node T_1851 = bits(hitsVec, 10, 10) + node T_1852 = bits(hitsVec, 11, 11) + node T_1853 = bits(hitsVec, 12, 12) + node T_1854 = bits(hitsVec, 13, 13) + node T_1855 = bits(hitsVec, 14, 14) + node T_1856 = bits(hitsVec, 15, 15) + node T_1857 = bits(hitsVec, 16, 16) + node T_1858 = bits(hitsVec, 17, 17) + node T_1859 = bits(hitsVec, 18, 18) + node T_1860 = bits(hitsVec, 19, 19) + node T_1861 = bits(hitsVec, 20, 20) + node T_1862 = bits(hitsVec, 21, 21) + node T_1863 = bits(hitsVec, 22, 22) + node T_1864 = bits(hitsVec, 23, 23) + node T_1865 = bits(hitsVec, 24, 24) + node T_1866 = bits(hitsVec, 25, 25) + node T_1867 = bits(hitsVec, 26, 26) + node T_1868 = bits(hitsVec, 27, 27) + node T_1869 = bits(hitsVec, 28, 28) + node T_1870 = bits(hitsVec, 29, 29) + node T_1871 = bits(hitsVec, 30, 30) + node T_1872 = bits(hitsVec, 31, 31) + node T_1873 = bits(hitsVec, 32, 32) + node T_1874 = bits(hitsVec, 33, 33) + node T_1875 = bits(hitsVec, 34, 34) + node T_1876 = bits(hitsVec, 35, 35) + node T_1877 = bits(hitsVec, 36, 36) + node T_1878 = bits(hitsVec, 37, 37) + node T_1879 = bits(hitsVec, 38, 38) + node T_1880 = bits(hitsVec, 39, 39) + node T_1882 = mux(T_1841, tgts[0], UInt<1>("h0")) + node T_1884 = mux(T_1842, tgts[1], UInt<1>("h0")) + node T_1886 = mux(T_1843, tgts[2], UInt<1>("h0")) + node T_1888 = mux(T_1844, tgts[3], UInt<1>("h0")) + node T_1890 = mux(T_1845, tgts[4], UInt<1>("h0")) + node T_1892 = mux(T_1846, tgts[5], UInt<1>("h0")) + node T_1894 = mux(T_1847, tgts[6], UInt<1>("h0")) + node T_1896 = mux(T_1848, tgts[7], UInt<1>("h0")) + node T_1898 = mux(T_1849, tgts[8], UInt<1>("h0")) + node T_1900 = mux(T_1850, tgts[9], UInt<1>("h0")) + node T_1902 = mux(T_1851, tgts[10], UInt<1>("h0")) + node T_1904 = mux(T_1852, tgts[11], UInt<1>("h0")) + node T_1906 = mux(T_1853, tgts[12], UInt<1>("h0")) + node T_1908 = mux(T_1854, tgts[13], UInt<1>("h0")) + node T_1910 = mux(T_1855, tgts[14], UInt<1>("h0")) + node T_1912 = mux(T_1856, tgts[15], UInt<1>("h0")) + node T_1914 = mux(T_1857, tgts[16], UInt<1>("h0")) + node T_1916 = mux(T_1858, tgts[17], UInt<1>("h0")) + node T_1918 = mux(T_1859, tgts[18], UInt<1>("h0")) + node T_1920 = mux(T_1860, tgts[19], UInt<1>("h0")) + node T_1922 = mux(T_1861, tgts[20], UInt<1>("h0")) + node T_1924 = mux(T_1862, tgts[21], UInt<1>("h0")) + node T_1926 = mux(T_1863, tgts[22], UInt<1>("h0")) + node T_1928 = mux(T_1864, tgts[23], UInt<1>("h0")) + node T_1930 = mux(T_1865, tgts[24], UInt<1>("h0")) + node T_1932 = mux(T_1866, tgts[25], UInt<1>("h0")) + node T_1934 = mux(T_1867, tgts[26], UInt<1>("h0")) + node T_1936 = mux(T_1868, tgts[27], UInt<1>("h0")) + node T_1938 = mux(T_1869, tgts[28], UInt<1>("h0")) + node T_1940 = mux(T_1870, tgts[29], UInt<1>("h0")) + node T_1942 = mux(T_1871, tgts[30], UInt<1>("h0")) + node T_1944 = mux(T_1872, tgts[31], UInt<1>("h0")) + node T_1946 = mux(T_1873, tgts[32], UInt<1>("h0")) + node T_1948 = mux(T_1874, tgts[33], UInt<1>("h0")) + node T_1950 = mux(T_1875, tgts[34], UInt<1>("h0")) + node T_1952 = mux(T_1876, tgts[35], UInt<1>("h0")) + node T_1954 = mux(T_1877, tgts[36], UInt<1>("h0")) + node T_1956 = mux(T_1878, tgts[37], UInt<1>("h0")) + node T_1958 = mux(T_1879, tgts[38], UInt<1>("h0")) + node T_1960 = mux(T_1880, tgts[39], UInt<1>("h0")) + node T_1962 = or(T_1882, T_1884) + node T_1963 = or(T_1962, T_1886) + node T_1964 = or(T_1963, T_1888) + node T_1965 = or(T_1964, T_1890) + node T_1966 = or(T_1965, T_1892) + node T_1967 = or(T_1966, T_1894) + node T_1968 = or(T_1967, T_1896) + node T_1969 = or(T_1968, T_1898) + node T_1970 = or(T_1969, T_1900) + node T_1971 = or(T_1970, T_1902) + node T_1972 = or(T_1971, T_1904) + node T_1973 = or(T_1972, T_1906) + node T_1974 = or(T_1973, T_1908) + node T_1975 = or(T_1974, T_1910) + node T_1976 = or(T_1975, T_1912) + node T_1977 = or(T_1976, T_1914) + node T_1978 = or(T_1977, T_1916) + node T_1979 = or(T_1978, T_1918) + node T_1980 = or(T_1979, T_1920) + node T_1981 = or(T_1980, T_1922) + node T_1982 = or(T_1981, T_1924) + node T_1983 = or(T_1982, T_1926) + node T_1984 = or(T_1983, T_1928) + node T_1985 = or(T_1984, T_1930) + node T_1986 = or(T_1985, T_1932) + node T_1987 = or(T_1986, T_1934) + node T_1988 = or(T_1987, T_1936) + node T_1989 = or(T_1988, T_1938) + node T_1990 = or(T_1989, T_1940) + node T_1991 = or(T_1990, T_1942) + node T_1992 = or(T_1991, T_1944) + node T_1993 = or(T_1992, T_1946) + node T_1994 = or(T_1993, T_1948) + node T_1995 = or(T_1994, T_1950) + node T_1996 = or(T_1995, T_1952) + node T_1997 = or(T_1996, T_1954) + node T_1998 = or(T_1997, T_1956) + node T_1999 = or(T_1998, T_1958) + node T_2000 = or(T_1999, T_1960) wire T_2001 : UInt<11> T_2001 is invalid - T_2001 <= T_2000 @[Mux.scala 18:72] - node T_2002 = shl(T_2001, 1) @[btb.scala 245:93] - node T_2003 = cat(T_1840, T_2002) @[Cat.scala 20:58] - io.resp.bits.target <= T_2003 @[btb.scala 245:23] - node T_2004 = bits(hitsVec, 39, 32) @[OneHot.scala 22:18] - node T_2005 = bits(hitsVec, 31, 0) @[OneHot.scala 23:18] - node T_2007 = neq(T_2004, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2008 = or(T_2004, T_2005) @[OneHot.scala 24:28] - node T_2009 = bits(T_2008, 31, 16) @[OneHot.scala 22:18] - node T_2010 = bits(T_2008, 15, 0) @[OneHot.scala 23:18] - node T_2012 = neq(T_2009, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2013 = or(T_2009, T_2010) @[OneHot.scala 24:28] - node T_2014 = bits(T_2013, 15, 8) @[OneHot.scala 22:18] - node T_2015 = bits(T_2013, 7, 0) @[OneHot.scala 23:18] - node T_2017 = neq(T_2014, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2018 = or(T_2014, T_2015) @[OneHot.scala 24:28] - node T_2019 = bits(T_2018, 7, 4) @[OneHot.scala 22:18] - node T_2020 = bits(T_2018, 3, 0) @[OneHot.scala 23:18] - node T_2022 = neq(T_2019, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2023 = or(T_2019, T_2020) @[OneHot.scala 24:28] - node T_2024 = bits(T_2023, 3, 2) @[OneHot.scala 22:18] - node T_2025 = bits(T_2023, 1, 0) @[OneHot.scala 23:18] - node T_2027 = neq(T_2024, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2028 = or(T_2024, T_2025) @[OneHot.scala 24:28] - node T_2029 = bits(T_2028, 1, 1) @[CircuitMath.scala 21:8] - node T_2030 = cat(T_2027, T_2029) @[Cat.scala 20:58] - node T_2031 = cat(T_2022, T_2030) @[Cat.scala 20:58] - node T_2032 = cat(T_2017, T_2031) @[Cat.scala 20:58] - node T_2033 = cat(T_2012, T_2032) @[Cat.scala 20:58] - node T_2034 = cat(T_2007, T_2033) @[Cat.scala 20:58] - io.resp.bits.entry <= T_2034 @[btb.scala 246:22] - node T_2035 = bits(hitsVec, 0, 0) @[Mux.scala 20:36] - node T_2036 = bits(hitsVec, 1, 1) @[Mux.scala 20:36] - node T_2037 = bits(hitsVec, 2, 2) @[Mux.scala 20:36] - node T_2038 = bits(hitsVec, 3, 3) @[Mux.scala 20:36] - node T_2039 = bits(hitsVec, 4, 4) @[Mux.scala 20:36] - node T_2040 = bits(hitsVec, 5, 5) @[Mux.scala 20:36] - node T_2041 = bits(hitsVec, 6, 6) @[Mux.scala 20:36] - node T_2042 = bits(hitsVec, 7, 7) @[Mux.scala 20:36] - node T_2043 = bits(hitsVec, 8, 8) @[Mux.scala 20:36] - node T_2044 = bits(hitsVec, 9, 9) @[Mux.scala 20:36] - node T_2045 = bits(hitsVec, 10, 10) @[Mux.scala 20:36] - node T_2046 = bits(hitsVec, 11, 11) @[Mux.scala 20:36] - node T_2047 = bits(hitsVec, 12, 12) @[Mux.scala 20:36] - node T_2048 = bits(hitsVec, 13, 13) @[Mux.scala 20:36] - node T_2049 = bits(hitsVec, 14, 14) @[Mux.scala 20:36] - node T_2050 = bits(hitsVec, 15, 15) @[Mux.scala 20:36] - node T_2051 = bits(hitsVec, 16, 16) @[Mux.scala 20:36] - node T_2052 = bits(hitsVec, 17, 17) @[Mux.scala 20:36] - node T_2053 = bits(hitsVec, 18, 18) @[Mux.scala 20:36] - node T_2054 = bits(hitsVec, 19, 19) @[Mux.scala 20:36] - node T_2055 = bits(hitsVec, 20, 20) @[Mux.scala 20:36] - node T_2056 = bits(hitsVec, 21, 21) @[Mux.scala 20:36] - node T_2057 = bits(hitsVec, 22, 22) @[Mux.scala 20:36] - node T_2058 = bits(hitsVec, 23, 23) @[Mux.scala 20:36] - node T_2059 = bits(hitsVec, 24, 24) @[Mux.scala 20:36] - node T_2060 = bits(hitsVec, 25, 25) @[Mux.scala 20:36] - node T_2061 = bits(hitsVec, 26, 26) @[Mux.scala 20:36] - node T_2062 = bits(hitsVec, 27, 27) @[Mux.scala 20:36] - node T_2063 = bits(hitsVec, 28, 28) @[Mux.scala 20:36] - node T_2064 = bits(hitsVec, 29, 29) @[Mux.scala 20:36] - node T_2065 = bits(hitsVec, 30, 30) @[Mux.scala 20:36] - node T_2066 = bits(hitsVec, 31, 31) @[Mux.scala 20:36] - node T_2067 = bits(hitsVec, 32, 32) @[Mux.scala 20:36] - node T_2068 = bits(hitsVec, 33, 33) @[Mux.scala 20:36] - node T_2069 = bits(hitsVec, 34, 34) @[Mux.scala 20:36] - node T_2070 = bits(hitsVec, 35, 35) @[Mux.scala 20:36] - node T_2071 = bits(hitsVec, 36, 36) @[Mux.scala 20:36] - node T_2072 = bits(hitsVec, 37, 37) @[Mux.scala 20:36] - node T_2073 = bits(hitsVec, 38, 38) @[Mux.scala 20:36] - node T_2074 = bits(hitsVec, 39, 39) @[Mux.scala 20:36] - node T_2076 = mux(T_2035, brIdx[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2078 = mux(T_2036, brIdx[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2080 = mux(T_2037, brIdx[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2082 = mux(T_2038, brIdx[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2084 = mux(T_2039, brIdx[4], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2086 = mux(T_2040, brIdx[5], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2088 = mux(T_2041, brIdx[6], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2090 = mux(T_2042, brIdx[7], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2092 = mux(T_2043, brIdx[8], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2094 = mux(T_2044, brIdx[9], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2096 = mux(T_2045, brIdx[10], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2098 = mux(T_2046, brIdx[11], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2100 = mux(T_2047, brIdx[12], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2102 = mux(T_2048, brIdx[13], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2104 = mux(T_2049, brIdx[14], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2106 = mux(T_2050, brIdx[15], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2108 = mux(T_2051, brIdx[16], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2110 = mux(T_2052, brIdx[17], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2112 = mux(T_2053, brIdx[18], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2114 = mux(T_2054, brIdx[19], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2116 = mux(T_2055, brIdx[20], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2118 = mux(T_2056, brIdx[21], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2120 = mux(T_2057, brIdx[22], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2122 = mux(T_2058, brIdx[23], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2124 = mux(T_2059, brIdx[24], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2126 = mux(T_2060, brIdx[25], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2128 = mux(T_2061, brIdx[26], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2130 = mux(T_2062, brIdx[27], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2132 = mux(T_2063, brIdx[28], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2134 = mux(T_2064, brIdx[29], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2136 = mux(T_2065, brIdx[30], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2138 = mux(T_2066, brIdx[31], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2140 = mux(T_2067, brIdx[32], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2142 = mux(T_2068, brIdx[33], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2144 = mux(T_2069, brIdx[34], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2146 = mux(T_2070, brIdx[35], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2148 = mux(T_2071, brIdx[36], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2150 = mux(T_2072, brIdx[37], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2152 = mux(T_2073, brIdx[38], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2154 = mux(T_2074, brIdx[39], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2156 = or(T_2076, T_2078) @[Mux.scala 18:72] - node T_2157 = or(T_2156, T_2080) @[Mux.scala 18:72] - node T_2158 = or(T_2157, T_2082) @[Mux.scala 18:72] - node T_2159 = or(T_2158, T_2084) @[Mux.scala 18:72] - node T_2160 = or(T_2159, T_2086) @[Mux.scala 18:72] - node T_2161 = or(T_2160, T_2088) @[Mux.scala 18:72] - node T_2162 = or(T_2161, T_2090) @[Mux.scala 18:72] - node T_2163 = or(T_2162, T_2092) @[Mux.scala 18:72] - node T_2164 = or(T_2163, T_2094) @[Mux.scala 18:72] - node T_2165 = or(T_2164, T_2096) @[Mux.scala 18:72] - node T_2166 = or(T_2165, T_2098) @[Mux.scala 18:72] - node T_2167 = or(T_2166, T_2100) @[Mux.scala 18:72] - node T_2168 = or(T_2167, T_2102) @[Mux.scala 18:72] - node T_2169 = or(T_2168, T_2104) @[Mux.scala 18:72] - node T_2170 = or(T_2169, T_2106) @[Mux.scala 18:72] - node T_2171 = or(T_2170, T_2108) @[Mux.scala 18:72] - node T_2172 = or(T_2171, T_2110) @[Mux.scala 18:72] - node T_2173 = or(T_2172, T_2112) @[Mux.scala 18:72] - node T_2174 = or(T_2173, T_2114) @[Mux.scala 18:72] - node T_2175 = or(T_2174, T_2116) @[Mux.scala 18:72] - node T_2176 = or(T_2175, T_2118) @[Mux.scala 18:72] - node T_2177 = or(T_2176, T_2120) @[Mux.scala 18:72] - node T_2178 = or(T_2177, T_2122) @[Mux.scala 18:72] - node T_2179 = or(T_2178, T_2124) @[Mux.scala 18:72] - node T_2180 = or(T_2179, T_2126) @[Mux.scala 18:72] - node T_2181 = or(T_2180, T_2128) @[Mux.scala 18:72] - node T_2182 = or(T_2181, T_2130) @[Mux.scala 18:72] - node T_2183 = or(T_2182, T_2132) @[Mux.scala 18:72] - node T_2184 = or(T_2183, T_2134) @[Mux.scala 18:72] - node T_2185 = or(T_2184, T_2136) @[Mux.scala 18:72] - node T_2186 = or(T_2185, T_2138) @[Mux.scala 18:72] - node T_2187 = or(T_2186, T_2140) @[Mux.scala 18:72] - node T_2188 = or(T_2187, T_2142) @[Mux.scala 18:72] - node T_2189 = or(T_2188, T_2144) @[Mux.scala 18:72] - node T_2190 = or(T_2189, T_2146) @[Mux.scala 18:72] - node T_2191 = or(T_2190, T_2148) @[Mux.scala 18:72] - node T_2192 = or(T_2191, T_2150) @[Mux.scala 18:72] - node T_2193 = or(T_2192, T_2152) @[Mux.scala 18:72] - node T_2194 = or(T_2193, T_2154) @[Mux.scala 18:72] + T_2001 <= T_2000 + node T_2002 = shl(T_2001, 1) + node T_2003 = cat(T_1840, T_2002) + io.resp.bits.target <= T_2003 + node T_2004 = bits(hitsVec, 39, 32) + node T_2005 = bits(hitsVec, 31, 0) + node T_2007 = neq(T_2004, UInt<1>("h0")) + node T_2008 = or(T_2004, T_2005) + node T_2009 = bits(T_2008, 31, 16) + node T_2010 = bits(T_2008, 15, 0) + node T_2012 = neq(T_2009, UInt<1>("h0")) + node T_2013 = or(T_2009, T_2010) + node T_2014 = bits(T_2013, 15, 8) + node T_2015 = bits(T_2013, 7, 0) + node T_2017 = neq(T_2014, UInt<1>("h0")) + node T_2018 = or(T_2014, T_2015) + node T_2019 = bits(T_2018, 7, 4) + node T_2020 = bits(T_2018, 3, 0) + node T_2022 = neq(T_2019, UInt<1>("h0")) + node T_2023 = or(T_2019, T_2020) + node T_2024 = bits(T_2023, 3, 2) + node T_2025 = bits(T_2023, 1, 0) + node T_2027 = neq(T_2024, UInt<1>("h0")) + node T_2028 = or(T_2024, T_2025) + node T_2029 = bits(T_2028, 1, 1) + node T_2030 = cat(T_2027, T_2029) + node T_2031 = cat(T_2022, T_2030) + node T_2032 = cat(T_2017, T_2031) + node T_2033 = cat(T_2012, T_2032) + node T_2034 = cat(T_2007, T_2033) + io.resp.bits.entry <= T_2034 + node T_2035 = bits(hitsVec, 0, 0) + node T_2036 = bits(hitsVec, 1, 1) + node T_2037 = bits(hitsVec, 2, 2) + node T_2038 = bits(hitsVec, 3, 3) + node T_2039 = bits(hitsVec, 4, 4) + node T_2040 = bits(hitsVec, 5, 5) + node T_2041 = bits(hitsVec, 6, 6) + node T_2042 = bits(hitsVec, 7, 7) + node T_2043 = bits(hitsVec, 8, 8) + node T_2044 = bits(hitsVec, 9, 9) + node T_2045 = bits(hitsVec, 10, 10) + node T_2046 = bits(hitsVec, 11, 11) + node T_2047 = bits(hitsVec, 12, 12) + node T_2048 = bits(hitsVec, 13, 13) + node T_2049 = bits(hitsVec, 14, 14) + node T_2050 = bits(hitsVec, 15, 15) + node T_2051 = bits(hitsVec, 16, 16) + node T_2052 = bits(hitsVec, 17, 17) + node T_2053 = bits(hitsVec, 18, 18) + node T_2054 = bits(hitsVec, 19, 19) + node T_2055 = bits(hitsVec, 20, 20) + node T_2056 = bits(hitsVec, 21, 21) + node T_2057 = bits(hitsVec, 22, 22) + node T_2058 = bits(hitsVec, 23, 23) + node T_2059 = bits(hitsVec, 24, 24) + node T_2060 = bits(hitsVec, 25, 25) + node T_2061 = bits(hitsVec, 26, 26) + node T_2062 = bits(hitsVec, 27, 27) + node T_2063 = bits(hitsVec, 28, 28) + node T_2064 = bits(hitsVec, 29, 29) + node T_2065 = bits(hitsVec, 30, 30) + node T_2066 = bits(hitsVec, 31, 31) + node T_2067 = bits(hitsVec, 32, 32) + node T_2068 = bits(hitsVec, 33, 33) + node T_2069 = bits(hitsVec, 34, 34) + node T_2070 = bits(hitsVec, 35, 35) + node T_2071 = bits(hitsVec, 36, 36) + node T_2072 = bits(hitsVec, 37, 37) + node T_2073 = bits(hitsVec, 38, 38) + node T_2074 = bits(hitsVec, 39, 39) + node T_2076 = mux(T_2035, brIdx[0], UInt<1>("h0")) + node T_2078 = mux(T_2036, brIdx[1], UInt<1>("h0")) + node T_2080 = mux(T_2037, brIdx[2], UInt<1>("h0")) + node T_2082 = mux(T_2038, brIdx[3], UInt<1>("h0")) + node T_2084 = mux(T_2039, brIdx[4], UInt<1>("h0")) + node T_2086 = mux(T_2040, brIdx[5], UInt<1>("h0")) + node T_2088 = mux(T_2041, brIdx[6], UInt<1>("h0")) + node T_2090 = mux(T_2042, brIdx[7], UInt<1>("h0")) + node T_2092 = mux(T_2043, brIdx[8], UInt<1>("h0")) + node T_2094 = mux(T_2044, brIdx[9], UInt<1>("h0")) + node T_2096 = mux(T_2045, brIdx[10], UInt<1>("h0")) + node T_2098 = mux(T_2046, brIdx[11], UInt<1>("h0")) + node T_2100 = mux(T_2047, brIdx[12], UInt<1>("h0")) + node T_2102 = mux(T_2048, brIdx[13], UInt<1>("h0")) + node T_2104 = mux(T_2049, brIdx[14], UInt<1>("h0")) + node T_2106 = mux(T_2050, brIdx[15], UInt<1>("h0")) + node T_2108 = mux(T_2051, brIdx[16], UInt<1>("h0")) + node T_2110 = mux(T_2052, brIdx[17], UInt<1>("h0")) + node T_2112 = mux(T_2053, brIdx[18], UInt<1>("h0")) + node T_2114 = mux(T_2054, brIdx[19], UInt<1>("h0")) + node T_2116 = mux(T_2055, brIdx[20], UInt<1>("h0")) + node T_2118 = mux(T_2056, brIdx[21], UInt<1>("h0")) + node T_2120 = mux(T_2057, brIdx[22], UInt<1>("h0")) + node T_2122 = mux(T_2058, brIdx[23], UInt<1>("h0")) + node T_2124 = mux(T_2059, brIdx[24], UInt<1>("h0")) + node T_2126 = mux(T_2060, brIdx[25], UInt<1>("h0")) + node T_2128 = mux(T_2061, brIdx[26], UInt<1>("h0")) + node T_2130 = mux(T_2062, brIdx[27], UInt<1>("h0")) + node T_2132 = mux(T_2063, brIdx[28], UInt<1>("h0")) + node T_2134 = mux(T_2064, brIdx[29], UInt<1>("h0")) + node T_2136 = mux(T_2065, brIdx[30], UInt<1>("h0")) + node T_2138 = mux(T_2066, brIdx[31], UInt<1>("h0")) + node T_2140 = mux(T_2067, brIdx[32], UInt<1>("h0")) + node T_2142 = mux(T_2068, brIdx[33], UInt<1>("h0")) + node T_2144 = mux(T_2069, brIdx[34], UInt<1>("h0")) + node T_2146 = mux(T_2070, brIdx[35], UInt<1>("h0")) + node T_2148 = mux(T_2071, brIdx[36], UInt<1>("h0")) + node T_2150 = mux(T_2072, brIdx[37], UInt<1>("h0")) + node T_2152 = mux(T_2073, brIdx[38], UInt<1>("h0")) + node T_2154 = mux(T_2074, brIdx[39], UInt<1>("h0")) + node T_2156 = or(T_2076, T_2078) + node T_2157 = or(T_2156, T_2080) + node T_2158 = or(T_2157, T_2082) + node T_2159 = or(T_2158, T_2084) + node T_2160 = or(T_2159, T_2086) + node T_2161 = or(T_2160, T_2088) + node T_2162 = or(T_2161, T_2090) + node T_2163 = or(T_2162, T_2092) + node T_2164 = or(T_2163, T_2094) + node T_2165 = or(T_2164, T_2096) + node T_2166 = or(T_2165, T_2098) + node T_2167 = or(T_2166, T_2100) + node T_2168 = or(T_2167, T_2102) + node T_2169 = or(T_2168, T_2104) + node T_2170 = or(T_2169, T_2106) + node T_2171 = or(T_2170, T_2108) + node T_2172 = or(T_2171, T_2110) + node T_2173 = or(T_2172, T_2112) + node T_2174 = or(T_2173, T_2114) + node T_2175 = or(T_2174, T_2116) + node T_2176 = or(T_2175, T_2118) + node T_2177 = or(T_2176, T_2120) + node T_2178 = or(T_2177, T_2122) + node T_2179 = or(T_2178, T_2124) + node T_2180 = or(T_2179, T_2126) + node T_2181 = or(T_2180, T_2128) + node T_2182 = or(T_2181, T_2130) + node T_2183 = or(T_2182, T_2132) + node T_2184 = or(T_2183, T_2134) + node T_2185 = or(T_2184, T_2136) + node T_2186 = or(T_2185, T_2138) + node T_2187 = or(T_2186, T_2140) + node T_2188 = or(T_2187, T_2142) + node T_2189 = or(T_2188, T_2144) + node T_2190 = or(T_2189, T_2146) + node T_2191 = or(T_2190, T_2148) + node T_2192 = or(T_2191, T_2150) + node T_2193 = or(T_2192, T_2152) + node T_2194 = or(T_2193, T_2154) wire T_2195 : UInt<1> T_2195 is invalid - T_2195 <= T_2194 @[Mux.scala 18:72] - io.resp.bits.bridx <= T_2195 @[btb.scala 247:22] - node T_2197 = not(io.resp.bits.bridx) @[btb.scala 248:65] - node T_2199 = mux(io.resp.bits.taken, T_2197, UInt<1>("h00")) @[btb.scala 248:44] - node T_2200 = not(T_2199) @[btb.scala 248:40] - node T_2201 = dshl(UInt<1>("h01"), T_2200) @[btb.scala 248:37] - node T_2203 = sub(T_2201, UInt<1>("h01")) @[btb.scala 248:95] - node T_2204 = tail(T_2203, 1) @[btb.scala 248:95] - node T_2206 = cat(T_2204, UInt<1>("h01")) @[Cat.scala 20:58] - io.resp.bits.mask <= T_2206 @[btb.scala 248:21] - cmem T_2209 : UInt<2>[128] @[btb.scala 84:26] - reg T_2211 : UInt<7>, clk - node T_2212 = and(hitsVec, isJump) @[btb.scala 252:27] - node T_2214 = neq(T_2212, UInt<1>("h00")) @[btb.scala 252:37] - node T_2216 = eq(T_2214, UInt<1>("h00")) @[btb.scala 252:20] - node T_2217 = and(io.req.valid, io.resp.valid) @[btb.scala 253:54] - node T_2218 = and(T_2217, T_2216) @[btb.scala 253:71] - wire T_2222 : {history : UInt<7>, value : UInt<2>} @[btb.scala 70:19] - T_2222 is invalid @[btb.scala 70:19] - node T_2225 = bits(io.req.bits.addr, 8, 1) @[btb.scala 71:21] - node T_2226 = xor(T_2225, T_2211) @[btb.scala 71:57] + T_2195 <= T_2194 + io.resp.bits.bridx <= T_2195 + node T_2197 = not(io.resp.bits.bridx) + node T_2199 = mux(io.resp.bits.taken, T_2197, UInt<1>("h0")) + node T_2200 = not(T_2199) + node T_2201 = dshl(UInt<1>("h1"), T_2200) + node T_2203 = sub(T_2201, UInt<1>("h1")) + node T_2204 = tail(T_2203, 1) + node T_2206 = cat(T_2204, UInt<1>("h1")) + io.resp.bits.mask <= T_2206 + cmem T_2209 : UInt<2> [128] + reg T_2211 : UInt<7>, clk with : + reset => (UInt<1>("h0"), T_2211) + node T_2212 = and(hitsVec, isJump) + node T_2214 = neq(T_2212, UInt<1>("h0")) + node T_2216 = eq(T_2214, UInt<1>("h0")) + node T_2217 = and(io.req.valid, io.resp.valid) + node T_2218 = and(T_2217, T_2216) + wire T_2222 : { history : UInt<7>, value : UInt<2>} + T_2222 is invalid + node T_2225 = bits(io.req.bits.addr, 8, 1) + node T_2226 = xor(T_2225, T_2211) infer mport T_2227 = T_2209[T_2226], clk - T_2222.value <= T_2227 @[btb.scala 72:15] - T_2222.history <= T_2211 @[btb.scala 73:17] - node T_2228 = bits(T_2222.value, 0, 0) @[btb.scala 74:26] - when T_2218 : @[btb.scala 75:19] - node T_2229 = bits(T_2211, 6, 1) @[btb.scala 75:50] - node T_2230 = cat(T_2228, T_2229) @[Cat.scala 20:58] - T_2211 <= T_2230 @[btb.scala 75:29] - skip @[btb.scala 75:19] - node T_2231 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) @[btb.scala 255:31] - when T_2231 : @[btb.scala 255:50] - node T_2232 = bits(io.bht_update.bits.pc, 8, 1) @[btb.scala 79:21] - node T_2233 = xor(T_2232, io.bht_update.bits.prediction.bits.bht.history) @[btb.scala 79:57] + T_2222.value <= T_2227 + T_2222.history <= T_2211 + node T_2228 = bits(T_2222.value, 0, 0) + when T_2218 : + node T_2229 = bits(T_2211, 6, 1) + node T_2230 = cat(T_2228, T_2229) + T_2211 <= T_2230 + node T_2231 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) + when T_2231 : + node T_2232 = bits(io.bht_update.bits.pc, 8, 1) + node T_2233 = xor(T_2232, io.bht_update.bits.prediction.bits.bht.history) infer mport T_2234 = T_2209[T_2233], clk - node T_2235 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) @[btb.scala 80:40] - node T_2236 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) @[btb.scala 80:53] - node T_2237 = and(T_2235, T_2236) @[btb.scala 80:44] - node T_2238 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) @[btb.scala 80:69] - node T_2239 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) @[btb.scala 80:82] - node T_2240 = or(T_2238, T_2239) @[btb.scala 80:73] - node T_2241 = and(T_2240, io.bht_update.bits.taken) @[btb.scala 80:87] - node T_2242 = or(T_2237, T_2241) @[btb.scala 80:58] - node T_2243 = cat(io.bht_update.bits.taken, T_2242) @[Cat.scala 20:58] - T_2234 <= T_2243 @[btb.scala 80:18] - when io.bht_update.bits.mispredict : @[btb.scala 81:23] - node T_2244 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) @[btb.scala 81:56] - node T_2245 = cat(io.bht_update.bits.taken, T_2244) @[Cat.scala 20:58] - T_2211 <= T_2245 @[btb.scala 81:33] - skip @[btb.scala 81:23] - skip @[btb.scala 255:50] - node T_2246 = bits(T_2222.value, 0, 0) @[btb.scala 258:21] - node T_2248 = eq(T_2246, UInt<1>("h00")) @[btb.scala 258:11] - node T_2249 = and(T_2248, T_2216) @[btb.scala 258:25] - when T_2249 : @[btb.scala 258:38] - io.resp.bits.taken <= UInt<1>("h00") @[btb.scala 258:59] - skip @[btb.scala 258:38] - io.resp.bits.bht <- T_2222 @[btb.scala 259:22] - reg T_2252 : UInt<2>, clk - reg T_2254 : UInt<1>, clk - reg T_2261 : UInt[2], clk - node T_2263 = and(hitsVec, isReturn) @[btb.scala 264:24] - node T_2265 = neq(T_2263, UInt<1>("h00")) @[btb.scala 264:36] - node T_2267 = eq(T_2252, UInt<1>("h00")) @[btb.scala 46:29] - node T_2269 = eq(T_2267, UInt<1>("h00")) @[btb.scala 265:11] - node T_2270 = and(T_2269, T_2265) @[btb.scala 265:24] - when T_2270 : @[btb.scala 265:35] - io.resp.bits.target <= T_2261[T_2254] @[btb.scala 266:27] - skip @[btb.scala 265:35] - when io.ras_update.valid : @[btb.scala 268:32] - when io.ras_update.bits.isCall : @[btb.scala 269:40] - node T_2272 = lt(T_2252, UInt<2>("h02")) @[btb.scala 35:17] - when T_2272 : @[btb.scala 35:25] - node T_2274 = add(T_2252, UInt<1>("h01")) @[btb.scala 35:42] - node T_2275 = tail(T_2274, 1) @[btb.scala 35:42] - T_2252 <= T_2275 @[btb.scala 35:33] - skip @[btb.scala 35:25] - node T_2278 = lt(T_2254, UInt<1>("h01")) @[btb.scala 36:49] - node T_2279 = or(UInt<1>("h01"), T_2278) @[btb.scala 36:42] - node T_2281 = add(T_2254, UInt<1>("h01")) @[btb.scala 36:62] - node T_2282 = tail(T_2281, 1) @[btb.scala 36:62] - node T_2284 = mux(T_2279, T_2282, UInt<1>("h00")) @[btb.scala 36:22] - T_2261[T_2284] <= io.ras_update.bits.returnAddr @[btb.scala 37:20] - T_2254 <= T_2284 @[btb.scala 38:9] - when T_2265 : @[btb.scala 271:23] - io.resp.bits.target <= io.ras_update.bits.returnAddr @[btb.scala 272:31] - skip @[btb.scala 271:23] - skip @[btb.scala 269:40] - node T_2285 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) @[btb.scala 274:47] - node T_2287 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) @[btb.scala 269:40] - node T_2288 = and(T_2287, T_2285) @[btb.scala 274:87] - when T_2288 : @[btb.scala 274:87] - node T_2290 = eq(T_2252, UInt<1>("h00")) @[btb.scala 46:29] - node T_2292 = eq(T_2290, UInt<1>("h00")) @[btb.scala 41:27] - when T_2292 : @[btb.scala 41:37] - node T_2294 = sub(T_2252, UInt<1>("h01")) @[btb.scala 42:20] - node T_2295 = tail(T_2294, 1) @[btb.scala 42:20] - T_2252 <= T_2295 @[btb.scala 42:11] - node T_2298 = gt(T_2254, UInt<1>("h00")) @[btb.scala 43:42] - node T_2299 = or(UInt<1>("h01"), T_2298) @[btb.scala 43:35] - node T_2301 = sub(T_2254, UInt<1>("h01")) @[btb.scala 43:50] - node T_2302 = tail(T_2301, 1) @[btb.scala 43:50] - node T_2304 = mux(T_2299, T_2302, UInt<1>("h01")) @[btb.scala 43:15] - T_2254 <= T_2304 @[btb.scala 43:9] - skip @[btb.scala 41:37] - skip @[btb.scala 274:87] - skip @[btb.scala 268:32] - - module Frontend : + node T_2235 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) + node T_2236 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) + node T_2237 = and(T_2235, T_2236) + node T_2238 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) + node T_2239 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) + node T_2240 = or(T_2238, T_2239) + node T_2241 = and(T_2240, io.bht_update.bits.taken) + node T_2242 = or(T_2237, T_2241) + node T_2243 = cat(io.bht_update.bits.taken, T_2242) + T_2234 <= T_2243 + when io.bht_update.bits.mispredict : + node T_2244 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) + node T_2245 = cat(io.bht_update.bits.taken, T_2244) + T_2211 <= T_2245 + node T_2246 = bits(T_2222.value, 0, 0) + node T_2248 = eq(T_2246, UInt<1>("h0")) + node T_2249 = and(T_2248, T_2216) + when T_2249 : + io.resp.bits.taken <= UInt<1>("h0") + io.resp.bits.bht <- T_2222 + reg T_2252 : UInt<2>, clk with : + reset => (UInt<1>("h0"), T_2252) + reg T_2254 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_2254) + reg T_2261 : UInt[2], clk with : + reset => (UInt<1>("h0"), T_2261) + node T_2263 = and(hitsVec, isReturn) + node T_2265 = neq(T_2263, UInt<1>("h0")) + node T_2267 = eq(T_2252, UInt<1>("h0")) + node T_2269 = eq(T_2267, UInt<1>("h0")) + node T_2270 = and(T_2269, T_2265) + when T_2270 : + io.resp.bits.target <= T_2261[T_2254] + when io.ras_update.valid : + when io.ras_update.bits.isCall : + node T_2272 = lt(T_2252, UInt<2>("h2")) + when T_2272 : + node T_2274 = add(T_2252, UInt<1>("h1")) + node T_2275 = tail(T_2274, 1) + T_2252 <= T_2275 + node T_2278 = lt(T_2254, UInt<1>("h1")) + node T_2279 = or(UInt<1>("h1"), T_2278) + node T_2281 = add(T_2254, UInt<1>("h1")) + node T_2282 = tail(T_2281, 1) + node T_2284 = mux(T_2279, T_2282, UInt<1>("h0")) + T_2261[T_2284] <= io.ras_update.bits.returnAddr + T_2254 <= T_2284 + when T_2265 : + io.resp.bits.target <= io.ras_update.bits.returnAddr + node T_2285 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) + node T_2287 = eq(io.ras_update.bits.isCall, UInt<1>("h0")) + node T_2288 = and(T_2287, T_2285) + when T_2288 : + node T_2290 = eq(T_2252, UInt<1>("h0")) + node T_2292 = eq(T_2290, UInt<1>("h0")) + when T_2292 : + node T_2294 = sub(T_2252, UInt<1>("h1")) + node T_2295 = tail(T_2294, 1) + T_2252 <= T_2295 + node T_2298 = gt(T_2254, UInt<1>("h0")) + node T_2299 = or(UInt<1>("h1"), T_2298) + node T_2301 = sub(T_2254, UInt<1>("h1")) + node T_2302 = tail(T_2301, 1) + node T_2304 = mux(T_2299, T_2302, UInt<1>("h1")) + T_2254 <= T_2304 + + module Frontend : input clk : Clock input reset : UInt<1> - output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip cpu : { req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : { valid : UInt<1>, bits : { prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : { valid : UInt<1>, bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, mem : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - inst icache of ICache @[frontend.scala 40:22] + inst icache of ICache icache.io is invalid icache.clk <= clk icache.reset <= reset - inst tlb of TLB @[frontend.scala 41:19] + inst tlb of TLB tlb.io is invalid tlb.clk <= clk tlb.reset <= reset - reg s1_pc_ : UInt<40>, clk - node T_1485 = not(s1_pc_) @[frontend.scala 44:17] - node T_1487 = or(T_1485, UInt<1>("h01")) @[frontend.scala 44:25] - node s1_pc = not(T_1487) @[frontend.scala 44:15] - reg s1_speculative : UInt<1>, clk - reg s1_same_block : UInt<1>, clk - reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - reg s2_pc : UInt, clk with : (reset => (reset, UInt<13>("h01000"))) - reg s2_btb_resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk - reg s2_xcpt_if : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s2_speculative : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg s2_cacheable : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1513 = not(s1_pc) @[frontend.scala 55:16] - node T_1515 = or(T_1513, UInt<2>("h03")) @[frontend.scala 55:23] - node T_1516 = not(T_1515) @[frontend.scala 55:14] - node T_1518 = add(T_1516, UInt<3>("h04")) @[frontend.scala 55:55] - node ntpc = tail(T_1518, 1) @[frontend.scala 55:55] - node T_1520 = and(ntpc, UInt<4>("h08")) @[frontend.scala 56:31] - node T_1522 = and(s1_pc, UInt<4>("h08")) @[frontend.scala 56:54] - node ntpc_same_block = eq(T_1520, T_1522) @[frontend.scala 56:43] + reg s1_pc_ : UInt<40>, clk with : + reset => (UInt<1>("h0"), s1_pc_) + node T_1485 = not(s1_pc_) + node T_1487 = or(T_1485, UInt<1>("h1")) + node s1_pc = not(T_1487) + reg s1_speculative : UInt<1>, clk with : + reset => (UInt<1>("h0"), s1_speculative) + reg s1_same_block : UInt<1>, clk with : + reset => (UInt<1>("h0"), s1_same_block) + reg s2_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h1")) + reg s2_pc : UInt, clk with : + reset => (reset, UInt<13>("h1000")) + reg s2_btb_resp_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg s2_btb_resp_bits : { taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<7>, value : UInt<2>}}, clk with : + reset => (UInt<1>("h0"), s2_btb_resp_bits) + reg s2_xcpt_if : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg s2_speculative : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg s2_cacheable : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_1513 = not(s1_pc) + node T_1515 = or(T_1513, UInt<2>("h3")) + node T_1516 = not(T_1515) + node T_1518 = add(T_1516, UInt<3>("h4")) + node ntpc = tail(T_1518, 1) + node T_1520 = and(ntpc, UInt<4>("h8")) + node T_1522 = and(s1_pc, UInt<4>("h8")) + node ntpc_same_block = eq(T_1520, T_1522) wire predicted_npc : UInt predicted_npc is invalid predicted_npc <= ntpc wire predicted_taken : UInt<1> predicted_taken is invalid - predicted_taken <= UInt<1>("h00") - node T_1525 = eq(icache.io.resp.valid, UInt<1>("h00")) @[frontend.scala 59:28] - node icmiss = and(s2_valid, T_1525) @[frontend.scala 59:25] - node npc = mux(icmiss, s2_pc, predicted_npc) @[frontend.scala 60:16] - node T_1527 = eq(predicted_taken, UInt<1>("h00")) @[frontend.scala 61:23] - node T_1529 = eq(icmiss, UInt<1>("h00")) @[frontend.scala 61:43] - node T_1530 = and(T_1527, T_1529) @[frontend.scala 61:40] - node T_1532 = eq(io.cpu.req.valid, UInt<1>("h00")) @[frontend.scala 61:54] - node T_1533 = and(T_1530, T_1532) @[frontend.scala 61:51] - node s0_same_block = and(T_1533, ntpc_same_block) @[frontend.scala 61:72] - node T_1535 = eq(io.cpu.resp.ready, UInt<1>("h00")) @[frontend.scala 63:36] - node stall = and(io.cpu.resp.valid, T_1535) @[frontend.scala 63:33] - node T_1537 = eq(stall, UInt<1>("h00")) @[frontend.scala 64:9] - when T_1537 : @[frontend.scala 64:17] - node T_1539 = eq(tlb.io.resp.miss, UInt<1>("h00")) @[frontend.scala 65:39] - node T_1540 = and(s0_same_block, T_1539) @[frontend.scala 65:36] - s1_same_block <= T_1540 @[frontend.scala 65:19] - s1_pc_ <= io.cpu.npc @[frontend.scala 66:12] - node T_1542 = eq(s2_speculative, UInt<1>("h00")) @[frontend.scala 70:58] - node T_1543 = and(s2_valid, T_1542) @[frontend.scala 70:55] - node T_1544 = or(s1_speculative, T_1543) @[frontend.scala 70:43] - node T_1545 = or(T_1544, predicted_taken) @[frontend.scala 70:74] - node T_1546 = mux(icmiss, s2_speculative, T_1545) @[frontend.scala 72:26] - s1_speculative <= T_1546 @[frontend.scala 72:20] - node T_1548 = eq(icmiss, UInt<1>("h00")) @[frontend.scala 73:17] - s2_valid <= T_1548 @[frontend.scala 73:14] - node T_1550 = eq(icmiss, UInt<1>("h00")) @[frontend.scala 74:11] - when T_1550 : @[frontend.scala 74:20] - s2_pc <= s1_pc @[frontend.scala 75:13] - s2_speculative <= s1_speculative @[frontend.scala 76:22] - s2_cacheable <= tlb.io.resp.cacheable @[frontend.scala 77:20] - s2_xcpt_if <= tlb.io.resp.xcpt_if @[frontend.scala 78:18] - skip @[frontend.scala 74:20] - skip @[frontend.scala 64:17] - when io.cpu.req.valid : @[frontend.scala 81:27] - s1_same_block <= UInt<1>("h00") @[frontend.scala 82:19] - s1_pc_ <= io.cpu.npc @[frontend.scala 83:12] - s1_speculative <= io.cpu.req.bits.speculative @[frontend.scala 84:20] - s2_valid <= UInt<1>("h00") @[frontend.scala 85:14] - skip @[frontend.scala 81:27] - inst BTB_1 of BTB @[frontend.scala 89:21] + predicted_taken <= UInt<1>("h0") + node T_1525 = eq(icache.io.resp.valid, UInt<1>("h0")) + node icmiss = and(s2_valid, T_1525) + node npc = mux(icmiss, s2_pc, predicted_npc) + node T_1527 = eq(predicted_taken, UInt<1>("h0")) + node T_1529 = eq(icmiss, UInt<1>("h0")) + node T_1530 = and(T_1527, T_1529) + node T_1532 = eq(io.cpu.req.valid, UInt<1>("h0")) + node T_1533 = and(T_1530, T_1532) + node s0_same_block = and(T_1533, ntpc_same_block) + node T_1535 = eq(io.cpu.resp.ready, UInt<1>("h0")) + node stall = and(io.cpu.resp.valid, T_1535) + node T_1537 = eq(stall, UInt<1>("h0")) + when T_1537 : + node T_1539 = eq(tlb.io.resp.miss, UInt<1>("h0")) + node T_1540 = and(s0_same_block, T_1539) + s1_same_block <= T_1540 + s1_pc_ <= io.cpu.npc + node T_1542 = eq(s2_speculative, UInt<1>("h0")) + node T_1543 = and(s2_valid, T_1542) + node T_1544 = or(s1_speculative, T_1543) + node T_1545 = or(T_1544, predicted_taken) + node T_1546 = mux(icmiss, s2_speculative, T_1545) + s1_speculative <= T_1546 + node T_1548 = eq(icmiss, UInt<1>("h0")) + s2_valid <= T_1548 + node T_1550 = eq(icmiss, UInt<1>("h0")) + when T_1550 : + s2_pc <= s1_pc + s2_speculative <= s1_speculative + s2_cacheable <= tlb.io.resp.cacheable + s2_xcpt_if <= tlb.io.resp.xcpt_if + when io.cpu.req.valid : + s1_same_block <= UInt<1>("h0") + s1_pc_ <= io.cpu.npc + s1_speculative <= io.cpu.req.bits.speculative + s2_valid <= UInt<1>("h0") + inst BTB_1 of BTB BTB_1.io is invalid BTB_1.clk <= clk BTB_1.reset <= reset - BTB_1.io.req.valid <= UInt<1>("h00") @[frontend.scala 90:22] - BTB_1.io.req.bits.addr <= s1_pc_ @[frontend.scala 91:26] - BTB_1.io.btb_update <- io.cpu.btb_update @[frontend.scala 92:23] - BTB_1.io.bht_update <- io.cpu.bht_update @[frontend.scala 93:23] - BTB_1.io.ras_update <- io.cpu.ras_update @[frontend.scala 94:23] - node T_1555 = eq(stall, UInt<1>("h00")) @[frontend.scala 95:11] - node T_1557 = eq(icmiss, UInt<1>("h00")) @[frontend.scala 95:21] - node T_1558 = and(T_1555, T_1557) @[frontend.scala 95:18] - when T_1558 : @[frontend.scala 95:30] - BTB_1.io.req.valid <= UInt<1>("h01") @[frontend.scala 96:24] - s2_btb_resp_valid <= BTB_1.io.resp.valid @[frontend.scala 97:25] - s2_btb_resp_bits <- BTB_1.io.resp.bits @[frontend.scala 98:24] - skip @[frontend.scala 95:30] - node T_1560 = and(BTB_1.io.resp.valid, BTB_1.io.resp.bits.taken) @[frontend.scala 100:29] - when T_1560 : @[frontend.scala 100:56] - node T_1561 = bits(BTB_1.io.resp.bits.target, 38, 38) @[util.scala 21:38] - node T_1562 = cat(T_1561, BTB_1.io.resp.bits.target) @[Cat.scala 20:58] - predicted_npc <= T_1562 @[frontend.scala 101:21] - predicted_taken <= UInt<1>("h01") @[frontend.scala 102:23] - skip @[frontend.scala 100:56] - io.ptw <- tlb.io.ptw @[frontend.scala 106:10] - node T_1565 = eq(stall, UInt<1>("h00")) @[frontend.scala 107:23] - node T_1567 = eq(icmiss, UInt<1>("h00")) @[frontend.scala 107:33] - node T_1568 = and(T_1565, T_1567) @[frontend.scala 107:30] - tlb.io.req.valid <= T_1568 @[frontend.scala 107:20] - node T_1569 = shr(s1_pc, 12) @[frontend.scala 108:32] - tlb.io.req.bits.vpn <= T_1569 @[frontend.scala 108:23] - tlb.io.req.bits.passthrough <= UInt<1>("h00") @[frontend.scala 109:31] - tlb.io.req.bits.instruction <= UInt<1>("h01") @[frontend.scala 110:31] - tlb.io.req.bits.store <= UInt<1>("h00") @[frontend.scala 111:25] - io.mem <- icache.io.mem @[frontend.scala 113:10] - node T_1574 = eq(stall, UInt<1>("h00")) @[frontend.scala 114:26] - node T_1576 = eq(s0_same_block, UInt<1>("h00")) @[frontend.scala 114:36] - node T_1577 = and(T_1574, T_1576) @[frontend.scala 114:33] - icache.io.req.valid <= T_1577 @[frontend.scala 114:23] - icache.io.req.bits.addr <= io.cpu.npc @[frontend.scala 115:27] - icache.io.invalidate <= io.cpu.flush_icache @[frontend.scala 116:24] - icache.io.s1_ppn <= tlb.io.resp.ppn @[frontend.scala 117:20] - node T_1578 = or(io.cpu.req.valid, tlb.io.resp.miss) @[frontend.scala 118:41] - node T_1579 = or(T_1578, tlb.io.resp.xcpt_if) @[frontend.scala 118:61] - node T_1580 = or(T_1579, icmiss) @[frontend.scala 118:84] - node T_1581 = or(T_1580, io.cpu.flush_tlb) @[frontend.scala 118:94] - icache.io.s1_kill <= T_1581 @[frontend.scala 118:21] - node T_1583 = eq(s2_cacheable, UInt<1>("h00")) @[frontend.scala 119:42] - node T_1584 = and(s2_speculative, T_1583) @[frontend.scala 119:39] - icache.io.s2_kill <= T_1584 @[frontend.scala 119:21] - node T_1586 = eq(stall, UInt<1>("h00")) @[frontend.scala 120:27] - node T_1588 = eq(s1_same_block, UInt<1>("h00")) @[frontend.scala 120:37] - node T_1589 = and(T_1586, T_1588) @[frontend.scala 120:34] - icache.io.resp.ready <= T_1589 @[frontend.scala 120:24] - node T_1590 = or(icache.io.resp.valid, icache.io.s2_kill) @[frontend.scala 122:58] - node T_1591 = or(T_1590, s2_xcpt_if) @[frontend.scala 122:79] - node T_1592 = and(s2_valid, T_1591) @[frontend.scala 122:33] - io.cpu.resp.valid <= T_1592 @[frontend.scala 122:21] - io.cpu.resp.bits.pc <= s2_pc @[frontend.scala 123:23] - node T_1593 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) @[frontend.scala 124:20] - io.cpu.npc <= T_1593 @[frontend.scala 124:14] - node T_1594 = bits(s2_pc, 2, 2) @[util.scala 25:13] - node T_1595 = shl(T_1594, 5) @[frontend.scala 127:133] - node T_1596 = dshr(icache.io.resp.bits.datablock, T_1595) @[frontend.scala 127:58] - io.cpu.resp.bits.data <= T_1596 @[frontend.scala 127:25] - node T_1598 = bits(s2_pc, 1, 1) @[util.scala 25:13] - node T_1599 = dshl(UInt<2>("h03"), T_1598) @[frontend.scala 128:54] - io.cpu.resp.bits.mask <= T_1599 @[frontend.scala 128:25] - io.cpu.resp.bits.xcpt_if <= s2_xcpt_if @[frontend.scala 129:28] - node T_1601 = eq(icache.io.resp.valid, UInt<1>("h00")) @[frontend.scala 130:51] - node T_1602 = and(icache.io.s2_kill, T_1601) @[frontend.scala 130:48] - node T_1604 = eq(s2_xcpt_if, UInt<1>("h00")) @[frontend.scala 130:76] - node T_1605 = and(T_1602, T_1604) @[frontend.scala 130:73] - io.cpu.resp.bits.replay <= T_1605 @[frontend.scala 130:27] - io.cpu.resp.bits.btb.valid <= s2_btb_resp_valid @[frontend.scala 131:30] - io.cpu.resp.bits.btb.bits <- s2_btb_resp_bits @[frontend.scala 132:29] - - module FinishQueue : + BTB_1.io.req.valid <= UInt<1>("h0") + BTB_1.io.req.bits.addr <= s1_pc_ + BTB_1.io.btb_update <- io.cpu.btb_update + BTB_1.io.bht_update <- io.cpu.bht_update + BTB_1.io.ras_update <- io.cpu.ras_update + node T_1555 = eq(stall, UInt<1>("h0")) + node T_1557 = eq(icmiss, UInt<1>("h0")) + node T_1558 = and(T_1555, T_1557) + when T_1558 : + BTB_1.io.req.valid <= UInt<1>("h1") + s2_btb_resp_valid <= BTB_1.io.resp.valid + s2_btb_resp_bits <- BTB_1.io.resp.bits + node T_1560 = and(BTB_1.io.resp.valid, BTB_1.io.resp.bits.taken) + when T_1560 : + node T_1561 = bits(BTB_1.io.resp.bits.target, 38, 38) + node T_1562 = cat(T_1561, BTB_1.io.resp.bits.target) + predicted_npc <= T_1562 + predicted_taken <= UInt<1>("h1") + io.ptw <- tlb.io.ptw + node T_1565 = eq(stall, UInt<1>("h0")) + node T_1567 = eq(icmiss, UInt<1>("h0")) + node T_1568 = and(T_1565, T_1567) + tlb.io.req.valid <= T_1568 + node T_1569 = shr(s1_pc, 12) + tlb.io.req.bits.vpn <= T_1569 + tlb.io.req.bits.passthrough <= UInt<1>("h0") + tlb.io.req.bits.instruction <= UInt<1>("h1") + tlb.io.req.bits.store <= UInt<1>("h0") + io.mem <- icache.io.mem + node T_1574 = eq(stall, UInt<1>("h0")) + node T_1576 = eq(s0_same_block, UInt<1>("h0")) + node T_1577 = and(T_1574, T_1576) + icache.io.req.valid <= T_1577 + icache.io.req.bits.addr <= io.cpu.npc + icache.io.invalidate <= io.cpu.flush_icache + icache.io.s1_ppn <= tlb.io.resp.ppn + node T_1578 = or(io.cpu.req.valid, tlb.io.resp.miss) + node T_1579 = or(T_1578, tlb.io.resp.xcpt_if) + node T_1580 = or(T_1579, icmiss) + node T_1581 = or(T_1580, io.cpu.flush_tlb) + icache.io.s1_kill <= T_1581 + node T_1583 = eq(s2_cacheable, UInt<1>("h0")) + node T_1584 = and(s2_speculative, T_1583) + icache.io.s2_kill <= T_1584 + node T_1586 = eq(stall, UInt<1>("h0")) + node T_1588 = eq(s1_same_block, UInt<1>("h0")) + node T_1589 = and(T_1586, T_1588) + icache.io.resp.ready <= T_1589 + node T_1590 = or(icache.io.resp.valid, icache.io.s2_kill) + node T_1591 = or(T_1590, s2_xcpt_if) + node T_1592 = and(s2_valid, T_1591) + io.cpu.resp.valid <= T_1592 + io.cpu.resp.bits.pc <= s2_pc + node T_1593 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) + io.cpu.npc <= T_1593 + node T_1594 = bits(s2_pc, 2, 2) + node T_1595 = shl(T_1594, 5) + node T_1596 = dshr(icache.io.resp.bits.datablock, T_1595) + io.cpu.resp.bits.data <= T_1596 + node T_1598 = bits(s2_pc, 1, 1) + node T_1599 = dshl(UInt<2>("h3"), T_1598) + io.cpu.resp.bits.mask <= T_1599 + io.cpu.resp.bits.xcpt_if <= s2_xcpt_if + node T_1601 = eq(icache.io.resp.valid, UInt<1>("h0")) + node T_1602 = and(icache.io.s2_kill, T_1601) + node T_1604 = eq(s2_xcpt_if, UInt<1>("h0")) + node T_1605 = and(T_1602, T_1604) + io.cpu.resp.bits.replay <= T_1605 + io.cpu.resp.bits.btb.valid <= s2_btb_resp_valid + io.cpu.resp.bits.btb.bits <- s2_btb_resp_bits + + module FinishQueue : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}, count : UInt<1>} + io is invalid - cmem ram : {manager_xact_id : UInt<4>, manager_id : UInt<1>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_221 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_221) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_222 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { manager_xact_id : UInt<4>, manager_id : UInt<1>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_221 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_221) + node full = and(ptr_match, maybe_full) + node T_222 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_222 - node T_223 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_223 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_223 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_224 = ram[UInt<1>("h00")], clk - T_224 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_249 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_249 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_251 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_251 @[Decoupled.scala 184:16] - node T_253 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_253 @[Decoupled.scala 185:16] - infer mport T_254 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_254 @[Decoupled.scala 186:15] - node T_277 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_277, 1) @[Decoupled.scala 201:32] - node T_278 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_279 = cat(T_278, ptr_diff) @[Cat.scala 20:58] - io.count <= T_279 @[Decoupled.scala 203:14] - - module Arbiter : + when do_enq : + infer mport T_224 = ram[UInt<1>("h0")], clk + T_224 <- io.enq.bits + when do_deq : + skip + node T_249 = neq(do_enq, do_deq) + when T_249 : + maybe_full <= do_enq + node T_251 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_251 + node T_253 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_253 + infer mport T_254 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_254 + node T_277 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_277, 1) + node T_278 = and(maybe_full, ptr_match) + node T_279 = cat(T_278, ptr_diff) + io.count <= T_279 + + module Arbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>}}, chosen : UInt<2>} + io is invalid - io.chosen <= UInt<2>("h02") @[Arbiter.scala 106:13] - io.out.bits <- io.in[2].bits @[Arbiter.scala 107:15] - when io.in[1].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h01") @[Arbiter.scala 110:17] - io.out.bits <- io.in[1].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - when io.in[0].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h00") @[Arbiter.scala 110:17] - io.out.bits <- io.in[0].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - node T_637 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 23:72] - node grant_1 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 23:82] - node grant_2 = eq(T_637, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_640 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 117:19] - io.in[0].ready <= T_640 @[Arbiter.scala 117:14] - node T_641 = and(grant_1, io.out.ready) @[Arbiter.scala 117:19] - io.in[1].ready <= T_641 @[Arbiter.scala 117:14] - node T_642 = and(grant_2, io.out.ready) @[Arbiter.scala 117:19] - io.in[2].ready <= T_642 @[Arbiter.scala 117:14] - node T_644 = eq(grant_2, UInt<1>("h00")) @[Arbiter.scala 118:19] - node T_645 = or(T_644, io.in[2].valid) @[Arbiter.scala 118:31] - io.out.valid <= T_645 @[Arbiter.scala 118:16] - - module Arbiter_1 : + io.chosen <= UInt<2>("h2") + io.out.bits <- io.in[2].bits + when io.in[1].valid : + io.chosen <= UInt<1>("h1") + io.out.bits <- io.in[1].bits + when io.in[0].valid : + io.chosen <= UInt<1>("h0") + io.out.bits <- io.in[0].bits + node T_637 = or(io.in[0].valid, io.in[1].valid) + node grant_1 = eq(io.in[0].valid, UInt<1>("h0")) + node grant_2 = eq(T_637, UInt<1>("h0")) + node T_640 = and(UInt<1>("h1"), io.out.ready) + io.in[0].ready <= T_640 + node T_641 = and(grant_1, io.out.ready) + io.in[1].ready <= T_641 + node T_642 = and(grant_2, io.out.ready) + io.in[2].ready <= T_642 + node T_644 = eq(grant_2, UInt<1>("h0")) + node T_645 = or(T_644, io.in[2].valid) + io.out.valid <= T_645 + + module Arbiter_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, chosen : UInt<2>} + io is invalid - io.chosen <= UInt<2>("h02") @[Arbiter.scala 106:13] - io.out.bits <- io.in[2].bits @[Arbiter.scala 107:15] - when io.in[1].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h01") @[Arbiter.scala 110:17] - io.out.bits <- io.in[1].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - when io.in[0].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h00") @[Arbiter.scala 110:17] - io.out.bits <- io.in[0].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - node T_2821 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 23:72] - node grant_1 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 23:82] - node grant_2 = eq(T_2821, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_2824 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 117:19] - io.in[0].ready <= T_2824 @[Arbiter.scala 117:14] - node T_2825 = and(grant_1, io.out.ready) @[Arbiter.scala 117:19] - io.in[1].ready <= T_2825 @[Arbiter.scala 117:14] - node T_2826 = and(grant_2, io.out.ready) @[Arbiter.scala 117:19] - io.in[2].ready <= T_2826 @[Arbiter.scala 117:14] - node T_2828 = eq(grant_2, UInt<1>("h00")) @[Arbiter.scala 118:19] - node T_2829 = or(T_2828, io.in[2].valid) @[Arbiter.scala 118:31] - io.out.valid <= T_2829 @[Arbiter.scala 118:16] - - module DCacheDataArray : + io.chosen <= UInt<2>("h2") + io.out.bits <- io.in[2].bits + when io.in[1].valid : + io.chosen <= UInt<1>("h1") + io.out.bits <- io.in[1].bits + when io.in[0].valid : + io.chosen <= UInt<1>("h0") + io.out.bits <- io.in[0].bits + node T_2821 = or(io.in[0].valid, io.in[1].valid) + node grant_1 = eq(io.in[0].valid, UInt<1>("h0")) + node grant_2 = eq(T_2821, UInt<1>("h0")) + node T_2824 = and(UInt<1>("h1"), io.out.ready) + io.in[0].ready <= T_2824 + node T_2825 = and(grant_1, io.out.ready) + io.in[1].ready <= T_2825 + node T_2826 = and(grant_2, io.out.ready) + io.in[2].ready <= T_2826 + node T_2828 = eq(grant_2, UInt<1>("h0")) + node T_2829 = or(T_2828, io.in[2].valid) + io.out.valid <= T_2829 + + module DCacheDataArray : input clk : Clock input reset : UInt<1> - output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, resp : UInt<64>[4]} - + output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, resp : UInt<64>[4]} + io is invalid - node addr = shr(io.req.bits.addr, 3) @[dcache.scala 29:31] - smem T_406 : UInt<8>[8][512] @[dcache.scala 31:23] - node T_408 = bits(io.req.bits.way_en, 0, 0) @[dcache.scala 32:72] - node T_409 = or(UInt<1>("h00"), T_408) @[dcache.scala 32:51] - node T_410 = and(io.req.valid, T_409) @[dcache.scala 32:30] - node T_411 = and(T_410, io.req.bits.write) @[dcache.scala 33:17] - when T_411 : @[dcache.scala 33:39] - node T_412 = bits(io.req.bits.wdata, 7, 0) @[dcache.scala 34:63] - node T_413 = bits(io.req.bits.wdata, 15, 8) @[dcache.scala 34:63] - node T_414 = bits(io.req.bits.wdata, 23, 16) @[dcache.scala 34:63] - node T_415 = bits(io.req.bits.wdata, 31, 24) @[dcache.scala 34:63] - node T_416 = bits(io.req.bits.wdata, 39, 32) @[dcache.scala 34:63] - node T_417 = bits(io.req.bits.wdata, 47, 40) @[dcache.scala 34:63] - node T_418 = bits(io.req.bits.wdata, 55, 48) @[dcache.scala 34:63] - node T_419 = bits(io.req.bits.wdata, 63, 56) @[dcache.scala 34:63] - wire T_425 : UInt<8>[8] @[dcache.scala 34:40] - T_425 is invalid @[dcache.scala 34:40] - T_425[0] <= T_412 @[dcache.scala 34:40] - T_425[1] <= T_413 @[dcache.scala 34:40] - T_425[2] <= T_414 @[dcache.scala 34:40] - T_425[3] <= T_415 @[dcache.scala 34:40] - T_425[4] <= T_416 @[dcache.scala 34:40] - T_425[5] <= T_417 @[dcache.scala 34:40] - T_425[6] <= T_418 @[dcache.scala 34:40] - T_425[7] <= T_419 @[dcache.scala 34:40] - node T_427 = bits(io.req.bits.wmask, 0, 0) @[dcache.scala 35:49] - node T_428 = bits(io.req.bits.wmask, 1, 1) @[dcache.scala 35:49] - node T_429 = bits(io.req.bits.wmask, 2, 2) @[dcache.scala 35:49] - node T_430 = bits(io.req.bits.wmask, 3, 3) @[dcache.scala 35:49] - node T_431 = bits(io.req.bits.wmask, 4, 4) @[dcache.scala 35:49] - node T_432 = bits(io.req.bits.wmask, 5, 5) @[dcache.scala 35:49] - node T_433 = bits(io.req.bits.wmask, 6, 6) @[dcache.scala 35:49] - node T_434 = bits(io.req.bits.wmask, 7, 7) @[dcache.scala 35:49] + node addr = shr(io.req.bits.addr, 3) + smem T_406 : UInt<8>[8] [512] + node T_408 = bits(io.req.bits.way_en, 0, 0) + node T_409 = or(UInt<1>("h0"), T_408) + node T_410 = and(io.req.valid, T_409) + node T_411 = and(T_410, io.req.bits.write) + when T_411 : + node T_412 = bits(io.req.bits.wdata, 7, 0) + node T_413 = bits(io.req.bits.wdata, 15, 8) + node T_414 = bits(io.req.bits.wdata, 23, 16) + node T_415 = bits(io.req.bits.wdata, 31, 24) + node T_416 = bits(io.req.bits.wdata, 39, 32) + node T_417 = bits(io.req.bits.wdata, 47, 40) + node T_418 = bits(io.req.bits.wdata, 55, 48) + node T_419 = bits(io.req.bits.wdata, 63, 56) + wire T_425 : UInt<8>[8] + T_425 is invalid + T_425[0] <= T_412 + T_425[1] <= T_413 + T_425[2] <= T_414 + T_425[3] <= T_415 + T_425[4] <= T_416 + T_425[5] <= T_417 + T_425[6] <= T_418 + T_425[7] <= T_419 + node T_427 = bits(io.req.bits.wmask, 0, 0) + node T_428 = bits(io.req.bits.wmask, 1, 1) + node T_429 = bits(io.req.bits.wmask, 2, 2) + node T_430 = bits(io.req.bits.wmask, 3, 3) + node T_431 = bits(io.req.bits.wmask, 4, 4) + node T_432 = bits(io.req.bits.wmask, 5, 5) + node T_433 = bits(io.req.bits.wmask, 6, 6) + node T_434 = bits(io.req.bits.wmask, 7, 7) write mport T_437 = T_406[addr], clk when T_427 : T_437[0] <= T_425[0] - skip when T_428 : T_437[1] <= T_425[1] - skip when T_429 : T_437[2] <= T_425[2] - skip when T_430 : T_437[3] <= T_425[3] - skip when T_431 : T_437[4] <= T_425[4] - skip when T_432 : T_437[5] <= T_425[5] - skip when T_433 : T_437[6] <= T_425[6] - skip when T_434 : T_437[7] <= T_425[7] - skip - skip @[dcache.scala 33:39] - node T_440 = eq(io.req.bits.write, UInt<1>("h00")) @[dcache.scala 37:45] - node T_441 = and(T_410, T_440) @[dcache.scala 37:42] + node T_440 = eq(io.req.bits.write, UInt<1>("h0")) + node T_441 = and(T_410, T_440) wire T_443 : UInt T_443 is invalid when T_441 : T_443 <= addr - skip read mport T_446 = T_406[T_443], clk - node T_448 = cat(T_446[1], T_446[0]) @[dcache.scala 37:65] - node T_449 = cat(T_446[3], T_446[2]) @[dcache.scala 37:65] - node T_450 = cat(T_449, T_448) @[dcache.scala 37:65] - node T_451 = cat(T_446[5], T_446[4]) @[dcache.scala 37:65] - node T_452 = cat(T_446[7], T_446[6]) @[dcache.scala 37:65] - node T_453 = cat(T_452, T_451) @[dcache.scala 37:65] - node T_454 = cat(T_453, T_450) @[dcache.scala 37:65] - io.resp[0] <= T_454 @[dcache.scala 37:16] - smem T_463 : UInt<8>[8][512] @[dcache.scala 31:23] - node T_465 = bits(io.req.bits.way_en, 1, 1) @[dcache.scala 32:72] - node T_466 = or(UInt<1>("h00"), T_465) @[dcache.scala 32:51] - node T_467 = and(io.req.valid, T_466) @[dcache.scala 32:30] - node T_468 = and(T_467, io.req.bits.write) @[dcache.scala 33:17] - when T_468 : @[dcache.scala 33:39] - node T_469 = bits(io.req.bits.wdata, 7, 0) @[dcache.scala 34:63] - node T_470 = bits(io.req.bits.wdata, 15, 8) @[dcache.scala 34:63] - node T_471 = bits(io.req.bits.wdata, 23, 16) @[dcache.scala 34:63] - node T_472 = bits(io.req.bits.wdata, 31, 24) @[dcache.scala 34:63] - node T_473 = bits(io.req.bits.wdata, 39, 32) @[dcache.scala 34:63] - node T_474 = bits(io.req.bits.wdata, 47, 40) @[dcache.scala 34:63] - node T_475 = bits(io.req.bits.wdata, 55, 48) @[dcache.scala 34:63] - node T_476 = bits(io.req.bits.wdata, 63, 56) @[dcache.scala 34:63] - wire T_482 : UInt<8>[8] @[dcache.scala 34:40] - T_482 is invalid @[dcache.scala 34:40] - T_482[0] <= T_469 @[dcache.scala 34:40] - T_482[1] <= T_470 @[dcache.scala 34:40] - T_482[2] <= T_471 @[dcache.scala 34:40] - T_482[3] <= T_472 @[dcache.scala 34:40] - T_482[4] <= T_473 @[dcache.scala 34:40] - T_482[5] <= T_474 @[dcache.scala 34:40] - T_482[6] <= T_475 @[dcache.scala 34:40] - T_482[7] <= T_476 @[dcache.scala 34:40] - node T_484 = bits(io.req.bits.wmask, 0, 0) @[dcache.scala 35:49] - node T_485 = bits(io.req.bits.wmask, 1, 1) @[dcache.scala 35:49] - node T_486 = bits(io.req.bits.wmask, 2, 2) @[dcache.scala 35:49] - node T_487 = bits(io.req.bits.wmask, 3, 3) @[dcache.scala 35:49] - node T_488 = bits(io.req.bits.wmask, 4, 4) @[dcache.scala 35:49] - node T_489 = bits(io.req.bits.wmask, 5, 5) @[dcache.scala 35:49] - node T_490 = bits(io.req.bits.wmask, 6, 6) @[dcache.scala 35:49] - node T_491 = bits(io.req.bits.wmask, 7, 7) @[dcache.scala 35:49] + node T_448 = cat(T_446[1], T_446[0]) + node T_449 = cat(T_446[3], T_446[2]) + node T_450 = cat(T_449, T_448) + node T_451 = cat(T_446[5], T_446[4]) + node T_452 = cat(T_446[7], T_446[6]) + node T_453 = cat(T_452, T_451) + node T_454 = cat(T_453, T_450) + io.resp[0] <= T_454 + smem T_463 : UInt<8>[8] [512] + node T_465 = bits(io.req.bits.way_en, 1, 1) + node T_466 = or(UInt<1>("h0"), T_465) + node T_467 = and(io.req.valid, T_466) + node T_468 = and(T_467, io.req.bits.write) + when T_468 : + node T_469 = bits(io.req.bits.wdata, 7, 0) + node T_470 = bits(io.req.bits.wdata, 15, 8) + node T_471 = bits(io.req.bits.wdata, 23, 16) + node T_472 = bits(io.req.bits.wdata, 31, 24) + node T_473 = bits(io.req.bits.wdata, 39, 32) + node T_474 = bits(io.req.bits.wdata, 47, 40) + node T_475 = bits(io.req.bits.wdata, 55, 48) + node T_476 = bits(io.req.bits.wdata, 63, 56) + wire T_482 : UInt<8>[8] + T_482 is invalid + T_482[0] <= T_469 + T_482[1] <= T_470 + T_482[2] <= T_471 + T_482[3] <= T_472 + T_482[4] <= T_473 + T_482[5] <= T_474 + T_482[6] <= T_475 + T_482[7] <= T_476 + node T_484 = bits(io.req.bits.wmask, 0, 0) + node T_485 = bits(io.req.bits.wmask, 1, 1) + node T_486 = bits(io.req.bits.wmask, 2, 2) + node T_487 = bits(io.req.bits.wmask, 3, 3) + node T_488 = bits(io.req.bits.wmask, 4, 4) + node T_489 = bits(io.req.bits.wmask, 5, 5) + node T_490 = bits(io.req.bits.wmask, 6, 6) + node T_491 = bits(io.req.bits.wmask, 7, 7) write mport T_494 = T_463[addr], clk when T_484 : T_494[0] <= T_482[0] - skip when T_485 : T_494[1] <= T_482[1] - skip when T_486 : T_494[2] <= T_482[2] - skip when T_487 : T_494[3] <= T_482[3] - skip when T_488 : T_494[4] <= T_482[4] - skip when T_489 : T_494[5] <= T_482[5] - skip when T_490 : T_494[6] <= T_482[6] - skip when T_491 : T_494[7] <= T_482[7] - skip - skip @[dcache.scala 33:39] - node T_497 = eq(io.req.bits.write, UInt<1>("h00")) @[dcache.scala 37:45] - node T_498 = and(T_467, T_497) @[dcache.scala 37:42] + node T_497 = eq(io.req.bits.write, UInt<1>("h0")) + node T_498 = and(T_467, T_497) wire T_500 : UInt T_500 is invalid when T_498 : T_500 <= addr - skip read mport T_503 = T_463[T_500], clk - node T_505 = cat(T_503[1], T_503[0]) @[dcache.scala 37:65] - node T_506 = cat(T_503[3], T_503[2]) @[dcache.scala 37:65] - node T_507 = cat(T_506, T_505) @[dcache.scala 37:65] - node T_508 = cat(T_503[5], T_503[4]) @[dcache.scala 37:65] - node T_509 = cat(T_503[7], T_503[6]) @[dcache.scala 37:65] - node T_510 = cat(T_509, T_508) @[dcache.scala 37:65] - node T_511 = cat(T_510, T_507) @[dcache.scala 37:65] - io.resp[1] <= T_511 @[dcache.scala 37:16] - smem T_520 : UInt<8>[8][512] @[dcache.scala 31:23] - node T_522 = bits(io.req.bits.way_en, 2, 2) @[dcache.scala 32:72] - node T_523 = or(UInt<1>("h00"), T_522) @[dcache.scala 32:51] - node T_524 = and(io.req.valid, T_523) @[dcache.scala 32:30] - node T_525 = and(T_524, io.req.bits.write) @[dcache.scala 33:17] - when T_525 : @[dcache.scala 33:39] - node T_526 = bits(io.req.bits.wdata, 7, 0) @[dcache.scala 34:63] - node T_527 = bits(io.req.bits.wdata, 15, 8) @[dcache.scala 34:63] - node T_528 = bits(io.req.bits.wdata, 23, 16) @[dcache.scala 34:63] - node T_529 = bits(io.req.bits.wdata, 31, 24) @[dcache.scala 34:63] - node T_530 = bits(io.req.bits.wdata, 39, 32) @[dcache.scala 34:63] - node T_531 = bits(io.req.bits.wdata, 47, 40) @[dcache.scala 34:63] - node T_532 = bits(io.req.bits.wdata, 55, 48) @[dcache.scala 34:63] - node T_533 = bits(io.req.bits.wdata, 63, 56) @[dcache.scala 34:63] - wire T_539 : UInt<8>[8] @[dcache.scala 34:40] - T_539 is invalid @[dcache.scala 34:40] - T_539[0] <= T_526 @[dcache.scala 34:40] - T_539[1] <= T_527 @[dcache.scala 34:40] - T_539[2] <= T_528 @[dcache.scala 34:40] - T_539[3] <= T_529 @[dcache.scala 34:40] - T_539[4] <= T_530 @[dcache.scala 34:40] - T_539[5] <= T_531 @[dcache.scala 34:40] - T_539[6] <= T_532 @[dcache.scala 34:40] - T_539[7] <= T_533 @[dcache.scala 34:40] - node T_541 = bits(io.req.bits.wmask, 0, 0) @[dcache.scala 35:49] - node T_542 = bits(io.req.bits.wmask, 1, 1) @[dcache.scala 35:49] - node T_543 = bits(io.req.bits.wmask, 2, 2) @[dcache.scala 35:49] - node T_544 = bits(io.req.bits.wmask, 3, 3) @[dcache.scala 35:49] - node T_545 = bits(io.req.bits.wmask, 4, 4) @[dcache.scala 35:49] - node T_546 = bits(io.req.bits.wmask, 5, 5) @[dcache.scala 35:49] - node T_547 = bits(io.req.bits.wmask, 6, 6) @[dcache.scala 35:49] - node T_548 = bits(io.req.bits.wmask, 7, 7) @[dcache.scala 35:49] + node T_505 = cat(T_503[1], T_503[0]) + node T_506 = cat(T_503[3], T_503[2]) + node T_507 = cat(T_506, T_505) + node T_508 = cat(T_503[5], T_503[4]) + node T_509 = cat(T_503[7], T_503[6]) + node T_510 = cat(T_509, T_508) + node T_511 = cat(T_510, T_507) + io.resp[1] <= T_511 + smem T_520 : UInt<8>[8] [512] + node T_522 = bits(io.req.bits.way_en, 2, 2) + node T_523 = or(UInt<1>("h0"), T_522) + node T_524 = and(io.req.valid, T_523) + node T_525 = and(T_524, io.req.bits.write) + when T_525 : + node T_526 = bits(io.req.bits.wdata, 7, 0) + node T_527 = bits(io.req.bits.wdata, 15, 8) + node T_528 = bits(io.req.bits.wdata, 23, 16) + node T_529 = bits(io.req.bits.wdata, 31, 24) + node T_530 = bits(io.req.bits.wdata, 39, 32) + node T_531 = bits(io.req.bits.wdata, 47, 40) + node T_532 = bits(io.req.bits.wdata, 55, 48) + node T_533 = bits(io.req.bits.wdata, 63, 56) + wire T_539 : UInt<8>[8] + T_539 is invalid + T_539[0] <= T_526 + T_539[1] <= T_527 + T_539[2] <= T_528 + T_539[3] <= T_529 + T_539[4] <= T_530 + T_539[5] <= T_531 + T_539[6] <= T_532 + T_539[7] <= T_533 + node T_541 = bits(io.req.bits.wmask, 0, 0) + node T_542 = bits(io.req.bits.wmask, 1, 1) + node T_543 = bits(io.req.bits.wmask, 2, 2) + node T_544 = bits(io.req.bits.wmask, 3, 3) + node T_545 = bits(io.req.bits.wmask, 4, 4) + node T_546 = bits(io.req.bits.wmask, 5, 5) + node T_547 = bits(io.req.bits.wmask, 6, 6) + node T_548 = bits(io.req.bits.wmask, 7, 7) write mport T_551 = T_520[addr], clk when T_541 : T_551[0] <= T_539[0] - skip when T_542 : T_551[1] <= T_539[1] - skip when T_543 : T_551[2] <= T_539[2] - skip when T_544 : T_551[3] <= T_539[3] - skip when T_545 : T_551[4] <= T_539[4] - skip when T_546 : T_551[5] <= T_539[5] - skip when T_547 : T_551[6] <= T_539[6] - skip when T_548 : T_551[7] <= T_539[7] - skip - skip @[dcache.scala 33:39] - node T_554 = eq(io.req.bits.write, UInt<1>("h00")) @[dcache.scala 37:45] - node T_555 = and(T_524, T_554) @[dcache.scala 37:42] + node T_554 = eq(io.req.bits.write, UInt<1>("h0")) + node T_555 = and(T_524, T_554) wire T_557 : UInt T_557 is invalid when T_555 : T_557 <= addr - skip read mport T_560 = T_520[T_557], clk - node T_562 = cat(T_560[1], T_560[0]) @[dcache.scala 37:65] - node T_563 = cat(T_560[3], T_560[2]) @[dcache.scala 37:65] - node T_564 = cat(T_563, T_562) @[dcache.scala 37:65] - node T_565 = cat(T_560[5], T_560[4]) @[dcache.scala 37:65] - node T_566 = cat(T_560[7], T_560[6]) @[dcache.scala 37:65] - node T_567 = cat(T_566, T_565) @[dcache.scala 37:65] - node T_568 = cat(T_567, T_564) @[dcache.scala 37:65] - io.resp[2] <= T_568 @[dcache.scala 37:16] - smem T_577 : UInt<8>[8][512] @[dcache.scala 31:23] - node T_579 = bits(io.req.bits.way_en, 3, 3) @[dcache.scala 32:72] - node T_580 = or(UInt<1>("h00"), T_579) @[dcache.scala 32:51] - node T_581 = and(io.req.valid, T_580) @[dcache.scala 32:30] - node T_582 = and(T_581, io.req.bits.write) @[dcache.scala 33:17] - when T_582 : @[dcache.scala 33:39] - node T_583 = bits(io.req.bits.wdata, 7, 0) @[dcache.scala 34:63] - node T_584 = bits(io.req.bits.wdata, 15, 8) @[dcache.scala 34:63] - node T_585 = bits(io.req.bits.wdata, 23, 16) @[dcache.scala 34:63] - node T_586 = bits(io.req.bits.wdata, 31, 24) @[dcache.scala 34:63] - node T_587 = bits(io.req.bits.wdata, 39, 32) @[dcache.scala 34:63] - node T_588 = bits(io.req.bits.wdata, 47, 40) @[dcache.scala 34:63] - node T_589 = bits(io.req.bits.wdata, 55, 48) @[dcache.scala 34:63] - node T_590 = bits(io.req.bits.wdata, 63, 56) @[dcache.scala 34:63] - wire T_596 : UInt<8>[8] @[dcache.scala 34:40] - T_596 is invalid @[dcache.scala 34:40] - T_596[0] <= T_583 @[dcache.scala 34:40] - T_596[1] <= T_584 @[dcache.scala 34:40] - T_596[2] <= T_585 @[dcache.scala 34:40] - T_596[3] <= T_586 @[dcache.scala 34:40] - T_596[4] <= T_587 @[dcache.scala 34:40] - T_596[5] <= T_588 @[dcache.scala 34:40] - T_596[6] <= T_589 @[dcache.scala 34:40] - T_596[7] <= T_590 @[dcache.scala 34:40] - node T_598 = bits(io.req.bits.wmask, 0, 0) @[dcache.scala 35:49] - node T_599 = bits(io.req.bits.wmask, 1, 1) @[dcache.scala 35:49] - node T_600 = bits(io.req.bits.wmask, 2, 2) @[dcache.scala 35:49] - node T_601 = bits(io.req.bits.wmask, 3, 3) @[dcache.scala 35:49] - node T_602 = bits(io.req.bits.wmask, 4, 4) @[dcache.scala 35:49] - node T_603 = bits(io.req.bits.wmask, 5, 5) @[dcache.scala 35:49] - node T_604 = bits(io.req.bits.wmask, 6, 6) @[dcache.scala 35:49] - node T_605 = bits(io.req.bits.wmask, 7, 7) @[dcache.scala 35:49] + node T_562 = cat(T_560[1], T_560[0]) + node T_563 = cat(T_560[3], T_560[2]) + node T_564 = cat(T_563, T_562) + node T_565 = cat(T_560[5], T_560[4]) + node T_566 = cat(T_560[7], T_560[6]) + node T_567 = cat(T_566, T_565) + node T_568 = cat(T_567, T_564) + io.resp[2] <= T_568 + smem T_577 : UInt<8>[8] [512] + node T_579 = bits(io.req.bits.way_en, 3, 3) + node T_580 = or(UInt<1>("h0"), T_579) + node T_581 = and(io.req.valid, T_580) + node T_582 = and(T_581, io.req.bits.write) + when T_582 : + node T_583 = bits(io.req.bits.wdata, 7, 0) + node T_584 = bits(io.req.bits.wdata, 15, 8) + node T_585 = bits(io.req.bits.wdata, 23, 16) + node T_586 = bits(io.req.bits.wdata, 31, 24) + node T_587 = bits(io.req.bits.wdata, 39, 32) + node T_588 = bits(io.req.bits.wdata, 47, 40) + node T_589 = bits(io.req.bits.wdata, 55, 48) + node T_590 = bits(io.req.bits.wdata, 63, 56) + wire T_596 : UInt<8>[8] + T_596 is invalid + T_596[0] <= T_583 + T_596[1] <= T_584 + T_596[2] <= T_585 + T_596[3] <= T_586 + T_596[4] <= T_587 + T_596[5] <= T_588 + T_596[6] <= T_589 + T_596[7] <= T_590 + node T_598 = bits(io.req.bits.wmask, 0, 0) + node T_599 = bits(io.req.bits.wmask, 1, 1) + node T_600 = bits(io.req.bits.wmask, 2, 2) + node T_601 = bits(io.req.bits.wmask, 3, 3) + node T_602 = bits(io.req.bits.wmask, 4, 4) + node T_603 = bits(io.req.bits.wmask, 5, 5) + node T_604 = bits(io.req.bits.wmask, 6, 6) + node T_605 = bits(io.req.bits.wmask, 7, 7) write mport T_608 = T_577[addr], clk when T_598 : T_608[0] <= T_596[0] - skip when T_599 : T_608[1] <= T_596[1] - skip when T_600 : T_608[2] <= T_596[2] - skip when T_601 : T_608[3] <= T_596[3] - skip when T_602 : T_608[4] <= T_596[4] - skip when T_603 : T_608[5] <= T_596[5] - skip when T_604 : T_608[6] <= T_596[6] - skip when T_605 : T_608[7] <= T_596[7] - skip - skip @[dcache.scala 33:39] - node T_611 = eq(io.req.bits.write, UInt<1>("h00")) @[dcache.scala 37:45] - node T_612 = and(T_581, T_611) @[dcache.scala 37:42] + node T_611 = eq(io.req.bits.write, UInt<1>("h0")) + node T_612 = and(T_581, T_611) wire T_614 : UInt T_614 is invalid when T_612 : T_614 <= addr - skip read mport T_617 = T_577[T_614], clk - node T_619 = cat(T_617[1], T_617[0]) @[dcache.scala 37:65] - node T_620 = cat(T_617[3], T_617[2]) @[dcache.scala 37:65] - node T_621 = cat(T_620, T_619) @[dcache.scala 37:65] - node T_622 = cat(T_617[5], T_617[4]) @[dcache.scala 37:65] - node T_623 = cat(T_617[7], T_617[6]) @[dcache.scala 37:65] - node T_624 = cat(T_623, T_622) @[dcache.scala 37:65] - node T_625 = cat(T_624, T_621) @[dcache.scala 37:65] - io.resp[3] <= T_625 @[dcache.scala 37:16] - - module Arbiter_2 : + node T_619 = cat(T_617[1], T_617[0]) + node T_620 = cat(T_617[3], T_617[2]) + node T_621 = cat(T_620, T_619) + node T_622 = cat(T_617[5], T_617[4]) + node T_623 = cat(T_617[7], T_617[6]) + node T_624 = cat(T_623, T_622) + node T_625 = cat(T_624, T_621) + io.resp[3] <= T_625 + + module Arbiter_2 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, write : UInt<1>, wdata : UInt<64>, wmask : UInt<8>, way_en : UInt<4>}}, chosen : UInt<2>} + io is invalid - io.chosen <= UInt<2>("h03") @[Arbiter.scala 106:13] - io.out.bits <- io.in[3].bits @[Arbiter.scala 107:15] - when io.in[2].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<2>("h02") @[Arbiter.scala 110:17] - io.out.bits <- io.in[2].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - when io.in[1].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h01") @[Arbiter.scala 110:17] - io.out.bits <- io.in[1].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - when io.in[0].valid : @[Arbiter.scala 109:27] - io.chosen <= UInt<1>("h00") @[Arbiter.scala 110:17] - io.out.bits <- io.in[0].bits @[Arbiter.scala 111:19] - skip @[Arbiter.scala 109:27] - node T_2024 = or(io.in[0].valid, io.in[1].valid) @[Arbiter.scala 23:72] - node T_2025 = or(T_2024, io.in[2].valid) @[Arbiter.scala 23:72] - node grant_1 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 23:82] - node grant_2 = eq(T_2024, UInt<1>("h00")) @[Arbiter.scala 23:82] - node grant_3 = eq(T_2025, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_2029 = and(UInt<1>("h01"), io.out.ready) @[Arbiter.scala 117:19] - io.in[0].ready <= T_2029 @[Arbiter.scala 117:14] - node T_2030 = and(grant_1, io.out.ready) @[Arbiter.scala 117:19] - io.in[1].ready <= T_2030 @[Arbiter.scala 117:14] - node T_2031 = and(grant_2, io.out.ready) @[Arbiter.scala 117:19] - io.in[2].ready <= T_2031 @[Arbiter.scala 117:14] - node T_2032 = and(grant_3, io.out.ready) @[Arbiter.scala 117:19] - io.in[3].ready <= T_2032 @[Arbiter.scala 117:14] - node T_2034 = eq(grant_3, UInt<1>("h00")) @[Arbiter.scala 118:19] - node T_2035 = or(T_2034, io.in[3].valid) @[Arbiter.scala 118:31] - io.out.valid <= T_2035 @[Arbiter.scala 118:16] - - module MetadataArray : + io.chosen <= UInt<2>("h3") + io.out.bits <- io.in[3].bits + when io.in[2].valid : + io.chosen <= UInt<2>("h2") + io.out.bits <- io.in[2].bits + when io.in[1].valid : + io.chosen <= UInt<1>("h1") + io.out.bits <- io.in[1].bits + when io.in[0].valid : + io.chosen <= UInt<1>("h0") + io.out.bits <- io.in[0].bits + node T_2024 = or(io.in[0].valid, io.in[1].valid) + node T_2025 = or(T_2024, io.in[2].valid) + node grant_1 = eq(io.in[0].valid, UInt<1>("h0")) + node grant_2 = eq(T_2024, UInt<1>("h0")) + node grant_3 = eq(T_2025, UInt<1>("h0")) + node T_2029 = and(UInt<1>("h1"), io.out.ready) + io.in[0].ready <= T_2029 + node T_2030 = and(grant_1, io.out.ready) + io.in[1].ready <= T_2030 + node T_2031 = and(grant_2, io.out.ready) + io.in[2].ready <= T_2031 + node T_2032 = and(grant_3, io.out.ready) + io.in[3].ready <= T_2032 + node T_2034 = eq(grant_3, UInt<1>("h0")) + node T_2035 = or(T_2034, io.in[3].valid) + io.out.valid <= T_2035 + + module MetadataArray : input clk : Clock input reset : UInt<1> - output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]} - + output io : { flip read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>}}, flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, data : { tag : UInt<20>, coh : { state : UInt<2>}}}}, resp : { tag : UInt<20>, coh : { state : UInt<2>}}[4]} + io is invalid - wire T_44 : {state : UInt<2>} @[Metadata.scala 158:20] - T_44 is invalid @[Metadata.scala 158:20] - T_44.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} @[nbdcache.scala 129:20] - rstVal is invalid @[nbdcache.scala 129:20] - rstVal.tag <= UInt<1>("h00") @[nbdcache.scala 130:14] - rstVal.coh <- T_44 @[nbdcache.scala 131:14] - reg rst_cnt : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) - node rst = lt(rst_cnt, UInt<7>("h040")) @[Cache.scala 152:21] - node waddr = mux(rst, rst_cnt, io.write.bits.idx) @[Cache.scala 153:18] - node T_2067 = mux(rst, rstVal, io.write.bits.data) @[Cache.scala 154:18] - node wdata = cat(T_2067.tag, T_2067.coh.state) @[Cache.scala 154:52] - node T_2152 = or(rst, UInt<1>("h00")) @[Cache.scala 155:23] - node T_2154 = asSInt(io.write.bits.way_en) @[Cache.scala 155:75] - node T_2155 = mux(T_2152, asSInt(UInt<1>("h01")), T_2154) @[Cache.scala 155:18] - node wmask_0 = bits(T_2155, 0, 0) @[Cache.scala 155:83] - node wmask_1 = bits(T_2155, 1, 1) @[Cache.scala 155:83] - node wmask_2 = bits(T_2155, 2, 2) @[Cache.scala 155:83] - node wmask_3 = bits(T_2155, 3, 3) @[Cache.scala 155:83] - node T_2157 = or(rst, UInt<1>("h00")) @[Cache.scala 156:23] - node T_2159 = asSInt(io.read.bits.way_en) @[Cache.scala 156:74] - node T_2160 = mux(T_2157, asSInt(UInt<1>("h01")), T_2159) @[Cache.scala 156:18] - node rmask_0 = bits(T_2160, 0, 0) @[Cache.scala 156:82] - node rmask_1 = bits(T_2160, 1, 1) @[Cache.scala 156:82] - node rmask_2 = bits(T_2160, 2, 2) @[Cache.scala 156:82] - node rmask_3 = bits(T_2160, 3, 3) @[Cache.scala 156:82] - when rst : @[Cache.scala 157:14] - node T_2162 = add(rst_cnt, UInt<1>("h01")) @[Cache.scala 157:34] - node T_2163 = tail(T_2162, 1) @[Cache.scala 157:34] - rst_cnt <= T_2163 @[Cache.scala 157:24] - skip @[Cache.scala 157:14] - smem T_2172 : UInt<22>[4][64] @[Cache.scala 171:25] - node T_2173 = or(rst, io.write.valid) @[Cache.scala 172:15] - when T_2173 : @[Cache.scala 172:34] - wire T_2179 : UInt<22>[4] @[Cache.scala 173:43] - T_2179 is invalid @[Cache.scala 173:43] - T_2179[0] <= wdata @[Cache.scala 173:43] - T_2179[1] <= wdata @[Cache.scala 173:43] - T_2179[2] <= wdata @[Cache.scala 173:43] - T_2179[3] <= wdata @[Cache.scala 173:43] + wire T_44 : { state : UInt<2>} + T_44 is invalid + T_44.state <= UInt<1>("h0") + wire rstVal : { tag : UInt<20>, coh : { state : UInt<2>}} + rstVal is invalid + rstVal.tag <= UInt<1>("h0") + rstVal.coh <- T_44 + reg rst_cnt : UInt<7>, clk with : + reset => (reset, UInt<7>("h0")) + node rst = lt(rst_cnt, UInt<7>("h40")) + node waddr = mux(rst, rst_cnt, io.write.bits.idx) + node T_2067 = mux(rst, rstVal, io.write.bits.data) + node wdata = cat(T_2067.tag, T_2067.coh.state) + node T_2152 = or(rst, UInt<1>("h0")) + node T_2154 = asSInt(io.write.bits.way_en) + node T_2155 = mux(T_2152, asSInt(UInt<1>("h1")), T_2154) + node wmask_0 = bits(T_2155, 0, 0) + node wmask_1 = bits(T_2155, 1, 1) + node wmask_2 = bits(T_2155, 2, 2) + node wmask_3 = bits(T_2155, 3, 3) + node T_2157 = or(rst, UInt<1>("h0")) + node T_2159 = asSInt(io.read.bits.way_en) + node T_2160 = mux(T_2157, asSInt(UInt<1>("h1")), T_2159) + node rmask_0 = bits(T_2160, 0, 0) + node rmask_1 = bits(T_2160, 1, 1) + node rmask_2 = bits(T_2160, 2, 2) + node rmask_3 = bits(T_2160, 3, 3) + when rst : + node T_2162 = add(rst_cnt, UInt<1>("h1")) + node T_2163 = tail(T_2162, 1) + rst_cnt <= T_2163 + smem T_2172 : UInt<22>[4] [64] + node T_2173 = or(rst, io.write.valid) + when T_2173 : + wire T_2179 : UInt<22>[4] + T_2179 is invalid + T_2179[0] <= wdata + T_2179[1] <= wdata + T_2179[2] <= wdata + T_2179[3] <= wdata write mport T_2183 = T_2172[waddr], clk when wmask_0 : T_2183[0] <= T_2179[0] - skip when wmask_1 : T_2183[1] <= T_2179[1] - skip when wmask_2 : T_2183[2] <= T_2179[2] - skip when wmask_3 : T_2183[3] <= T_2179[3] - skip - skip @[Cache.scala 172:34] wire T_2186 : UInt T_2186 is invalid when io.read.valid : T_2186 <= io.read.bits.idx - skip read mport T_2189 = T_2172[T_2186], clk - wire T_2275 : {tag : UInt<20>, coh : {state : UInt<2>}} @[Cache.scala 175:81] - T_2275 is invalid @[Cache.scala 175:81] - node T_2359 = bits(T_2189[0], 1, 0) @[Cache.scala 175:81] - T_2275.coh.state <= T_2359 @[Cache.scala 175:81] - node T_2360 = bits(T_2189[0], 21, 2) @[Cache.scala 175:81] - T_2275.tag <= T_2360 @[Cache.scala 175:81] - wire T_2445 : {tag : UInt<20>, coh : {state : UInt<2>}} @[Cache.scala 175:81] - T_2445 is invalid @[Cache.scala 175:81] - node T_2529 = bits(T_2189[1], 1, 0) @[Cache.scala 175:81] - T_2445.coh.state <= T_2529 @[Cache.scala 175:81] - node T_2530 = bits(T_2189[1], 21, 2) @[Cache.scala 175:81] - T_2445.tag <= T_2530 @[Cache.scala 175:81] - wire T_2615 : {tag : UInt<20>, coh : {state : UInt<2>}} @[Cache.scala 175:81] - T_2615 is invalid @[Cache.scala 175:81] - node T_2699 = bits(T_2189[2], 1, 0) @[Cache.scala 175:81] - T_2615.coh.state <= T_2699 @[Cache.scala 175:81] - node T_2700 = bits(T_2189[2], 21, 2) @[Cache.scala 175:81] - T_2615.tag <= T_2700 @[Cache.scala 175:81] - wire T_2785 : {tag : UInt<20>, coh : {state : UInt<2>}} @[Cache.scala 175:81] - T_2785 is invalid @[Cache.scala 175:81] - node T_2869 = bits(T_2189[3], 1, 0) @[Cache.scala 175:81] - T_2785.coh.state <= T_2869 @[Cache.scala 175:81] - node T_2870 = bits(T_2189[3], 21, 2) @[Cache.scala 175:81] - T_2785.tag <= T_2870 @[Cache.scala 175:81] - io.resp[0] <- T_2275 @[Cache.scala 175:13] - io.resp[1] <- T_2445 @[Cache.scala 175:13] - io.resp[2] <- T_2615 @[Cache.scala 175:13] - io.resp[3] <- T_2785 @[Cache.scala 175:13] - node T_2872 = eq(rst, UInt<1>("h00")) @[Cache.scala 178:20] - node T_2874 = eq(io.write.valid, UInt<1>("h00")) @[Cache.scala 178:28] - node T_2875 = and(T_2872, T_2874) @[Cache.scala 178:25] - io.read.ready <= T_2875 @[Cache.scala 178:17] - node T_2877 = eq(rst, UInt<1>("h00")) @[Cache.scala 179:21] - io.write.ready <= T_2877 @[Cache.scala 179:18] - - module AMOALU : + wire T_2275 : { tag : UInt<20>, coh : { state : UInt<2>}} + T_2275 is invalid + node T_2359 = bits(T_2189[0], 1, 0) + T_2275.coh.state <= T_2359 + node T_2360 = bits(T_2189[0], 21, 2) + T_2275.tag <= T_2360 + wire T_2445 : { tag : UInt<20>, coh : { state : UInt<2>}} + T_2445 is invalid + node T_2529 = bits(T_2189[1], 1, 0) + T_2445.coh.state <= T_2529 + node T_2530 = bits(T_2189[1], 21, 2) + T_2445.tag <= T_2530 + wire T_2615 : { tag : UInt<20>, coh : { state : UInt<2>}} + T_2615 is invalid + node T_2699 = bits(T_2189[2], 1, 0) + T_2615.coh.state <= T_2699 + node T_2700 = bits(T_2189[2], 21, 2) + T_2615.tag <= T_2700 + wire T_2785 : { tag : UInt<20>, coh : { state : UInt<2>}} + T_2785 is invalid + node T_2869 = bits(T_2189[3], 1, 0) + T_2785.coh.state <= T_2869 + node T_2870 = bits(T_2189[3], 21, 2) + T_2785.tag <= T_2870 + io.resp[0] <- T_2275 + io.resp[1] <- T_2445 + io.resp[2] <- T_2615 + io.resp[3] <- T_2785 + node T_2872 = eq(rst, UInt<1>("h0")) + node T_2874 = eq(io.write.valid, UInt<1>("h0")) + node T_2875 = and(T_2872, T_2874) + io.read.ready <= T_2875 + node T_2877 = eq(rst, UInt<1>("h0")) + io.write.ready <= T_2877 + + module AMOALU : input clk : Clock input reset : UInt<1> - output io : {flip addr : UInt<3>, flip cmd : UInt<5>, flip typ : UInt<2>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} - + output io : { flip addr : UInt<3>, flip cmd : UInt<5>, flip typ : UInt<2>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} + io is invalid - node T_6 = bits(io.typ, 1, 0) @[AmoAlu.scala 11:17] - node T_8 = eq(T_6, UInt<2>("h02")) @[AmoAlu.scala 27:19] - node T_9 = bits(io.rhs, 31, 0) @[AmoAlu.scala 27:66] - node T_10 = cat(T_9, T_9) @[Cat.scala 20:58] - node rhs = mux(T_8, T_10, io.rhs) @[AmoAlu.scala 27:13] - node T_11 = eq(io.cmd, UInt<5>("h0c")) @[AmoAlu.scala 72:22] - node T_12 = eq(io.cmd, UInt<5>("h0d")) @[AmoAlu.scala 72:45] - node sgned = or(T_11, T_12) @[AmoAlu.scala 72:35] - node T_13 = eq(io.cmd, UInt<5>("h0d")) @[AmoAlu.scala 73:20] - node T_14 = eq(io.cmd, UInt<5>("h0f")) @[AmoAlu.scala 73:43] - node max = or(T_13, T_14) @[AmoAlu.scala 73:33] - node T_15 = eq(io.cmd, UInt<5>("h0c")) @[AmoAlu.scala 74:20] - node T_16 = eq(io.cmd, UInt<5>("h0e")) @[AmoAlu.scala 74:43] - node min = or(T_15, T_16) @[AmoAlu.scala 74:33] - node T_18 = not(UInt<64>("h00")) @[AmoAlu.scala 79:18] - node T_19 = bits(io.addr, 2, 2) @[AmoAlu.scala 79:40] - node T_20 = shl(T_19, 31) @[AmoAlu.scala 79:44] - node T_21 = xor(T_18, T_20) @[AmoAlu.scala 79:30] - node T_22 = and(io.lhs, T_21) @[AmoAlu.scala 80:15] - node T_23 = and(rhs, T_21) @[AmoAlu.scala 80:30] - node T_24 = add(T_22, T_23) @[AmoAlu.scala 80:23] - node adder_out = tail(T_24, 1) @[AmoAlu.scala 80:23] - node T_25 = bits(io.typ, 0, 0) @[AmoAlu.scala 86:25] - node T_27 = eq(T_25, UInt<1>("h00")) @[AmoAlu.scala 86:18] - node T_28 = bits(io.addr, 2, 2) @[AmoAlu.scala 87:41] - node T_30 = eq(T_28, UInt<1>("h00")) @[AmoAlu.scala 87:33] - node T_31 = and(T_27, T_30) @[AmoAlu.scala 87:30] - node T_32 = bits(io.lhs, 31, 31) @[AmoAlu.scala 87:52] - node T_33 = bits(io.lhs, 63, 63) @[AmoAlu.scala 87:64] - node T_34 = mux(T_31, T_32, T_33) @[AmoAlu.scala 87:24] - node T_35 = bits(io.addr, 2, 2) @[AmoAlu.scala 88:41] - node T_37 = eq(T_35, UInt<1>("h00")) @[AmoAlu.scala 88:33] - node T_38 = and(T_27, T_37) @[AmoAlu.scala 88:30] - node T_39 = bits(rhs, 31, 31) @[AmoAlu.scala 88:49] - node T_40 = bits(rhs, 63, 63) @[AmoAlu.scala 88:58] - node T_41 = mux(T_38, T_39, T_40) @[AmoAlu.scala 88:24] - node T_42 = bits(io.lhs, 31, 0) @[AmoAlu.scala 89:25] - node T_43 = bits(rhs, 31, 0) @[AmoAlu.scala 89:37] - node T_44 = lt(T_42, T_43) @[AmoAlu.scala 89:32] - node T_45 = bits(io.lhs, 63, 32) @[AmoAlu.scala 90:25] - node T_46 = bits(rhs, 63, 32) @[AmoAlu.scala 90:38] - node T_47 = lt(T_45, T_46) @[AmoAlu.scala 90:33] - node T_48 = bits(io.lhs, 63, 32) @[AmoAlu.scala 91:25] - node T_49 = bits(rhs, 63, 32) @[AmoAlu.scala 91:40] - node T_50 = eq(T_48, T_49) @[AmoAlu.scala 91:33] - node T_51 = bits(io.addr, 2, 2) @[AmoAlu.scala 92:37] - node T_52 = mux(T_51, T_47, T_44) @[AmoAlu.scala 92:29] - node T_53 = and(T_50, T_44) @[AmoAlu.scala 92:72] - node T_54 = or(T_47, T_53) @[AmoAlu.scala 92:63] - node T_55 = mux(T_27, T_52, T_54) @[AmoAlu.scala 92:19] - node T_56 = eq(T_34, T_41) @[AmoAlu.scala 93:19] - node T_57 = mux(sgned, T_34, T_41) @[AmoAlu.scala 93:39] - node less = mux(T_56, T_55, T_57) @[AmoAlu.scala 93:10] - node T_58 = eq(io.cmd, UInt<5>("h08")) @[AmoAlu.scala 96:24] - node T_59 = eq(io.cmd, UInt<5>("h0b")) @[AmoAlu.scala 97:24] - node T_60 = and(io.lhs, rhs) @[AmoAlu.scala 97:45] - node T_61 = eq(io.cmd, UInt<5>("h0a")) @[AmoAlu.scala 98:24] - node T_62 = or(io.lhs, rhs) @[AmoAlu.scala 98:45] - node T_63 = eq(io.cmd, UInt<5>("h09")) @[AmoAlu.scala 99:24] - node T_64 = xor(io.lhs, rhs) @[AmoAlu.scala 99:45] - node T_65 = mux(less, min, max) @[AmoAlu.scala 100:20] - node T_67 = eq(T_6, UInt<1>("h00")) @[AmoAlu.scala 27:19] - node T_68 = bits(io.rhs, 7, 0) @[AmoAlu.scala 27:66] - node T_69 = cat(T_68, T_68) @[Cat.scala 20:58] - node T_70 = cat(T_69, T_69) @[Cat.scala 20:58] - node T_71 = cat(T_70, T_70) @[Cat.scala 20:58] - node T_73 = eq(T_6, UInt<1>("h01")) @[AmoAlu.scala 27:19] - node T_74 = bits(io.rhs, 15, 0) @[AmoAlu.scala 27:66] - node T_75 = cat(T_74, T_74) @[Cat.scala 20:58] - node T_76 = cat(T_75, T_75) @[Cat.scala 20:58] - node T_78 = eq(T_6, UInt<2>("h02")) @[AmoAlu.scala 27:19] - node T_79 = bits(io.rhs, 31, 0) @[AmoAlu.scala 27:66] - node T_80 = cat(T_79, T_79) @[Cat.scala 20:58] - node T_81 = mux(T_78, T_80, io.rhs) @[AmoAlu.scala 27:13] - node T_82 = mux(T_73, T_76, T_81) @[AmoAlu.scala 27:13] - node T_83 = mux(T_67, T_71, T_82) @[AmoAlu.scala 27:13] - node T_84 = mux(T_65, io.lhs, T_83) @[AmoAlu.scala 100:16] - node T_85 = mux(T_63, T_64, T_84) @[AmoAlu.scala 99:16] - node T_86 = mux(T_61, T_62, T_85) @[AmoAlu.scala 98:16] - node T_87 = mux(T_59, T_60, T_86) @[AmoAlu.scala 97:16] - node out = mux(T_58, adder_out, T_87) @[AmoAlu.scala 96:16] - node T_89 = bits(io.addr, 0, 0) @[AmoAlu.scala 18:27] - node T_91 = mux(T_89, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_93 = geq(T_6, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_96 = mux(T_93, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_97 = or(T_91, T_96) @[AmoAlu.scala 18:46] - node T_98 = bits(io.addr, 0, 0) @[AmoAlu.scala 19:27] - node T_100 = mux(T_98, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_101 = cat(T_97, T_100) @[Cat.scala 20:58] - node T_102 = bits(io.addr, 1, 1) @[AmoAlu.scala 18:27] - node T_104 = mux(T_102, T_101, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_106 = geq(T_6, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_109 = mux(T_106, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_110 = or(T_104, T_109) @[AmoAlu.scala 18:46] - node T_111 = bits(io.addr, 1, 1) @[AmoAlu.scala 19:27] - node T_113 = mux(T_111, UInt<1>("h00"), T_101) @[AmoAlu.scala 19:22] - node T_114 = cat(T_110, T_113) @[Cat.scala 20:58] - node T_115 = bits(io.addr, 2, 2) @[AmoAlu.scala 18:27] - node T_117 = mux(T_115, T_114, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_119 = geq(T_6, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_122 = mux(T_119, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_123 = or(T_117, T_122) @[AmoAlu.scala 18:46] - node T_124 = bits(io.addr, 2, 2) @[AmoAlu.scala 19:27] - node T_126 = mux(T_124, UInt<1>("h00"), T_114) @[AmoAlu.scala 19:22] - node T_127 = cat(T_123, T_126) @[Cat.scala 20:58] - node T_128 = bits(T_127, 0, 0) @[Bitwise.scala 13:51] - node T_129 = bits(T_127, 1, 1) @[Bitwise.scala 13:51] - node T_130 = bits(T_127, 2, 2) @[Bitwise.scala 13:51] - node T_131 = bits(T_127, 3, 3) @[Bitwise.scala 13:51] - node T_132 = bits(T_127, 4, 4) @[Bitwise.scala 13:51] - node T_133 = bits(T_127, 5, 5) @[Bitwise.scala 13:51] - node T_134 = bits(T_127, 6, 6) @[Bitwise.scala 13:51] - node T_135 = bits(T_127, 7, 7) @[Bitwise.scala 13:51] - node T_136 = bits(T_128, 0, 0) @[Bitwise.scala 33:15] - node T_139 = mux(T_136, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_140 = bits(T_129, 0, 0) @[Bitwise.scala 33:15] - node T_143 = mux(T_140, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_144 = bits(T_130, 0, 0) @[Bitwise.scala 33:15] - node T_147 = mux(T_144, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_148 = bits(T_131, 0, 0) @[Bitwise.scala 33:15] - node T_151 = mux(T_148, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_152 = bits(T_132, 0, 0) @[Bitwise.scala 33:15] - node T_155 = mux(T_152, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_156 = bits(T_133, 0, 0) @[Bitwise.scala 33:15] - node T_159 = mux(T_156, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_160 = bits(T_134, 0, 0) @[Bitwise.scala 33:15] - node T_163 = mux(T_160, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_164 = bits(T_135, 0, 0) @[Bitwise.scala 33:15] - node T_167 = mux(T_164, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_168 = cat(T_143, T_139) @[Cat.scala 20:58] - node T_169 = cat(T_151, T_147) @[Cat.scala 20:58] - node T_170 = cat(T_169, T_168) @[Cat.scala 20:58] - node T_171 = cat(T_159, T_155) @[Cat.scala 20:58] - node T_172 = cat(T_167, T_163) @[Cat.scala 20:58] - node T_173 = cat(T_172, T_171) @[Cat.scala 20:58] - node wmask = cat(T_173, T_170) @[Cat.scala 20:58] - node T_174 = and(wmask, out) @[AmoAlu.scala 104:19] - node T_175 = not(wmask) @[AmoAlu.scala 104:27] - node T_176 = and(T_175, io.lhs) @[AmoAlu.scala 104:34] - node T_177 = or(T_174, T_176) @[AmoAlu.scala 104:25] - io.out <= T_177 @[AmoAlu.scala 104:10] - - module DCache : + node T_6 = bits(io.typ, 1, 0) + node T_8 = eq(T_6, UInt<2>("h2")) + node T_9 = bits(io.rhs, 31, 0) + node T_10 = cat(T_9, T_9) + node rhs = mux(T_8, T_10, io.rhs) + node T_11 = eq(io.cmd, UInt<5>("hc")) + node T_12 = eq(io.cmd, UInt<5>("hd")) + node sgned = or(T_11, T_12) + node T_13 = eq(io.cmd, UInt<5>("hd")) + node T_14 = eq(io.cmd, UInt<5>("hf")) + node max = or(T_13, T_14) + node T_15 = eq(io.cmd, UInt<5>("hc")) + node T_16 = eq(io.cmd, UInt<5>("he")) + node min = or(T_15, T_16) + node T_18 = not(UInt<64>("h0")) + node T_19 = bits(io.addr, 2, 2) + node T_20 = shl(T_19, 31) + node T_21 = xor(T_18, T_20) + node T_22 = and(io.lhs, T_21) + node T_23 = and(rhs, T_21) + node T_24 = add(T_22, T_23) + node adder_out = tail(T_24, 1) + node T_25 = bits(io.typ, 0, 0) + node T_27 = eq(T_25, UInt<1>("h0")) + node T_28 = bits(io.addr, 2, 2) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = and(T_27, T_30) + node T_32 = bits(io.lhs, 31, 31) + node T_33 = bits(io.lhs, 63, 63) + node T_34 = mux(T_31, T_32, T_33) + node T_35 = bits(io.addr, 2, 2) + node T_37 = eq(T_35, UInt<1>("h0")) + node T_38 = and(T_27, T_37) + node T_39 = bits(rhs, 31, 31) + node T_40 = bits(rhs, 63, 63) + node T_41 = mux(T_38, T_39, T_40) + node T_42 = bits(io.lhs, 31, 0) + node T_43 = bits(rhs, 31, 0) + node T_44 = lt(T_42, T_43) + node T_45 = bits(io.lhs, 63, 32) + node T_46 = bits(rhs, 63, 32) + node T_47 = lt(T_45, T_46) + node T_48 = bits(io.lhs, 63, 32) + node T_49 = bits(rhs, 63, 32) + node T_50 = eq(T_48, T_49) + node T_51 = bits(io.addr, 2, 2) + node T_52 = mux(T_51, T_47, T_44) + node T_53 = and(T_50, T_44) + node T_54 = or(T_47, T_53) + node T_55 = mux(T_27, T_52, T_54) + node T_56 = eq(T_34, T_41) + node T_57 = mux(sgned, T_34, T_41) + node less = mux(T_56, T_55, T_57) + node T_58 = eq(io.cmd, UInt<5>("h8")) + node T_59 = eq(io.cmd, UInt<5>("hb")) + node T_60 = and(io.lhs, rhs) + node T_61 = eq(io.cmd, UInt<5>("ha")) + node T_62 = or(io.lhs, rhs) + node T_63 = eq(io.cmd, UInt<5>("h9")) + node T_64 = xor(io.lhs, rhs) + node T_65 = mux(less, min, max) + node T_67 = eq(T_6, UInt<1>("h0")) + node T_68 = bits(io.rhs, 7, 0) + node T_69 = cat(T_68, T_68) + node T_70 = cat(T_69, T_69) + node T_71 = cat(T_70, T_70) + node T_73 = eq(T_6, UInt<1>("h1")) + node T_74 = bits(io.rhs, 15, 0) + node T_75 = cat(T_74, T_74) + node T_76 = cat(T_75, T_75) + node T_78 = eq(T_6, UInt<2>("h2")) + node T_79 = bits(io.rhs, 31, 0) + node T_80 = cat(T_79, T_79) + node T_81 = mux(T_78, T_80, io.rhs) + node T_82 = mux(T_73, T_76, T_81) + node T_83 = mux(T_67, T_71, T_82) + node T_84 = mux(T_65, io.lhs, T_83) + node T_85 = mux(T_63, T_64, T_84) + node T_86 = mux(T_61, T_62, T_85) + node T_87 = mux(T_59, T_60, T_86) + node out = mux(T_58, adder_out, T_87) + node T_89 = bits(io.addr, 0, 0) + node T_91 = mux(T_89, UInt<1>("h1"), UInt<1>("h0")) + node T_93 = geq(T_6, UInt<1>("h1")) + node T_96 = mux(T_93, UInt<1>("h1"), UInt<1>("h0")) + node T_97 = or(T_91, T_96) + node T_98 = bits(io.addr, 0, 0) + node T_100 = mux(T_98, UInt<1>("h0"), UInt<1>("h1")) + node T_101 = cat(T_97, T_100) + node T_102 = bits(io.addr, 1, 1) + node T_104 = mux(T_102, T_101, UInt<1>("h0")) + node T_106 = geq(T_6, UInt<2>("h2")) + node T_109 = mux(T_106, UInt<2>("h3"), UInt<1>("h0")) + node T_110 = or(T_104, T_109) + node T_111 = bits(io.addr, 1, 1) + node T_113 = mux(T_111, UInt<1>("h0"), T_101) + node T_114 = cat(T_110, T_113) + node T_115 = bits(io.addr, 2, 2) + node T_117 = mux(T_115, T_114, UInt<1>("h0")) + node T_119 = geq(T_6, UInt<2>("h3")) + node T_122 = mux(T_119, UInt<4>("hf"), UInt<1>("h0")) + node T_123 = or(T_117, T_122) + node T_124 = bits(io.addr, 2, 2) + node T_126 = mux(T_124, UInt<1>("h0"), T_114) + node T_127 = cat(T_123, T_126) + node T_128 = bits(T_127, 0, 0) + node T_129 = bits(T_127, 1, 1) + node T_130 = bits(T_127, 2, 2) + node T_131 = bits(T_127, 3, 3) + node T_132 = bits(T_127, 4, 4) + node T_133 = bits(T_127, 5, 5) + node T_134 = bits(T_127, 6, 6) + node T_135 = bits(T_127, 7, 7) + node T_136 = bits(T_128, 0, 0) + node T_139 = mux(T_136, UInt<8>("hff"), UInt<8>("h0")) + node T_140 = bits(T_129, 0, 0) + node T_143 = mux(T_140, UInt<8>("hff"), UInt<8>("h0")) + node T_144 = bits(T_130, 0, 0) + node T_147 = mux(T_144, UInt<8>("hff"), UInt<8>("h0")) + node T_148 = bits(T_131, 0, 0) + node T_151 = mux(T_148, UInt<8>("hff"), UInt<8>("h0")) + node T_152 = bits(T_132, 0, 0) + node T_155 = mux(T_152, UInt<8>("hff"), UInt<8>("h0")) + node T_156 = bits(T_133, 0, 0) + node T_159 = mux(T_156, UInt<8>("hff"), UInt<8>("h0")) + node T_160 = bits(T_134, 0, 0) + node T_163 = mux(T_160, UInt<8>("hff"), UInt<8>("h0")) + node T_164 = bits(T_135, 0, 0) + node T_167 = mux(T_164, UInt<8>("hff"), UInt<8>("h0")) + node T_168 = cat(T_143, T_139) + node T_169 = cat(T_151, T_147) + node T_170 = cat(T_169, T_168) + node T_171 = cat(T_159, T_155) + node T_172 = cat(T_167, T_163) + node T_173 = cat(T_172, T_171) + node wmask = cat(T_173, T_170) + node T_174 = and(wmask, out) + node T_175 = not(wmask) + node T_176 = and(T_175, io.lhs) + node T_177 = or(T_174, T_176) + io.out <= T_177 + + module DCache : input clk : Clock input reset : UInt<1> - output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}}} - + output io : { flip cpu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, mem : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}}} + + wire T_4091 : UInt<1> + T_4091 is invalid + wire T_3923 : UInt<1> + T_3923 is invalid io is invalid - inst fq of FinishQueue @[dcache.scala 48:18] + inst fq of FinishQueue fq.io is invalid fq.clk <= clk fq.reset <= reset - wire T_1926 : UInt<1> @[Cache.scala 59:29] - T_1926 is invalid @[Cache.scala 59:29] - T_1926 <= UInt<1>("h00") @[Cache.scala 60:11] - reg T_1929 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) - when T_1926 : @[LFSR.scala 19:22] - node T_1930 = bits(T_1929, 0, 0) @[LFSR.scala 19:40] - node T_1931 = bits(T_1929, 2, 2) @[LFSR.scala 19:48] - node T_1932 = xor(T_1930, T_1931) @[LFSR.scala 19:43] - node T_1933 = bits(T_1929, 3, 3) @[LFSR.scala 19:56] - node T_1934 = xor(T_1932, T_1933) @[LFSR.scala 19:51] - node T_1935 = bits(T_1929, 5, 5) @[LFSR.scala 19:64] - node T_1936 = xor(T_1934, T_1935) @[LFSR.scala 19:59] - node T_1937 = bits(T_1929, 15, 1) @[LFSR.scala 19:73] - node T_1938 = cat(T_1936, T_1937) @[Cat.scala 20:58] - T_1929 <= T_1938 @[LFSR.scala 19:29] - skip @[LFSR.scala 19:22] - inst metaReadArb of Arbiter @[dcache.scala 57:27] + wire T_1926 : UInt<1> + T_1926 is invalid + T_1926 <= UInt<1>("h0") + reg T_1929 : UInt<16>, clk with : + reset => (reset, UInt<16>("h1")) + when T_1926 : + node T_1930 = bits(T_1929, 0, 0) + node T_1931 = bits(T_1929, 2, 2) + node T_1932 = xor(T_1930, T_1931) + node T_1933 = bits(T_1929, 3, 3) + node T_1934 = xor(T_1932, T_1933) + node T_1935 = bits(T_1929, 5, 5) + node T_1936 = xor(T_1934, T_1935) + node T_1937 = bits(T_1929, 15, 1) + node T_1938 = cat(T_1936, T_1937) + T_1929 <= T_1938 + inst metaReadArb of Arbiter metaReadArb.io is invalid metaReadArb.clk <= clk metaReadArb.reset <= reset - inst metaWriteArb of Arbiter_1 @[dcache.scala 58:28] + inst metaWriteArb of Arbiter_1 metaWriteArb.io is invalid metaWriteArb.clk <= clk metaWriteArb.reset <= reset - inst data of DCacheDataArray @[dcache.scala 61:20] + inst data of DCacheDataArray data.io is invalid data.clk <= clk data.reset <= reset - inst dataArb of Arbiter_2 @[dcache.scala 62:23] + inst dataArb of Arbiter_2 dataArb.io is invalid dataArb.clk <= clk dataArb.reset <= reset - data.io.req <- dataArb.io.out @[dcache.scala 63:15] - dataArb.io.out.ready <= UInt<1>("h01") @[dcache.scala 64:24] - node T_2220 = and(io.cpu.req.ready, io.cpu.req.valid) @[Decoupled.scala 21:42] - reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + data.io.req <- dataArb.io.out + dataArb.io.out.ready <= UInt<1>("h1") + node T_2220 = and(io.cpu.req.ready, io.cpu.req.valid) + reg s1_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) s1_valid <= T_2220 - node T_2222 = and(io.mem.probe.ready, io.mem.probe.valid) @[Decoupled.scala 21:42] - reg s1_probe : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_2222 = and(io.mem.probe.ready, io.mem.probe.valid) + reg s1_probe : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) s1_probe <= T_2222 - node T_2224 = and(io.mem.probe.ready, io.mem.probe.valid) @[Decoupled.scala 21:42] - reg probe_bits : {addr_block : UInt<26>, p_type : UInt<2>}, clk - when T_2224 : @[Reg.scala 29:19] - probe_bits <- io.mem.probe.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] + node T_2224 = and(io.mem.probe.ready, io.mem.probe.valid) + reg probe_bits : { addr_block : UInt<26>, p_type : UInt<2>}, clk with : + reset => (UInt<1>("h0"), probe_bits) + when T_2224 : + probe_bits <- io.mem.probe.bits wire s1_nack : UInt<1> s1_nack is invalid - s1_nack <= UInt<1>("h00") - node T_2249 = eq(io.cpu.s1_kill, UInt<1>("h00")) @[dcache.scala 70:37] - node T_2250 = and(s1_valid, T_2249) @[dcache.scala 70:34] - node T_2251 = cat(io.cpu.xcpt.pf.ld, io.cpu.xcpt.pf.st) @[dcache.scala 70:69] - node T_2252 = cat(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) @[dcache.scala 70:69] - node T_2253 = cat(T_2252, T_2251) @[dcache.scala 70:69] - node T_2255 = neq(T_2253, UInt<1>("h00")) @[dcache.scala 70:76] - node T_2257 = eq(T_2255, UInt<1>("h00")) @[dcache.scala 70:56] - node s1_valid_masked = and(T_2250, T_2257) @[dcache.scala 70:53] - node T_2259 = eq(s1_nack, UInt<1>("h00")) @[dcache.scala 71:48] - node s1_valid_not_nacked = and(s1_valid_masked, T_2259) @[dcache.scala 71:45] - reg s1_req : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clk - when metaReadArb.io.out.valid : @[dcache.scala 73:35] - s1_req <- io.cpu.req.bits @[dcache.scala 74:12] - node T_2326 = shr(io.cpu.req.bits.addr, 12) @[dcache.scala 75:45] - node T_2327 = bits(io.cpu.req.bits.addr, 5, 0) @[dcache.scala 75:108] - node T_2328 = cat(T_2326, metaReadArb.io.out.bits.idx) @[Cat.scala 20:58] - node T_2329 = cat(T_2328, T_2327) @[Cat.scala 20:58] - s1_req.addr <= T_2329 @[dcache.scala 75:17] - skip @[dcache.scala 73:35] - node T_2330 = eq(s1_req.cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2331 = eq(s1_req.cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2332 = or(T_2330, T_2331) @[Consts.scala 35:41] - node T_2333 = eq(s1_req.cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2334 = or(T_2332, T_2333) @[Consts.scala 35:58] - node T_2335 = bits(s1_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2336 = eq(s1_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2337 = or(T_2335, T_2336) @[Consts.scala 33:33] - node s1_read = or(T_2334, T_2337) @[Consts.scala 35:75] - node T_2338 = eq(s1_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2339 = eq(s1_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2340 = or(T_2338, T_2339) @[Consts.scala 36:42] - node T_2341 = bits(s1_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2342 = eq(s1_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2343 = or(T_2341, T_2342) @[Consts.scala 33:33] - node s1_write = or(T_2340, T_2343) @[Consts.scala 36:59] - node s1_readwrite = or(s1_read, s1_write) @[dcache.scala 79:30] - reg s1_flush_valid : UInt<1>, clk - reg grant_wait : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg release_ack_wait : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg release_state : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - wire pstore1_valid : UInt<1> @[dcache.scala 86:27] - pstore1_valid is invalid @[dcache.scala 86:27] - reg pstore2_valid : UInt<1>, clk - node T_2350 = eq(release_state, UInt<3>("h02")) @[Package.scala 7:47] - node T_2351 = eq(release_state, UInt<3>("h03")) @[Package.scala 7:47] - node inWriteback = or(T_2350, T_2351) @[Package.scala 7:62] - wire releaseWay : UInt @[dcache.scala 89:24] - releaseWay is invalid @[dcache.scala 89:24] - node T_2353 = eq(release_state, UInt<3>("h00")) @[dcache.scala 90:38] - node T_2355 = eq(grant_wait, UInt<1>("h00")) @[dcache.scala 90:54] - node T_2356 = and(T_2353, T_2355) @[dcache.scala 90:51] - node T_2358 = eq(s1_nack, UInt<1>("h00")) @[dcache.scala 90:69] - node T_2359 = and(T_2356, T_2358) @[dcache.scala 90:66] - io.cpu.req.ready <= T_2359 @[dcache.scala 90:20] - node T_2360 = eq(io.cpu.req.bits.cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2361 = eq(io.cpu.req.bits.cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2362 = or(T_2360, T_2361) @[Consts.scala 35:41] - node T_2363 = eq(io.cpu.req.bits.cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2364 = or(T_2362, T_2363) @[Consts.scala 35:58] - node T_2365 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] - node T_2366 = eq(io.cpu.req.bits.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2367 = or(T_2365, T_2366) @[Consts.scala 33:33] - node T_2368 = or(T_2364, T_2367) @[Consts.scala 35:75] - node T_2369 = and(io.cpu.req.valid, T_2368) @[dcache.scala 93:46] - dataArb.io.in[3].valid <= T_2369 @[dcache.scala 93:26] - dataArb.io.in[3].bits.write <= UInt<1>("h00") @[dcache.scala 94:31] - dataArb.io.in[3].bits.addr <= io.cpu.req.bits.addr @[dcache.scala 95:30] - node T_2372 = not(UInt<4>("h00")) @[dcache.scala 96:35] - dataArb.io.in[3].bits.way_en <= T_2372 @[dcache.scala 96:32] - node T_2374 = eq(dataArb.io.in[3].ready, UInt<1>("h00")) @[dcache.scala 97:9] - node T_2375 = eq(io.cpu.req.bits.cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2376 = eq(io.cpu.req.bits.cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2377 = or(T_2375, T_2376) @[Consts.scala 35:41] - node T_2378 = eq(io.cpu.req.bits.cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2379 = or(T_2377, T_2378) @[Consts.scala 35:58] - node T_2380 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] - node T_2381 = eq(io.cpu.req.bits.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2382 = or(T_2380, T_2381) @[Consts.scala 33:33] - node T_2383 = or(T_2379, T_2382) @[Consts.scala 35:75] - node T_2384 = and(T_2374, T_2383) @[dcache.scala 97:33] - when T_2384 : @[dcache.scala 97:65] - io.cpu.req.ready <= UInt<1>("h00") @[dcache.scala 97:84] - skip @[dcache.scala 97:65] - metaReadArb.io.in[2].valid <= io.cpu.req.valid @[dcache.scala 98:30] - node T_2386 = bits(io.cpu.req.bits.addr, 11, 6) @[dcache.scala 99:56] - metaReadArb.io.in[2].bits.idx <= T_2386 @[dcache.scala 99:33] - node T_2388 = not(UInt<4>("h00")) @[dcache.scala 100:39] - metaReadArb.io.in[2].bits.way_en <= T_2388 @[dcache.scala 100:36] - node T_2390 = eq(metaReadArb.io.in[2].ready, UInt<1>("h00")) @[dcache.scala 101:9] - when T_2390 : @[dcache.scala 101:38] - io.cpu.req.ready <= UInt<1>("h00") @[dcache.scala 101:57] - skip @[dcache.scala 101:38] - inst tlb of TLB @[dcache.scala 104:19] + s1_nack <= UInt<1>("h0") + node T_2249 = eq(io.cpu.s1_kill, UInt<1>("h0")) + node T_2250 = and(s1_valid, T_2249) + node T_2251 = cat(io.cpu.xcpt.pf.ld, io.cpu.xcpt.pf.st) + node T_2252 = cat(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) + node T_2253 = cat(T_2252, T_2251) + node T_2255 = neq(T_2253, UInt<1>("h0")) + node T_2257 = eq(T_2255, UInt<1>("h0")) + node s1_valid_masked = and(T_2250, T_2257) + node T_2259 = eq(s1_nack, UInt<1>("h0")) + node s1_valid_not_nacked = and(s1_valid_masked, T_2259) + reg s1_req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clk with : + reset => (UInt<1>("h0"), s1_req) + when metaReadArb.io.out.valid : + s1_req <- io.cpu.req.bits + node T_2326 = shr(io.cpu.req.bits.addr, 12) + node T_2327 = bits(io.cpu.req.bits.addr, 5, 0) + node T_2328 = cat(T_2326, metaReadArb.io.out.bits.idx) + node T_2329 = cat(T_2328, T_2327) + s1_req.addr <= T_2329 + node T_2330 = eq(s1_req.cmd, UInt<5>("h0")) + node T_2331 = eq(s1_req.cmd, UInt<5>("h6")) + node T_2332 = or(T_2330, T_2331) + node T_2333 = eq(s1_req.cmd, UInt<5>("h7")) + node T_2334 = or(T_2332, T_2333) + node T_2335 = bits(s1_req.cmd, 3, 3) + node T_2336 = eq(s1_req.cmd, UInt<5>("h4")) + node T_2337 = or(T_2335, T_2336) + node s1_read = or(T_2334, T_2337) + node T_2338 = eq(s1_req.cmd, UInt<5>("h1")) + node T_2339 = eq(s1_req.cmd, UInt<5>("h7")) + node T_2340 = or(T_2338, T_2339) + node T_2341 = bits(s1_req.cmd, 3, 3) + node T_2342 = eq(s1_req.cmd, UInt<5>("h4")) + node T_2343 = or(T_2341, T_2342) + node s1_write = or(T_2340, T_2343) + node s1_readwrite = or(s1_read, s1_write) + reg s1_flush_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), s1_flush_valid) + reg grant_wait : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg release_ack_wait : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg release_state : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + wire pstore1_valid : UInt<1> + pstore1_valid is invalid + reg pstore2_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), pstore2_valid) + node T_2350 = eq(release_state, UInt<3>("h2")) + node T_2351 = eq(release_state, UInt<3>("h3")) + node inWriteback = or(T_2350, T_2351) + wire releaseWay : UInt + releaseWay is invalid + node T_2353 = eq(release_state, UInt<3>("h0")) + node T_2355 = eq(grant_wait, UInt<1>("h0")) + node T_2356 = and(T_2353, T_2355) + node T_2358 = eq(s1_nack, UInt<1>("h0")) + node T_2359 = and(T_2356, T_2358) + io.cpu.req.ready <= T_2359 + node T_2360 = eq(io.cpu.req.bits.cmd, UInt<5>("h0")) + node T_2361 = eq(io.cpu.req.bits.cmd, UInt<5>("h6")) + node T_2362 = or(T_2360, T_2361) + node T_2363 = eq(io.cpu.req.bits.cmd, UInt<5>("h7")) + node T_2364 = or(T_2362, T_2363) + node T_2365 = bits(io.cpu.req.bits.cmd, 3, 3) + node T_2366 = eq(io.cpu.req.bits.cmd, UInt<5>("h4")) + node T_2367 = or(T_2365, T_2366) + node T_2368 = or(T_2364, T_2367) + node T_2369 = and(io.cpu.req.valid, T_2368) + dataArb.io.in[3].valid <= T_2369 + dataArb.io.in[3].bits.write <= UInt<1>("h0") + dataArb.io.in[3].bits.addr <= io.cpu.req.bits.addr + node T_2372 = not(UInt<4>("h0")) + dataArb.io.in[3].bits.way_en <= T_2372 + node T_2374 = eq(dataArb.io.in[3].ready, UInt<1>("h0")) + node T_2375 = eq(io.cpu.req.bits.cmd, UInt<5>("h0")) + node T_2376 = eq(io.cpu.req.bits.cmd, UInt<5>("h6")) + node T_2377 = or(T_2375, T_2376) + node T_2378 = eq(io.cpu.req.bits.cmd, UInt<5>("h7")) + node T_2379 = or(T_2377, T_2378) + node T_2380 = bits(io.cpu.req.bits.cmd, 3, 3) + node T_2381 = eq(io.cpu.req.bits.cmd, UInt<5>("h4")) + node T_2382 = or(T_2380, T_2381) + node T_2383 = or(T_2379, T_2382) + node T_2384 = and(T_2374, T_2383) + when T_2384 : + io.cpu.req.ready <= UInt<1>("h0") + metaReadArb.io.in[2].valid <= io.cpu.req.valid + node T_2386 = bits(io.cpu.req.bits.addr, 11, 6) + metaReadArb.io.in[2].bits.idx <= T_2386 + node T_2388 = not(UInt<4>("h0")) + metaReadArb.io.in[2].bits.way_en <= T_2388 + node T_2390 = eq(metaReadArb.io.in[2].ready, UInt<1>("h0")) + when T_2390 : + io.cpu.req.ready <= UInt<1>("h0") + inst tlb of TLB tlb.io is invalid tlb.clk <= clk tlb.reset <= reset - io.ptw <- tlb.io.ptw @[dcache.scala 105:10] - node T_2392 = and(s1_valid_masked, s1_readwrite) @[dcache.scala 106:39] - tlb.io.req.valid <= T_2392 @[dcache.scala 106:20] - tlb.io.req.bits.passthrough <= s1_req.phys @[dcache.scala 107:31] - node T_2393 = shr(s1_req.addr, 12) @[dcache.scala 108:38] - tlb.io.req.bits.vpn <= T_2393 @[dcache.scala 108:23] - tlb.io.req.bits.instruction <= UInt<1>("h00") @[dcache.scala 109:31] - tlb.io.req.bits.store <= s1_write @[dcache.scala 110:25] - node T_2396 = eq(tlb.io.req.ready, UInt<1>("h00")) @[dcache.scala 111:9] - node T_2398 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) @[dcache.scala 111:30] - node T_2399 = and(T_2396, T_2398) @[dcache.scala 111:27] - when T_2399 : @[dcache.scala 111:53] - io.cpu.req.ready <= UInt<1>("h00") @[dcache.scala 111:72] - skip @[dcache.scala 111:53] - node T_2401 = and(s1_valid, s1_readwrite) @[dcache.scala 112:18] - node T_2402 = and(T_2401, tlb.io.resp.miss) @[dcache.scala 112:34] - when T_2402 : @[dcache.scala 112:55] - s1_nack <= UInt<1>("h01") @[dcache.scala 112:65] - skip @[dcache.scala 112:55] - node T_2404 = bits(s1_req.addr, 11, 0) @[dcache.scala 114:50] - node s1_paddr = cat(tlb.io.resp.ppn, T_2404) @[Cat.scala 20:58] - node T_2405 = shr(probe_bits.addr_block, 6) @[dcache.scala 115:52] - node T_2406 = bits(s1_paddr, 31, 12) @[dcache.scala 115:72] - node s1_tag = mux(s1_probe, T_2405, T_2406) @[dcache.scala 115:19] - node T_2407 = bits(T_1929, 1, 0) @[Cache.scala 63:44] + io.ptw <- tlb.io.ptw + node T_2392 = and(s1_valid_masked, s1_readwrite) + tlb.io.req.valid <= T_2392 + tlb.io.req.bits.passthrough <= s1_req.phys + node T_2393 = shr(s1_req.addr, 12) + tlb.io.req.bits.vpn <= T_2393 + tlb.io.req.bits.instruction <= UInt<1>("h0") + tlb.io.req.bits.store <= s1_write + node T_2396 = eq(tlb.io.req.ready, UInt<1>("h0")) + node T_2398 = eq(io.cpu.req.bits.phys, UInt<1>("h0")) + node T_2399 = and(T_2396, T_2398) + when T_2399 : + io.cpu.req.ready <= UInt<1>("h0") + node T_2401 = and(s1_valid, s1_readwrite) + node T_2402 = and(T_2401, tlb.io.resp.miss) + when T_2402 : + s1_nack <= UInt<1>("h1") + node T_2404 = bits(s1_req.addr, 11, 0) + node s1_paddr = cat(tlb.io.resp.ppn, T_2404) + node T_2405 = shr(probe_bits.addr_block, 6) + node T_2406 = bits(s1_paddr, 31, 12) + node s1_tag = mux(s1_probe, T_2405, T_2406) + node T_2407 = bits(T_1929, 1, 0) wire s1_victim_way : UInt s1_victim_way is invalid s1_victim_way <= T_2407 - inst MetadataArray_1 of MetadataArray @[dcache.scala 126:24] + inst MetadataArray_1 of MetadataArray MetadataArray_1.io is invalid MetadataArray_1.clk <= clk MetadataArray_1.reset <= reset - MetadataArray_1.io.read <- metaReadArb.io.out @[dcache.scala 127:20] - MetadataArray_1.io.write <- metaWriteArb.io.out @[dcache.scala 128:21] - node T_2408 = neq(MetadataArray_1.io.resp[0].coh.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2409 = eq(MetadataArray_1.io.resp[0].tag, s1_tag) @[dcache.scala 130:66] - node T_2410 = and(T_2408, T_2409) @[dcache.scala 130:57] - node T_2411 = neq(MetadataArray_1.io.resp[1].coh.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2412 = eq(MetadataArray_1.io.resp[1].tag, s1_tag) @[dcache.scala 130:66] - node T_2413 = and(T_2411, T_2412) @[dcache.scala 130:57] - node T_2414 = neq(MetadataArray_1.io.resp[2].coh.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2415 = eq(MetadataArray_1.io.resp[2].tag, s1_tag) @[dcache.scala 130:66] - node T_2416 = and(T_2414, T_2415) @[dcache.scala 130:57] - node T_2417 = neq(MetadataArray_1.io.resp[3].coh.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2418 = eq(MetadataArray_1.io.resp[3].tag, s1_tag) @[dcache.scala 130:66] - node T_2419 = and(T_2417, T_2418) @[dcache.scala 130:57] - node T_2420 = cat(T_2413, T_2410) @[Cat.scala 20:58] - node T_2421 = cat(T_2419, T_2416) @[Cat.scala 20:58] - node s1_hit_way = cat(T_2421, T_2420) @[Cat.scala 20:58] - wire T_2445 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2445 is invalid @[Metadata.scala 158:20] - T_2445.state <= UInt<1>("h00") @[Metadata.scala 159:16] - node T_2467 = eq(MetadataArray_1.io.resp[0].tag, s1_tag) @[dcache.scala 132:36] - node T_2469 = mux(T_2467, MetadataArray_1.io.resp[0].coh.state, UInt<1>("h00")) @[dcache.scala 132:29] - node T_2470 = eq(MetadataArray_1.io.resp[1].tag, s1_tag) @[dcache.scala 132:36] - node T_2472 = mux(T_2470, MetadataArray_1.io.resp[1].coh.state, UInt<1>("h00")) @[dcache.scala 132:29] - node T_2473 = eq(MetadataArray_1.io.resp[2].tag, s1_tag) @[dcache.scala 132:36] - node T_2475 = mux(T_2473, MetadataArray_1.io.resp[2].coh.state, UInt<1>("h00")) @[dcache.scala 132:29] - node T_2476 = eq(MetadataArray_1.io.resp[3].tag, s1_tag) @[dcache.scala 132:36] - node T_2478 = mux(T_2476, MetadataArray_1.io.resp[3].coh.state, UInt<1>("h00")) @[dcache.scala 132:29] - node T_2479 = or(T_2469, T_2472) @[dcache.scala 133:19] - node T_2480 = or(T_2479, T_2475) @[dcache.scala 133:19] - node T_2481 = or(T_2480, T_2478) @[dcache.scala 133:19] - wire s1_hit_state : {state : UInt<2>} @[dcache.scala 131:57] - s1_hit_state is invalid @[dcache.scala 131:57] - node T_2525 = bits(T_2481, 1, 0) @[dcache.scala 131:57] - s1_hit_state.state <= T_2525 @[dcache.scala 131:57] - node s1_data_way = mux(inWriteback, releaseWay, s1_hit_way) @[dcache.scala 136:24] - node T_2609 = bits(s1_data_way, 0, 0) @[Mux.scala 20:36] - node T_2610 = bits(s1_data_way, 1, 1) @[Mux.scala 20:36] - node T_2611 = bits(s1_data_way, 2, 2) @[Mux.scala 20:36] - node T_2612 = bits(s1_data_way, 3, 3) @[Mux.scala 20:36] - node T_2614 = mux(T_2609, data.io.resp[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2616 = mux(T_2610, data.io.resp[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2618 = mux(T_2611, data.io.resp[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2620 = mux(T_2612, data.io.resp[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2622 = or(T_2614, T_2616) @[Mux.scala 18:72] - node T_2623 = or(T_2622, T_2618) @[Mux.scala 18:72] - node T_2624 = or(T_2623, T_2620) @[Mux.scala 18:72] + MetadataArray_1.io.read <- metaReadArb.io.out + MetadataArray_1.io.write <- metaWriteArb.io.out + node T_2408 = neq(MetadataArray_1.io.resp[0].coh.state, UInt<2>("h0")) + node T_2409 = eq(MetadataArray_1.io.resp[0].tag, s1_tag) + node T_2410 = and(T_2408, T_2409) + node T_2411 = neq(MetadataArray_1.io.resp[1].coh.state, UInt<2>("h0")) + node T_2412 = eq(MetadataArray_1.io.resp[1].tag, s1_tag) + node T_2413 = and(T_2411, T_2412) + node T_2414 = neq(MetadataArray_1.io.resp[2].coh.state, UInt<2>("h0")) + node T_2415 = eq(MetadataArray_1.io.resp[2].tag, s1_tag) + node T_2416 = and(T_2414, T_2415) + node T_2417 = neq(MetadataArray_1.io.resp[3].coh.state, UInt<2>("h0")) + node T_2418 = eq(MetadataArray_1.io.resp[3].tag, s1_tag) + node T_2419 = and(T_2417, T_2418) + node T_2420 = cat(T_2413, T_2410) + node T_2421 = cat(T_2419, T_2416) + node s1_hit_way = cat(T_2421, T_2420) + wire T_2445 : { state : UInt<2>} + T_2445 is invalid + T_2445.state <= UInt<1>("h0") + node T_2467 = eq(MetadataArray_1.io.resp[0].tag, s1_tag) + node T_2469 = mux(T_2467, MetadataArray_1.io.resp[0].coh.state, UInt<1>("h0")) + node T_2470 = eq(MetadataArray_1.io.resp[1].tag, s1_tag) + node T_2472 = mux(T_2470, MetadataArray_1.io.resp[1].coh.state, UInt<1>("h0")) + node T_2473 = eq(MetadataArray_1.io.resp[2].tag, s1_tag) + node T_2475 = mux(T_2473, MetadataArray_1.io.resp[2].coh.state, UInt<1>("h0")) + node T_2476 = eq(MetadataArray_1.io.resp[3].tag, s1_tag) + node T_2478 = mux(T_2476, MetadataArray_1.io.resp[3].coh.state, UInt<1>("h0")) + node T_2479 = or(T_2469, T_2472) + node T_2480 = or(T_2479, T_2475) + node T_2481 = or(T_2480, T_2478) + wire s1_hit_state : { state : UInt<2>} + s1_hit_state is invalid + node T_2525 = bits(T_2481, 1, 0) + s1_hit_state.state <= T_2525 + node s1_data_way = mux(inWriteback, releaseWay, s1_hit_way) + node T_2609 = bits(s1_data_way, 0, 0) + node T_2610 = bits(s1_data_way, 1, 1) + node T_2611 = bits(s1_data_way, 2, 2) + node T_2612 = bits(s1_data_way, 3, 3) + node T_2614 = mux(T_2609, data.io.resp[0], UInt<1>("h0")) + node T_2616 = mux(T_2610, data.io.resp[1], UInt<1>("h0")) + node T_2618 = mux(T_2611, data.io.resp[2], UInt<1>("h0")) + node T_2620 = mux(T_2612, data.io.resp[3], UInt<1>("h0")) + node T_2622 = or(T_2614, T_2616) + node T_2623 = or(T_2622, T_2618) + node T_2624 = or(T_2623, T_2620) wire s1_data : UInt<64> s1_data is invalid - s1_data <= T_2624 @[Mux.scala 18:72] - reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + s1_data <= T_2624 + reg s2_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) s2_valid <= s1_valid_masked - reg s2_probe : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg s2_probe : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) s2_probe <= s1_probe - node T_2627 = or(s1_probe, s2_probe) @[dcache.scala 141:34] - node T_2628 = neq(release_state, UInt<3>("h00")) @[dcache.scala 141:63] - node releaseInFlight = or(T_2627, T_2628) @[dcache.scala 141:46] - node T_2630 = eq(s1_nack, UInt<1>("h00")) @[dcache.scala 142:48] - reg T_2631 : UInt<1>, clk + node T_2627 = or(s1_probe, s2_probe) + node T_2628 = neq(release_state, UInt<3>("h0")) + node releaseInFlight = or(T_2627, T_2628) + node T_2630 = eq(s1_nack, UInt<1>("h0")) + reg T_2631 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_2631) T_2631 <= T_2630 - node s2_valid_masked = and(s2_valid, T_2631) @[dcache.scala 142:34] - reg s2_req : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clk - reg s2_uncached : UInt<1>, clk - node T_2699 = or(s1_valid_not_nacked, s1_flush_valid) @[dcache.scala 145:29] - when T_2699 : @[dcache.scala 145:48] - s2_req <- s1_req @[dcache.scala 146:12] - s2_req.addr <= s1_paddr @[dcache.scala 147:17] - node T_2701 = eq(tlb.io.resp.cacheable, UInt<1>("h00")) @[dcache.scala 148:20] - node T_2703 = or(T_2701, UInt<1>("h00")) @[dcache.scala 148:43] - s2_uncached <= T_2703 @[dcache.scala 148:17] - skip @[dcache.scala 145:48] - node T_2704 = eq(s2_req.cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2705 = eq(s2_req.cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2706 = or(T_2704, T_2705) @[Consts.scala 35:41] - node T_2707 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2708 = or(T_2706, T_2707) @[Consts.scala 35:58] - node T_2709 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2710 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2711 = or(T_2709, T_2710) @[Consts.scala 33:33] - node s2_read = or(T_2708, T_2711) @[Consts.scala 35:75] - node T_2712 = eq(s2_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2713 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2714 = or(T_2712, T_2713) @[Consts.scala 36:42] - node T_2715 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2716 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2717 = or(T_2715, T_2716) @[Consts.scala 33:33] - node s2_write = or(T_2714, T_2717) @[Consts.scala 36:59] - node s2_readwrite = or(s2_read, s2_write) @[dcache.scala 152:30] - reg s2_flush_valid : UInt<1>, clk + node s2_valid_masked = and(s2_valid, T_2631) + reg s2_req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}, clk with : + reset => (UInt<1>("h0"), s2_req) + reg s2_uncached : UInt<1>, clk with : + reset => (UInt<1>("h0"), s2_uncached) + node T_2699 = or(s1_valid_not_nacked, s1_flush_valid) + when T_2699 : + s2_req <- s1_req + s2_req.addr <= s1_paddr + node T_2701 = eq(tlb.io.resp.cacheable, UInt<1>("h0")) + node T_2703 = or(T_2701, UInt<1>("h0")) + s2_uncached <= T_2703 + node T_2704 = eq(s2_req.cmd, UInt<5>("h0")) + node T_2705 = eq(s2_req.cmd, UInt<5>("h6")) + node T_2706 = or(T_2704, T_2705) + node T_2707 = eq(s2_req.cmd, UInt<5>("h7")) + node T_2708 = or(T_2706, T_2707) + node T_2709 = bits(s2_req.cmd, 3, 3) + node T_2710 = eq(s2_req.cmd, UInt<5>("h4")) + node T_2711 = or(T_2709, T_2710) + node s2_read = or(T_2708, T_2711) + node T_2712 = eq(s2_req.cmd, UInt<5>("h1")) + node T_2713 = eq(s2_req.cmd, UInt<5>("h7")) + node T_2714 = or(T_2712, T_2713) + node T_2715 = bits(s2_req.cmd, 3, 3) + node T_2716 = eq(s2_req.cmd, UInt<5>("h4")) + node T_2717 = or(T_2715, T_2716) + node s2_write = or(T_2714, T_2717) + node s2_readwrite = or(s2_read, s2_write) + reg s2_flush_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), s2_flush_valid) s2_flush_valid <= s1_flush_valid - node T_2718 = or(s1_valid, inWriteback) @[dcache.scala 154:45] - reg s2_data : UInt<64>, clk - when T_2718 : @[Reg.scala 29:19] - s2_data <= s1_data @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg s2_probe_way : UInt<4>, clk - when s1_probe : @[Reg.scala 29:19] - s2_probe_way <= s1_hit_way @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg s2_probe_state : {state : UInt<2>}, clk - when s1_probe : @[Reg.scala 29:19] - s2_probe_state <- s1_hit_state @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg s2_hit_way : UInt<4>, clk - when s1_valid_not_nacked : @[Reg.scala 29:19] - s2_hit_way <= s1_hit_way @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg s2_hit_state : {state : UInt<2>}, clk - when s1_valid_not_nacked : @[Reg.scala 29:19] - s2_hit_state <- s1_hit_state @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2761 = eq(s2_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2762 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2763 = or(T_2761, T_2762) @[Consts.scala 36:42] - node T_2764 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2765 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2766 = or(T_2764, T_2765) @[Consts.scala 33:33] - node T_2767 = or(T_2763, T_2766) @[Consts.scala 36:59] - node T_2768 = eq(s2_req.cmd, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2769 = or(T_2767, T_2768) @[Consts.scala 37:47] - node T_2770 = eq(s2_req.cmd, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2771 = or(T_2769, T_2770) @[Consts.scala 37:64] - node T_2772 = eq(s2_hit_state.state, UInt<2>("h01")) @[Package.scala 7:47] - node T_2773 = eq(s2_hit_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2774 = or(T_2772, T_2773) @[Package.scala 7:62] - node T_2775 = eq(s2_hit_state.state, UInt<2>("h01")) @[Package.scala 7:47] - node T_2776 = eq(s2_hit_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2777 = or(T_2775, T_2776) @[Package.scala 7:62] - node s2_hit = mux(T_2771, T_2774, T_2777) @[Policies.scala 58:8] - node T_2778 = and(s2_valid_masked, s2_readwrite) @[dcache.scala 160:38] - node s2_valid_hit = and(T_2778, s2_hit) @[dcache.scala 160:54] - node T_2779 = and(s2_valid_masked, s2_readwrite) @[dcache.scala 161:39] - node T_2781 = eq(s2_hit, UInt<1>("h00")) @[dcache.scala 161:58] - node T_2782 = and(T_2779, T_2781) @[dcache.scala 161:55] - node T_2783 = or(pstore1_valid, pstore2_valid) @[dcache.scala 161:85] - node T_2785 = eq(T_2783, UInt<1>("h00")) @[dcache.scala 161:69] - node T_2786 = and(T_2782, T_2785) @[dcache.scala 161:66] - node T_2788 = eq(release_ack_wait, UInt<1>("h00")) @[dcache.scala 161:106] - node s2_valid_miss = and(T_2786, T_2788) @[dcache.scala 161:103] - node T_2790 = eq(s2_uncached, UInt<1>("h00")) @[dcache.scala 162:47] - node s2_valid_cached_miss = and(s2_valid_miss, T_2790) @[dcache.scala 162:44] - node s2_victimize = or(s2_valid_cached_miss, s2_flush_valid) @[dcache.scala 163:43] - node s2_valid_uncached = and(s2_valid_miss, s2_uncached) @[dcache.scala 164:41] - node T_2791 = neq(s2_hit_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2793 = eq(s2_flush_valid, UInt<1>("h00")) @[dcache.scala 165:53] - node T_2794 = and(T_2791, T_2793) @[dcache.scala 165:50] - node T_2795 = or(s1_valid_not_nacked, s1_flush_valid) @[dcache.scala 165:136] - reg T_2796 : UInt, clk - when T_2795 : @[Reg.scala 29:19] - T_2796 <= s1_victim_way @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2798 = dshl(UInt<1>("h01"), T_2796) @[OneHot.scala 44:15] - node s2_victim_way = mux(T_2794, s2_hit_way, T_2798) @[dcache.scala 165:26] - node T_2799 = or(s1_valid_not_nacked, s1_flush_valid) @[dcache.scala 166:73] - reg s2_victim_tag : UInt<20>, clk - when T_2799 : @[Reg.scala 29:19] - s2_victim_tag <= MetadataArray_1.io.resp[s1_victim_way].tag @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2800 = neq(s2_hit_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_2802 = eq(s2_flush_valid, UInt<1>("h00")) @[dcache.scala 167:55] - node T_2803 = and(T_2800, T_2802) @[dcache.scala 167:52] - node T_2804 = or(s1_valid_not_nacked, s1_flush_valid) @[dcache.scala 167:136] - reg T_2805 : {state : UInt<2>}, clk - when T_2804 : @[Reg.scala 29:19] - T_2805 <- MetadataArray_1.io.resp[s1_victim_way].coh @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node s2_victim_state = mux(T_2803, s2_hit_state, T_2805) @[dcache.scala 167:28] - node s2_victim_valid = neq(s2_victim_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node s2_victim_dirty = eq(s2_victim_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2848 = eq(s2_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2849 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2850 = or(T_2848, T_2849) @[Consts.scala 36:42] - node T_2851 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_2852 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2853 = or(T_2851, T_2852) @[Consts.scala 33:33] - node T_2854 = or(T_2850, T_2853) @[Consts.scala 36:59] - node T_2855 = mux(T_2854, UInt<2>("h02"), s2_hit_state.state) @[Policies.scala 257:23] - wire s2_new_hit_state : {state : UInt<2>} @[Metadata.scala 158:20] - s2_new_hit_state is invalid @[Metadata.scala 158:20] - s2_new_hit_state.state <= T_2855 @[Metadata.scala 159:16] - node T_2899 = eq(s2_hit_state.state, s2_new_hit_state.state) @[Metadata.scala 30:51] - node s2_update_meta = eq(T_2899, UInt<1>("h00")) @[Metadata.scala 31:40] - node T_2902 = eq(s2_valid_hit, UInt<1>("h00")) @[dcache.scala 172:33] - node T_2903 = and(s2_valid, T_2902) @[dcache.scala 172:30] - node T_2904 = and(s2_valid_uncached, io.mem.acquire.ready) @[dcache.scala 172:70] - node T_2906 = eq(T_2904, UInt<1>("h00")) @[dcache.scala 172:50] - node T_2907 = and(T_2903, T_2906) @[dcache.scala 172:47] - io.cpu.s2_nack <= T_2907 @[dcache.scala 172:18] - node T_2909 = eq(s2_valid_hit, UInt<1>("h00")) @[dcache.scala 173:22] - node T_2910 = or(T_2909, s2_update_meta) @[dcache.scala 173:36] - node T_2911 = and(s2_valid, T_2910) @[dcache.scala 173:18] - when T_2911 : @[dcache.scala 173:56] - s1_nack <= UInt<1>("h01") @[dcache.scala 173:66] - skip @[dcache.scala 173:56] - node T_2914 = bits(s1_req.typ, 1, 0) @[AmoAlu.scala 11:17] - node T_2916 = dshl(UInt<1>("h01"), T_2914) @[AmoAlu.scala 13:23] - node T_2918 = sub(T_2916, UInt<1>("h01")) @[AmoAlu.scala 13:32] - node T_2919 = tail(T_2918, 1) @[AmoAlu.scala 13:32] - node T_2920 = bits(T_2919, 2, 0) @[AmoAlu.scala 13:42] - node T_2921 = and(s1_req.addr, T_2920) @[AmoAlu.scala 13:11] - node T_2923 = neq(T_2921, UInt<1>("h00")) @[AmoAlu.scala 13:65] - node T_2924 = and(s1_read, T_2923) @[dcache.scala 177:32] - io.cpu.xcpt.ma.ld <= T_2924 @[dcache.scala 177:21] - node T_2926 = dshl(UInt<1>("h01"), T_2914) @[AmoAlu.scala 13:23] - node T_2928 = sub(T_2926, UInt<1>("h01")) @[AmoAlu.scala 13:32] - node T_2929 = tail(T_2928, 1) @[AmoAlu.scala 13:32] - node T_2930 = bits(T_2929, 2, 0) @[AmoAlu.scala 13:42] - node T_2931 = and(s1_req.addr, T_2930) @[AmoAlu.scala 13:11] - node T_2933 = neq(T_2931, UInt<1>("h00")) @[AmoAlu.scala 13:65] - node T_2934 = and(s1_write, T_2933) @[dcache.scala 178:33] - io.cpu.xcpt.ma.st <= T_2934 @[dcache.scala 178:21] - node T_2935 = and(s1_read, tlb.io.resp.xcpt_ld) @[dcache.scala 179:32] - io.cpu.xcpt.pf.ld <= T_2935 @[dcache.scala 179:21] - node T_2936 = and(s1_write, tlb.io.resp.xcpt_st) @[dcache.scala 180:33] - io.cpu.xcpt.pf.st <= T_2936 @[dcache.scala 180:21] - node T_2938 = eq(s2_req.cmd, UInt<5>("h06")) @[dcache.scala 183:48] - node s2_lr = and(UInt<1>("h01"), T_2938) @[dcache.scala 183:34] - node T_2940 = eq(s2_req.cmd, UInt<5>("h07")) @[dcache.scala 184:48] - node s2_sc = and(UInt<1>("h01"), T_2940) @[dcache.scala 184:34] - reg lrscCount : UInt, clk with : (reset => (reset, UInt<1>("h00"))) - node lrscValid = gt(lrscCount, UInt<1>("h00")) @[dcache.scala 186:29] - reg lrscAddr : UInt, clk - node T_2944 = shr(s2_req.addr, 6) @[dcache.scala 188:70] - node T_2945 = eq(lrscAddr, T_2944) @[dcache.scala 188:53] - node T_2946 = and(lrscValid, T_2945) @[dcache.scala 188:41] - node T_2948 = eq(T_2946, UInt<1>("h00")) @[dcache.scala 188:29] - node s2_sc_fail = and(s2_sc, T_2948) @[dcache.scala 188:26] - node T_2949 = and(s2_valid_hit, s2_lr) @[dcache.scala 189:22] - when T_2949 : @[dcache.scala 189:32] - lrscCount <= UInt<5>("h01f") @[dcache.scala 190:15] - node T_2951 = shr(s2_req.addr, 6) @[dcache.scala 191:29] - lrscAddr <= T_2951 @[dcache.scala 191:14] - skip @[dcache.scala 189:32] - when lrscValid : @[dcache.scala 193:20] - node T_2953 = sub(lrscCount, UInt<1>("h01")) @[dcache.scala 193:45] - node T_2954 = tail(T_2953, 1) @[dcache.scala 193:45] - lrscCount <= T_2954 @[dcache.scala 193:32] - skip @[dcache.scala 193:20] - node T_2955 = and(s2_valid_hit, s2_sc) @[dcache.scala 194:23] - node T_2956 = or(T_2955, io.cpu.invalidate_lr) @[dcache.scala 194:33] - when T_2956 : @[dcache.scala 194:58] - lrscCount <= UInt<1>("h00") @[dcache.scala 194:70] - skip @[dcache.scala 194:58] - node T_2958 = and(s1_valid_not_nacked, s1_write) @[dcache.scala 197:63] - reg pstore1_cmd : UInt<5>, clk - when T_2958 : @[Reg.scala 29:19] - pstore1_cmd <= s1_req.cmd @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2959 = and(s1_valid_not_nacked, s1_write) @[dcache.scala 198:63] - reg pstore1_typ : UInt<3>, clk - when T_2959 : @[Reg.scala 29:19] - pstore1_typ <= s1_req.typ @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2960 = and(s1_valid_not_nacked, s1_write) @[dcache.scala 199:62] - reg pstore1_addr : UInt<32>, clk - when T_2960 : @[Reg.scala 29:19] - pstore1_addr <= s1_paddr @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2961 = and(s1_valid_not_nacked, s1_write) @[dcache.scala 200:68] - reg pstore1_data : UInt<64>, clk - when T_2961 : @[Reg.scala 29:19] - pstore1_data <= io.cpu.s1_data @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2962 = and(s1_valid_not_nacked, s1_write) @[dcache.scala 201:63] - reg pstore1_way : UInt<4>, clk - when T_2962 : @[Reg.scala 29:19] - pstore1_way <= s1_hit_way @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_2963 = bits(pstore1_typ, 1, 0) @[AmoAlu.scala 11:17] - node T_2965 = eq(T_2963, UInt<1>("h00")) @[AmoAlu.scala 27:19] - node T_2966 = bits(pstore1_data, 7, 0) @[AmoAlu.scala 27:66] - node T_2967 = cat(T_2966, T_2966) @[Cat.scala 20:58] - node T_2968 = cat(T_2967, T_2967) @[Cat.scala 20:58] - node T_2969 = cat(T_2968, T_2968) @[Cat.scala 20:58] - node T_2971 = eq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 27:19] - node T_2972 = bits(pstore1_data, 15, 0) @[AmoAlu.scala 27:66] - node T_2973 = cat(T_2972, T_2972) @[Cat.scala 20:58] - node T_2974 = cat(T_2973, T_2973) @[Cat.scala 20:58] - node T_2976 = eq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 27:19] - node T_2977 = bits(pstore1_data, 31, 0) @[AmoAlu.scala 27:66] - node T_2978 = cat(T_2977, T_2977) @[Cat.scala 20:58] - node T_2979 = mux(T_2976, T_2978, pstore1_data) @[AmoAlu.scala 27:13] - node T_2980 = mux(T_2971, T_2974, T_2979) @[AmoAlu.scala 27:13] - node T_2981 = mux(T_2965, T_2969, T_2980) @[AmoAlu.scala 27:13] + node T_2718 = or(s1_valid, inWriteback) + reg s2_data : UInt<64>, clk with : + reset => (UInt<1>("h0"), s2_data) + when T_2718 : + s2_data <= s1_data + reg s2_probe_way : UInt<4>, clk with : + reset => (UInt<1>("h0"), s2_probe_way) + when s1_probe : + s2_probe_way <= s1_hit_way + reg s2_probe_state : { state : UInt<2>}, clk with : + reset => (UInt<1>("h0"), s2_probe_state) + when s1_probe : + s2_probe_state <- s1_hit_state + reg s2_hit_way : UInt<4>, clk with : + reset => (UInt<1>("h0"), s2_hit_way) + when s1_valid_not_nacked : + s2_hit_way <= s1_hit_way + reg s2_hit_state : { state : UInt<2>}, clk with : + reset => (UInt<1>("h0"), s2_hit_state) + when s1_valid_not_nacked : + s2_hit_state <- s1_hit_state + node T_2761 = eq(s2_req.cmd, UInt<5>("h1")) + node T_2762 = eq(s2_req.cmd, UInt<5>("h7")) + node T_2763 = or(T_2761, T_2762) + node T_2764 = bits(s2_req.cmd, 3, 3) + node T_2765 = eq(s2_req.cmd, UInt<5>("h4")) + node T_2766 = or(T_2764, T_2765) + node T_2767 = or(T_2763, T_2766) + node T_2768 = eq(s2_req.cmd, UInt<5>("h3")) + node T_2769 = or(T_2767, T_2768) + node T_2770 = eq(s2_req.cmd, UInt<5>("h6")) + node T_2771 = or(T_2769, T_2770) + node T_2772 = eq(s2_hit_state.state, UInt<2>("h1")) + node T_2773 = eq(s2_hit_state.state, UInt<2>("h2")) + node T_2774 = or(T_2772, T_2773) + node T_2775 = eq(s2_hit_state.state, UInt<2>("h1")) + node T_2776 = eq(s2_hit_state.state, UInt<2>("h2")) + node T_2777 = or(T_2775, T_2776) + node s2_hit = mux(T_2771, T_2774, T_2777) + node T_2778 = and(s2_valid_masked, s2_readwrite) + node s2_valid_hit = and(T_2778, s2_hit) + node T_2779 = and(s2_valid_masked, s2_readwrite) + node T_2781 = eq(s2_hit, UInt<1>("h0")) + node T_2782 = and(T_2779, T_2781) + node T_2783 = or(pstore1_valid, pstore2_valid) + node T_2785 = eq(T_2783, UInt<1>("h0")) + node T_2786 = and(T_2782, T_2785) + node T_2788 = eq(release_ack_wait, UInt<1>("h0")) + node s2_valid_miss = and(T_2786, T_2788) + node T_2790 = eq(s2_uncached, UInt<1>("h0")) + node s2_valid_cached_miss = and(s2_valid_miss, T_2790) + node s2_victimize = or(s2_valid_cached_miss, s2_flush_valid) + node s2_valid_uncached = and(s2_valid_miss, s2_uncached) + node T_2791 = neq(s2_hit_state.state, UInt<2>("h0")) + node T_2793 = eq(s2_flush_valid, UInt<1>("h0")) + node T_2794 = and(T_2791, T_2793) + node T_2795 = or(s1_valid_not_nacked, s1_flush_valid) + reg T_2796 : UInt, clk with : + reset => (UInt<1>("h0"), T_2796) + when T_2795 : + T_2796 <= s1_victim_way + node T_2798 = dshl(UInt<1>("h1"), T_2796) + node s2_victim_way = mux(T_2794, s2_hit_way, T_2798) + node T_2799 = or(s1_valid_not_nacked, s1_flush_valid) + reg s2_victim_tag : UInt<20>, clk with : + reset => (UInt<1>("h0"), s2_victim_tag) + when T_2799 : + s2_victim_tag <= MetadataArray_1.io.resp[s1_victim_way].tag + node T_2800 = neq(s2_hit_state.state, UInt<2>("h0")) + node T_2802 = eq(s2_flush_valid, UInt<1>("h0")) + node T_2803 = and(T_2800, T_2802) + node T_2804 = or(s1_valid_not_nacked, s1_flush_valid) + reg T_2805 : { state : UInt<2>}, clk with : + reset => (UInt<1>("h0"), T_2805) + when T_2804 : + T_2805 <- MetadataArray_1.io.resp[s1_victim_way].coh + node s2_victim_state = mux(T_2803, s2_hit_state, T_2805) + node s2_victim_valid = neq(s2_victim_state.state, UInt<2>("h0")) + node s2_victim_dirty = eq(s2_victim_state.state, UInt<2>("h2")) + node T_2848 = eq(s2_req.cmd, UInt<5>("h1")) + node T_2849 = eq(s2_req.cmd, UInt<5>("h7")) + node T_2850 = or(T_2848, T_2849) + node T_2851 = bits(s2_req.cmd, 3, 3) + node T_2852 = eq(s2_req.cmd, UInt<5>("h4")) + node T_2853 = or(T_2851, T_2852) + node T_2854 = or(T_2850, T_2853) + node T_2855 = mux(T_2854, UInt<2>("h2"), s2_hit_state.state) + wire s2_new_hit_state : { state : UInt<2>} + s2_new_hit_state is invalid + s2_new_hit_state.state <= T_2855 + node T_2899 = eq(s2_hit_state.state, s2_new_hit_state.state) + node s2_update_meta = eq(T_2899, UInt<1>("h0")) + node T_2902 = eq(s2_valid_hit, UInt<1>("h0")) + node T_2903 = and(s2_valid, T_2902) + node T_2904 = and(s2_valid_uncached, io.mem.acquire.ready) + node T_2906 = eq(T_2904, UInt<1>("h0")) + node T_2907 = and(T_2903, T_2906) + io.cpu.s2_nack <= T_2907 + node T_2909 = eq(s2_valid_hit, UInt<1>("h0")) + node T_2910 = or(T_2909, s2_update_meta) + node T_2911 = and(s2_valid, T_2910) + when T_2911 : + s1_nack <= UInt<1>("h1") + node T_2914 = bits(s1_req.typ, 1, 0) + node T_2916 = dshl(UInt<1>("h1"), T_2914) + node T_2918 = sub(T_2916, UInt<1>("h1")) + node T_2919 = tail(T_2918, 1) + node T_2920 = bits(T_2919, 2, 0) + node T_2921 = and(s1_req.addr, T_2920) + node T_2923 = neq(T_2921, UInt<1>("h0")) + node T_2924 = and(s1_read, T_2923) + io.cpu.xcpt.ma.ld <= T_2924 + node T_2926 = dshl(UInt<1>("h1"), T_2914) + node T_2928 = sub(T_2926, UInt<1>("h1")) + node T_2929 = tail(T_2928, 1) + node T_2930 = bits(T_2929, 2, 0) + node T_2931 = and(s1_req.addr, T_2930) + node T_2933 = neq(T_2931, UInt<1>("h0")) + node T_2934 = and(s1_write, T_2933) + io.cpu.xcpt.ma.st <= T_2934 + node T_2935 = and(s1_read, tlb.io.resp.xcpt_ld) + io.cpu.xcpt.pf.ld <= T_2935 + node T_2936 = and(s1_write, tlb.io.resp.xcpt_st) + io.cpu.xcpt.pf.st <= T_2936 + node T_2938 = eq(s2_req.cmd, UInt<5>("h6")) + node s2_lr = and(UInt<1>("h1"), T_2938) + node T_2940 = eq(s2_req.cmd, UInt<5>("h7")) + node s2_sc = and(UInt<1>("h1"), T_2940) + reg lrscCount : UInt, clk with : + reset => (reset, UInt<1>("h0")) + node lrscValid = gt(lrscCount, UInt<1>("h0")) + reg lrscAddr : UInt, clk with : + reset => (UInt<1>("h0"), lrscAddr) + node T_2944 = shr(s2_req.addr, 6) + node T_2945 = eq(lrscAddr, T_2944) + node T_2946 = and(lrscValid, T_2945) + node T_2948 = eq(T_2946, UInt<1>("h0")) + node s2_sc_fail = and(s2_sc, T_2948) + node T_2949 = and(s2_valid_hit, s2_lr) + when T_2949 : + lrscCount <= UInt<5>("h1f") + node T_2951 = shr(s2_req.addr, 6) + lrscAddr <= T_2951 + when lrscValid : + node T_2953 = sub(lrscCount, UInt<1>("h1")) + node T_2954 = tail(T_2953, 1) + lrscCount <= T_2954 + node T_2955 = and(s2_valid_hit, s2_sc) + node T_2956 = or(T_2955, io.cpu.invalidate_lr) + when T_2956 : + lrscCount <= UInt<1>("h0") + node T_2958 = and(s1_valid_not_nacked, s1_write) + reg pstore1_cmd : UInt<5>, clk with : + reset => (UInt<1>("h0"), pstore1_cmd) + when T_2958 : + pstore1_cmd <= s1_req.cmd + node T_2959 = and(s1_valid_not_nacked, s1_write) + reg pstore1_typ : UInt<3>, clk with : + reset => (UInt<1>("h0"), pstore1_typ) + when T_2959 : + pstore1_typ <= s1_req.typ + node T_2960 = and(s1_valid_not_nacked, s1_write) + reg pstore1_addr : UInt<32>, clk with : + reset => (UInt<1>("h0"), pstore1_addr) + when T_2960 : + pstore1_addr <= s1_paddr + node T_2961 = and(s1_valid_not_nacked, s1_write) + reg pstore1_data : UInt<64>, clk with : + reset => (UInt<1>("h0"), pstore1_data) + when T_2961 : + pstore1_data <= io.cpu.s1_data + node T_2962 = and(s1_valid_not_nacked, s1_write) + reg pstore1_way : UInt<4>, clk with : + reset => (UInt<1>("h0"), pstore1_way) + when T_2962 : + pstore1_way <= s1_hit_way + node T_2963 = bits(pstore1_typ, 1, 0) + node T_2965 = eq(T_2963, UInt<1>("h0")) + node T_2966 = bits(pstore1_data, 7, 0) + node T_2967 = cat(T_2966, T_2966) + node T_2968 = cat(T_2967, T_2967) + node T_2969 = cat(T_2968, T_2968) + node T_2971 = eq(T_2963, UInt<1>("h1")) + node T_2972 = bits(pstore1_data, 15, 0) + node T_2973 = cat(T_2972, T_2972) + node T_2974 = cat(T_2973, T_2973) + node T_2976 = eq(T_2963, UInt<2>("h2")) + node T_2977 = bits(pstore1_data, 31, 0) + node T_2978 = cat(T_2977, T_2977) + node T_2979 = mux(T_2976, T_2978, pstore1_data) + node T_2980 = mux(T_2971, T_2974, T_2979) + node T_2981 = mux(T_2965, T_2969, T_2980) wire pstore1_storegen_data : UInt pstore1_storegen_data is invalid pstore1_storegen_data <= T_2981 - node T_2983 = eq(pstore1_cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2984 = eq(pstore1_cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2985 = or(T_2983, T_2984) @[Consts.scala 35:41] - node T_2986 = eq(pstore1_cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2987 = or(T_2985, T_2986) @[Consts.scala 35:58] - node T_2988 = bits(pstore1_cmd, 3, 3) @[Consts.scala 33:29] - node T_2989 = eq(pstore1_cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2990 = or(T_2988, T_2989) @[Consts.scala 33:33] - node T_2991 = or(T_2987, T_2990) @[Consts.scala 35:75] - node pstore1_amo = and(UInt<1>("h01"), T_2991) @[dcache.scala 204:40] - node T_2992 = and(pstore1_valid, pstore2_valid) @[dcache.scala 205:47] - node T_2993 = and(s1_valid, s1_write) @[dcache.scala 205:78] - node T_2994 = or(T_2993, pstore1_amo) @[dcache.scala 205:91] - node pstore_drain_structural = and(T_2992, T_2994) @[dcache.scala 205:64] - node T_2995 = eq(io.cpu.req.bits.cmd, UInt<5>("h00")) @[Consts.scala 35:31] - node T_2996 = eq(io.cpu.req.bits.cmd, UInt<5>("h06")) @[Consts.scala 35:48] - node T_2997 = or(T_2995, T_2996) @[Consts.scala 35:41] - node T_2998 = eq(io.cpu.req.bits.cmd, UInt<5>("h07")) @[Consts.scala 35:65] - node T_2999 = or(T_2997, T_2998) @[Consts.scala 35:58] - node T_3000 = bits(io.cpu.req.bits.cmd, 3, 3) @[Consts.scala 33:29] - node T_3001 = eq(io.cpu.req.bits.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_3002 = or(T_3000, T_3001) @[Consts.scala 33:33] - node T_3003 = or(T_2999, T_3002) @[Consts.scala 35:75] - node T_3004 = and(io.cpu.req.valid, T_3003) @[dcache.scala 206:55] - node pstore_drain_opportunistic = eq(T_3004, UInt<1>("h00")) @[dcache.scala 206:36] - node pstore_drain_on_miss = or(releaseInFlight, io.cpu.s2_nack) @[dcache.scala 207:46] - node T_3007 = and(UInt<1>("h01"), pstore_drain_structural) @[dcache.scala 209:24] - node T_3009 = eq(pstore1_amo, UInt<1>("h00")) @[dcache.scala 210:25] - node T_3010 = and(pstore1_valid, T_3009) @[dcache.scala 210:22] - node T_3011 = or(T_3010, pstore2_valid) @[dcache.scala 210:39] - node T_3012 = or(pstore_drain_opportunistic, pstore_drain_on_miss) @[dcache.scala 210:88] - node T_3013 = and(T_3011, T_3012) @[dcache.scala 210:57] - node pstore_drain = or(T_3007, T_3013) @[dcache.scala 209:51] - node T_3014 = and(s2_valid_hit, s2_write) @[dcache.scala 212:39] - node T_3016 = eq(s2_sc_fail, UInt<1>("h00")) @[dcache.scala 212:54] - node T_3017 = and(T_3014, T_3016) @[dcache.scala 212:51] - reg T_3019 : UInt<1>, clk - node T_3021 = eq(T_3017, UInt<1>("h00")) @[dcache.scala 214:12] - node T_3023 = eq(T_3019, UInt<1>("h00")) @[dcache.scala 214:31] - node T_3024 = or(T_3021, T_3023) @[dcache.scala 214:28] - node T_3025 = or(T_3024, reset) @[dcache.scala 214:11] - node T_3027 = eq(T_3025, UInt<1>("h00")) @[dcache.scala 214:11] - when T_3027 : @[dcache.scala 214:11] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:214 assert(!s2_store_valid || !pstore1_held)\n") @[dcache.scala 214:11] - stop(clk, UInt<1>(1), 1) @[dcache.scala 214:11] - skip @[dcache.scala 214:11] - node T_3028 = or(T_3017, T_3019) @[dcache.scala 215:37] - node T_3029 = and(T_3028, pstore2_valid) @[dcache.scala 215:54] - node T_3031 = eq(pstore_drain, UInt<1>("h00")) @[dcache.scala 215:74] - node T_3032 = and(T_3029, T_3031) @[dcache.scala 215:71] - T_3019 <= T_3032 @[dcache.scala 215:18] - node T_3033 = or(T_3017, T_3019) @[dcache.scala 216:20] - pstore1_valid <= T_3033 @[dcache.scala 211:17] - node T_3034 = eq(pstore2_valid, pstore_drain) @[dcache.scala 218:57] - node advance_pstore1 = and(pstore1_valid, T_3034) @[dcache.scala 218:39] - node T_3036 = eq(pstore_drain, UInt<1>("h00")) @[dcache.scala 219:37] - node T_3037 = and(pstore2_valid, T_3036) @[dcache.scala 219:34] - node T_3038 = or(T_3037, advance_pstore1) @[dcache.scala 219:51] - pstore2_valid <= T_3038 @[dcache.scala 219:17] - reg pstore2_addr : UInt<32>, clk - when advance_pstore1 : @[Reg.scala 29:19] - pstore2_addr <= pstore1_addr @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg pstore2_way : UInt<4>, clk - when advance_pstore1 : @[Reg.scala 29:19] - pstore2_way <= pstore1_way @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg pstore2_storegen_data : UInt, clk - when advance_pstore1 : @[Reg.scala 29:19] - pstore2_storegen_data <= pstore1_storegen_data @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_3040 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3042 = mux(T_3040, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3044 = geq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3047 = mux(T_3044, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3048 = or(T_3042, T_3047) @[AmoAlu.scala 18:46] - node T_3049 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3051 = mux(T_3049, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3052 = cat(T_3048, T_3051) @[Cat.scala 20:58] - node T_3053 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3055 = mux(T_3053, T_3052, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3057 = geq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3060 = mux(T_3057, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3061 = or(T_3055, T_3060) @[AmoAlu.scala 18:46] - node T_3062 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3064 = mux(T_3062, UInt<1>("h00"), T_3052) @[AmoAlu.scala 19:22] - node T_3065 = cat(T_3061, T_3064) @[Cat.scala 20:58] - node T_3066 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3068 = mux(T_3066, T_3065, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3070 = geq(T_2963, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3073 = mux(T_3070, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3074 = or(T_3068, T_3073) @[AmoAlu.scala 18:46] - node T_3075 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3077 = mux(T_3075, UInt<1>("h00"), T_3065) @[AmoAlu.scala 19:22] - node T_3078 = cat(T_3074, T_3077) @[Cat.scala 20:58] - reg pstore2_storegen_mask : UInt<8>, clk - when advance_pstore1 : @[Reg.scala 29:19] - pstore2_storegen_mask <= T_3078 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - dataArb.io.in[0].valid <= pstore_drain @[dcache.scala 224:26] - dataArb.io.in[0].bits.write <= UInt<1>("h01") @[dcache.scala 225:31] - node T_3080 = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[dcache.scala 226:36] - dataArb.io.in[0].bits.addr <= T_3080 @[dcache.scala 226:30] - node T_3081 = mux(pstore2_valid, pstore2_way, pstore1_way) @[dcache.scala 227:38] - dataArb.io.in[0].bits.way_en <= T_3081 @[dcache.scala 227:32] - node T_3082 = mux(pstore2_valid, pstore2_storegen_data, pstore1_storegen_data) @[dcache.scala 228:52] - dataArb.io.in[0].bits.wdata <= T_3082 @[dcache.scala 228:31] - node T_3083 = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[dcache.scala 229:30] - node pstore_mask_shift = shl(UInt<1>("h00"), 3) @[dcache.scala 229:106] - node T_3086 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3088 = mux(T_3086, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3090 = geq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3093 = mux(T_3090, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3094 = or(T_3088, T_3093) @[AmoAlu.scala 18:46] - node T_3095 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3097 = mux(T_3095, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3098 = cat(T_3094, T_3097) @[Cat.scala 20:58] - node T_3099 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3101 = mux(T_3099, T_3098, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3103 = geq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3106 = mux(T_3103, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3107 = or(T_3101, T_3106) @[AmoAlu.scala 18:46] - node T_3108 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3110 = mux(T_3108, UInt<1>("h00"), T_3098) @[AmoAlu.scala 19:22] - node T_3111 = cat(T_3107, T_3110) @[Cat.scala 20:58] - node T_3112 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3114 = mux(T_3112, T_3111, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3116 = geq(T_2963, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3119 = mux(T_3116, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3120 = or(T_3114, T_3119) @[AmoAlu.scala 18:46] - node T_3121 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3123 = mux(T_3121, UInt<1>("h00"), T_3111) @[AmoAlu.scala 19:22] - node T_3124 = cat(T_3120, T_3123) @[Cat.scala 20:58] - node T_3125 = mux(pstore2_valid, pstore2_storegen_mask, T_3124) @[dcache.scala 230:37] - node T_3126 = dshl(T_3125, pstore_mask_shift) @[dcache.scala 230:99] - dataArb.io.in[0].bits.wmask <= T_3126 @[dcache.scala 230:31] - node s1_idx = bits(s1_req.addr, 11, 3) @[dcache.scala 233:27] - node T_3127 = bits(pstore1_addr, 11, 3) @[dcache.scala 235:36] - node T_3128 = eq(T_3127, s1_idx) @[dcache.scala 235:58] - node T_3129 = and(pstore1_valid, T_3128) @[dcache.scala 235:21] - node T_3131 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3133 = mux(T_3131, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3135 = geq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3138 = mux(T_3135, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3139 = or(T_3133, T_3138) @[AmoAlu.scala 18:46] - node T_3140 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3142 = mux(T_3140, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3143 = cat(T_3139, T_3142) @[Cat.scala 20:58] - node T_3144 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3146 = mux(T_3144, T_3143, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3148 = geq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3151 = mux(T_3148, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3152 = or(T_3146, T_3151) @[AmoAlu.scala 18:46] - node T_3153 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3155 = mux(T_3153, UInt<1>("h00"), T_3143) @[AmoAlu.scala 19:22] - node T_3156 = cat(T_3152, T_3155) @[Cat.scala 20:58] - node T_3157 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3159 = mux(T_3157, T_3156, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3161 = geq(T_2963, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3164 = mux(T_3161, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3165 = or(T_3159, T_3164) @[AmoAlu.scala 18:46] - node T_3166 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3168 = mux(T_3166, UInt<1>("h00"), T_3156) @[AmoAlu.scala 19:22] - node T_3169 = cat(T_3165, T_3168) @[Cat.scala 20:58] - node T_3171 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3173 = mux(T_3171, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3175 = geq(T_2914, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3178 = mux(T_3175, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3179 = or(T_3173, T_3178) @[AmoAlu.scala 18:46] - node T_3180 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3182 = mux(T_3180, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3183 = cat(T_3179, T_3182) @[Cat.scala 20:58] - node T_3184 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3186 = mux(T_3184, T_3183, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3188 = geq(T_2914, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3191 = mux(T_3188, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3192 = or(T_3186, T_3191) @[AmoAlu.scala 18:46] - node T_3193 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3195 = mux(T_3193, UInt<1>("h00"), T_3183) @[AmoAlu.scala 19:22] - node T_3196 = cat(T_3192, T_3195) @[Cat.scala 20:58] - node T_3197 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3199 = mux(T_3197, T_3196, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3201 = geq(T_2914, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3204 = mux(T_3201, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3205 = or(T_3199, T_3204) @[AmoAlu.scala 18:46] - node T_3206 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3208 = mux(T_3206, UInt<1>("h00"), T_3196) @[AmoAlu.scala 19:22] - node T_3209 = cat(T_3205, T_3208) @[Cat.scala 20:58] - node T_3210 = and(T_3169, T_3209) @[dcache.scala 235:95] - node T_3212 = neq(T_3210, UInt<1>("h00")) @[dcache.scala 235:115] - node T_3213 = and(T_3129, T_3212) @[dcache.scala 235:69] - node T_3214 = bits(pstore2_addr, 11, 3) @[dcache.scala 236:36] - node T_3215 = eq(T_3214, s1_idx) @[dcache.scala 236:58] - node T_3216 = and(pstore2_valid, T_3215) @[dcache.scala 236:21] - node T_3218 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3220 = mux(T_3218, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3222 = geq(T_2914, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3225 = mux(T_3222, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3226 = or(T_3220, T_3225) @[AmoAlu.scala 18:46] - node T_3227 = bits(s1_req.addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3229 = mux(T_3227, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3230 = cat(T_3226, T_3229) @[Cat.scala 20:58] - node T_3231 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3233 = mux(T_3231, T_3230, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3235 = geq(T_2914, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3238 = mux(T_3235, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3239 = or(T_3233, T_3238) @[AmoAlu.scala 18:46] - node T_3240 = bits(s1_req.addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3242 = mux(T_3240, UInt<1>("h00"), T_3230) @[AmoAlu.scala 19:22] - node T_3243 = cat(T_3239, T_3242) @[Cat.scala 20:58] - node T_3244 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3246 = mux(T_3244, T_3243, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3248 = geq(T_2914, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3251 = mux(T_3248, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3252 = or(T_3246, T_3251) @[AmoAlu.scala 18:46] - node T_3253 = bits(s1_req.addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3255 = mux(T_3253, UInt<1>("h00"), T_3243) @[AmoAlu.scala 19:22] - node T_3256 = cat(T_3252, T_3255) @[Cat.scala 20:58] - node T_3257 = and(pstore2_storegen_mask, T_3256) @[dcache.scala 236:95] - node T_3259 = neq(T_3257, UInt<1>("h00")) @[dcache.scala 236:115] - node T_3260 = and(T_3216, T_3259) @[dcache.scala 236:69] - node T_3261 = or(T_3213, T_3260) @[dcache.scala 235:120] - node s1_raw_hazard = and(s1_read, T_3261) @[dcache.scala 234:31] - node T_3262 = and(s1_valid, s1_raw_hazard) @[dcache.scala 237:18] - when T_3262 : @[dcache.scala 237:36] - s1_nack <= UInt<1>("h01") @[dcache.scala 237:46] - skip @[dcache.scala 237:36] - node T_3264 = and(s2_valid_hit, s2_update_meta) @[dcache.scala 239:48] - node T_3266 = eq(s2_victim_dirty, UInt<1>("h00")) @[dcache.scala 239:87] - node T_3267 = and(s2_victimize, T_3266) @[dcache.scala 239:84] - node T_3268 = or(T_3264, T_3267) @[dcache.scala 239:67] - metaWriteArb.io.in[0].valid <= T_3268 @[dcache.scala 239:31] - metaWriteArb.io.in[0].bits.way_en <= s2_victim_way @[dcache.scala 240:37] - node T_3269 = bits(s2_req.addr, 11, 6) @[dcache.scala 241:48] - metaWriteArb.io.in[0].bits.idx <= T_3269 @[dcache.scala 241:34] - wire T_3293 : {state : UInt<2>} @[Metadata.scala 158:20] - T_3293 is invalid @[Metadata.scala 158:20] - T_3293.state <= UInt<1>("h00") @[Metadata.scala 159:16] - node T_3315 = mux(s2_valid_hit, s2_new_hit_state, T_3293) @[dcache.scala 242:45] - metaWriteArb.io.in[0].bits.data.coh <- T_3315 @[dcache.scala 242:39] - node T_3337 = bits(s2_req.addr, 31, 12) @[dcache.scala 243:53] - metaWriteArb.io.in[0].bits.data.tag <= T_3337 @[dcache.scala 243:39] - node T_3339 = bits(s2_req.addr, 31, 6) @[dcache.scala 248:29] - node T_3341 = eq(s2_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_3342 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_3343 = or(T_3341, T_3342) @[Consts.scala 36:42] - node T_3344 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_3345 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_3346 = or(T_3344, T_3345) @[Consts.scala 33:33] - node T_3347 = or(T_3343, T_3346) @[Consts.scala 36:59] - node T_3348 = eq(s2_req.cmd, UInt<5>("h03")) @[Consts.scala 37:54] - node T_3349 = or(T_3347, T_3348) @[Consts.scala 37:47] - node T_3350 = eq(s2_req.cmd, UInt<5>("h06")) @[Consts.scala 37:71] - node T_3351 = or(T_3349, T_3350) @[Consts.scala 37:64] - node T_3352 = mux(T_3351, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_3354 = cat(s2_req.cmd, UInt<1>("h01")) @[Cat.scala 20:58] - wire cachedGetMessage : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - cachedGetMessage is invalid @[Definitions.scala 417:19] - cachedGetMessage.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - cachedGetMessage.a_type <= T_3352 @[Definitions.scala 419:16] - cachedGetMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - cachedGetMessage.addr_block <= T_3339 @[Definitions.scala 421:20] - cachedGetMessage.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - cachedGetMessage.data <= UInt<1>("h00") @[Definitions.scala 423:14] - cachedGetMessage.union <= T_3354 @[Definitions.scala 424:15] - node T_3413 = bits(s2_req.addr, 31, 6) @[dcache.scala 252:29] - node T_3414 = bits(s2_req.addr, 5, 3) @[dcache.scala 253:28] - node T_3415 = bits(s2_req.addr, 2, 0) @[dcache.scala 254:28] - node T_3442 = or(UInt<3>("h00"), T_3415) @[Definitions.scala 386:49] - node T_3443 = bits(T_3442, 2, 0) @[Definitions.scala 386:61] - node T_3445 = or(UInt<2>("h00"), s2_req.typ) @[Definitions.scala 387:61] - node T_3446 = bits(T_3445, 1, 0) @[Definitions.scala 387:76] - node T_3448 = or(UInt<5>("h00"), UInt<5>("h00")) @[Definitions.scala 388:36] - node T_3449 = bits(T_3448, 4, 0) @[Definitions.scala 388:45] - node T_3451 = or(UInt<8>("h00"), UInt<1>("h00")) @[Definitions.scala 389:46] - node T_3452 = bits(T_3451, 7, 0) @[Definitions.scala 389:54] - node T_3455 = cat(T_3449, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3456 = cat(T_3443, T_3446) @[Cat.scala 20:58] - node T_3457 = cat(T_3456, T_3455) @[Cat.scala 20:58] - node T_3459 = cat(T_3446, T_3449) @[Cat.scala 20:58] - node T_3460 = cat(T_3459, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3462 = cat(T_3452, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3464 = cat(T_3452, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3466 = cat(T_3449, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3467 = cat(T_3443, T_3446) @[Cat.scala 20:58] - node T_3468 = cat(T_3467, T_3466) @[Cat.scala 20:58] - node T_3470 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3472 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3473 = eq(UInt<3>("h06"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3474 = mux(T_3473, T_3472, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3475 = eq(UInt<3>("h05"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3476 = mux(T_3475, T_3470, T_3474) @[Mux.scala 46:16] - node T_3477 = eq(UInt<3>("h04"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3478 = mux(T_3477, T_3468, T_3476) @[Mux.scala 46:16] - node T_3479 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3480 = mux(T_3479, T_3464, T_3478) @[Mux.scala 46:16] - node T_3481 = eq(UInt<3>("h02"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3482 = mux(T_3481, T_3462, T_3480) @[Mux.scala 46:16] - node T_3483 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3484 = mux(T_3483, T_3460, T_3482) @[Mux.scala 46:16] - node T_3485 = eq(UInt<3>("h00"), UInt<3>("h00")) @[Mux.scala 46:19] - node T_3486 = mux(T_3485, T_3457, T_3484) @[Mux.scala 46:16] - wire uncachedGetMessage : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - uncachedGetMessage is invalid @[Definitions.scala 417:19] - uncachedGetMessage.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - uncachedGetMessage.a_type <= UInt<3>("h00") @[Definitions.scala 419:16] - uncachedGetMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - uncachedGetMessage.addr_block <= T_3413 @[Definitions.scala 421:20] - uncachedGetMessage.addr_beat <= T_3414 @[Definitions.scala 422:19] - uncachedGetMessage.data <= UInt<1>("h00") @[Definitions.scala 423:14] - uncachedGetMessage.union <= T_3486 @[Definitions.scala 424:15] - node T_3543 = bits(s2_req.addr, 31, 6) @[dcache.scala 260:29] - node T_3544 = bits(s2_req.addr, 5, 3) @[dcache.scala 261:28] - node T_3546 = eq(T_2963, UInt<1>("h00")) @[AmoAlu.scala 27:19] - node T_3547 = bits(pstore1_data, 7, 0) @[AmoAlu.scala 27:66] - node T_3548 = cat(T_3547, T_3547) @[Cat.scala 20:58] - node T_3549 = cat(T_3548, T_3548) @[Cat.scala 20:58] - node T_3550 = cat(T_3549, T_3549) @[Cat.scala 20:58] - node T_3552 = eq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 27:19] - node T_3553 = bits(pstore1_data, 15, 0) @[AmoAlu.scala 27:66] - node T_3554 = cat(T_3553, T_3553) @[Cat.scala 20:58] - node T_3555 = cat(T_3554, T_3554) @[Cat.scala 20:58] - node T_3557 = eq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 27:19] - node T_3558 = bits(pstore1_data, 31, 0) @[AmoAlu.scala 27:66] - node T_3559 = cat(T_3558, T_3558) @[Cat.scala 20:58] - node T_3560 = mux(T_3557, T_3559, pstore1_data) @[AmoAlu.scala 27:13] - node T_3561 = mux(T_3552, T_3555, T_3560) @[AmoAlu.scala 27:13] - node T_3562 = mux(T_3546, T_3550, T_3561) @[AmoAlu.scala 27:13] - node T_3564 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 18:27] - node T_3566 = mux(T_3564, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3568 = geq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 18:57] - node T_3571 = mux(T_3568, UInt<1>("h01"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3572 = or(T_3566, T_3571) @[AmoAlu.scala 18:46] - node T_3573 = bits(pstore1_addr, 0, 0) @[AmoAlu.scala 19:27] - node T_3575 = mux(T_3573, UInt<1>("h00"), UInt<1>("h01")) @[AmoAlu.scala 19:22] - node T_3576 = cat(T_3572, T_3575) @[Cat.scala 20:58] - node T_3577 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 18:27] - node T_3579 = mux(T_3577, T_3576, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3581 = geq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 18:57] - node T_3584 = mux(T_3581, UInt<2>("h03"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3585 = or(T_3579, T_3584) @[AmoAlu.scala 18:46] - node T_3586 = bits(pstore1_addr, 1, 1) @[AmoAlu.scala 19:27] - node T_3588 = mux(T_3586, UInt<1>("h00"), T_3576) @[AmoAlu.scala 19:22] - node T_3589 = cat(T_3585, T_3588) @[Cat.scala 20:58] - node T_3590 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 18:27] - node T_3592 = mux(T_3590, T_3589, UInt<1>("h00")) @[AmoAlu.scala 18:22] - node T_3594 = geq(T_2963, UInt<2>("h03")) @[AmoAlu.scala 18:57] - node T_3597 = mux(T_3594, UInt<4>("h0f"), UInt<1>("h00")) @[AmoAlu.scala 18:51] - node T_3598 = or(T_3592, T_3597) @[AmoAlu.scala 18:46] - node T_3599 = bits(pstore1_addr, 2, 2) @[AmoAlu.scala 19:27] - node T_3601 = mux(T_3599, UInt<1>("h00"), T_3589) @[AmoAlu.scala 19:22] - node T_3602 = cat(T_3598, T_3601) @[Cat.scala 20:58] - node T_3603 = shl(UInt<1>("h00"), 3) @[dcache.scala 263:62] - node T_3604 = dshl(T_3602, T_3603) @[dcache.scala 263:40] - node T_3632 = or(UInt<3>("h00"), UInt<1>("h00")) @[Definitions.scala 386:49] - node T_3633 = bits(T_3632, 2, 0) @[Definitions.scala 386:61] - node T_3635 = or(UInt<2>("h00"), UInt<1>("h00")) @[Definitions.scala 387:61] - node T_3636 = bits(T_3635, 1, 0) @[Definitions.scala 387:76] - node T_3638 = or(UInt<5>("h00"), UInt<1>("h00")) @[Definitions.scala 388:36] - node T_3639 = bits(T_3638, 4, 0) @[Definitions.scala 388:45] - node T_3641 = or(UInt<8>("h00"), T_3604) @[Definitions.scala 389:46] - node T_3642 = bits(T_3641, 7, 0) @[Definitions.scala 389:54] - node T_3645 = cat(T_3639, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3646 = cat(T_3633, T_3636) @[Cat.scala 20:58] - node T_3647 = cat(T_3646, T_3645) @[Cat.scala 20:58] - node T_3649 = cat(T_3636, T_3639) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3652 = cat(T_3642, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3654 = cat(T_3642, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3656 = cat(T_3639, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3657 = cat(T_3633, T_3636) @[Cat.scala 20:58] - node T_3658 = cat(T_3657, T_3656) @[Cat.scala 20:58] - node T_3660 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3662 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3663 = eq(UInt<3>("h06"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3664 = mux(T_3663, T_3662, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3665 = eq(UInt<3>("h05"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3666 = mux(T_3665, T_3660, T_3664) @[Mux.scala 46:16] - node T_3667 = eq(UInt<3>("h04"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3668 = mux(T_3667, T_3658, T_3666) @[Mux.scala 46:16] - node T_3669 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3670 = mux(T_3669, T_3654, T_3668) @[Mux.scala 46:16] - node T_3671 = eq(UInt<3>("h02"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3672 = mux(T_3671, T_3652, T_3670) @[Mux.scala 46:16] - node T_3673 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3674 = mux(T_3673, T_3650, T_3672) @[Mux.scala 46:16] - node T_3675 = eq(UInt<3>("h00"), UInt<3>("h02")) @[Mux.scala 46:19] - node T_3676 = mux(T_3675, T_3647, T_3674) @[Mux.scala 46:16] - wire uncachedPutMessage : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - uncachedPutMessage is invalid @[Definitions.scala 417:19] - uncachedPutMessage.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - uncachedPutMessage.a_type <= UInt<3>("h02") @[Definitions.scala 419:16] - uncachedPutMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - uncachedPutMessage.addr_block <= T_3543 @[Definitions.scala 421:20] - uncachedPutMessage.addr_beat <= T_3544 @[Definitions.scala 422:19] - uncachedPutMessage.data <= T_3562 @[Definitions.scala 423:14] - uncachedPutMessage.union <= T_3676 @[Definitions.scala 424:15] - node T_3733 = bits(s2_req.addr, 31, 6) @[dcache.scala 267:29] - node T_3734 = bits(s2_req.addr, 5, 3) @[dcache.scala 268:28] - node T_3735 = bits(s2_req.addr, 2, 0) @[dcache.scala 269:28] - node T_3737 = eq(T_2963, UInt<1>("h00")) @[AmoAlu.scala 27:19] - node T_3738 = bits(pstore1_data, 7, 0) @[AmoAlu.scala 27:66] - node T_3739 = cat(T_3738, T_3738) @[Cat.scala 20:58] - node T_3740 = cat(T_3739, T_3739) @[Cat.scala 20:58] - node T_3741 = cat(T_3740, T_3740) @[Cat.scala 20:58] - node T_3743 = eq(T_2963, UInt<1>("h01")) @[AmoAlu.scala 27:19] - node T_3744 = bits(pstore1_data, 15, 0) @[AmoAlu.scala 27:66] - node T_3745 = cat(T_3744, T_3744) @[Cat.scala 20:58] - node T_3746 = cat(T_3745, T_3745) @[Cat.scala 20:58] - node T_3748 = eq(T_2963, UInt<2>("h02")) @[AmoAlu.scala 27:19] - node T_3749 = bits(pstore1_data, 31, 0) @[AmoAlu.scala 27:66] - node T_3750 = cat(T_3749, T_3749) @[Cat.scala 20:58] - node T_3751 = mux(T_3748, T_3750, pstore1_data) @[AmoAlu.scala 27:13] - node T_3752 = mux(T_3743, T_3746, T_3751) @[AmoAlu.scala 27:13] - node T_3753 = mux(T_3737, T_3741, T_3752) @[AmoAlu.scala 27:13] - node T_3779 = or(UInt<3>("h00"), T_3735) @[Definitions.scala 386:49] - node T_3780 = bits(T_3779, 2, 0) @[Definitions.scala 386:61] - node T_3782 = or(UInt<2>("h00"), s2_req.typ) @[Definitions.scala 387:61] - node T_3783 = bits(T_3782, 1, 0) @[Definitions.scala 387:76] - node T_3785 = or(UInt<5>("h00"), s2_req.cmd) @[Definitions.scala 388:36] - node T_3786 = bits(T_3785, 4, 0) @[Definitions.scala 388:45] - node T_3788 = or(UInt<8>("h00"), UInt<1>("h00")) @[Definitions.scala 389:46] - node T_3789 = bits(T_3788, 7, 0) @[Definitions.scala 389:54] - node T_3792 = cat(T_3786, UInt<1>("h01")) @[Cat.scala 20:58] - node T_3793 = cat(T_3780, T_3783) @[Cat.scala 20:58] - node T_3794 = cat(T_3793, T_3792) @[Cat.scala 20:58] - node T_3796 = cat(T_3783, T_3786) @[Cat.scala 20:58] - node T_3797 = cat(T_3796, UInt<1>("h01")) @[Cat.scala 20:58] - node T_3799 = cat(T_3789, UInt<1>("h01")) @[Cat.scala 20:58] - node T_3801 = cat(T_3789, UInt<1>("h01")) @[Cat.scala 20:58] - node T_3803 = cat(T_3786, UInt<1>("h01")) @[Cat.scala 20:58] - node T_3804 = cat(T_3780, T_3783) @[Cat.scala 20:58] - node T_3805 = cat(T_3804, T_3803) @[Cat.scala 20:58] - node T_3807 = cat(UInt<5>("h00"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_3809 = cat(UInt<5>("h01"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_3810 = eq(UInt<3>("h06"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3811 = mux(T_3810, T_3809, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3812 = eq(UInt<3>("h05"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3813 = mux(T_3812, T_3807, T_3811) @[Mux.scala 46:16] - node T_3814 = eq(UInt<3>("h04"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3815 = mux(T_3814, T_3805, T_3813) @[Mux.scala 46:16] - node T_3816 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3817 = mux(T_3816, T_3801, T_3815) @[Mux.scala 46:16] - node T_3818 = eq(UInt<3>("h02"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3819 = mux(T_3818, T_3799, T_3817) @[Mux.scala 46:16] - node T_3820 = eq(UInt<3>("h01"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3821 = mux(T_3820, T_3797, T_3819) @[Mux.scala 46:16] - node T_3822 = eq(UInt<3>("h00"), UInt<3>("h04")) @[Mux.scala 46:19] - node T_3823 = mux(T_3822, T_3794, T_3821) @[Mux.scala 46:16] - wire uncachedPutAtomicMessage : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - uncachedPutAtomicMessage is invalid @[Definitions.scala 417:19] - uncachedPutAtomicMessage.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - uncachedPutAtomicMessage.a_type <= UInt<3>("h04") @[Definitions.scala 419:16] - uncachedPutAtomicMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - uncachedPutAtomicMessage.addr_block <= T_3733 @[Definitions.scala 421:20] - uncachedPutAtomicMessage.addr_beat <= T_3734 @[Definitions.scala 422:19] - uncachedPutAtomicMessage.data <= T_3753 @[Definitions.scala 423:14] - uncachedPutAtomicMessage.union <= T_3823 @[Definitions.scala 424:15] - node T_3880 = eq(s2_victim_dirty, UInt<1>("h00")) @[dcache.scala 273:53] - node T_3881 = and(s2_valid_cached_miss, T_3880) @[dcache.scala 273:50] - node T_3882 = or(T_3881, s2_valid_uncached) @[dcache.scala 273:71] - node T_3883 = and(T_3882, fq.io.enq.ready) @[dcache.scala 273:93] - io.mem.acquire.valid <= T_3883 @[dcache.scala 273:24] - io.mem.acquire.bits <- cachedGetMessage @[dcache.scala 274:23] - when s2_uncached : @[dcache.scala 275:22] - node T_3885 = eq(s2_valid_masked, UInt<1>("h00")) @[dcache.scala 277:14] - node T_3886 = neq(s2_hit_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_3888 = eq(T_3886, UInt<1>("h00")) @[dcache.scala 277:34] - node T_3889 = or(T_3885, T_3888) @[dcache.scala 277:31] - node T_3890 = or(T_3889, reset) @[dcache.scala 277:13] - node T_3892 = eq(T_3890, UInt<1>("h00")) @[dcache.scala 277:13] - when T_3892 : @[dcache.scala 277:13] - printf(clk, UInt<1>(1), "Assertion failed: cache hit on uncached access\n at dcache.scala:277 assert(!s2_valid_masked || !s2_hit_state.isValid(), \"cache hit on uncached access\")\n") @[dcache.scala 277:13] - stop(clk, UInt<1>(1), 1) @[dcache.scala 277:13] - skip @[dcache.scala 277:13] - io.mem.acquire.bits <- uncachedGetMessage @[dcache.scala 278:25] - when s2_write : @[dcache.scala 279:21] - io.mem.acquire.bits <- uncachedPutMessage @[dcache.scala 280:27] - when pstore1_amo : @[dcache.scala 281:26] - io.mem.acquire.bits <- uncachedPutAtomicMessage @[dcache.scala 282:29] - skip @[dcache.scala 281:26] - skip @[dcache.scala 279:21] - skip @[dcache.scala 275:22] - node T_3893 = and(io.mem.acquire.ready, io.mem.acquire.valid) @[Decoupled.scala 21:42] - when T_3893 : @[dcache.scala 286:32] - grant_wait <= UInt<1>("h01") @[dcache.scala 286:45] - skip @[dcache.scala 286:32] - wire T_3902 : UInt<3>[1] @[Definitions.scala 853:34] - T_3902 is invalid @[Definitions.scala 853:34] - T_3902[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3904 = eq(io.mem.grant.bits.g_type, T_3902[0]) @[Package.scala 7:47] - node T_3905 = eq(io.mem.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3906 = mux(io.mem.grant.bits.is_builtin_type, T_3904, T_3905) @[Definitions.scala 274:33] - node grantIsRefill = and(UInt<1>("h01"), T_3906) @[Definitions.scala 274:27] - node T_3908 = eq(io.mem.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node grantIsVoluntary = and(io.mem.grant.bits.is_builtin_type, T_3908) @[Definitions.scala 277:59] - node T_3910 = eq(grantIsRefill, UInt<1>("h00")) @[dcache.scala 291:25] - node T_3912 = eq(grantIsVoluntary, UInt<1>("h00")) @[dcache.scala 291:43] - node grantIsUncached = and(T_3910, T_3912) @[dcache.scala 291:40] - when io.mem.grant.valid : @[dcache.scala 292:29] - node T_3913 = and(grantIsVoluntary, release_ack_wait) @[dcache.scala 293:43] - node T_3914 = or(grant_wait, T_3913) @[dcache.scala 293:23] - node T_3915 = or(T_3914, reset) @[dcache.scala 293:11] - node T_3917 = eq(T_3915, UInt<1>("h00")) @[dcache.scala 293:11] - when T_3917 : @[dcache.scala 293:11] - printf(clk, UInt<1>(1), "Assertion failed: unexpected grant\n at dcache.scala:293 assert(grant_wait || grantIsVoluntary && release_ack_wait, \"unexpected grant\")\n") @[dcache.scala 293:11] - stop(clk, UInt<1>(1), 1) @[dcache.scala 293:11] - skip @[dcache.scala 293:11] - when grantIsUncached : @[dcache.scala 294:28] - s2_data <= io.mem.grant.bits.data @[dcache.scala 294:38] - skip @[dcache.scala 294:28] - when grantIsVoluntary : @[dcache.scala 295:29] - release_ack_wait <= UInt<1>("h00") @[dcache.scala 295:48] - skip @[dcache.scala 295:29] - skip @[dcache.scala 292:29] - node T_3919 = and(io.mem.grant.ready, io.mem.grant.valid) @[Decoupled.scala 21:42] - node T_3920 = and(T_3919, grantIsRefill) @[dcache.scala 297:63] - reg refillCount : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3920 : @[Counter.scala 43:17] - node T_3923 = eq(refillCount, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3925 = add(refillCount, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3926 = tail(T_3925, 1) @[Counter.scala 21:22] - refillCount <= T_3926 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node refillDone = and(T_3920, T_3923) @[Counter.scala 44:20] - node grantDone = or(refillDone, grantIsUncached) @[dcache.scala 298:30] - node T_3927 = and(io.mem.grant.ready, io.mem.grant.valid) @[Decoupled.scala 21:42] - node T_3928 = and(T_3927, grantDone) @[dcache.scala 299:29] - when T_3928 : @[dcache.scala 299:43] - grant_wait <= UInt<1>("h00") @[dcache.scala 299:56] - skip @[dcache.scala 299:43] - node T_3930 = and(grantIsRefill, io.mem.grant.valid) @[dcache.scala 302:43] - dataArb.io.in[1].valid <= T_3930 @[dcache.scala 302:26] - io.mem.grant.ready <= UInt<1>("h01") @[dcache.scala 303:22] - node T_3933 = eq(dataArb.io.in[1].valid, UInt<1>("h00")) @[dcache.scala 304:36] - node T_3934 = or(dataArb.io.in[1].ready, T_3933) @[dcache.scala 304:33] - node T_3935 = or(T_3934, reset) @[dcache.scala 304:9] - node T_3937 = eq(T_3935, UInt<1>("h00")) @[dcache.scala 304:9] - when T_3937 : @[dcache.scala 304:9] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:304 assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid)\n") @[dcache.scala 304:9] - stop(clk, UInt<1>(1), 1) @[dcache.scala 304:9] - skip @[dcache.scala 304:9] - dataArb.io.in[1].bits.write <= UInt<1>("h01") @[dcache.scala 305:31] - node T_3939 = bits(s2_req.addr, 31, 6) @[dcache.scala 306:48] - node T_3940 = cat(T_3939, io.mem.grant.bits.addr_beat) @[Cat.scala 20:58] - node T_3941 = shl(T_3940, 3) @[dcache.scala 306:106] - dataArb.io.in[1].bits.addr <= T_3941 @[dcache.scala 306:30] - dataArb.io.in[1].bits.way_en <= s2_victim_way @[dcache.scala 307:32] - dataArb.io.in[1].bits.wdata <= io.mem.grant.bits.data @[dcache.scala 308:31] - node T_3943 = not(UInt<8>("h00")) @[dcache.scala 309:34] - dataArb.io.in[1].bits.wmask <= T_3943 @[dcache.scala 309:31] - metaWriteArb.io.in[1].valid <= refillDone @[dcache.scala 311:31] - node T_3945 = eq(metaWriteArb.io.in[1].valid, UInt<1>("h00")) @[dcache.scala 312:10] - node T_3946 = or(T_3945, metaWriteArb.io.in[1].ready) @[dcache.scala 312:39] - node T_3947 = or(T_3946, reset) @[dcache.scala 312:9] - node T_3949 = eq(T_3947, UInt<1>("h00")) @[dcache.scala 312:9] - when T_3949 : @[dcache.scala 312:9] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:312 assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready)\n") @[dcache.scala 312:9] - stop(clk, UInt<1>(1), 1) @[dcache.scala 312:9] - skip @[dcache.scala 312:9] - metaWriteArb.io.in[1].bits.way_en <= s2_victim_way @[dcache.scala 313:37] - node T_3950 = bits(s2_req.addr, 11, 6) @[dcache.scala 314:48] - metaWriteArb.io.in[1].bits.idx <= T_3950 @[dcache.scala 314:34] - node T_3951 = eq(s2_req.cmd, UInt<5>("h01")) @[Consts.scala 36:32] - node T_3952 = eq(s2_req.cmd, UInt<5>("h07")) @[Consts.scala 36:49] - node T_3953 = or(T_3951, T_3952) @[Consts.scala 36:42] - node T_3954 = bits(s2_req.cmd, 3, 3) @[Consts.scala 33:29] - node T_3955 = eq(s2_req.cmd, UInt<5>("h04")) @[Consts.scala 33:40] - node T_3956 = or(T_3954, T_3955) @[Consts.scala 33:33] - node T_3957 = or(T_3953, T_3956) @[Consts.scala 36:59] - node T_3958 = mux(T_3957, UInt<2>("h02"), UInt<2>("h01")) @[Policies.scala 268:12] - node T_3959 = mux(io.mem.grant.bits.is_builtin_type, UInt<2>("h00"), T_3958) @[Policies.scala 267:10] - wire T_3982 : {state : UInt<2>} @[Metadata.scala 158:20] - T_3982 is invalid @[Metadata.scala 158:20] - T_3982.state <= T_3959 @[Metadata.scala 159:16] - metaWriteArb.io.in[1].bits.data.coh <- T_3982 @[dcache.scala 315:39] - node T_4004 = bits(s2_req.addr, 31, 12) @[dcache.scala 316:53] - metaWriteArb.io.in[1].bits.data.tag <= T_4004 @[dcache.scala 316:39] - node T_4005 = and(io.mem.grant.ready, io.mem.grant.valid) @[Decoupled.scala 21:42] - node T_4008 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_4010 = eq(io.mem.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_4011 = and(io.mem.grant.bits.is_builtin_type, T_4010) @[Definitions.scala 277:59] - node T_4013 = eq(T_4011, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_4014 = and(T_4008, T_4013) @[Definitions.scala 278:89] - node T_4015 = and(T_4005, T_4014) @[dcache.scala 319:42] - node T_4017 = eq(grantIsRefill, UInt<1>("h00")) @[dcache.scala 319:81] - node T_4018 = or(T_4017, refillDone) @[dcache.scala 319:96] - node T_4019 = and(T_4015, T_4018) @[dcache.scala 319:77] - fq.io.enq.valid <= T_4019 @[dcache.scala 319:19] - wire T_4043 : {manager_xact_id : UInt<4>, manager_id : UInt<1>} @[Definitions.scala 816:17] - T_4043 is invalid @[Definitions.scala 816:17] - T_4043.manager_xact_id <= io.mem.grant.bits.manager_xact_id @[Definitions.scala 817:23] - T_4043.manager_id <= io.mem.grant.bits.manager_id @[Definitions.scala 818:18] - fq.io.enq.bits <- T_4043 @[dcache.scala 320:18] - io.mem.finish <- fq.io.deq @[dcache.scala 321:17] - when fq.io.enq.valid : @[dcache.scala 322:26] - node T_4066 = or(fq.io.enq.ready, reset) @[dcache.scala 322:34] - node T_4068 = eq(T_4066, UInt<1>("h00")) @[dcache.scala 322:34] - when T_4068 : @[dcache.scala 322:34] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:322 when (fq.io.enq.valid) { assert(fq.io.enq.ready) }\n") @[dcache.scala 322:34] - stop(clk, UInt<1>(1), 1) @[dcache.scala 322:34] - skip @[dcache.scala 322:34] - skip @[dcache.scala 322:26] - when refillDone : @[dcache.scala 323:21] - T_1926 <= UInt<1>("h01") @[Cache.scala 64:22] - skip @[dcache.scala 323:21] - node T_4070 = or(releaseInFlight, lrscValid) @[dcache.scala 326:37] - node T_4071 = and(s2_valid_hit, s2_lr) @[dcache.scala 326:67] - node block_probe = or(T_4070, T_4071) @[dcache.scala 326:50] - node T_4073 = eq(block_probe, UInt<1>("h00")) @[dcache.scala 327:55] - node T_4074 = and(io.mem.probe.valid, T_4073) @[dcache.scala 327:52] - metaReadArb.io.in[1].valid <= T_4074 @[dcache.scala 327:30] - node T_4076 = eq(block_probe, UInt<1>("h00")) @[dcache.scala 328:55] - node T_4077 = and(metaReadArb.io.in[1].ready, T_4076) @[dcache.scala 328:52] - node T_4079 = eq(s1_valid, UInt<1>("h00")) @[dcache.scala 328:71] - node T_4080 = and(T_4077, T_4079) @[dcache.scala 328:68] - node T_4082 = eq(s2_valid, UInt<1>("h00")) @[dcache.scala 328:85] - node T_4083 = or(T_4082, s2_valid_hit) @[dcache.scala 328:95] - node T_4084 = and(T_4080, T_4083) @[dcache.scala 328:81] - io.mem.probe.ready <= T_4084 @[dcache.scala 328:22] - metaReadArb.io.in[1].bits.idx <= io.mem.probe.bits.addr_block @[dcache.scala 329:33] - node T_4086 = not(UInt<4>("h00")) @[dcache.scala 330:39] - metaReadArb.io.in[1].bits.way_en <= T_4086 @[dcache.scala 330:36] - node T_4087 = and(io.mem.release.ready, io.mem.release.valid) @[Decoupled.scala 21:42] - node T_4088 = and(T_4087, inWriteback) @[dcache.scala 333:71] - reg writebackCount : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_4088 : @[Counter.scala 43:17] - node T_4091 = eq(writebackCount, UInt<3>("h07")) @[Counter.scala 20:24] - node T_4093 = add(writebackCount, UInt<1>("h01")) @[Counter.scala 21:22] - node T_4094 = tail(T_4093, 1) @[Counter.scala 21:22] - writebackCount <= T_4094 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node writebackDone = and(T_4088, T_4091) @[Counter.scala 44:20] - node T_4095 = and(io.mem.release.ready, io.mem.release.valid) @[Decoupled.scala 21:42] - node T_4097 = eq(inWriteback, UInt<1>("h00")) @[dcache.scala 334:64] - node T_4098 = and(T_4095, T_4097) @[dcache.scala 334:61] - node releaseDone = or(writebackDone, T_4098) @[dcache.scala 334:35] - node T_4100 = eq(io.mem.release.ready, UInt<1>("h00")) @[dcache.scala 335:49] - node releaseRejected = and(io.mem.release.valid, T_4100) @[dcache.scala 335:46] - node T_4101 = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid) @[Decoupled.scala 21:42] - reg s1_release_data_valid : UInt<1>, clk + node T_2983 = eq(pstore1_cmd, UInt<5>("h0")) + node T_2984 = eq(pstore1_cmd, UInt<5>("h6")) + node T_2985 = or(T_2983, T_2984) + node T_2986 = eq(pstore1_cmd, UInt<5>("h7")) + node T_2987 = or(T_2985, T_2986) + node T_2988 = bits(pstore1_cmd, 3, 3) + node T_2989 = eq(pstore1_cmd, UInt<5>("h4")) + node T_2990 = or(T_2988, T_2989) + node T_2991 = or(T_2987, T_2990) + node pstore1_amo = and(UInt<1>("h1"), T_2991) + node T_2992 = and(pstore1_valid, pstore2_valid) + node T_2993 = and(s1_valid, s1_write) + node T_2994 = or(T_2993, pstore1_amo) + node pstore_drain_structural = and(T_2992, T_2994) + node T_2995 = eq(io.cpu.req.bits.cmd, UInt<5>("h0")) + node T_2996 = eq(io.cpu.req.bits.cmd, UInt<5>("h6")) + node T_2997 = or(T_2995, T_2996) + node T_2998 = eq(io.cpu.req.bits.cmd, UInt<5>("h7")) + node T_2999 = or(T_2997, T_2998) + node T_3000 = bits(io.cpu.req.bits.cmd, 3, 3) + node T_3001 = eq(io.cpu.req.bits.cmd, UInt<5>("h4")) + node T_3002 = or(T_3000, T_3001) + node T_3003 = or(T_2999, T_3002) + node T_3004 = and(io.cpu.req.valid, T_3003) + node pstore_drain_opportunistic = eq(T_3004, UInt<1>("h0")) + node pstore_drain_on_miss = or(releaseInFlight, io.cpu.s2_nack) + node T_3007 = and(UInt<1>("h1"), pstore_drain_structural) + node T_3009 = eq(pstore1_amo, UInt<1>("h0")) + node T_3010 = and(pstore1_valid, T_3009) + node T_3011 = or(T_3010, pstore2_valid) + node T_3012 = or(pstore_drain_opportunistic, pstore_drain_on_miss) + node T_3013 = and(T_3011, T_3012) + node pstore_drain = or(T_3007, T_3013) + node T_3014 = and(s2_valid_hit, s2_write) + node T_3016 = eq(s2_sc_fail, UInt<1>("h0")) + node T_3017 = and(T_3014, T_3016) + reg T_3019 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_3019) + node T_3021 = eq(T_3017, UInt<1>("h0")) + node T_3023 = eq(T_3019, UInt<1>("h0")) + node T_3024 = or(T_3021, T_3023) + node T_3025 = or(T_3024, reset) + node T_3027 = eq(T_3025, UInt<1>("h0")) + when T_3027 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:214 assert(!s2_store_valid || !pstore1_held)\n") + stop(clk, UInt<1>("h1"), 1) + node T_3028 = or(T_3017, T_3019) + node T_3029 = and(T_3028, pstore2_valid) + node T_3031 = eq(pstore_drain, UInt<1>("h0")) + node T_3032 = and(T_3029, T_3031) + T_3019 <= T_3032 + node T_3033 = or(T_3017, T_3019) + pstore1_valid <= T_3033 + node T_3034 = eq(pstore2_valid, pstore_drain) + node advance_pstore1 = and(pstore1_valid, T_3034) + node T_3036 = eq(pstore_drain, UInt<1>("h0")) + node T_3037 = and(pstore2_valid, T_3036) + node T_3038 = or(T_3037, advance_pstore1) + pstore2_valid <= T_3038 + reg pstore2_addr : UInt<32>, clk with : + reset => (UInt<1>("h0"), pstore2_addr) + when advance_pstore1 : + pstore2_addr <= pstore1_addr + reg pstore2_way : UInt<4>, clk with : + reset => (UInt<1>("h0"), pstore2_way) + when advance_pstore1 : + pstore2_way <= pstore1_way + reg pstore2_storegen_data : UInt, clk with : + reset => (UInt<1>("h0"), pstore2_storegen_data) + when advance_pstore1 : + pstore2_storegen_data <= pstore1_storegen_data + node T_3040 = bits(pstore1_addr, 0, 0) + node T_3042 = mux(T_3040, UInt<1>("h1"), UInt<1>("h0")) + node T_3044 = geq(T_2963, UInt<1>("h1")) + node T_3047 = mux(T_3044, UInt<1>("h1"), UInt<1>("h0")) + node T_3048 = or(T_3042, T_3047) + node T_3049 = bits(pstore1_addr, 0, 0) + node T_3051 = mux(T_3049, UInt<1>("h0"), UInt<1>("h1")) + node T_3052 = cat(T_3048, T_3051) + node T_3053 = bits(pstore1_addr, 1, 1) + node T_3055 = mux(T_3053, T_3052, UInt<1>("h0")) + node T_3057 = geq(T_2963, UInt<2>("h2")) + node T_3060 = mux(T_3057, UInt<2>("h3"), UInt<1>("h0")) + node T_3061 = or(T_3055, T_3060) + node T_3062 = bits(pstore1_addr, 1, 1) + node T_3064 = mux(T_3062, UInt<1>("h0"), T_3052) + node T_3065 = cat(T_3061, T_3064) + node T_3066 = bits(pstore1_addr, 2, 2) + node T_3068 = mux(T_3066, T_3065, UInt<1>("h0")) + node T_3070 = geq(T_2963, UInt<2>("h3")) + node T_3073 = mux(T_3070, UInt<4>("hf"), UInt<1>("h0")) + node T_3074 = or(T_3068, T_3073) + node T_3075 = bits(pstore1_addr, 2, 2) + node T_3077 = mux(T_3075, UInt<1>("h0"), T_3065) + node T_3078 = cat(T_3074, T_3077) + reg pstore2_storegen_mask : UInt<8>, clk with : + reset => (UInt<1>("h0"), pstore2_storegen_mask) + when advance_pstore1 : + pstore2_storegen_mask <= T_3078 + dataArb.io.in[0].valid <= pstore_drain + dataArb.io.in[0].bits.write <= UInt<1>("h1") + node T_3080 = mux(pstore2_valid, pstore2_addr, pstore1_addr) + dataArb.io.in[0].bits.addr <= T_3080 + node T_3081 = mux(pstore2_valid, pstore2_way, pstore1_way) + dataArb.io.in[0].bits.way_en <= T_3081 + node T_3082 = mux(pstore2_valid, pstore2_storegen_data, pstore1_storegen_data) + dataArb.io.in[0].bits.wdata <= T_3082 + node T_3083 = mux(pstore2_valid, pstore2_addr, pstore1_addr) + node pstore_mask_shift = shl(UInt<1>("h0"), 3) + node T_3086 = bits(pstore1_addr, 0, 0) + node T_3088 = mux(T_3086, UInt<1>("h1"), UInt<1>("h0")) + node T_3090 = geq(T_2963, UInt<1>("h1")) + node T_3093 = mux(T_3090, UInt<1>("h1"), UInt<1>("h0")) + node T_3094 = or(T_3088, T_3093) + node T_3095 = bits(pstore1_addr, 0, 0) + node T_3097 = mux(T_3095, UInt<1>("h0"), UInt<1>("h1")) + node T_3098 = cat(T_3094, T_3097) + node T_3099 = bits(pstore1_addr, 1, 1) + node T_3101 = mux(T_3099, T_3098, UInt<1>("h0")) + node T_3103 = geq(T_2963, UInt<2>("h2")) + node T_3106 = mux(T_3103, UInt<2>("h3"), UInt<1>("h0")) + node T_3107 = or(T_3101, T_3106) + node T_3108 = bits(pstore1_addr, 1, 1) + node T_3110 = mux(T_3108, UInt<1>("h0"), T_3098) + node T_3111 = cat(T_3107, T_3110) + node T_3112 = bits(pstore1_addr, 2, 2) + node T_3114 = mux(T_3112, T_3111, UInt<1>("h0")) + node T_3116 = geq(T_2963, UInt<2>("h3")) + node T_3119 = mux(T_3116, UInt<4>("hf"), UInt<1>("h0")) + node T_3120 = or(T_3114, T_3119) + node T_3121 = bits(pstore1_addr, 2, 2) + node T_3123 = mux(T_3121, UInt<1>("h0"), T_3111) + node T_3124 = cat(T_3120, T_3123) + node T_3125 = mux(pstore2_valid, pstore2_storegen_mask, T_3124) + node T_3126 = dshl(T_3125, pstore_mask_shift) + dataArb.io.in[0].bits.wmask <= T_3126 + node s1_idx = bits(s1_req.addr, 11, 3) + node T_3127 = bits(pstore1_addr, 11, 3) + node T_3128 = eq(T_3127, s1_idx) + node T_3129 = and(pstore1_valid, T_3128) + node T_3131 = bits(pstore1_addr, 0, 0) + node T_3133 = mux(T_3131, UInt<1>("h1"), UInt<1>("h0")) + node T_3135 = geq(T_2963, UInt<1>("h1")) + node T_3138 = mux(T_3135, UInt<1>("h1"), UInt<1>("h0")) + node T_3139 = or(T_3133, T_3138) + node T_3140 = bits(pstore1_addr, 0, 0) + node T_3142 = mux(T_3140, UInt<1>("h0"), UInt<1>("h1")) + node T_3143 = cat(T_3139, T_3142) + node T_3144 = bits(pstore1_addr, 1, 1) + node T_3146 = mux(T_3144, T_3143, UInt<1>("h0")) + node T_3148 = geq(T_2963, UInt<2>("h2")) + node T_3151 = mux(T_3148, UInt<2>("h3"), UInt<1>("h0")) + node T_3152 = or(T_3146, T_3151) + node T_3153 = bits(pstore1_addr, 1, 1) + node T_3155 = mux(T_3153, UInt<1>("h0"), T_3143) + node T_3156 = cat(T_3152, T_3155) + node T_3157 = bits(pstore1_addr, 2, 2) + node T_3159 = mux(T_3157, T_3156, UInt<1>("h0")) + node T_3161 = geq(T_2963, UInt<2>("h3")) + node T_3164 = mux(T_3161, UInt<4>("hf"), UInt<1>("h0")) + node T_3165 = or(T_3159, T_3164) + node T_3166 = bits(pstore1_addr, 2, 2) + node T_3168 = mux(T_3166, UInt<1>("h0"), T_3156) + node T_3169 = cat(T_3165, T_3168) + node T_3171 = bits(s1_req.addr, 0, 0) + node T_3173 = mux(T_3171, UInt<1>("h1"), UInt<1>("h0")) + node T_3175 = geq(T_2914, UInt<1>("h1")) + node T_3178 = mux(T_3175, UInt<1>("h1"), UInt<1>("h0")) + node T_3179 = or(T_3173, T_3178) + node T_3180 = bits(s1_req.addr, 0, 0) + node T_3182 = mux(T_3180, UInt<1>("h0"), UInt<1>("h1")) + node T_3183 = cat(T_3179, T_3182) + node T_3184 = bits(s1_req.addr, 1, 1) + node T_3186 = mux(T_3184, T_3183, UInt<1>("h0")) + node T_3188 = geq(T_2914, UInt<2>("h2")) + node T_3191 = mux(T_3188, UInt<2>("h3"), UInt<1>("h0")) + node T_3192 = or(T_3186, T_3191) + node T_3193 = bits(s1_req.addr, 1, 1) + node T_3195 = mux(T_3193, UInt<1>("h0"), T_3183) + node T_3196 = cat(T_3192, T_3195) + node T_3197 = bits(s1_req.addr, 2, 2) + node T_3199 = mux(T_3197, T_3196, UInt<1>("h0")) + node T_3201 = geq(T_2914, UInt<2>("h3")) + node T_3204 = mux(T_3201, UInt<4>("hf"), UInt<1>("h0")) + node T_3205 = or(T_3199, T_3204) + node T_3206 = bits(s1_req.addr, 2, 2) + node T_3208 = mux(T_3206, UInt<1>("h0"), T_3196) + node T_3209 = cat(T_3205, T_3208) + node T_3210 = and(T_3169, T_3209) + node T_3212 = neq(T_3210, UInt<1>("h0")) + node T_3213 = and(T_3129, T_3212) + node T_3214 = bits(pstore2_addr, 11, 3) + node T_3215 = eq(T_3214, s1_idx) + node T_3216 = and(pstore2_valid, T_3215) + node T_3218 = bits(s1_req.addr, 0, 0) + node T_3220 = mux(T_3218, UInt<1>("h1"), UInt<1>("h0")) + node T_3222 = geq(T_2914, UInt<1>("h1")) + node T_3225 = mux(T_3222, UInt<1>("h1"), UInt<1>("h0")) + node T_3226 = or(T_3220, T_3225) + node T_3227 = bits(s1_req.addr, 0, 0) + node T_3229 = mux(T_3227, UInt<1>("h0"), UInt<1>("h1")) + node T_3230 = cat(T_3226, T_3229) + node T_3231 = bits(s1_req.addr, 1, 1) + node T_3233 = mux(T_3231, T_3230, UInt<1>("h0")) + node T_3235 = geq(T_2914, UInt<2>("h2")) + node T_3238 = mux(T_3235, UInt<2>("h3"), UInt<1>("h0")) + node T_3239 = or(T_3233, T_3238) + node T_3240 = bits(s1_req.addr, 1, 1) + node T_3242 = mux(T_3240, UInt<1>("h0"), T_3230) + node T_3243 = cat(T_3239, T_3242) + node T_3244 = bits(s1_req.addr, 2, 2) + node T_3246 = mux(T_3244, T_3243, UInt<1>("h0")) + node T_3248 = geq(T_2914, UInt<2>("h3")) + node T_3251 = mux(T_3248, UInt<4>("hf"), UInt<1>("h0")) + node T_3252 = or(T_3246, T_3251) + node T_3253 = bits(s1_req.addr, 2, 2) + node T_3255 = mux(T_3253, UInt<1>("h0"), T_3243) + node T_3256 = cat(T_3252, T_3255) + node T_3257 = and(pstore2_storegen_mask, T_3256) + node T_3259 = neq(T_3257, UInt<1>("h0")) + node T_3260 = and(T_3216, T_3259) + node T_3261 = or(T_3213, T_3260) + node s1_raw_hazard = and(s1_read, T_3261) + node T_3262 = and(s1_valid, s1_raw_hazard) + when T_3262 : + s1_nack <= UInt<1>("h1") + node T_3264 = and(s2_valid_hit, s2_update_meta) + node T_3266 = eq(s2_victim_dirty, UInt<1>("h0")) + node T_3267 = and(s2_victimize, T_3266) + node T_3268 = or(T_3264, T_3267) + metaWriteArb.io.in[0].valid <= T_3268 + metaWriteArb.io.in[0].bits.way_en <= s2_victim_way + node T_3269 = bits(s2_req.addr, 11, 6) + metaWriteArb.io.in[0].bits.idx <= T_3269 + wire T_3293 : { state : UInt<2>} + T_3293 is invalid + T_3293.state <= UInt<1>("h0") + node T_3315 = mux(s2_valid_hit, s2_new_hit_state, T_3293) + metaWriteArb.io.in[0].bits.data.coh <- T_3315 + node T_3337 = bits(s2_req.addr, 31, 12) + metaWriteArb.io.in[0].bits.data.tag <= T_3337 + node T_3339 = bits(s2_req.addr, 31, 6) + node T_3341 = eq(s2_req.cmd, UInt<5>("h1")) + node T_3342 = eq(s2_req.cmd, UInt<5>("h7")) + node T_3343 = or(T_3341, T_3342) + node T_3344 = bits(s2_req.cmd, 3, 3) + node T_3345 = eq(s2_req.cmd, UInt<5>("h4")) + node T_3346 = or(T_3344, T_3345) + node T_3347 = or(T_3343, T_3346) + node T_3348 = eq(s2_req.cmd, UInt<5>("h3")) + node T_3349 = or(T_3347, T_3348) + node T_3350 = eq(s2_req.cmd, UInt<5>("h6")) + node T_3351 = or(T_3349, T_3350) + node T_3352 = mux(T_3351, UInt<1>("h1"), UInt<1>("h0")) + node T_3354 = cat(s2_req.cmd, UInt<1>("h1")) + wire cachedGetMessage : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + cachedGetMessage is invalid + cachedGetMessage.is_builtin_type <= UInt<1>("h0") + cachedGetMessage.a_type <= T_3352 + cachedGetMessage.client_xact_id <= UInt<1>("h0") + cachedGetMessage.addr_block <= T_3339 + cachedGetMessage.addr_beat <= UInt<1>("h0") + cachedGetMessage.data <= UInt<1>("h0") + cachedGetMessage.union <= T_3354 + node T_3413 = bits(s2_req.addr, 31, 6) + node T_3414 = bits(s2_req.addr, 5, 3) + node T_3415 = bits(s2_req.addr, 2, 0) + node T_3442 = or(UInt<3>("h0"), T_3415) + node T_3443 = bits(T_3442, 2, 0) + node T_3445 = or(UInt<2>("h0"), s2_req.typ) + node T_3446 = bits(T_3445, 1, 0) + node T_3448 = or(UInt<5>("h0"), UInt<5>("h0")) + node T_3449 = bits(T_3448, 4, 0) + node T_3451 = or(UInt<8>("h0"), UInt<1>("h0")) + node T_3452 = bits(T_3451, 7, 0) + node T_3455 = cat(T_3449, UInt<1>("h0")) + node T_3456 = cat(T_3443, T_3446) + node T_3457 = cat(T_3456, T_3455) + node T_3459 = cat(T_3446, T_3449) + node T_3460 = cat(T_3459, UInt<1>("h0")) + node T_3462 = cat(T_3452, UInt<1>("h0")) + node T_3464 = cat(T_3452, UInt<1>("h0")) + node T_3466 = cat(T_3449, UInt<1>("h0")) + node T_3467 = cat(T_3443, T_3446) + node T_3468 = cat(T_3467, T_3466) + node T_3470 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3472 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3473 = eq(UInt<3>("h6"), UInt<3>("h0")) + node T_3474 = mux(T_3473, T_3472, UInt<1>("h0")) + node T_3475 = eq(UInt<3>("h5"), UInt<3>("h0")) + node T_3476 = mux(T_3475, T_3470, T_3474) + node T_3477 = eq(UInt<3>("h4"), UInt<3>("h0")) + node T_3478 = mux(T_3477, T_3468, T_3476) + node T_3479 = eq(UInt<3>("h3"), UInt<3>("h0")) + node T_3480 = mux(T_3479, T_3464, T_3478) + node T_3481 = eq(UInt<3>("h2"), UInt<3>("h0")) + node T_3482 = mux(T_3481, T_3462, T_3480) + node T_3483 = eq(UInt<3>("h1"), UInt<3>("h0")) + node T_3484 = mux(T_3483, T_3460, T_3482) + node T_3485 = eq(UInt<3>("h0"), UInt<3>("h0")) + node T_3486 = mux(T_3485, T_3457, T_3484) + wire uncachedGetMessage : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + uncachedGetMessage is invalid + uncachedGetMessage.is_builtin_type <= UInt<1>("h1") + uncachedGetMessage.a_type <= UInt<3>("h0") + uncachedGetMessage.client_xact_id <= UInt<1>("h0") + uncachedGetMessage.addr_block <= T_3413 + uncachedGetMessage.addr_beat <= T_3414 + uncachedGetMessage.data <= UInt<1>("h0") + uncachedGetMessage.union <= T_3486 + node T_3543 = bits(s2_req.addr, 31, 6) + node T_3544 = bits(s2_req.addr, 5, 3) + node T_3546 = eq(T_2963, UInt<1>("h0")) + node T_3547 = bits(pstore1_data, 7, 0) + node T_3548 = cat(T_3547, T_3547) + node T_3549 = cat(T_3548, T_3548) + node T_3550 = cat(T_3549, T_3549) + node T_3552 = eq(T_2963, UInt<1>("h1")) + node T_3553 = bits(pstore1_data, 15, 0) + node T_3554 = cat(T_3553, T_3553) + node T_3555 = cat(T_3554, T_3554) + node T_3557 = eq(T_2963, UInt<2>("h2")) + node T_3558 = bits(pstore1_data, 31, 0) + node T_3559 = cat(T_3558, T_3558) + node T_3560 = mux(T_3557, T_3559, pstore1_data) + node T_3561 = mux(T_3552, T_3555, T_3560) + node T_3562 = mux(T_3546, T_3550, T_3561) + node T_3564 = bits(pstore1_addr, 0, 0) + node T_3566 = mux(T_3564, UInt<1>("h1"), UInt<1>("h0")) + node T_3568 = geq(T_2963, UInt<1>("h1")) + node T_3571 = mux(T_3568, UInt<1>("h1"), UInt<1>("h0")) + node T_3572 = or(T_3566, T_3571) + node T_3573 = bits(pstore1_addr, 0, 0) + node T_3575 = mux(T_3573, UInt<1>("h0"), UInt<1>("h1")) + node T_3576 = cat(T_3572, T_3575) + node T_3577 = bits(pstore1_addr, 1, 1) + node T_3579 = mux(T_3577, T_3576, UInt<1>("h0")) + node T_3581 = geq(T_2963, UInt<2>("h2")) + node T_3584 = mux(T_3581, UInt<2>("h3"), UInt<1>("h0")) + node T_3585 = or(T_3579, T_3584) + node T_3586 = bits(pstore1_addr, 1, 1) + node T_3588 = mux(T_3586, UInt<1>("h0"), T_3576) + node T_3589 = cat(T_3585, T_3588) + node T_3590 = bits(pstore1_addr, 2, 2) + node T_3592 = mux(T_3590, T_3589, UInt<1>("h0")) + node T_3594 = geq(T_2963, UInt<2>("h3")) + node T_3597 = mux(T_3594, UInt<4>("hf"), UInt<1>("h0")) + node T_3598 = or(T_3592, T_3597) + node T_3599 = bits(pstore1_addr, 2, 2) + node T_3601 = mux(T_3599, UInt<1>("h0"), T_3589) + node T_3602 = cat(T_3598, T_3601) + node T_3603 = shl(UInt<1>("h0"), 3) + node T_3604 = dshl(T_3602, T_3603) + node T_3632 = or(UInt<3>("h0"), UInt<1>("h0")) + node T_3633 = bits(T_3632, 2, 0) + node T_3635 = or(UInt<2>("h0"), UInt<1>("h0")) + node T_3636 = bits(T_3635, 1, 0) + node T_3638 = or(UInt<5>("h0"), UInt<1>("h0")) + node T_3639 = bits(T_3638, 4, 0) + node T_3641 = or(UInt<8>("h0"), T_3604) + node T_3642 = bits(T_3641, 7, 0) + node T_3645 = cat(T_3639, UInt<1>("h0")) + node T_3646 = cat(T_3633, T_3636) + node T_3647 = cat(T_3646, T_3645) + node T_3649 = cat(T_3636, T_3639) + node T_3650 = cat(T_3649, UInt<1>("h0")) + node T_3652 = cat(T_3642, UInt<1>("h0")) + node T_3654 = cat(T_3642, UInt<1>("h0")) + node T_3656 = cat(T_3639, UInt<1>("h0")) + node T_3657 = cat(T_3633, T_3636) + node T_3658 = cat(T_3657, T_3656) + node T_3660 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3662 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3663 = eq(UInt<3>("h6"), UInt<3>("h2")) + node T_3664 = mux(T_3663, T_3662, UInt<1>("h0")) + node T_3665 = eq(UInt<3>("h5"), UInt<3>("h2")) + node T_3666 = mux(T_3665, T_3660, T_3664) + node T_3667 = eq(UInt<3>("h4"), UInt<3>("h2")) + node T_3668 = mux(T_3667, T_3658, T_3666) + node T_3669 = eq(UInt<3>("h3"), UInt<3>("h2")) + node T_3670 = mux(T_3669, T_3654, T_3668) + node T_3671 = eq(UInt<3>("h2"), UInt<3>("h2")) + node T_3672 = mux(T_3671, T_3652, T_3670) + node T_3673 = eq(UInt<3>("h1"), UInt<3>("h2")) + node T_3674 = mux(T_3673, T_3650, T_3672) + node T_3675 = eq(UInt<3>("h0"), UInt<3>("h2")) + node T_3676 = mux(T_3675, T_3647, T_3674) + wire uncachedPutMessage : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + uncachedPutMessage is invalid + uncachedPutMessage.is_builtin_type <= UInt<1>("h1") + uncachedPutMessage.a_type <= UInt<3>("h2") + uncachedPutMessage.client_xact_id <= UInt<1>("h0") + uncachedPutMessage.addr_block <= T_3543 + uncachedPutMessage.addr_beat <= T_3544 + uncachedPutMessage.data <= T_3562 + uncachedPutMessage.union <= T_3676 + node T_3733 = bits(s2_req.addr, 31, 6) + node T_3734 = bits(s2_req.addr, 5, 3) + node T_3735 = bits(s2_req.addr, 2, 0) + node T_3737 = eq(T_2963, UInt<1>("h0")) + node T_3738 = bits(pstore1_data, 7, 0) + node T_3739 = cat(T_3738, T_3738) + node T_3740 = cat(T_3739, T_3739) + node T_3741 = cat(T_3740, T_3740) + node T_3743 = eq(T_2963, UInt<1>("h1")) + node T_3744 = bits(pstore1_data, 15, 0) + node T_3745 = cat(T_3744, T_3744) + node T_3746 = cat(T_3745, T_3745) + node T_3748 = eq(T_2963, UInt<2>("h2")) + node T_3749 = bits(pstore1_data, 31, 0) + node T_3750 = cat(T_3749, T_3749) + node T_3751 = mux(T_3748, T_3750, pstore1_data) + node T_3752 = mux(T_3743, T_3746, T_3751) + node T_3753 = mux(T_3737, T_3741, T_3752) + node T_3779 = or(UInt<3>("h0"), T_3735) + node T_3780 = bits(T_3779, 2, 0) + node T_3782 = or(UInt<2>("h0"), s2_req.typ) + node T_3783 = bits(T_3782, 1, 0) + node T_3785 = or(UInt<5>("h0"), s2_req.cmd) + node T_3786 = bits(T_3785, 4, 0) + node T_3788 = or(UInt<8>("h0"), UInt<1>("h0")) + node T_3789 = bits(T_3788, 7, 0) + node T_3792 = cat(T_3786, UInt<1>("h1")) + node T_3793 = cat(T_3780, T_3783) + node T_3794 = cat(T_3793, T_3792) + node T_3796 = cat(T_3783, T_3786) + node T_3797 = cat(T_3796, UInt<1>("h1")) + node T_3799 = cat(T_3789, UInt<1>("h1")) + node T_3801 = cat(T_3789, UInt<1>("h1")) + node T_3803 = cat(T_3786, UInt<1>("h1")) + node T_3804 = cat(T_3780, T_3783) + node T_3805 = cat(T_3804, T_3803) + node T_3807 = cat(UInt<5>("h0"), UInt<1>("h1")) + node T_3809 = cat(UInt<5>("h1"), UInt<1>("h1")) + node T_3810 = eq(UInt<3>("h6"), UInt<3>("h4")) + node T_3811 = mux(T_3810, T_3809, UInt<1>("h0")) + node T_3812 = eq(UInt<3>("h5"), UInt<3>("h4")) + node T_3813 = mux(T_3812, T_3807, T_3811) + node T_3814 = eq(UInt<3>("h4"), UInt<3>("h4")) + node T_3815 = mux(T_3814, T_3805, T_3813) + node T_3816 = eq(UInt<3>("h3"), UInt<3>("h4")) + node T_3817 = mux(T_3816, T_3801, T_3815) + node T_3818 = eq(UInt<3>("h2"), UInt<3>("h4")) + node T_3819 = mux(T_3818, T_3799, T_3817) + node T_3820 = eq(UInt<3>("h1"), UInt<3>("h4")) + node T_3821 = mux(T_3820, T_3797, T_3819) + node T_3822 = eq(UInt<3>("h0"), UInt<3>("h4")) + node T_3823 = mux(T_3822, T_3794, T_3821) + wire uncachedPutAtomicMessage : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + uncachedPutAtomicMessage is invalid + uncachedPutAtomicMessage.is_builtin_type <= UInt<1>("h1") + uncachedPutAtomicMessage.a_type <= UInt<3>("h4") + uncachedPutAtomicMessage.client_xact_id <= UInt<1>("h0") + uncachedPutAtomicMessage.addr_block <= T_3733 + uncachedPutAtomicMessage.addr_beat <= T_3734 + uncachedPutAtomicMessage.data <= T_3753 + uncachedPutAtomicMessage.union <= T_3823 + node T_3880 = eq(s2_victim_dirty, UInt<1>("h0")) + node T_3881 = and(s2_valid_cached_miss, T_3880) + node T_3882 = or(T_3881, s2_valid_uncached) + node T_3883 = and(T_3882, fq.io.enq.ready) + io.mem.acquire.valid <= T_3883 + io.mem.acquire.bits <- cachedGetMessage + when s2_uncached : + node T_3885 = eq(s2_valid_masked, UInt<1>("h0")) + node T_3886 = neq(s2_hit_state.state, UInt<2>("h0")) + node T_3888 = eq(T_3886, UInt<1>("h0")) + node T_3889 = or(T_3885, T_3888) + node T_3890 = or(T_3889, reset) + node T_3892 = eq(T_3890, UInt<1>("h0")) + when T_3892 : + printf(clk, UInt<1>("h1"), "Assertion failed: cache hit on uncached access\n at dcache.scala:277 assert(!s2_valid_masked || !s2_hit_state.isValid(), \"cache hit on uncached access\")\n") + stop(clk, UInt<1>("h1"), 1) + io.mem.acquire.bits <- uncachedGetMessage + when s2_write : + io.mem.acquire.bits <- uncachedPutMessage + when pstore1_amo : + io.mem.acquire.bits <- uncachedPutAtomicMessage + node T_3893 = and(io.mem.acquire.ready, io.mem.acquire.valid) + when T_3893 : + grant_wait <= UInt<1>("h1") + wire T_3902 : UInt<3>[1] + T_3902 is invalid + T_3902[0] <= UInt<3>("h5") + node T_3904 = eq(io.mem.grant.bits.g_type, T_3902[0]) + node T_3905 = eq(io.mem.grant.bits.g_type, UInt<1>("h0")) + node T_3906 = mux(io.mem.grant.bits.is_builtin_type, T_3904, T_3905) + node grantIsRefill = and(UInt<1>("h1"), T_3906) + node T_3908 = eq(io.mem.grant.bits.g_type, UInt<3>("h0")) + node grantIsVoluntary = and(io.mem.grant.bits.is_builtin_type, T_3908) + node T_3910 = eq(grantIsRefill, UInt<1>("h0")) + node T_3912 = eq(grantIsVoluntary, UInt<1>("h0")) + node grantIsUncached = and(T_3910, T_3912) + when io.mem.grant.valid : + node T_3913 = and(grantIsVoluntary, release_ack_wait) + node T_3914 = or(grant_wait, T_3913) + node T_3915 = or(T_3914, reset) + node T_3917 = eq(T_3915, UInt<1>("h0")) + when T_3917 : + printf(clk, UInt<1>("h1"), "Assertion failed: unexpected grant\n at dcache.scala:293 assert(grant_wait || grantIsVoluntary && release_ack_wait, \"unexpected grant\")\n") + stop(clk, UInt<1>("h1"), 1) + when grantIsUncached : + s2_data <= io.mem.grant.bits.data + when grantIsVoluntary : + release_ack_wait <= UInt<1>("h0") + node T_3919 = and(io.mem.grant.ready, io.mem.grant.valid) + node T_3920 = and(T_3919, grantIsRefill) + reg refillCount : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3920 : + T_3923 <= eq(refillCount, UInt<3>("h7")) + node T_3925 = add(refillCount, UInt<1>("h1")) + node T_3926 = tail(T_3925, 1) + refillCount <= T_3926 + node refillDone = and(T_3920, T_3923) + node grantDone = or(refillDone, grantIsUncached) + node T_3927 = and(io.mem.grant.ready, io.mem.grant.valid) + node T_3928 = and(T_3927, grantDone) + when T_3928 : + grant_wait <= UInt<1>("h0") + node T_3930 = and(grantIsRefill, io.mem.grant.valid) + dataArb.io.in[1].valid <= T_3930 + io.mem.grant.ready <= UInt<1>("h1") + node T_3933 = eq(dataArb.io.in[1].valid, UInt<1>("h0")) + node T_3934 = or(dataArb.io.in[1].ready, T_3933) + node T_3935 = or(T_3934, reset) + node T_3937 = eq(T_3935, UInt<1>("h0")) + when T_3937 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:304 assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid)\n") + stop(clk, UInt<1>("h1"), 1) + dataArb.io.in[1].bits.write <= UInt<1>("h1") + node T_3939 = bits(s2_req.addr, 31, 6) + node T_3940 = cat(T_3939, io.mem.grant.bits.addr_beat) + node T_3941 = shl(T_3940, 3) + dataArb.io.in[1].bits.addr <= T_3941 + dataArb.io.in[1].bits.way_en <= s2_victim_way + dataArb.io.in[1].bits.wdata <= io.mem.grant.bits.data + node T_3943 = not(UInt<8>("h0")) + dataArb.io.in[1].bits.wmask <= T_3943 + metaWriteArb.io.in[1].valid <= refillDone + node T_3945 = eq(metaWriteArb.io.in[1].valid, UInt<1>("h0")) + node T_3946 = or(T_3945, metaWriteArb.io.in[1].ready) + node T_3947 = or(T_3946, reset) + node T_3949 = eq(T_3947, UInt<1>("h0")) + when T_3949 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:312 assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready)\n") + stop(clk, UInt<1>("h1"), 1) + metaWriteArb.io.in[1].bits.way_en <= s2_victim_way + node T_3950 = bits(s2_req.addr, 11, 6) + metaWriteArb.io.in[1].bits.idx <= T_3950 + node T_3951 = eq(s2_req.cmd, UInt<5>("h1")) + node T_3952 = eq(s2_req.cmd, UInt<5>("h7")) + node T_3953 = or(T_3951, T_3952) + node T_3954 = bits(s2_req.cmd, 3, 3) + node T_3955 = eq(s2_req.cmd, UInt<5>("h4")) + node T_3956 = or(T_3954, T_3955) + node T_3957 = or(T_3953, T_3956) + node T_3958 = mux(T_3957, UInt<2>("h2"), UInt<2>("h1")) + node T_3959 = mux(io.mem.grant.bits.is_builtin_type, UInt<2>("h0"), T_3958) + wire T_3982 : { state : UInt<2>} + T_3982 is invalid + T_3982.state <= T_3959 + metaWriteArb.io.in[1].bits.data.coh <- T_3982 + node T_4004 = bits(s2_req.addr, 31, 12) + metaWriteArb.io.in[1].bits.data.tag <= T_4004 + node T_4005 = and(io.mem.grant.ready, io.mem.grant.valid) + node T_4008 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_4010 = eq(io.mem.grant.bits.g_type, UInt<3>("h0")) + node T_4011 = and(io.mem.grant.bits.is_builtin_type, T_4010) + node T_4013 = eq(T_4011, UInt<1>("h0")) + node T_4014 = and(T_4008, T_4013) + node T_4015 = and(T_4005, T_4014) + node T_4017 = eq(grantIsRefill, UInt<1>("h0")) + node T_4018 = or(T_4017, refillDone) + node T_4019 = and(T_4015, T_4018) + fq.io.enq.valid <= T_4019 + wire T_4043 : { manager_xact_id : UInt<4>, manager_id : UInt<1>} + T_4043 is invalid + T_4043.manager_xact_id <= io.mem.grant.bits.manager_xact_id + T_4043.manager_id <= io.mem.grant.bits.manager_id + fq.io.enq.bits <- T_4043 + io.mem.finish <- fq.io.deq + when fq.io.enq.valid : + node T_4066 = or(fq.io.enq.ready, reset) + node T_4068 = eq(T_4066, UInt<1>("h0")) + when T_4068 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:322 when (fq.io.enq.valid) { assert(fq.io.enq.ready) }\n") + stop(clk, UInt<1>("h1"), 1) + when refillDone : + T_1926 <= UInt<1>("h1") + node T_4070 = or(releaseInFlight, lrscValid) + node T_4071 = and(s2_valid_hit, s2_lr) + node block_probe = or(T_4070, T_4071) + node T_4073 = eq(block_probe, UInt<1>("h0")) + node T_4074 = and(io.mem.probe.valid, T_4073) + metaReadArb.io.in[1].valid <= T_4074 + node T_4076 = eq(block_probe, UInt<1>("h0")) + node T_4077 = and(metaReadArb.io.in[1].ready, T_4076) + node T_4079 = eq(s1_valid, UInt<1>("h0")) + node T_4080 = and(T_4077, T_4079) + node T_4082 = eq(s2_valid, UInt<1>("h0")) + node T_4083 = or(T_4082, s2_valid_hit) + node T_4084 = and(T_4080, T_4083) + io.mem.probe.ready <= T_4084 + metaReadArb.io.in[1].bits.idx <= io.mem.probe.bits.addr_block + node T_4086 = not(UInt<4>("h0")) + metaReadArb.io.in[1].bits.way_en <= T_4086 + node T_4087 = and(io.mem.release.ready, io.mem.release.valid) + node T_4088 = and(T_4087, inWriteback) + reg writebackCount : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_4088 : + T_4091 <= eq(writebackCount, UInt<3>("h7")) + node T_4093 = add(writebackCount, UInt<1>("h1")) + node T_4094 = tail(T_4093, 1) + writebackCount <= T_4094 + node writebackDone = and(T_4088, T_4091) + node T_4095 = and(io.mem.release.ready, io.mem.release.valid) + node T_4097 = eq(inWriteback, UInt<1>("h0")) + node T_4098 = and(T_4095, T_4097) + node releaseDone = or(writebackDone, T_4098) + node T_4100 = eq(io.mem.release.ready, UInt<1>("h0")) + node releaseRejected = and(io.mem.release.valid, T_4100) + node T_4101 = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid) + reg s1_release_data_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), s1_release_data_valid) s1_release_data_valid <= T_4101 - node T_4103 = eq(releaseRejected, UInt<1>("h00")) @[dcache.scala 337:67] - node T_4104 = and(s1_release_data_valid, T_4103) @[dcache.scala 337:64] - reg s2_release_data_valid : UInt<1>, clk + node T_4103 = eq(releaseRejected, UInt<1>("h0")) + node T_4104 = and(s1_release_data_valid, T_4103) + reg s2_release_data_valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), s2_release_data_valid) s2_release_data_valid <= T_4104 - node T_4106 = cat(UInt<1>("h00"), writebackCount) @[Cat.scala 20:58] - node T_4109 = cat(UInt<1>("h00"), s2_release_data_valid) @[Cat.scala 20:58] - node T_4110 = add(s1_release_data_valid, T_4109) @[dcache.scala 338:108] - node T_4111 = tail(T_4110, 1) @[dcache.scala 338:108] - node T_4112 = mux(releaseRejected, UInt<1>("h00"), T_4111) @[dcache.scala 338:59] - node T_4113 = add(T_4106, T_4112) @[dcache.scala 338:54] - node releaseDataBeat = tail(T_4113, 1) @[dcache.scala 338:54] - io.mem.release.valid <= s2_release_data_valid @[dcache.scala 339:24] - wire T_4137 : {state : UInt<2>} @[Metadata.scala 158:20] - T_4137 is invalid @[Metadata.scala 158:20] - T_4137.state <= UInt<1>("h00") @[Metadata.scala 159:16] - node T_4162 = eq(T_4137.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4163 = mux(T_4162, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4164 = mux(T_4162, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4165 = mux(T_4162, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4166 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4167 = mux(T_4166, T_4165, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4168 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4169 = mux(T_4168, T_4164, T_4167) @[Mux.scala 46:16] - node T_4170 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4171 = mux(T_4170, T_4163, T_4169) @[Mux.scala 46:16] - node T_4172 = eq(T_4137.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4173 = mux(T_4172, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4174 = mux(T_4172, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4175 = mux(T_4172, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4176 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4177 = mux(T_4176, T_4175, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4178 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4179 = mux(T_4178, T_4174, T_4177) @[Mux.scala 46:16] - node T_4180 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4181 = mux(T_4180, T_4173, T_4179) @[Mux.scala 46:16] - node T_4182 = eq(T_4137.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4183 = mux(T_4182, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4184 = mux(T_4182, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4185 = mux(T_4182, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4186 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4187 = mux(T_4186, T_4185, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4188 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4189 = mux(T_4188, T_4184, T_4187) @[Mux.scala 46:16] - node T_4190 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4191 = mux(T_4190, T_4183, T_4189) @[Mux.scala 46:16] - node T_4192 = eq(UInt<2>("h02"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4193 = mux(T_4192, T_4191, UInt<3>("h03")) @[Mux.scala 46:16] - node T_4194 = eq(UInt<2>("h01"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4195 = mux(T_4194, T_4181, T_4193) @[Mux.scala 46:16] - node T_4196 = eq(UInt<2>("h00"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4197 = mux(T_4196, T_4171, T_4195) @[Mux.scala 46:16] - wire T_4226 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_4226 is invalid @[Definitions.scala 754:19] - T_4226.r_type <= T_4197 @[Definitions.scala 755:16] - T_4226.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_4226.addr_block <= probe_bits.addr_block @[Definitions.scala 757:20] - T_4226.addr_beat <= UInt<1>("h00") @[Definitions.scala 758:19] - T_4226.data <= UInt<1>("h00") @[Definitions.scala 759:14] - T_4226.voluntary <= UInt<1>("h00") @[Definitions.scala 760:19] - io.mem.release.bits <- T_4226 @[dcache.scala 340:23] - node T_4258 = eq(s2_victim_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4259 = mux(T_4258, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4260 = mux(T_4258, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4261 = mux(T_4258, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4262 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4263 = mux(T_4262, T_4261, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4264 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4265 = mux(T_4264, T_4260, T_4263) @[Mux.scala 46:16] - node T_4266 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4267 = mux(T_4266, T_4259, T_4265) @[Mux.scala 46:16] - wire voluntaryReleaseMessage : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - voluntaryReleaseMessage is invalid @[Definitions.scala 754:19] - voluntaryReleaseMessage.r_type <= T_4267 @[Definitions.scala 755:16] - voluntaryReleaseMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - voluntaryReleaseMessage.addr_block <= UInt<1>("h00") @[Definitions.scala 757:20] - voluntaryReleaseMessage.addr_beat <= UInt<1>("h00") @[Definitions.scala 758:19] - voluntaryReleaseMessage.data <= UInt<1>("h00") @[Definitions.scala 759:14] - voluntaryReleaseMessage.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - node T_4321 = eq(s2_victim_state.state, UInt<2>("h02")) @[Policies.scala 263:35] - node T_4322 = mux(T_4321, UInt<2>("h01"), s2_victim_state.state) @[Policies.scala 263:23] - node T_4323 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4324 = mux(T_4323, T_4322, s2_victim_state.state) @[Mux.scala 46:16] - node T_4325 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4326 = mux(T_4325, UInt<2>("h00"), T_4324) @[Mux.scala 46:16] - wire voluntaryNewCoh : {state : UInt<2>} @[Metadata.scala 158:20] - voluntaryNewCoh is invalid @[Metadata.scala 158:20] - voluntaryNewCoh.state <= T_4326 @[Metadata.scala 159:16] - node T_4373 = eq(s2_probe_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4374 = mux(T_4373, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4375 = mux(T_4373, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4376 = mux(T_4373, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4377 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4378 = mux(T_4377, T_4376, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4379 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4380 = mux(T_4379, T_4375, T_4378) @[Mux.scala 46:16] - node T_4381 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4382 = mux(T_4381, T_4374, T_4380) @[Mux.scala 46:16] - node T_4383 = eq(s2_probe_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4384 = mux(T_4383, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4385 = mux(T_4383, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4386 = mux(T_4383, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4387 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4388 = mux(T_4387, T_4386, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4389 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4390 = mux(T_4389, T_4385, T_4388) @[Mux.scala 46:16] - node T_4391 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4392 = mux(T_4391, T_4384, T_4390) @[Mux.scala 46:16] - node T_4393 = eq(s2_probe_state.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_4394 = mux(T_4393, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_4395 = mux(T_4393, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_4396 = mux(T_4393, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_4397 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4398 = mux(T_4397, T_4396, UInt<3>("h05")) @[Mux.scala 46:16] - node T_4399 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4400 = mux(T_4399, T_4395, T_4398) @[Mux.scala 46:16] - node T_4401 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_4402 = mux(T_4401, T_4394, T_4400) @[Mux.scala 46:16] - node T_4403 = eq(UInt<2>("h02"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4404 = mux(T_4403, T_4402, UInt<3>("h03")) @[Mux.scala 46:16] - node T_4405 = eq(UInt<2>("h01"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4406 = mux(T_4405, T_4392, T_4404) @[Mux.scala 46:16] - node T_4407 = eq(UInt<2>("h00"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4408 = mux(T_4407, T_4382, T_4406) @[Mux.scala 46:16] - wire probeResponseMessage : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - probeResponseMessage is invalid @[Definitions.scala 754:19] - probeResponseMessage.r_type <= T_4408 @[Definitions.scala 755:16] - probeResponseMessage.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - probeResponseMessage.addr_block <= probe_bits.addr_block @[Definitions.scala 757:20] - probeResponseMessage.addr_beat <= UInt<1>("h00") @[Definitions.scala 758:19] - probeResponseMessage.data <= UInt<1>("h00") @[Definitions.scala 759:14] - probeResponseMessage.voluntary <= UInt<1>("h00") @[Definitions.scala 760:19] - node T_4463 = eq(UInt<2>("h02"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4464 = mux(T_4463, UInt<2>("h00"), s2_probe_state.state) @[Mux.scala 46:16] - node T_4465 = eq(UInt<2>("h01"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4466 = mux(T_4465, UInt<2>("h00"), T_4464) @[Mux.scala 46:16] - node T_4467 = eq(UInt<2>("h00"), probe_bits.p_type) @[Mux.scala 46:19] - node T_4468 = mux(T_4467, UInt<2>("h00"), T_4466) @[Mux.scala 46:16] - wire probeNewCoh : {state : UInt<2>} @[Metadata.scala 158:20] - probeNewCoh is invalid @[Metadata.scala 158:20] - probeNewCoh.state <= T_4468 @[Metadata.scala 159:16] - wire newCoh : {state : UInt<2>} + node T_4106 = cat(UInt<1>("h0"), writebackCount) + node T_4109 = cat(UInt<1>("h0"), s2_release_data_valid) + node T_4110 = add(s1_release_data_valid, T_4109) + node T_4111 = tail(T_4110, 1) + node T_4112 = mux(releaseRejected, UInt<1>("h0"), T_4111) + node T_4113 = add(T_4106, T_4112) + node releaseDataBeat = tail(T_4113, 1) + io.mem.release.valid <= s2_release_data_valid + wire T_4137 : { state : UInt<2>} + T_4137 is invalid + T_4137.state <= UInt<1>("h0") + node T_4162 = eq(T_4137.state, UInt<2>("h2")) + node T_4163 = mux(T_4162, UInt<3>("h0"), UInt<3>("h3")) + node T_4164 = mux(T_4162, UInt<3>("h1"), UInt<3>("h4")) + node T_4165 = mux(T_4162, UInt<3>("h2"), UInt<3>("h5")) + node T_4166 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4167 = mux(T_4166, T_4165, UInt<3>("h5")) + node T_4168 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4169 = mux(T_4168, T_4164, T_4167) + node T_4170 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4171 = mux(T_4170, T_4163, T_4169) + node T_4172 = eq(T_4137.state, UInt<2>("h2")) + node T_4173 = mux(T_4172, UInt<3>("h0"), UInt<3>("h3")) + node T_4174 = mux(T_4172, UInt<3>("h1"), UInt<3>("h4")) + node T_4175 = mux(T_4172, UInt<3>("h2"), UInt<3>("h5")) + node T_4176 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4177 = mux(T_4176, T_4175, UInt<3>("h5")) + node T_4178 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4179 = mux(T_4178, T_4174, T_4177) + node T_4180 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4181 = mux(T_4180, T_4173, T_4179) + node T_4182 = eq(T_4137.state, UInt<2>("h2")) + node T_4183 = mux(T_4182, UInt<3>("h0"), UInt<3>("h3")) + node T_4184 = mux(T_4182, UInt<3>("h1"), UInt<3>("h4")) + node T_4185 = mux(T_4182, UInt<3>("h2"), UInt<3>("h5")) + node T_4186 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4187 = mux(T_4186, T_4185, UInt<3>("h5")) + node T_4188 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4189 = mux(T_4188, T_4184, T_4187) + node T_4190 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4191 = mux(T_4190, T_4183, T_4189) + node T_4192 = eq(UInt<2>("h2"), probe_bits.p_type) + node T_4193 = mux(T_4192, T_4191, UInt<3>("h3")) + node T_4194 = eq(UInt<2>("h1"), probe_bits.p_type) + node T_4195 = mux(T_4194, T_4181, T_4193) + node T_4196 = eq(UInt<2>("h0"), probe_bits.p_type) + node T_4197 = mux(T_4196, T_4171, T_4195) + wire T_4226 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_4226 is invalid + T_4226.r_type <= T_4197 + T_4226.client_xact_id <= UInt<1>("h0") + T_4226.addr_block <= probe_bits.addr_block + T_4226.addr_beat <= UInt<1>("h0") + T_4226.data <= UInt<1>("h0") + T_4226.voluntary <= UInt<1>("h0") + io.mem.release.bits <- T_4226 + node T_4258 = eq(s2_victim_state.state, UInt<2>("h2")) + node T_4259 = mux(T_4258, UInt<3>("h0"), UInt<3>("h3")) + node T_4260 = mux(T_4258, UInt<3>("h1"), UInt<3>("h4")) + node T_4261 = mux(T_4258, UInt<3>("h2"), UInt<3>("h5")) + node T_4262 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4263 = mux(T_4262, T_4261, UInt<3>("h5")) + node T_4264 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4265 = mux(T_4264, T_4260, T_4263) + node T_4266 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4267 = mux(T_4266, T_4259, T_4265) + wire voluntaryReleaseMessage : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + voluntaryReleaseMessage is invalid + voluntaryReleaseMessage.r_type <= T_4267 + voluntaryReleaseMessage.client_xact_id <= UInt<1>("h0") + voluntaryReleaseMessage.addr_block <= UInt<1>("h0") + voluntaryReleaseMessage.addr_beat <= UInt<1>("h0") + voluntaryReleaseMessage.data <= UInt<1>("h0") + voluntaryReleaseMessage.voluntary <= UInt<1>("h1") + node T_4321 = eq(s2_victim_state.state, UInt<2>("h2")) + node T_4322 = mux(T_4321, UInt<2>("h1"), s2_victim_state.state) + node T_4323 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4324 = mux(T_4323, T_4322, s2_victim_state.state) + node T_4325 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4326 = mux(T_4325, UInt<2>("h0"), T_4324) + wire voluntaryNewCoh : { state : UInt<2>} + voluntaryNewCoh is invalid + voluntaryNewCoh.state <= T_4326 + node T_4373 = eq(s2_probe_state.state, UInt<2>("h2")) + node T_4374 = mux(T_4373, UInt<3>("h0"), UInt<3>("h3")) + node T_4375 = mux(T_4373, UInt<3>("h1"), UInt<3>("h4")) + node T_4376 = mux(T_4373, UInt<3>("h2"), UInt<3>("h5")) + node T_4377 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4378 = mux(T_4377, T_4376, UInt<3>("h5")) + node T_4379 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4380 = mux(T_4379, T_4375, T_4378) + node T_4381 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4382 = mux(T_4381, T_4374, T_4380) + node T_4383 = eq(s2_probe_state.state, UInt<2>("h2")) + node T_4384 = mux(T_4383, UInt<3>("h0"), UInt<3>("h3")) + node T_4385 = mux(T_4383, UInt<3>("h1"), UInt<3>("h4")) + node T_4386 = mux(T_4383, UInt<3>("h2"), UInt<3>("h5")) + node T_4387 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4388 = mux(T_4387, T_4386, UInt<3>("h5")) + node T_4389 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4390 = mux(T_4389, T_4385, T_4388) + node T_4391 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4392 = mux(T_4391, T_4384, T_4390) + node T_4393 = eq(s2_probe_state.state, UInt<2>("h2")) + node T_4394 = mux(T_4393, UInt<3>("h0"), UInt<3>("h3")) + node T_4395 = mux(T_4393, UInt<3>("h1"), UInt<3>("h4")) + node T_4396 = mux(T_4393, UInt<3>("h2"), UInt<3>("h5")) + node T_4397 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_4398 = mux(T_4397, T_4396, UInt<3>("h5")) + node T_4399 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_4400 = mux(T_4399, T_4395, T_4398) + node T_4401 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_4402 = mux(T_4401, T_4394, T_4400) + node T_4403 = eq(UInt<2>("h2"), probe_bits.p_type) + node T_4404 = mux(T_4403, T_4402, UInt<3>("h3")) + node T_4405 = eq(UInt<2>("h1"), probe_bits.p_type) + node T_4406 = mux(T_4405, T_4392, T_4404) + node T_4407 = eq(UInt<2>("h0"), probe_bits.p_type) + node T_4408 = mux(T_4407, T_4382, T_4406) + wire probeResponseMessage : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + probeResponseMessage is invalid + probeResponseMessage.r_type <= T_4408 + probeResponseMessage.client_xact_id <= UInt<1>("h0") + probeResponseMessage.addr_block <= probe_bits.addr_block + probeResponseMessage.addr_beat <= UInt<1>("h0") + probeResponseMessage.data <= UInt<1>("h0") + probeResponseMessage.voluntary <= UInt<1>("h0") + node T_4463 = eq(UInt<2>("h2"), probe_bits.p_type) + node T_4464 = mux(T_4463, UInt<2>("h0"), s2_probe_state.state) + node T_4465 = eq(UInt<2>("h1"), probe_bits.p_type) + node T_4466 = mux(T_4465, UInt<2>("h0"), T_4464) + node T_4467 = eq(UInt<2>("h0"), probe_bits.p_type) + node T_4468 = mux(T_4467, UInt<2>("h0"), T_4466) + wire probeNewCoh : { state : UInt<2>} + probeNewCoh is invalid + probeNewCoh.state <= T_4468 + wire newCoh : { state : UInt<2>} newCoh is invalid newCoh <- probeNewCoh - releaseWay <= s2_probe_way @[dcache.scala 346:14] - node T_4533 = and(s2_victimize, s2_victim_dirty) @[dcache.scala 347:22] - when T_4533 : @[dcache.scala 347:42] - node T_4534 = neq(s2_hit_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_4535 = and(s2_valid, T_4534) @[dcache.scala 348:23] - node T_4537 = eq(T_4535, UInt<1>("h00")) @[dcache.scala 348:12] - node T_4538 = or(T_4537, reset) @[dcache.scala 348:11] - node T_4540 = eq(T_4538, UInt<1>("h00")) @[dcache.scala 348:11] - when T_4540 : @[dcache.scala 348:11] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:348 assert(!(s2_valid && s2_hit_state.isValid()))\n") @[dcache.scala 348:11] - stop(clk, UInt<1>(1), 1) @[dcache.scala 348:11] - skip @[dcache.scala 348:11] - release_state <= UInt<3>("h02") @[dcache.scala 349:19] - node T_4541 = bits(s2_req.addr, 11, 6) @[dcache.scala 350:60] - node T_4542 = cat(s2_victim_tag, T_4541) @[Cat.scala 20:58] - probe_bits.addr_block <= T_4542 @[dcache.scala 350:27] - skip @[dcache.scala 347:42] - when s2_probe : @[dcache.scala 352:19] - node T_4543 = eq(s2_probe_state.state, UInt<2>("h02")) @[Package.scala 7:47] - when T_4543 : @[dcache.scala 353:56] - release_state <= UInt<3>("h03") @[dcache.scala 353:72] - skip @[dcache.scala 353:56] - node T_4544 = neq(s2_probe_state.state, UInt<2>("h00")) @[Policies.scala 237:51] - node T_4546 = eq(T_4543, UInt<1>("h00")) @[dcache.scala 353:56] - node T_4547 = and(T_4546, T_4544) @[dcache.scala 354:42] - when T_4547 : @[dcache.scala 354:42] - release_state <= UInt<3>("h04") @[dcache.scala 354:58] - skip @[dcache.scala 354:42] - node T_4549 = eq(T_4543, UInt<1>("h00")) @[dcache.scala 353:56] - node T_4551 = eq(T_4544, UInt<1>("h00")) @[dcache.scala 354:42] - node T_4552 = and(T_4549, T_4551) @[dcache.scala 354:42] - when T_4552 : @[dcache.scala 355:16] - io.mem.release.valid <= UInt<1>("h01") @[dcache.scala 356:28] - release_state <= UInt<3>("h05") @[dcache.scala 357:21] - skip @[dcache.scala 355:16] - skip @[dcache.scala 352:19] - when releaseDone : @[dcache.scala 360:22] - release_state <= UInt<3>("h00") @[dcache.scala 360:38] - skip @[dcache.scala 360:22] - node T_4554 = eq(release_state, UInt<3>("h05")) @[Package.scala 7:47] - node T_4555 = eq(release_state, UInt<3>("h04")) @[Package.scala 7:47] - node T_4556 = or(T_4554, T_4555) @[Package.scala 7:62] - when T_4556 : @[dcache.scala 361:69] - io.mem.release.valid <= UInt<1>("h01") @[dcache.scala 362:26] - skip @[dcache.scala 361:69] - node T_4558 = eq(release_state, UInt<3>("h04")) @[Package.scala 7:47] - node T_4559 = eq(release_state, UInt<3>("h03")) @[Package.scala 7:47] - node T_4560 = or(T_4558, T_4559) @[Package.scala 7:62] - when T_4560 : @[dcache.scala 364:70] - io.mem.release.bits <- probeResponseMessage @[dcache.scala 365:25] - when releaseDone : @[dcache.scala 366:24] - release_state <= UInt<3>("h07") @[dcache.scala 366:40] - skip @[dcache.scala 366:24] - skip @[dcache.scala 364:70] - node T_4561 = eq(release_state, UInt<3>("h02")) @[Package.scala 7:47] - node T_4562 = eq(release_state, UInt<3>("h06")) @[Package.scala 7:47] - node T_4563 = or(T_4561, T_4562) @[Package.scala 7:62] - when T_4563 : @[dcache.scala 368:79] - io.mem.release.bits <- voluntaryReleaseMessage @[dcache.scala 369:25] - newCoh <- voluntaryNewCoh @[dcache.scala 370:12] - releaseWay <= s2_victim_way @[dcache.scala 371:16] - when releaseDone : @[dcache.scala 372:24] - release_state <= UInt<3>("h06") @[dcache.scala 373:21] - release_ack_wait <= UInt<1>("h01") @[dcache.scala 374:24] - skip @[dcache.scala 372:24] - skip @[dcache.scala 368:79] - node T_4565 = and(io.mem.release.ready, io.mem.release.valid) @[Decoupled.scala 21:42] - node T_4567 = eq(T_4565, UInt<1>("h00")) @[dcache.scala 377:21] - node T_4568 = and(s2_probe, T_4567) @[dcache.scala 377:18] - when T_4568 : @[dcache.scala 377:45] - s1_nack <= UInt<1>("h01") @[dcache.scala 377:55] - skip @[dcache.scala 377:45] - io.mem.release.bits.addr_block <= probe_bits.addr_block @[dcache.scala 378:34] - io.mem.release.bits.addr_beat <= writebackCount @[dcache.scala 379:33] - io.mem.release.bits.data <= s2_data @[dcache.scala 380:28] - node T_4571 = lt(releaseDataBeat, UInt<4>("h08")) @[dcache.scala 382:60] - node T_4572 = and(inWriteback, T_4571) @[dcache.scala 382:41] - dataArb.io.in[2].valid <= T_4572 @[dcache.scala 382:26] - dataArb.io.in[2].bits.write <= UInt<1>("h00") @[dcache.scala 383:31] - node T_4574 = bits(releaseDataBeat, 2, 0) @[dcache.scala 384:84] - node T_4575 = cat(io.mem.release.bits.addr_block, T_4574) @[Cat.scala 20:58] - node T_4576 = shl(T_4575, 3) @[dcache.scala 384:112] - dataArb.io.in[2].bits.addr <= T_4576 @[dcache.scala 384:30] - node T_4578 = not(UInt<4>("h00")) @[dcache.scala 385:35] - dataArb.io.in[2].bits.way_en <= T_4578 @[dcache.scala 385:32] - node T_4579 = eq(release_state, UInt<3>("h06")) @[Package.scala 7:47] - node T_4580 = eq(release_state, UInt<3>("h07")) @[Package.scala 7:47] - node T_4581 = or(T_4579, T_4580) @[Package.scala 7:62] - metaWriteArb.io.in[2].valid <= T_4581 @[dcache.scala 387:31] - metaWriteArb.io.in[2].bits.way_en <= releaseWay @[dcache.scala 388:37] - node T_4583 = cat(io.mem.release.bits.addr_block, io.mem.release.bits.addr_beat) @[Cat.scala 20:58] - node T_4584 = cat(T_4583, UInt<3>("h00")) @[Cat.scala 20:58] - node T_4585 = bits(T_4584, 11, 6) @[dcache.scala 389:68] - metaWriteArb.io.in[2].bits.idx <= T_4585 @[dcache.scala 389:34] - metaWriteArb.io.in[2].bits.data.coh <- newCoh @[dcache.scala 390:39] - node T_4587 = cat(io.mem.release.bits.addr_block, io.mem.release.bits.addr_beat) @[Cat.scala 20:58] - node T_4588 = cat(T_4587, UInt<3>("h00")) @[Cat.scala 20:58] - node T_4589 = bits(T_4588, 31, 12) @[dcache.scala 391:73] - metaWriteArb.io.in[2].bits.data.tag <= T_4589 @[dcache.scala 391:39] - node T_4590 = and(metaWriteArb.io.in[2].ready, metaWriteArb.io.in[2].valid) @[Decoupled.scala 21:42] - when T_4590 : @[dcache.scala 392:39] - release_state <= UInt<3>("h00") @[dcache.scala 392:55] - skip @[dcache.scala 392:39] - io.cpu.resp.valid <= s2_valid_hit @[dcache.scala 395:21] - io.cpu.resp.bits <- s2_req @[dcache.scala 396:20] - io.cpu.resp.bits.has_data <= s2_read @[dcache.scala 397:29] - io.cpu.resp.bits.replay <= UInt<1>("h00") @[dcache.scala 398:27] - node T_4592 = or(s1_valid, s2_valid) @[dcache.scala 399:32] - node T_4593 = or(T_4592, grant_wait) @[dcache.scala 399:44] - node T_4595 = eq(T_4593, UInt<1>("h00")) @[dcache.scala 399:21] - io.cpu.ordered <= T_4595 @[dcache.scala 399:18] - node T_4596 = and(io.mem.grant.valid, grantIsUncached) @[dcache.scala 402:44] - io.cpu.replay_next <= T_4596 @[dcache.scala 402:22] - reg doUncachedResp : UInt<1>, clk + releaseWay <= s2_probe_way + node T_4533 = and(s2_victimize, s2_victim_dirty) + when T_4533 : + node T_4534 = neq(s2_hit_state.state, UInt<2>("h0")) + node T_4535 = and(s2_valid, T_4534) + node T_4537 = eq(T_4535, UInt<1>("h0")) + node T_4538 = or(T_4537, reset) + node T_4540 = eq(T_4538, UInt<1>("h0")) + when T_4540 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:348 assert(!(s2_valid && s2_hit_state.isValid()))\n") + stop(clk, UInt<1>("h1"), 1) + release_state <= UInt<3>("h2") + node T_4541 = bits(s2_req.addr, 11, 6) + node T_4542 = cat(s2_victim_tag, T_4541) + probe_bits.addr_block <= T_4542 + when s2_probe : + node T_4543 = eq(s2_probe_state.state, UInt<2>("h2")) + when T_4543 : + release_state <= UInt<3>("h3") + node T_4544 = neq(s2_probe_state.state, UInt<2>("h0")) + node T_4546 = eq(T_4543, UInt<1>("h0")) + node T_4547 = and(T_4546, T_4544) + when T_4547 : + release_state <= UInt<3>("h4") + node T_4549 = eq(T_4543, UInt<1>("h0")) + node T_4551 = eq(T_4544, UInt<1>("h0")) + node T_4552 = and(T_4549, T_4551) + when T_4552 : + io.mem.release.valid <= UInt<1>("h1") + release_state <= UInt<3>("h5") + when releaseDone : + release_state <= UInt<3>("h0") + node T_4554 = eq(release_state, UInt<3>("h5")) + node T_4555 = eq(release_state, UInt<3>("h4")) + node T_4556 = or(T_4554, T_4555) + when T_4556 : + io.mem.release.valid <= UInt<1>("h1") + node T_4558 = eq(release_state, UInt<3>("h4")) + node T_4559 = eq(release_state, UInt<3>("h3")) + node T_4560 = or(T_4558, T_4559) + when T_4560 : + io.mem.release.bits <- probeResponseMessage + when releaseDone : + release_state <= UInt<3>("h7") + node T_4561 = eq(release_state, UInt<3>("h2")) + node T_4562 = eq(release_state, UInt<3>("h6")) + node T_4563 = or(T_4561, T_4562) + when T_4563 : + io.mem.release.bits <- voluntaryReleaseMessage + newCoh <- voluntaryNewCoh + releaseWay <= s2_victim_way + when releaseDone : + release_state <= UInt<3>("h6") + release_ack_wait <= UInt<1>("h1") + node T_4565 = and(io.mem.release.ready, io.mem.release.valid) + node T_4567 = eq(T_4565, UInt<1>("h0")) + node T_4568 = and(s2_probe, T_4567) + when T_4568 : + s1_nack <= UInt<1>("h1") + io.mem.release.bits.addr_block <= probe_bits.addr_block + io.mem.release.bits.addr_beat <= writebackCount + io.mem.release.bits.data <= s2_data + node T_4571 = lt(releaseDataBeat, UInt<4>("h8")) + node T_4572 = and(inWriteback, T_4571) + dataArb.io.in[2].valid <= T_4572 + dataArb.io.in[2].bits.write <= UInt<1>("h0") + node T_4574 = bits(releaseDataBeat, 2, 0) + node T_4575 = cat(io.mem.release.bits.addr_block, T_4574) + node T_4576 = shl(T_4575, 3) + dataArb.io.in[2].bits.addr <= T_4576 + node T_4578 = not(UInt<4>("h0")) + dataArb.io.in[2].bits.way_en <= T_4578 + node T_4579 = eq(release_state, UInt<3>("h6")) + node T_4580 = eq(release_state, UInt<3>("h7")) + node T_4581 = or(T_4579, T_4580) + metaWriteArb.io.in[2].valid <= T_4581 + metaWriteArb.io.in[2].bits.way_en <= releaseWay + node T_4583 = cat(io.mem.release.bits.addr_block, io.mem.release.bits.addr_beat) + node T_4584 = cat(T_4583, UInt<3>("h0")) + node T_4585 = bits(T_4584, 11, 6) + metaWriteArb.io.in[2].bits.idx <= T_4585 + metaWriteArb.io.in[2].bits.data.coh <- newCoh + node T_4587 = cat(io.mem.release.bits.addr_block, io.mem.release.bits.addr_beat) + node T_4588 = cat(T_4587, UInt<3>("h0")) + node T_4589 = bits(T_4588, 31, 12) + metaWriteArb.io.in[2].bits.data.tag <= T_4589 + node T_4590 = and(metaWriteArb.io.in[2].ready, metaWriteArb.io.in[2].valid) + when T_4590 : + release_state <= UInt<3>("h0") + io.cpu.resp.valid <= s2_valid_hit + io.cpu.resp.bits <- s2_req + io.cpu.resp.bits.has_data <= s2_read + io.cpu.resp.bits.replay <= UInt<1>("h0") + node T_4592 = or(s1_valid, s2_valid) + node T_4593 = or(T_4592, grant_wait) + node T_4595 = eq(T_4593, UInt<1>("h0")) + io.cpu.ordered <= T_4595 + node T_4596 = and(io.mem.grant.valid, grantIsUncached) + io.cpu.replay_next <= T_4596 + reg doUncachedResp : UInt<1>, clk with : + reset => (UInt<1>("h0"), doUncachedResp) doUncachedResp <= io.cpu.replay_next - when doUncachedResp : @[dcache.scala 404:25] - node T_4598 = eq(s2_valid_hit, UInt<1>("h00")) @[dcache.scala 405:12] - node T_4599 = or(T_4598, reset) @[dcache.scala 405:11] - node T_4601 = eq(T_4599, UInt<1>("h00")) @[dcache.scala 405:11] - when T_4601 : @[dcache.scala 405:11] - printf(clk, UInt<1>(1), "Assertion failed\n at dcache.scala:405 assert(!s2_valid_hit)\n") @[dcache.scala 405:11] - stop(clk, UInt<1>(1), 1) @[dcache.scala 405:11] - skip @[dcache.scala 405:11] - io.cpu.resp.valid <= UInt<1>("h01") @[dcache.scala 406:23] - io.cpu.resp.bits.replay <= UInt<1>("h01") @[dcache.scala 407:29] - skip @[dcache.scala 404:25] - node T_4605 = cat(UInt<1>("h00"), UInt<6>("h00")) @[Cat.scala 20:58] - node s2_data_word = dshr(s2_data, T_4605) @[dcache.scala 412:30] - node T_4606 = bits(s2_req.typ, 2, 2) @[consts.scala 20:31] - node T_4608 = eq(T_4606, UInt<1>("h00")) @[consts.scala 20:28] - node T_4609 = bits(s2_req.typ, 1, 0) @[AmoAlu.scala 11:17] - node T_4610 = bits(s2_req.addr, 2, 2) @[AmoAlu.scala 44:29] - node T_4611 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 44:37] - node T_4612 = bits(s2_data_word, 31, 0) @[AmoAlu.scala 44:55] - node T_4613 = mux(T_4610, T_4611, T_4612) @[AmoAlu.scala 44:24] - node T_4615 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 45:33] - node T_4617 = mux(T_4615, UInt<1>("h00"), T_4613) @[AmoAlu.scala 46:23] - node T_4619 = eq(T_4609, UInt<2>("h02")) @[AmoAlu.scala 47:26] - node T_4620 = or(T_4619, T_4615) @[AmoAlu.scala 47:38] - node T_4621 = bits(T_4617, 31, 31) @[AmoAlu.scala 47:85] - node T_4622 = and(T_4608, T_4621) @[AmoAlu.scala 47:76] - node T_4623 = bits(T_4622, 0, 0) @[Bitwise.scala 33:15] - node T_4626 = mux(T_4623, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_4627 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 47:98] - node T_4628 = mux(T_4620, T_4626, T_4627) @[AmoAlu.scala 47:20] - node T_4629 = cat(T_4628, T_4617) @[Cat.scala 20:58] - node T_4630 = bits(s2_req.addr, 1, 1) @[AmoAlu.scala 44:29] - node T_4631 = bits(T_4629, 31, 16) @[AmoAlu.scala 44:37] - node T_4632 = bits(T_4629, 15, 0) @[AmoAlu.scala 44:55] - node T_4633 = mux(T_4630, T_4631, T_4632) @[AmoAlu.scala 44:24] - node T_4635 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 45:33] - node T_4637 = mux(T_4635, UInt<1>("h00"), T_4633) @[AmoAlu.scala 46:23] - node T_4639 = eq(T_4609, UInt<1>("h01")) @[AmoAlu.scala 47:26] - node T_4640 = or(T_4639, T_4635) @[AmoAlu.scala 47:38] - node T_4641 = bits(T_4637, 15, 15) @[AmoAlu.scala 47:85] - node T_4642 = and(T_4608, T_4641) @[AmoAlu.scala 47:76] - node T_4643 = bits(T_4642, 0, 0) @[Bitwise.scala 33:15] - node T_4646 = mux(T_4643, UInt<48>("h0ffffffffffff"), UInt<48>("h00")) @[Bitwise.scala 33:12] - node T_4647 = bits(T_4629, 63, 16) @[AmoAlu.scala 47:98] - node T_4648 = mux(T_4640, T_4646, T_4647) @[AmoAlu.scala 47:20] - node T_4649 = cat(T_4648, T_4637) @[Cat.scala 20:58] - node T_4650 = bits(s2_req.addr, 0, 0) @[AmoAlu.scala 44:29] - node T_4651 = bits(T_4649, 15, 8) @[AmoAlu.scala 44:37] - node T_4652 = bits(T_4649, 7, 0) @[AmoAlu.scala 44:55] - node T_4653 = mux(T_4650, T_4651, T_4652) @[AmoAlu.scala 44:24] - node T_4655 = and(UInt<1>("h01"), s2_sc) @[AmoAlu.scala 45:33] - node T_4657 = mux(T_4655, UInt<1>("h00"), T_4653) @[AmoAlu.scala 46:23] - node T_4659 = eq(T_4609, UInt<1>("h00")) @[AmoAlu.scala 47:26] - node T_4660 = or(T_4659, T_4655) @[AmoAlu.scala 47:38] - node T_4661 = bits(T_4657, 7, 7) @[AmoAlu.scala 47:85] - node T_4662 = and(T_4608, T_4661) @[AmoAlu.scala 47:76] - node T_4663 = bits(T_4662, 0, 0) @[Bitwise.scala 33:15] - node T_4666 = mux(T_4663, UInt<56>("h0ffffffffffffff"), UInt<56>("h00")) @[Bitwise.scala 33:12] - node T_4667 = bits(T_4649, 63, 8) @[AmoAlu.scala 47:98] - node T_4668 = mux(T_4660, T_4666, T_4667) @[AmoAlu.scala 47:20] - node T_4669 = cat(T_4668, T_4657) @[Cat.scala 20:58] - node T_4670 = or(T_4669, s2_sc_fail) @[dcache.scala 414:41] - io.cpu.resp.bits.data <= T_4670 @[dcache.scala 414:25] - node T_4671 = bits(s2_req.addr, 2, 2) @[AmoAlu.scala 44:29] - node T_4672 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 44:37] - node T_4673 = bits(s2_data_word, 31, 0) @[AmoAlu.scala 44:55] - node T_4674 = mux(T_4671, T_4672, T_4673) @[AmoAlu.scala 44:24] - node T_4676 = and(UInt<1>("h00"), s2_sc) @[AmoAlu.scala 45:33] - node T_4678 = mux(T_4676, UInt<1>("h00"), T_4674) @[AmoAlu.scala 46:23] - node T_4680 = eq(T_4609, UInt<2>("h02")) @[AmoAlu.scala 47:26] - node T_4681 = or(T_4680, T_4676) @[AmoAlu.scala 47:38] - node T_4682 = bits(T_4678, 31, 31) @[AmoAlu.scala 47:85] - node T_4683 = and(T_4608, T_4682) @[AmoAlu.scala 47:76] - node T_4684 = bits(T_4683, 0, 0) @[Bitwise.scala 33:15] - node T_4687 = mux(T_4684, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_4688 = bits(s2_data_word, 63, 32) @[AmoAlu.scala 47:98] - node T_4689 = mux(T_4681, T_4687, T_4688) @[AmoAlu.scala 47:20] - node T_4690 = cat(T_4689, T_4678) @[Cat.scala 20:58] - io.cpu.resp.bits.data_word_bypass <= T_4690 @[dcache.scala 415:37] - io.cpu.resp.bits.store_data <= pstore1_data @[dcache.scala 416:31] - inst AMOALU_1 of AMOALU @[dcache.scala 420:24] + when doUncachedResp : + node T_4598 = eq(s2_valid_hit, UInt<1>("h0")) + node T_4599 = or(T_4598, reset) + node T_4601 = eq(T_4599, UInt<1>("h0")) + when T_4601 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at dcache.scala:405 assert(!s2_valid_hit)\n") + stop(clk, UInt<1>("h1"), 1) + io.cpu.resp.valid <= UInt<1>("h1") + io.cpu.resp.bits.replay <= UInt<1>("h1") + node T_4605 = cat(UInt<1>("h0"), UInt<6>("h0")) + node s2_data_word = dshr(s2_data, T_4605) + node T_4606 = bits(s2_req.typ, 2, 2) + node T_4608 = eq(T_4606, UInt<1>("h0")) + node T_4609 = bits(s2_req.typ, 1, 0) + node T_4610 = bits(s2_req.addr, 2, 2) + node T_4611 = bits(s2_data_word, 63, 32) + node T_4612 = bits(s2_data_word, 31, 0) + node T_4613 = mux(T_4610, T_4611, T_4612) + node T_4615 = and(UInt<1>("h0"), s2_sc) + node T_4617 = mux(T_4615, UInt<1>("h0"), T_4613) + node T_4619 = eq(T_4609, UInt<2>("h2")) + node T_4620 = or(T_4619, T_4615) + node T_4621 = bits(T_4617, 31, 31) + node T_4622 = and(T_4608, T_4621) + node T_4623 = bits(T_4622, 0, 0) + node T_4626 = mux(T_4623, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_4627 = bits(s2_data_word, 63, 32) + node T_4628 = mux(T_4620, T_4626, T_4627) + node T_4629 = cat(T_4628, T_4617) + node T_4630 = bits(s2_req.addr, 1, 1) + node T_4631 = bits(T_4629, 31, 16) + node T_4632 = bits(T_4629, 15, 0) + node T_4633 = mux(T_4630, T_4631, T_4632) + node T_4635 = and(UInt<1>("h0"), s2_sc) + node T_4637 = mux(T_4635, UInt<1>("h0"), T_4633) + node T_4639 = eq(T_4609, UInt<1>("h1")) + node T_4640 = or(T_4639, T_4635) + node T_4641 = bits(T_4637, 15, 15) + node T_4642 = and(T_4608, T_4641) + node T_4643 = bits(T_4642, 0, 0) + node T_4646 = mux(T_4643, UInt<48>("hffffffffffff"), UInt<48>("h0")) + node T_4647 = bits(T_4629, 63, 16) + node T_4648 = mux(T_4640, T_4646, T_4647) + node T_4649 = cat(T_4648, T_4637) + node T_4650 = bits(s2_req.addr, 0, 0) + node T_4651 = bits(T_4649, 15, 8) + node T_4652 = bits(T_4649, 7, 0) + node T_4653 = mux(T_4650, T_4651, T_4652) + node T_4655 = and(UInt<1>("h1"), s2_sc) + node T_4657 = mux(T_4655, UInt<1>("h0"), T_4653) + node T_4659 = eq(T_4609, UInt<1>("h0")) + node T_4660 = or(T_4659, T_4655) + node T_4661 = bits(T_4657, 7, 7) + node T_4662 = and(T_4608, T_4661) + node T_4663 = bits(T_4662, 0, 0) + node T_4666 = mux(T_4663, UInt<56>("hffffffffffffff"), UInt<56>("h0")) + node T_4667 = bits(T_4649, 63, 8) + node T_4668 = mux(T_4660, T_4666, T_4667) + node T_4669 = cat(T_4668, T_4657) + node T_4670 = or(T_4669, s2_sc_fail) + io.cpu.resp.bits.data <= T_4670 + node T_4671 = bits(s2_req.addr, 2, 2) + node T_4672 = bits(s2_data_word, 63, 32) + node T_4673 = bits(s2_data_word, 31, 0) + node T_4674 = mux(T_4671, T_4672, T_4673) + node T_4676 = and(UInt<1>("h0"), s2_sc) + node T_4678 = mux(T_4676, UInt<1>("h0"), T_4674) + node T_4680 = eq(T_4609, UInt<2>("h2")) + node T_4681 = or(T_4680, T_4676) + node T_4682 = bits(T_4678, 31, 31) + node T_4683 = and(T_4608, T_4682) + node T_4684 = bits(T_4683, 0, 0) + node T_4687 = mux(T_4684, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_4688 = bits(s2_data_word, 63, 32) + node T_4689 = mux(T_4681, T_4687, T_4688) + node T_4690 = cat(T_4689, T_4678) + io.cpu.resp.bits.data_word_bypass <= T_4690 + io.cpu.resp.bits.store_data <= pstore1_data + inst AMOALU_1 of AMOALU AMOALU_1.io is invalid AMOALU_1.clk <= clk AMOALU_1.reset <= reset - AMOALU_1.io.addr <= pstore1_addr @[dcache.scala 421:20] - AMOALU_1.io.cmd <= pstore1_cmd @[dcache.scala 422:19] - AMOALU_1.io.typ <= pstore1_typ @[dcache.scala 423:19] - AMOALU_1.io.lhs <= s2_data_word @[dcache.scala 424:19] - AMOALU_1.io.rhs <= pstore1_data @[dcache.scala 425:19] - pstore1_storegen_data <= AMOALU_1.io.out @[dcache.scala 426:27] - reg flushed : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) - reg flushing : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_4694 : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - node T_4695 = and(io.mem.acquire.ready, io.mem.acquire.valid) @[Decoupled.scala 21:42] - node T_4697 = eq(s2_uncached, UInt<1>("h00")) @[dcache.scala 435:34] - node T_4698 = and(T_4695, T_4697) @[dcache.scala 435:31] - when T_4698 : @[dcache.scala 435:48] - flushed <= UInt<1>("h00") @[dcache.scala 435:58] - skip @[dcache.scala 435:48] - node T_4700 = eq(s2_req.cmd, UInt<5>("h05")) @[dcache.scala 436:39] - node T_4701 = and(s2_valid_masked, T_4700) @[dcache.scala 436:25] - when T_4701 : @[dcache.scala 436:56] - node T_4703 = eq(flushed, UInt<1>("h00")) @[dcache.scala 437:23] - io.cpu.s2_nack <= T_4703 @[dcache.scala 437:20] - node T_4705 = eq(flushed, UInt<1>("h00")) @[dcache.scala 438:11] - when T_4705 : @[dcache.scala 438:21] - node T_4707 = eq(release_ack_wait, UInt<1>("h00")) @[dcache.scala 439:19] - flushing <= T_4707 @[dcache.scala 439:16] - skip @[dcache.scala 438:21] - skip @[dcache.scala 436:56] - node T_4708 = and(metaReadArb.io.in[0].ready, metaReadArb.io.in[0].valid) @[Decoupled.scala 21:42] - node T_4710 = eq(s1_flush_valid, UInt<1>("h00")) @[dcache.scala 442:52] - node T_4711 = and(T_4708, T_4710) @[dcache.scala 442:49] - node T_4713 = eq(s2_flush_valid, UInt<1>("h00")) @[dcache.scala 442:71] - node T_4714 = and(T_4711, T_4713) @[dcache.scala 442:68] - node T_4715 = eq(release_state, UInt<3>("h00")) @[dcache.scala 442:104] - node T_4716 = and(T_4714, T_4715) @[dcache.scala 442:87] - node T_4718 = eq(release_ack_wait, UInt<1>("h00")) @[dcache.scala 442:119] - node T_4719 = and(T_4716, T_4718) @[dcache.scala 442:116] - s1_flush_valid <= T_4719 @[dcache.scala 442:18] - metaReadArb.io.in[0].valid <= flushing @[dcache.scala 443:30] - metaReadArb.io.in[0].bits.idx <= T_4694 @[dcache.scala 444:33] - node T_4721 = not(UInt<4>("h00")) @[dcache.scala 445:39] - metaReadArb.io.in[0].bits.way_en <= T_4721 @[dcache.scala 445:36] - when flushing : @[dcache.scala 446:19] - node T_4722 = shr(T_4694, 6) @[dcache.scala 447:41] - s1_victim_way <= T_4722 @[dcache.scala 447:19] - when s2_flush_valid : @[dcache.scala 448:27] - node T_4724 = eq(T_4694, UInt<8>("h0ff")) @[Counter.scala 20:24] - node T_4726 = add(T_4694, UInt<1>("h01")) @[Counter.scala 21:22] - node T_4727 = tail(T_4726, 1) @[Counter.scala 21:22] - T_4694 <= T_4727 @[Counter.scala 21:13] - when T_4724 : @[dcache.scala 449:33] - flushed <= UInt<1>("h01") @[dcache.scala 450:17] - skip @[dcache.scala 449:33] - skip @[dcache.scala 448:27] - node T_4729 = eq(release_state, UInt<3>("h00")) @[dcache.scala 453:36] - node T_4730 = and(flushed, T_4729) @[dcache.scala 453:19] - node T_4732 = eq(release_ack_wait, UInt<1>("h00")) @[dcache.scala 453:51] - node T_4733 = and(T_4730, T_4732) @[dcache.scala 453:48] - when T_4733 : @[dcache.scala 453:70] - flushing <= UInt<1>("h00") @[dcache.scala 454:16] - skip @[dcache.scala 453:70] - skip @[dcache.scala 446:19] - - module FPUDecoder : + AMOALU_1.io.addr <= pstore1_addr + AMOALU_1.io.cmd <= pstore1_cmd + AMOALU_1.io.typ <= pstore1_typ + AMOALU_1.io.lhs <= s2_data_word + AMOALU_1.io.rhs <= pstore1_data + pstore1_storegen_data <= AMOALU_1.io.out + reg flushed : UInt<1>, clk with : + reset => (reset, UInt<1>("h1")) + reg flushing : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_4694 : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + node T_4695 = and(io.mem.acquire.ready, io.mem.acquire.valid) + node T_4697 = eq(s2_uncached, UInt<1>("h0")) + node T_4698 = and(T_4695, T_4697) + when T_4698 : + flushed <= UInt<1>("h0") + node T_4700 = eq(s2_req.cmd, UInt<5>("h5")) + node T_4701 = and(s2_valid_masked, T_4700) + when T_4701 : + node T_4703 = eq(flushed, UInt<1>("h0")) + io.cpu.s2_nack <= T_4703 + node T_4705 = eq(flushed, UInt<1>("h0")) + when T_4705 : + node T_4707 = eq(release_ack_wait, UInt<1>("h0")) + flushing <= T_4707 + node T_4708 = and(metaReadArb.io.in[0].ready, metaReadArb.io.in[0].valid) + node T_4710 = eq(s1_flush_valid, UInt<1>("h0")) + node T_4711 = and(T_4708, T_4710) + node T_4713 = eq(s2_flush_valid, UInt<1>("h0")) + node T_4714 = and(T_4711, T_4713) + node T_4715 = eq(release_state, UInt<3>("h0")) + node T_4716 = and(T_4714, T_4715) + node T_4718 = eq(release_ack_wait, UInt<1>("h0")) + node T_4719 = and(T_4716, T_4718) + s1_flush_valid <= T_4719 + metaReadArb.io.in[0].valid <= flushing + metaReadArb.io.in[0].bits.idx <= T_4694 + node T_4721 = not(UInt<4>("h0")) + metaReadArb.io.in[0].bits.way_en <= T_4721 + when flushing : + node T_4722 = shr(T_4694, 6) + s1_victim_way <= T_4722 + when s2_flush_valid : + node T_4724 = eq(T_4694, UInt<8>("hff")) + node T_4726 = add(T_4694, UInt<1>("h1")) + node T_4727 = tail(T_4726, 1) + T_4694 <= T_4727 + when T_4724 : + flushed <= UInt<1>("h1") + node T_4729 = eq(release_state, UInt<3>("h0")) + node T_4730 = and(flushed, T_4729) + node T_4732 = eq(release_ack_wait, UInt<1>("h0")) + node T_4733 = and(T_4730, T_4732) + when T_4733 : + flushing <= UInt<1>("h0") + + module FPUDecoder : input clk : Clock input reset : UInt<1> - output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} - + output io : { flip inst : UInt<32>, sigs : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} + io is invalid - node T_20 = and(io.inst, UInt<32>("h04")) @[decode.scala 13:65] - node T_22 = eq(T_20, UInt<32>("h04")) @[decode.scala 13:121] - node T_24 = and(io.inst, UInt<32>("h08000010")) @[decode.scala 13:65] - node T_26 = eq(T_24, UInt<32>("h08000010")) @[decode.scala 13:121] - node T_28 = or(UInt<1>("h00"), T_22) @[decode.scala 14:30] - node T_29 = or(T_28, T_26) @[decode.scala 14:30] - node T_31 = and(io.inst, UInt<32>("h08")) @[decode.scala 13:65] - node T_33 = eq(T_31, UInt<32>("h08")) @[decode.scala 13:121] - node T_35 = and(io.inst, UInt<32>("h010000010")) @[decode.scala 13:65] - node T_37 = eq(T_35, UInt<32>("h010000010")) @[decode.scala 13:121] - node T_39 = or(UInt<1>("h00"), T_33) @[decode.scala 14:30] - node T_40 = or(T_39, T_37) @[decode.scala 14:30] - node T_42 = and(io.inst, UInt<32>("h040")) @[decode.scala 13:65] - node T_44 = eq(T_42, UInt<32>("h00")) @[decode.scala 13:121] - node T_46 = and(io.inst, UInt<32>("h020000000")) @[decode.scala 13:65] - node T_48 = eq(T_46, UInt<32>("h020000000")) @[decode.scala 13:121] - node T_50 = or(UInt<1>("h00"), T_44) @[decode.scala 14:30] - node T_51 = or(T_50, T_48) @[decode.scala 14:30] - node T_53 = and(io.inst, UInt<32>("h040000000")) @[decode.scala 13:65] - node T_55 = eq(T_53, UInt<32>("h040000000")) @[decode.scala 13:121] - node T_57 = or(UInt<1>("h00"), T_44) @[decode.scala 14:30] - node T_58 = or(T_57, T_55) @[decode.scala 14:30] - node T_60 = and(io.inst, UInt<32>("h010")) @[decode.scala 13:65] - node T_62 = eq(T_60, UInt<32>("h00")) @[decode.scala 13:121] - node T_64 = or(UInt<1>("h00"), T_62) @[decode.scala 14:30] - node T_65 = cat(T_40, T_29) @[Cat.scala 20:58] - node T_66 = cat(T_64, T_58) @[Cat.scala 20:58] - node T_67 = cat(T_66, T_51) @[Cat.scala 20:58] - node decoder_0 = cat(T_67, T_65) @[Cat.scala 20:58] - node decoder_1 = or(UInt<1>("h00"), T_44) @[decode.scala 14:30] - node T_70 = and(io.inst, UInt<32>("h080000020")) @[decode.scala 13:65] - node T_72 = eq(T_70, UInt<32>("h00")) @[decode.scala 13:121] - node T_74 = and(io.inst, UInt<32>("h030")) @[decode.scala 13:65] - node T_76 = eq(T_74, UInt<32>("h00")) @[decode.scala 13:121] - node T_78 = and(io.inst, UInt<32>("h010000020")) @[decode.scala 13:65] - node T_80 = eq(T_78, UInt<32>("h010000000")) @[decode.scala 13:121] - node T_82 = or(UInt<1>("h00"), T_72) @[decode.scala 14:30] - node T_83 = or(T_82, T_76) @[decode.scala 14:30] - node decoder_2 = or(T_83, T_80) @[decode.scala 14:30] - node T_85 = and(io.inst, UInt<32>("h080000004")) @[decode.scala 13:65] - node T_87 = eq(T_85, UInt<32>("h00")) @[decode.scala 13:121] - node T_89 = and(io.inst, UInt<32>("h010000004")) @[decode.scala 13:65] - node T_91 = eq(T_89, UInt<32>("h00")) @[decode.scala 13:121] - node T_93 = and(io.inst, UInt<32>("h050")) @[decode.scala 13:65] - node T_95 = eq(T_93, UInt<32>("h040")) @[decode.scala 13:121] - node T_97 = or(UInt<1>("h00"), T_87) @[decode.scala 14:30] - node T_98 = or(T_97, T_91) @[decode.scala 14:30] - node decoder_3 = or(T_98, T_95) @[decode.scala 14:30] - node T_100 = and(io.inst, UInt<32>("h040000004")) @[decode.scala 13:65] - node T_102 = eq(T_100, UInt<32>("h00")) @[decode.scala 13:121] - node T_104 = and(io.inst, UInt<32>("h020")) @[decode.scala 13:65] - node T_106 = eq(T_104, UInt<32>("h020")) @[decode.scala 13:121] - node T_108 = or(UInt<1>("h00"), T_102) @[decode.scala 14:30] - node T_109 = or(T_108, T_106) @[decode.scala 14:30] - node decoder_4 = or(T_109, T_95) @[decode.scala 14:30] - node decoder_5 = or(UInt<1>("h00"), T_95) @[decode.scala 14:30] - node T_112 = and(io.inst, UInt<32>("h050000010")) @[decode.scala 13:65] - node T_114 = eq(T_112, UInt<32>("h050000010")) @[decode.scala 13:121] - node T_116 = or(UInt<1>("h00"), T_44) @[decode.scala 14:30] - node decoder_6 = or(T_116, T_114) @[decode.scala 14:30] - node T_118 = and(io.inst, UInt<32>("h030000010")) @[decode.scala 13:65] - node T_120 = eq(T_118, UInt<32>("h010")) @[decode.scala 13:121] - node decoder_7 = or(UInt<1>("h00"), T_120) @[decode.scala 14:30] - node T_123 = and(io.inst, UInt<32>("h01040")) @[decode.scala 13:65] - node T_125 = eq(T_123, UInt<32>("h00")) @[decode.scala 13:121] - node T_127 = and(io.inst, UInt<32>("h02000040")) @[decode.scala 13:65] - node T_129 = eq(T_127, UInt<32>("h040")) @[decode.scala 13:121] - node T_131 = or(UInt<1>("h00"), T_125) @[decode.scala 14:30] - node decoder_8 = or(T_131, T_129) @[decode.scala 14:30] - node T_133 = and(io.inst, UInt<32>("h090000010")) @[decode.scala 13:65] - node T_135 = eq(T_133, UInt<32>("h090000010")) @[decode.scala 13:121] - node decoder_9 = or(UInt<1>("h00"), T_135) @[decode.scala 14:30] - node T_138 = and(io.inst, UInt<32>("h090000010")) @[decode.scala 13:65] - node T_140 = eq(T_138, UInt<32>("h080000010")) @[decode.scala 13:121] - node T_142 = or(UInt<1>("h00"), T_106) @[decode.scala 14:30] - node decoder_10 = or(T_142, T_140) @[decode.scala 14:30] - node T_144 = and(io.inst, UInt<32>("h0a0000010")) @[decode.scala 13:65] - node T_146 = eq(T_144, UInt<32>("h020000010")) @[decode.scala 13:121] - node T_148 = and(io.inst, UInt<32>("h0d0000010")) @[decode.scala 13:65] - node T_150 = eq(T_148, UInt<32>("h040000010")) @[decode.scala 13:121] - node T_152 = or(UInt<1>("h00"), T_146) @[decode.scala 14:30] - node decoder_11 = or(T_152, T_150) @[decode.scala 14:30] - node T_154 = and(io.inst, UInt<32>("h070000004")) @[decode.scala 13:65] - node T_156 = eq(T_154, UInt<32>("h00")) @[decode.scala 13:121] - node T_158 = and(io.inst, UInt<32>("h068000004")) @[decode.scala 13:65] - node T_160 = eq(T_158, UInt<32>("h00")) @[decode.scala 13:121] - node T_162 = or(UInt<1>("h00"), T_156) @[decode.scala 14:30] - node T_163 = or(T_162, T_160) @[decode.scala 14:30] - node decoder_12 = or(T_163, T_95) @[decode.scala 14:30] - node T_165 = and(io.inst, UInt<32>("h058000010")) @[decode.scala 13:65] - node T_167 = eq(T_165, UInt<32>("h018000010")) @[decode.scala 13:121] - node decoder_13 = or(UInt<1>("h00"), T_167) @[decode.scala 14:30] - node T_170 = and(io.inst, UInt<32>("h0d0000010")) @[decode.scala 13:65] - node T_172 = eq(T_170, UInt<32>("h050000010")) @[decode.scala 13:121] - node decoder_14 = or(UInt<1>("h00"), T_172) @[decode.scala 14:30] - node T_175 = and(io.inst, UInt<32>("h020000004")) @[decode.scala 13:65] - node T_177 = eq(T_175, UInt<32>("h00")) @[decode.scala 13:121] - node T_179 = and(io.inst, UInt<32>("h040002000")) @[decode.scala 13:65] - node T_181 = eq(T_179, UInt<32>("h040000000")) @[decode.scala 13:121] - node T_183 = or(UInt<1>("h00"), T_177) @[decode.scala 14:30] - node T_184 = or(T_183, T_95) @[decode.scala 14:30] - node decoder_15 = or(T_184, T_181) @[decode.scala 14:30] - node T_186 = and(io.inst, UInt<32>("h08002000")) @[decode.scala 13:65] - node T_188 = eq(T_186, UInt<32>("h08000000")) @[decode.scala 13:121] - node T_190 = and(io.inst, UInt<32>("h0c0000004")) @[decode.scala 13:65] - node T_192 = eq(T_190, UInt<32>("h080000000")) @[decode.scala 13:121] - node T_194 = or(UInt<1>("h00"), T_177) @[decode.scala 14:30] - node T_195 = or(T_194, T_95) @[decode.scala 14:30] - node T_196 = or(T_195, T_188) @[decode.scala 14:30] - node decoder_16 = or(T_196, T_192) @[decode.scala 14:30] - io.sigs.cmd <= decoder_0 @[fpu.scala 148:40] - io.sigs.ldst <= decoder_1 @[fpu.scala 148:40] - io.sigs.wen <= decoder_2 @[fpu.scala 148:40] - io.sigs.ren1 <= decoder_3 @[fpu.scala 148:40] - io.sigs.ren2 <= decoder_4 @[fpu.scala 148:40] - io.sigs.ren3 <= decoder_5 @[fpu.scala 148:40] - io.sigs.swap12 <= decoder_6 @[fpu.scala 148:40] - io.sigs.swap23 <= decoder_7 @[fpu.scala 148:40] - io.sigs.single <= decoder_8 @[fpu.scala 148:40] - io.sigs.fromint <= decoder_9 @[fpu.scala 148:40] - io.sigs.toint <= decoder_10 @[fpu.scala 148:40] - io.sigs.fastpipe <= decoder_11 @[fpu.scala 148:40] - io.sigs.fma <= decoder_12 @[fpu.scala 148:40] - io.sigs.div <= decoder_13 @[fpu.scala 148:40] - io.sigs.sqrt <= decoder_14 @[fpu.scala 148:40] - io.sigs.round <= decoder_15 @[fpu.scala 148:40] - io.sigs.wflags <= decoder_16 @[fpu.scala 148:40] - - module MulAddRecFN_preMul : + node T_20 = and(io.inst, UInt<32>("h4")) + node T_22 = eq(T_20, UInt<32>("h4")) + node T_24 = and(io.inst, UInt<32>("h8000010")) + node T_26 = eq(T_24, UInt<32>("h8000010")) + node T_28 = or(UInt<1>("h0"), T_22) + node T_29 = or(T_28, T_26) + node T_31 = and(io.inst, UInt<32>("h8")) + node T_33 = eq(T_31, UInt<32>("h8")) + node T_35 = and(io.inst, UInt<32>("h10000010")) + node T_37 = eq(T_35, UInt<32>("h10000010")) + node T_39 = or(UInt<1>("h0"), T_33) + node T_40 = or(T_39, T_37) + node T_42 = and(io.inst, UInt<32>("h40")) + node T_44 = eq(T_42, UInt<32>("h0")) + node T_46 = and(io.inst, UInt<32>("h20000000")) + node T_48 = eq(T_46, UInt<32>("h20000000")) + node T_50 = or(UInt<1>("h0"), T_44) + node T_51 = or(T_50, T_48) + node T_53 = and(io.inst, UInt<32>("h40000000")) + node T_55 = eq(T_53, UInt<32>("h40000000")) + node T_57 = or(UInt<1>("h0"), T_44) + node T_58 = or(T_57, T_55) + node T_60 = and(io.inst, UInt<32>("h10")) + node T_62 = eq(T_60, UInt<32>("h0")) + node T_64 = or(UInt<1>("h0"), T_62) + node T_65 = cat(T_40, T_29) + node T_66 = cat(T_64, T_58) + node T_67 = cat(T_66, T_51) + node decoder_0 = cat(T_67, T_65) + node decoder_1 = or(UInt<1>("h0"), T_44) + node T_70 = and(io.inst, UInt<32>("h80000020")) + node T_72 = eq(T_70, UInt<32>("h0")) + node T_74 = and(io.inst, UInt<32>("h30")) + node T_76 = eq(T_74, UInt<32>("h0")) + node T_78 = and(io.inst, UInt<32>("h10000020")) + node T_80 = eq(T_78, UInt<32>("h10000000")) + node T_82 = or(UInt<1>("h0"), T_72) + node T_83 = or(T_82, T_76) + node decoder_2 = or(T_83, T_80) + node T_85 = and(io.inst, UInt<32>("h80000004")) + node T_87 = eq(T_85, UInt<32>("h0")) + node T_89 = and(io.inst, UInt<32>("h10000004")) + node T_91 = eq(T_89, UInt<32>("h0")) + node T_93 = and(io.inst, UInt<32>("h50")) + node T_95 = eq(T_93, UInt<32>("h40")) + node T_97 = or(UInt<1>("h0"), T_87) + node T_98 = or(T_97, T_91) + node decoder_3 = or(T_98, T_95) + node T_100 = and(io.inst, UInt<32>("h40000004")) + node T_102 = eq(T_100, UInt<32>("h0")) + node T_104 = and(io.inst, UInt<32>("h20")) + node T_106 = eq(T_104, UInt<32>("h20")) + node T_108 = or(UInt<1>("h0"), T_102) + node T_109 = or(T_108, T_106) + node decoder_4 = or(T_109, T_95) + node decoder_5 = or(UInt<1>("h0"), T_95) + node T_112 = and(io.inst, UInt<32>("h50000010")) + node T_114 = eq(T_112, UInt<32>("h50000010")) + node T_116 = or(UInt<1>("h0"), T_44) + node decoder_6 = or(T_116, T_114) + node T_118 = and(io.inst, UInt<32>("h30000010")) + node T_120 = eq(T_118, UInt<32>("h10")) + node decoder_7 = or(UInt<1>("h0"), T_120) + node T_123 = and(io.inst, UInt<32>("h1040")) + node T_125 = eq(T_123, UInt<32>("h0")) + node T_127 = and(io.inst, UInt<32>("h2000040")) + node T_129 = eq(T_127, UInt<32>("h40")) + node T_131 = or(UInt<1>("h0"), T_125) + node decoder_8 = or(T_131, T_129) + node T_133 = and(io.inst, UInt<32>("h90000010")) + node T_135 = eq(T_133, UInt<32>("h90000010")) + node decoder_9 = or(UInt<1>("h0"), T_135) + node T_138 = and(io.inst, UInt<32>("h90000010")) + node T_140 = eq(T_138, UInt<32>("h80000010")) + node T_142 = or(UInt<1>("h0"), T_106) + node decoder_10 = or(T_142, T_140) + node T_144 = and(io.inst, UInt<32>("ha0000010")) + node T_146 = eq(T_144, UInt<32>("h20000010")) + node T_148 = and(io.inst, UInt<32>("hd0000010")) + node T_150 = eq(T_148, UInt<32>("h40000010")) + node T_152 = or(UInt<1>("h0"), T_146) + node decoder_11 = or(T_152, T_150) + node T_154 = and(io.inst, UInt<32>("h70000004")) + node T_156 = eq(T_154, UInt<32>("h0")) + node T_158 = and(io.inst, UInt<32>("h68000004")) + node T_160 = eq(T_158, UInt<32>("h0")) + node T_162 = or(UInt<1>("h0"), T_156) + node T_163 = or(T_162, T_160) + node decoder_12 = or(T_163, T_95) + node T_165 = and(io.inst, UInt<32>("h58000010")) + node T_167 = eq(T_165, UInt<32>("h18000010")) + node decoder_13 = or(UInt<1>("h0"), T_167) + node T_170 = and(io.inst, UInt<32>("hd0000010")) + node T_172 = eq(T_170, UInt<32>("h50000010")) + node decoder_14 = or(UInt<1>("h0"), T_172) + node T_175 = and(io.inst, UInt<32>("h20000004")) + node T_177 = eq(T_175, UInt<32>("h0")) + node T_179 = and(io.inst, UInt<32>("h40002000")) + node T_181 = eq(T_179, UInt<32>("h40000000")) + node T_183 = or(UInt<1>("h0"), T_177) + node T_184 = or(T_183, T_95) + node decoder_15 = or(T_184, T_181) + node T_186 = and(io.inst, UInt<32>("h8002000")) + node T_188 = eq(T_186, UInt<32>("h8000000")) + node T_190 = and(io.inst, UInt<32>("hc0000004")) + node T_192 = eq(T_190, UInt<32>("h80000000")) + node T_194 = or(UInt<1>("h0"), T_177) + node T_195 = or(T_194, T_95) + node T_196 = or(T_195, T_188) + node decoder_16 = or(T_196, T_192) + io.sigs.cmd <= decoder_0 + io.sigs.ldst <= decoder_1 + io.sigs.wen <= decoder_2 + io.sigs.ren1 <= decoder_3 + io.sigs.ren2 <= decoder_4 + io.sigs.ren3 <= decoder_5 + io.sigs.swap12 <= decoder_6 + io.sigs.swap23 <= decoder_7 + io.sigs.single <= decoder_8 + io.sigs.fromint <= decoder_9 + io.sigs.toint <= decoder_10 + io.sigs.fastpipe <= decoder_11 + io.sigs.fma <= decoder_12 + io.sigs.div <= decoder_13 + io.sigs.sqrt <= decoder_14 + io.sigs.round <= decoder_15 + io.sigs.wflags <= decoder_16 + + module MulAddRecFN_preMul : input clk : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} - + output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} + io is invalid - node signA = bits(io.a, 32, 32) @[MulAddRecFN.scala 102:22] - node expA = bits(io.a, 31, 23) @[MulAddRecFN.scala 103:22] - node fractA = bits(io.a, 22, 0) @[MulAddRecFN.scala 104:22] - node T_42 = bits(expA, 8, 6) @[MulAddRecFN.scala 105:24] - node isZeroA = eq(T_42, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] - node T_45 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] - node sigA = cat(T_45, fractA) @[Cat.scala 20:58] - node signB = bits(io.b, 32, 32) @[MulAddRecFN.scala 108:22] - node expB = bits(io.b, 31, 23) @[MulAddRecFN.scala 109:22] - node fractB = bits(io.b, 22, 0) @[MulAddRecFN.scala 110:22] - node T_46 = bits(expB, 8, 6) @[MulAddRecFN.scala 111:24] - node isZeroB = eq(T_46, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] - node T_49 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] - node sigB = cat(T_49, fractB) @[Cat.scala 20:58] - node T_50 = bits(io.c, 32, 32) @[MulAddRecFN.scala 114:23] - node T_51 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] - node opSignC = xor(T_50, T_51) @[MulAddRecFN.scala 114:45] - node expC = bits(io.c, 31, 23) @[MulAddRecFN.scala 115:22] - node fractC = bits(io.c, 22, 0) @[MulAddRecFN.scala 116:22] - node T_52 = bits(expC, 8, 6) @[MulAddRecFN.scala 117:24] - node isZeroC = eq(T_52, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] - node T_55 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] - node sigC = cat(T_55, fractC) @[Cat.scala 20:58] - node T_56 = xor(signA, signB) @[MulAddRecFN.scala 122:26] - node T_57 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] - node signProd = xor(T_56, T_57) @[MulAddRecFN.scala 122:34] - node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] - node T_58 = bits(expB, 8, 8) @[MulAddRecFN.scala 125:34] - node T_60 = eq(T_58, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] - node T_61 = bits(T_60, 0, 0) @[Bitwise.scala 33:15] - node T_64 = mux(T_61, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_65 = bits(expB, 7, 0) @[MulAddRecFN.scala 125:51] - node T_66 = cat(T_64, T_65) @[Cat.scala 20:58] - node T_67 = add(expA, T_66) @[MulAddRecFN.scala 125:14] - node T_68 = tail(T_67, 1) @[MulAddRecFN.scala 125:14] - node T_70 = add(T_68, UInt<5>("h01b")) @[MulAddRecFN.scala 125:70] - node sExpAlignedProd = tail(T_70, 1) @[MulAddRecFN.scala 125:70] - node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] - node T_71 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] - node sNatCAlignDist = tail(T_71, 1) @[MulAddRecFN.scala 132:42] - node T_72 = bits(sNatCAlignDist, 10, 10) @[MulAddRecFN.scala 133:56] - node CAlignDist_floor = or(isZeroProd, T_72) @[MulAddRecFN.scala 133:39] - node T_73 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 135:44] - node T_75 = eq(T_73, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] - node CAlignDist_0 = or(CAlignDist_floor, T_75) @[MulAddRecFN.scala 135:26] - node T_77 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] - node T_78 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 139:33] - node T_80 = lt(T_78, UInt<5>("h019")) @[MulAddRecFN.scala 139:51] - node T_81 = or(CAlignDist_floor, T_80) @[MulAddRecFN.scala 138:31] - node isCDominant = and(T_77, T_81) @[MulAddRecFN.scala 137:19] - node T_83 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 143:31] - node T_85 = lt(T_83, UInt<7>("h04a")) @[MulAddRecFN.scala 143:49] - node T_86 = bits(sNatCAlignDist, 6, 0) @[MulAddRecFN.scala 144:31] - node T_88 = mux(T_85, T_86, UInt<7>("h04a")) @[MulAddRecFN.scala 143:16] - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_88) @[MulAddRecFN.scala 141:12] - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] - node T_89 = bits(CAlignDist, 6, 6) @[primitives.scala 56:25] - node T_90 = bits(CAlignDist, 5, 0) @[primitives.scala 57:26] - node T_92 = dshr(asSInt(UInt<65>("h010000000000000000")), T_90) @[primitives.scala 68:52] - node T_93 = bits(T_92, 63, 54) @[primitives.scala 69:26] - node T_94 = bits(T_93, 7, 0) @[Bitwise.scala 65:18] - node T_97 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 58:47] - node T_98 = xor(UInt<8>("h0ff"), T_97) @[Bitwise.scala 58:21] - node T_99 = shr(T_94, 4) @[Bitwise.scala 59:21] - node T_100 = and(T_99, T_98) @[Bitwise.scala 59:31] - node T_101 = bits(T_94, 3, 0) @[Bitwise.scala 59:46] - node T_102 = shl(T_101, 4) @[Bitwise.scala 59:65] - node T_103 = not(T_98) @[Bitwise.scala 59:77] - node T_104 = and(T_102, T_103) @[Bitwise.scala 59:75] - node T_105 = or(T_100, T_104) @[Bitwise.scala 59:39] - node T_106 = bits(T_98, 5, 0) @[Bitwise.scala 58:28] - node T_107 = shl(T_106, 2) @[Bitwise.scala 58:47] - node T_108 = xor(T_98, T_107) @[Bitwise.scala 58:21] - node T_109 = shr(T_105, 2) @[Bitwise.scala 59:21] - node T_110 = and(T_109, T_108) @[Bitwise.scala 59:31] - node T_111 = bits(T_105, 5, 0) @[Bitwise.scala 59:46] - node T_112 = shl(T_111, 2) @[Bitwise.scala 59:65] - node T_113 = not(T_108) @[Bitwise.scala 59:77] - node T_114 = and(T_112, T_113) @[Bitwise.scala 59:75] - node T_115 = or(T_110, T_114) @[Bitwise.scala 59:39] - node T_116 = bits(T_108, 6, 0) @[Bitwise.scala 58:28] - node T_117 = shl(T_116, 1) @[Bitwise.scala 58:47] - node T_118 = xor(T_108, T_117) @[Bitwise.scala 58:21] - node T_119 = shr(T_115, 1) @[Bitwise.scala 59:21] - node T_120 = and(T_119, T_118) @[Bitwise.scala 59:31] - node T_121 = bits(T_115, 6, 0) @[Bitwise.scala 59:46] - node T_122 = shl(T_121, 1) @[Bitwise.scala 59:65] - node T_123 = not(T_118) @[Bitwise.scala 59:77] - node T_124 = and(T_122, T_123) @[Bitwise.scala 59:75] - node T_125 = or(T_120, T_124) @[Bitwise.scala 59:39] - node T_126 = bits(T_93, 9, 8) @[Bitwise.scala 65:44] - node T_127 = bits(T_126, 0, 0) @[Bitwise.scala 65:18] - node T_128 = bits(T_126, 1, 1) @[Bitwise.scala 65:44] - node T_129 = cat(T_127, T_128) @[Cat.scala 20:58] - node T_130 = cat(T_125, T_129) @[Cat.scala 20:58] - node T_132 = cat(T_130, UInt<14>("h03fff")) @[Cat.scala 20:58] - node T_134 = dshr(asSInt(UInt<65>("h010000000000000000")), T_90) @[primitives.scala 68:52] - node T_135 = bits(T_134, 13, 0) @[primitives.scala 69:26] - node T_136 = bits(T_135, 7, 0) @[Bitwise.scala 65:18] - node T_139 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 58:47] - node T_140 = xor(UInt<8>("h0ff"), T_139) @[Bitwise.scala 58:21] - node T_141 = shr(T_136, 4) @[Bitwise.scala 59:21] - node T_142 = and(T_141, T_140) @[Bitwise.scala 59:31] - node T_143 = bits(T_136, 3, 0) @[Bitwise.scala 59:46] - node T_144 = shl(T_143, 4) @[Bitwise.scala 59:65] - node T_145 = not(T_140) @[Bitwise.scala 59:77] - node T_146 = and(T_144, T_145) @[Bitwise.scala 59:75] - node T_147 = or(T_142, T_146) @[Bitwise.scala 59:39] - node T_148 = bits(T_140, 5, 0) @[Bitwise.scala 58:28] - node T_149 = shl(T_148, 2) @[Bitwise.scala 58:47] - node T_150 = xor(T_140, T_149) @[Bitwise.scala 58:21] - node T_151 = shr(T_147, 2) @[Bitwise.scala 59:21] - node T_152 = and(T_151, T_150) @[Bitwise.scala 59:31] - node T_153 = bits(T_147, 5, 0) @[Bitwise.scala 59:46] - node T_154 = shl(T_153, 2) @[Bitwise.scala 59:65] - node T_155 = not(T_150) @[Bitwise.scala 59:77] - node T_156 = and(T_154, T_155) @[Bitwise.scala 59:75] - node T_157 = or(T_152, T_156) @[Bitwise.scala 59:39] - node T_158 = bits(T_150, 6, 0) @[Bitwise.scala 58:28] - node T_159 = shl(T_158, 1) @[Bitwise.scala 58:47] - node T_160 = xor(T_150, T_159) @[Bitwise.scala 58:21] - node T_161 = shr(T_157, 1) @[Bitwise.scala 59:21] - node T_162 = and(T_161, T_160) @[Bitwise.scala 59:31] - node T_163 = bits(T_157, 6, 0) @[Bitwise.scala 59:46] - node T_164 = shl(T_163, 1) @[Bitwise.scala 59:65] - node T_165 = not(T_160) @[Bitwise.scala 59:77] - node T_166 = and(T_164, T_165) @[Bitwise.scala 59:75] - node T_167 = or(T_162, T_166) @[Bitwise.scala 59:39] - node T_168 = bits(T_135, 13, 8) @[Bitwise.scala 65:44] - node T_169 = bits(T_168, 3, 0) @[Bitwise.scala 65:18] - node T_170 = bits(T_169, 1, 0) @[Bitwise.scala 65:18] - node T_171 = bits(T_170, 0, 0) @[Bitwise.scala 65:18] - node T_172 = bits(T_170, 1, 1) @[Bitwise.scala 65:44] - node T_173 = cat(T_171, T_172) @[Cat.scala 20:58] - node T_174 = bits(T_169, 3, 2) @[Bitwise.scala 65:44] - node T_175 = bits(T_174, 0, 0) @[Bitwise.scala 65:18] - node T_176 = bits(T_174, 1, 1) @[Bitwise.scala 65:44] - node T_177 = cat(T_175, T_176) @[Cat.scala 20:58] - node T_178 = cat(T_173, T_177) @[Cat.scala 20:58] - node T_179 = bits(T_168, 5, 4) @[Bitwise.scala 65:44] - node T_180 = bits(T_179, 0, 0) @[Bitwise.scala 65:18] - node T_181 = bits(T_179, 1, 1) @[Bitwise.scala 65:44] - node T_182 = cat(T_180, T_181) @[Cat.scala 20:58] - node T_183 = cat(T_178, T_182) @[Cat.scala 20:58] - node T_184 = cat(T_167, T_183) @[Cat.scala 20:58] - node CExtraMask = mux(T_89, T_132, T_184) @[primitives.scala 61:20] - node T_185 = not(sigC) @[MulAddRecFN.scala 151:34] - node negSigC = mux(doSubMags, T_185, sigC) @[MulAddRecFN.scala 151:22] - node T_186 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_189 = mux(T_186, UInt<50>("h03ffffffffffff"), UInt<50>("h00")) @[Bitwise.scala 33:12] - node T_190 = cat(doSubMags, negSigC) @[Cat.scala 20:58] - node T_191 = cat(T_190, T_189) @[Cat.scala 20:58] - node T_192 = asSInt(T_191) @[MulAddRecFN.scala 154:64] - node T_193 = dshr(T_192, CAlignDist) @[MulAddRecFN.scala 154:70] - node T_194 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] - node T_196 = neq(T_194, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] - node T_197 = xor(T_196, doSubMags) @[MulAddRecFN.scala 156:37] - node T_198 = asUInt(T_193) @[Cat.scala 20:58] - node T_199 = cat(T_198, T_197) @[Cat.scala 20:58] - node alignedNegSigC = bits(T_199, 74, 0) @[MulAddRecFN.scala 157:10] - io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] - io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] - node T_200 = bits(alignedNegSigC, 48, 1) @[MulAddRecFN.scala 161:33] - io.mulAddC <= T_200 @[MulAddRecFN.scala 161:16] - node T_201 = bits(expA, 8, 6) @[MulAddRecFN.scala 163:44] - io.toPostMul.highExpA <= T_201 @[MulAddRecFN.scala 163:37] - node T_202 = bits(fractA, 22, 22) @[MulAddRecFN.scala 164:46] - io.toPostMul.isNaN_isQuietNaNA <= T_202 @[MulAddRecFN.scala 164:37] - node T_203 = bits(expB, 8, 6) @[MulAddRecFN.scala 165:44] - io.toPostMul.highExpB <= T_203 @[MulAddRecFN.scala 165:37] - node T_204 = bits(fractB, 22, 22) @[MulAddRecFN.scala 166:46] - io.toPostMul.isNaN_isQuietNaNB <= T_204 @[MulAddRecFN.scala 166:37] - io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] - io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] - io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] - node T_205 = bits(expC, 8, 6) @[MulAddRecFN.scala 170:44] - io.toPostMul.highExpC <= T_205 @[MulAddRecFN.scala 170:37] - node T_206 = bits(fractC, 22, 22) @[MulAddRecFN.scala 171:46] - io.toPostMul.isNaN_isQuietNaNC <= T_206 @[MulAddRecFN.scala 171:37] - io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] - io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] - io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] - node T_207 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] - io.toPostMul.bit0AlignedNegSigC <= T_207 @[MulAddRecFN.scala 175:37] - node T_208 = bits(alignedNegSigC, 74, 49) @[MulAddRecFN.scala 177:23] - io.toPostMul.highAlignedNegSigC <= T_208 @[MulAddRecFN.scala 176:37] - io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] - io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] - - module MulAddRecFN_postMul : + node signA = bits(io.a, 32, 32) + node expA = bits(io.a, 31, 23) + node fractA = bits(io.a, 22, 0) + node T_42 = bits(expA, 8, 6) + node isZeroA = eq(T_42, UInt<1>("h0")) + node T_45 = eq(isZeroA, UInt<1>("h0")) + node sigA = cat(T_45, fractA) + node signB = bits(io.b, 32, 32) + node expB = bits(io.b, 31, 23) + node fractB = bits(io.b, 22, 0) + node T_46 = bits(expB, 8, 6) + node isZeroB = eq(T_46, UInt<1>("h0")) + node T_49 = eq(isZeroB, UInt<1>("h0")) + node sigB = cat(T_49, fractB) + node T_50 = bits(io.c, 32, 32) + node T_51 = bits(io.op, 0, 0) + node opSignC = xor(T_50, T_51) + node expC = bits(io.c, 31, 23) + node fractC = bits(io.c, 22, 0) + node T_52 = bits(expC, 8, 6) + node isZeroC = eq(T_52, UInt<1>("h0")) + node T_55 = eq(isZeroC, UInt<1>("h0")) + node sigC = cat(T_55, fractC) + node T_56 = xor(signA, signB) + node T_57 = bits(io.op, 1, 1) + node signProd = xor(T_56, T_57) + node isZeroProd = or(isZeroA, isZeroB) + node T_58 = bits(expB, 8, 8) + node T_60 = eq(T_58, UInt<1>("h0")) + node T_61 = bits(T_60, 0, 0) + node T_64 = mux(T_61, UInt<3>("h7"), UInt<3>("h0")) + node T_65 = bits(expB, 7, 0) + node T_66 = cat(T_64, T_65) + node T_67 = add(expA, T_66) + node T_68 = tail(T_67, 1) + node T_70 = add(T_68, UInt<5>("h1b")) + node sExpAlignedProd = tail(T_70, 1) + node doSubMags = xor(signProd, opSignC) + node T_71 = sub(sExpAlignedProd, expC) + node sNatCAlignDist = tail(T_71, 1) + node T_72 = bits(sNatCAlignDist, 10, 10) + node CAlignDist_floor = or(isZeroProd, T_72) + node T_73 = bits(sNatCAlignDist, 9, 0) + node T_75 = eq(T_73, UInt<1>("h0")) + node CAlignDist_0 = or(CAlignDist_floor, T_75) + node T_77 = eq(isZeroC, UInt<1>("h0")) + node T_78 = bits(sNatCAlignDist, 9, 0) + node T_80 = lt(T_78, UInt<5>("h19")) + node T_81 = or(CAlignDist_floor, T_80) + node isCDominant = and(T_77, T_81) + node T_83 = bits(sNatCAlignDist, 9, 0) + node T_85 = lt(T_83, UInt<7>("h4a")) + node T_86 = bits(sNatCAlignDist, 6, 0) + node T_88 = mux(T_85, T_86, UInt<7>("h4a")) + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h0"), T_88) + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) + node T_89 = bits(CAlignDist, 6, 6) + node T_90 = bits(CAlignDist, 5, 0) + node T_92 = dshr(asSInt(UInt<65>("h10000000000000000")), T_90) + node T_93 = bits(T_92, 63, 54) + node T_94 = bits(T_93, 7, 0) + node T_97 = shl(UInt<4>("hf"), 4) + node T_98 = xor(UInt<8>("hff"), T_97) + node T_99 = shr(T_94, 4) + node T_100 = and(T_99, T_98) + node T_101 = bits(T_94, 3, 0) + node T_102 = shl(T_101, 4) + node T_103 = not(T_98) + node T_104 = and(T_102, T_103) + node T_105 = or(T_100, T_104) + node T_106 = bits(T_98, 5, 0) + node T_107 = shl(T_106, 2) + node T_108 = xor(T_98, T_107) + node T_109 = shr(T_105, 2) + node T_110 = and(T_109, T_108) + node T_111 = bits(T_105, 5, 0) + node T_112 = shl(T_111, 2) + node T_113 = not(T_108) + node T_114 = and(T_112, T_113) + node T_115 = or(T_110, T_114) + node T_116 = bits(T_108, 6, 0) + node T_117 = shl(T_116, 1) + node T_118 = xor(T_108, T_117) + node T_119 = shr(T_115, 1) + node T_120 = and(T_119, T_118) + node T_121 = bits(T_115, 6, 0) + node T_122 = shl(T_121, 1) + node T_123 = not(T_118) + node T_124 = and(T_122, T_123) + node T_125 = or(T_120, T_124) + node T_126 = bits(T_93, 9, 8) + node T_127 = bits(T_126, 0, 0) + node T_128 = bits(T_126, 1, 1) + node T_129 = cat(T_127, T_128) + node T_130 = cat(T_125, T_129) + node T_132 = cat(T_130, UInt<14>("h3fff")) + node T_134 = dshr(asSInt(UInt<65>("h10000000000000000")), T_90) + node T_135 = bits(T_134, 13, 0) + node T_136 = bits(T_135, 7, 0) + node T_139 = shl(UInt<4>("hf"), 4) + node T_140 = xor(UInt<8>("hff"), T_139) + node T_141 = shr(T_136, 4) + node T_142 = and(T_141, T_140) + node T_143 = bits(T_136, 3, 0) + node T_144 = shl(T_143, 4) + node T_145 = not(T_140) + node T_146 = and(T_144, T_145) + node T_147 = or(T_142, T_146) + node T_148 = bits(T_140, 5, 0) + node T_149 = shl(T_148, 2) + node T_150 = xor(T_140, T_149) + node T_151 = shr(T_147, 2) + node T_152 = and(T_151, T_150) + node T_153 = bits(T_147, 5, 0) + node T_154 = shl(T_153, 2) + node T_155 = not(T_150) + node T_156 = and(T_154, T_155) + node T_157 = or(T_152, T_156) + node T_158 = bits(T_150, 6, 0) + node T_159 = shl(T_158, 1) + node T_160 = xor(T_150, T_159) + node T_161 = shr(T_157, 1) + node T_162 = and(T_161, T_160) + node T_163 = bits(T_157, 6, 0) + node T_164 = shl(T_163, 1) + node T_165 = not(T_160) + node T_166 = and(T_164, T_165) + node T_167 = or(T_162, T_166) + node T_168 = bits(T_135, 13, 8) + node T_169 = bits(T_168, 3, 0) + node T_170 = bits(T_169, 1, 0) + node T_171 = bits(T_170, 0, 0) + node T_172 = bits(T_170, 1, 1) + node T_173 = cat(T_171, T_172) + node T_174 = bits(T_169, 3, 2) + node T_175 = bits(T_174, 0, 0) + node T_176 = bits(T_174, 1, 1) + node T_177 = cat(T_175, T_176) + node T_178 = cat(T_173, T_177) + node T_179 = bits(T_168, 5, 4) + node T_180 = bits(T_179, 0, 0) + node T_181 = bits(T_179, 1, 1) + node T_182 = cat(T_180, T_181) + node T_183 = cat(T_178, T_182) + node T_184 = cat(T_167, T_183) + node CExtraMask = mux(T_89, T_132, T_184) + node T_185 = not(sigC) + node negSigC = mux(doSubMags, T_185, sigC) + node T_186 = bits(doSubMags, 0, 0) + node T_189 = mux(T_186, UInt<50>("h3ffffffffffff"), UInt<50>("h0")) + node T_190 = cat(doSubMags, negSigC) + node T_191 = cat(T_190, T_189) + node T_192 = asSInt(T_191) + node T_193 = dshr(T_192, CAlignDist) + node T_194 = and(sigC, CExtraMask) + node T_196 = neq(T_194, UInt<1>("h0")) + node T_197 = xor(T_196, doSubMags) + node T_198 = asUInt(T_193) + node T_199 = cat(T_198, T_197) + node alignedNegSigC = bits(T_199, 74, 0) + io.mulAddA <= sigA + io.mulAddB <= sigB + node T_200 = bits(alignedNegSigC, 48, 1) + io.mulAddC <= T_200 + node T_201 = bits(expA, 8, 6) + io.toPostMul.highExpA <= T_201 + node T_202 = bits(fractA, 22, 22) + io.toPostMul.isNaN_isQuietNaNA <= T_202 + node T_203 = bits(expB, 8, 6) + io.toPostMul.highExpB <= T_203 + node T_204 = bits(fractB, 22, 22) + io.toPostMul.isNaN_isQuietNaNB <= T_204 + io.toPostMul.signProd <= signProd + io.toPostMul.isZeroProd <= isZeroProd + io.toPostMul.opSignC <= opSignC + node T_205 = bits(expC, 8, 6) + io.toPostMul.highExpC <= T_205 + node T_206 = bits(fractC, 22, 22) + io.toPostMul.isNaN_isQuietNaNC <= T_206 + io.toPostMul.isCDominant <= isCDominant + io.toPostMul.CAlignDist_0 <= CAlignDist_0 + io.toPostMul.CAlignDist <= CAlignDist + node T_207 = bits(alignedNegSigC, 0, 0) + io.toPostMul.bit0AlignedNegSigC <= T_207 + node T_208 = bits(alignedNegSigC, 74, 49) + io.toPostMul.highAlignedNegSigC <= T_208 + io.toPostMul.sExpSum <= sExpSum + io.toPostMul.roundingMode <= io.roundingMode + + module MulAddRecFN_postMul : input clk : Clock input reset : UInt<1> - output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip fromPreMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] - node T_38 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] - node isSpecialA = eq(T_38, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] - node T_40 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] - node T_42 = eq(T_40, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] - node isInfA = and(isSpecialA, T_42) @[MulAddRecFN.scala 209:29] - node T_43 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] - node isNaNA = and(isSpecialA, T_43) @[MulAddRecFN.scala 210:29] - node T_45 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] - node isSigNaNA = and(isNaNA, T_45) @[MulAddRecFN.scala 211:28] - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] - node T_47 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] - node isSpecialB = eq(T_47, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] - node T_49 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] - node T_51 = eq(T_49, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] - node isInfB = and(isSpecialB, T_51) @[MulAddRecFN.scala 215:29] - node T_52 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] - node isNaNB = and(isSpecialB, T_52) @[MulAddRecFN.scala 216:29] - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] - node isSigNaNB = and(isNaNB, T_54) @[MulAddRecFN.scala 217:28] - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] - node T_56 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] - node isSpecialC = eq(T_56, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] - node T_58 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] - node T_60 = eq(T_58, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] - node isInfC = and(isSpecialC, T_60) @[MulAddRecFN.scala 221:29] - node T_61 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] - node isNaNC = and(isSpecialC, T_61) @[MulAddRecFN.scala 222:29] - node T_63 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] - node isSigNaNC = and(isNaNC, T_63) @[MulAddRecFN.scala 223:28] - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] - node T_70 = bits(io.mulAddResult, 48, 48) @[MulAddRecFN.scala 237:32] - node T_72 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] - node T_73 = tail(T_72, 1) @[MulAddRecFN.scala 238:50] - node T_74 = mux(T_70, T_73, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] - node T_75 = bits(io.mulAddResult, 47, 0) @[MulAddRecFN.scala 241:28] - node T_76 = cat(T_74, T_75) @[Cat.scala 20:58] - node sigSum = cat(T_76, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 20:58] - node T_78 = bits(sigSum, 50, 1) @[MulAddRecFN.scala 248:38] - node T_79 = xor(UInt<50>("h00"), T_78) @[MulAddRecFN.scala 191:27] - node T_80 = or(UInt<50>("h00"), T_78) @[MulAddRecFN.scala 191:37] - node T_81 = shl(T_80, 1) @[MulAddRecFN.scala 191:41] - node T_82 = xor(T_79, T_81) @[MulAddRecFN.scala 191:32] - node T_84 = bits(T_82, 49, 0) @[primitives.scala 79:35] - node T_85 = bits(T_84, 49, 32) @[CircuitMath.scala 26:17] - node T_86 = bits(T_84, 31, 0) @[CircuitMath.scala 27:17] - node T_88 = neq(T_85, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_89 = bits(T_85, 17, 16) @[CircuitMath.scala 26:17] - node T_90 = bits(T_85, 15, 0) @[CircuitMath.scala 27:17] - node T_92 = neq(T_89, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_93 = bits(T_89, 1, 1) @[CircuitMath.scala 21:8] - node T_94 = bits(T_90, 15, 8) @[CircuitMath.scala 26:17] - node T_95 = bits(T_90, 7, 0) @[CircuitMath.scala 27:17] - node T_97 = neq(T_94, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_98 = bits(T_94, 7, 4) @[CircuitMath.scala 26:17] - node T_99 = bits(T_94, 3, 0) @[CircuitMath.scala 27:17] - node T_101 = neq(T_98, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_102 = bits(T_98, 3, 3) @[CircuitMath.scala 23:12] - node T_104 = bits(T_98, 2, 2) @[CircuitMath.scala 23:12] - node T_106 = bits(T_98, 1, 1) @[CircuitMath.scala 21:8] - node T_107 = shl(T_106, 0) @[CircuitMath.scala 23:10] - node T_108 = mux(T_104, UInt<2>("h02"), T_107) @[CircuitMath.scala 23:10] - node T_109 = mux(T_102, UInt<2>("h03"), T_108) @[CircuitMath.scala 23:10] - node T_110 = bits(T_99, 3, 3) @[CircuitMath.scala 23:12] - node T_112 = bits(T_99, 2, 2) @[CircuitMath.scala 23:12] - node T_114 = bits(T_99, 1, 1) @[CircuitMath.scala 21:8] - node T_115 = shl(T_114, 0) @[CircuitMath.scala 23:10] - node T_116 = mux(T_112, UInt<2>("h02"), T_115) @[CircuitMath.scala 23:10] - node T_117 = mux(T_110, UInt<2>("h03"), T_116) @[CircuitMath.scala 23:10] - node T_118 = mux(T_101, T_109, T_117) @[CircuitMath.scala 29:21] - node T_119 = cat(T_101, T_118) @[Cat.scala 20:58] - node T_120 = bits(T_95, 7, 4) @[CircuitMath.scala 26:17] - node T_121 = bits(T_95, 3, 0) @[CircuitMath.scala 27:17] - node T_123 = neq(T_120, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_124 = bits(T_120, 3, 3) @[CircuitMath.scala 23:12] - node T_126 = bits(T_120, 2, 2) @[CircuitMath.scala 23:12] - node T_128 = bits(T_120, 1, 1) @[CircuitMath.scala 21:8] - node T_129 = shl(T_128, 0) @[CircuitMath.scala 23:10] - node T_130 = mux(T_126, UInt<2>("h02"), T_129) @[CircuitMath.scala 23:10] - node T_131 = mux(T_124, UInt<2>("h03"), T_130) @[CircuitMath.scala 23:10] - node T_132 = bits(T_121, 3, 3) @[CircuitMath.scala 23:12] - node T_134 = bits(T_121, 2, 2) @[CircuitMath.scala 23:12] - node T_136 = bits(T_121, 1, 1) @[CircuitMath.scala 21:8] - node T_137 = shl(T_136, 0) @[CircuitMath.scala 23:10] - node T_138 = mux(T_134, UInt<2>("h02"), T_137) @[CircuitMath.scala 23:10] - node T_139 = mux(T_132, UInt<2>("h03"), T_138) @[CircuitMath.scala 23:10] - node T_140 = mux(T_123, T_131, T_139) @[CircuitMath.scala 29:21] - node T_141 = cat(T_123, T_140) @[Cat.scala 20:58] - node T_142 = mux(T_97, T_119, T_141) @[CircuitMath.scala 29:21] - node T_143 = cat(T_97, T_142) @[Cat.scala 20:58] - node T_144 = shl(T_93, 0) @[CircuitMath.scala 29:21] - node T_145 = mux(T_92, T_144, T_143) @[CircuitMath.scala 29:21] - node T_146 = cat(T_92, T_145) @[Cat.scala 20:58] - node T_147 = bits(T_86, 31, 16) @[CircuitMath.scala 26:17] - node T_148 = bits(T_86, 15, 0) @[CircuitMath.scala 27:17] - node T_150 = neq(T_147, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_151 = bits(T_147, 15, 8) @[CircuitMath.scala 26:17] - node T_152 = bits(T_147, 7, 0) @[CircuitMath.scala 27:17] - node T_154 = neq(T_151, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_155 = bits(T_151, 7, 4) @[CircuitMath.scala 26:17] - node T_156 = bits(T_151, 3, 0) @[CircuitMath.scala 27:17] - node T_158 = neq(T_155, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_159 = bits(T_155, 3, 3) @[CircuitMath.scala 23:12] - node T_161 = bits(T_155, 2, 2) @[CircuitMath.scala 23:12] - node T_163 = bits(T_155, 1, 1) @[CircuitMath.scala 21:8] - node T_164 = shl(T_163, 0) @[CircuitMath.scala 23:10] - node T_165 = mux(T_161, UInt<2>("h02"), T_164) @[CircuitMath.scala 23:10] - node T_166 = mux(T_159, UInt<2>("h03"), T_165) @[CircuitMath.scala 23:10] - node T_167 = bits(T_156, 3, 3) @[CircuitMath.scala 23:12] - node T_169 = bits(T_156, 2, 2) @[CircuitMath.scala 23:12] - node T_171 = bits(T_156, 1, 1) @[CircuitMath.scala 21:8] - node T_172 = shl(T_171, 0) @[CircuitMath.scala 23:10] - node T_173 = mux(T_169, UInt<2>("h02"), T_172) @[CircuitMath.scala 23:10] - node T_174 = mux(T_167, UInt<2>("h03"), T_173) @[CircuitMath.scala 23:10] - node T_175 = mux(T_158, T_166, T_174) @[CircuitMath.scala 29:21] - node T_176 = cat(T_158, T_175) @[Cat.scala 20:58] - node T_177 = bits(T_152, 7, 4) @[CircuitMath.scala 26:17] - node T_178 = bits(T_152, 3, 0) @[CircuitMath.scala 27:17] - node T_180 = neq(T_177, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_181 = bits(T_177, 3, 3) @[CircuitMath.scala 23:12] - node T_183 = bits(T_177, 2, 2) @[CircuitMath.scala 23:12] - node T_185 = bits(T_177, 1, 1) @[CircuitMath.scala 21:8] - node T_186 = shl(T_185, 0) @[CircuitMath.scala 23:10] - node T_187 = mux(T_183, UInt<2>("h02"), T_186) @[CircuitMath.scala 23:10] - node T_188 = mux(T_181, UInt<2>("h03"), T_187) @[CircuitMath.scala 23:10] - node T_189 = bits(T_178, 3, 3) @[CircuitMath.scala 23:12] - node T_191 = bits(T_178, 2, 2) @[CircuitMath.scala 23:12] - node T_193 = bits(T_178, 1, 1) @[CircuitMath.scala 21:8] - node T_194 = shl(T_193, 0) @[CircuitMath.scala 23:10] - node T_195 = mux(T_191, UInt<2>("h02"), T_194) @[CircuitMath.scala 23:10] - node T_196 = mux(T_189, UInt<2>("h03"), T_195) @[CircuitMath.scala 23:10] - node T_197 = mux(T_180, T_188, T_196) @[CircuitMath.scala 29:21] - node T_198 = cat(T_180, T_197) @[Cat.scala 20:58] - node T_199 = mux(T_154, T_176, T_198) @[CircuitMath.scala 29:21] - node T_200 = cat(T_154, T_199) @[Cat.scala 20:58] - node T_201 = bits(T_148, 15, 8) @[CircuitMath.scala 26:17] - node T_202 = bits(T_148, 7, 0) @[CircuitMath.scala 27:17] - node T_204 = neq(T_201, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_205 = bits(T_201, 7, 4) @[CircuitMath.scala 26:17] - node T_206 = bits(T_201, 3, 0) @[CircuitMath.scala 27:17] - node T_208 = neq(T_205, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_209 = bits(T_205, 3, 3) @[CircuitMath.scala 23:12] - node T_211 = bits(T_205, 2, 2) @[CircuitMath.scala 23:12] - node T_213 = bits(T_205, 1, 1) @[CircuitMath.scala 21:8] - node T_214 = shl(T_213, 0) @[CircuitMath.scala 23:10] - node T_215 = mux(T_211, UInt<2>("h02"), T_214) @[CircuitMath.scala 23:10] - node T_216 = mux(T_209, UInt<2>("h03"), T_215) @[CircuitMath.scala 23:10] - node T_217 = bits(T_206, 3, 3) @[CircuitMath.scala 23:12] - node T_219 = bits(T_206, 2, 2) @[CircuitMath.scala 23:12] - node T_221 = bits(T_206, 1, 1) @[CircuitMath.scala 21:8] - node T_222 = shl(T_221, 0) @[CircuitMath.scala 23:10] - node T_223 = mux(T_219, UInt<2>("h02"), T_222) @[CircuitMath.scala 23:10] - node T_224 = mux(T_217, UInt<2>("h03"), T_223) @[CircuitMath.scala 23:10] - node T_225 = mux(T_208, T_216, T_224) @[CircuitMath.scala 29:21] - node T_226 = cat(T_208, T_225) @[Cat.scala 20:58] - node T_227 = bits(T_202, 7, 4) @[CircuitMath.scala 26:17] - node T_228 = bits(T_202, 3, 0) @[CircuitMath.scala 27:17] - node T_230 = neq(T_227, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_231 = bits(T_227, 3, 3) @[CircuitMath.scala 23:12] - node T_233 = bits(T_227, 2, 2) @[CircuitMath.scala 23:12] - node T_235 = bits(T_227, 1, 1) @[CircuitMath.scala 21:8] - node T_236 = shl(T_235, 0) @[CircuitMath.scala 23:10] - node T_237 = mux(T_233, UInt<2>("h02"), T_236) @[CircuitMath.scala 23:10] - node T_238 = mux(T_231, UInt<2>("h03"), T_237) @[CircuitMath.scala 23:10] - node T_239 = bits(T_228, 3, 3) @[CircuitMath.scala 23:12] - node T_241 = bits(T_228, 2, 2) @[CircuitMath.scala 23:12] - node T_243 = bits(T_228, 1, 1) @[CircuitMath.scala 21:8] - node T_244 = shl(T_243, 0) @[CircuitMath.scala 23:10] - node T_245 = mux(T_241, UInt<2>("h02"), T_244) @[CircuitMath.scala 23:10] - node T_246 = mux(T_239, UInt<2>("h03"), T_245) @[CircuitMath.scala 23:10] - node T_247 = mux(T_230, T_238, T_246) @[CircuitMath.scala 29:21] - node T_248 = cat(T_230, T_247) @[Cat.scala 20:58] - node T_249 = mux(T_204, T_226, T_248) @[CircuitMath.scala 29:21] - node T_250 = cat(T_204, T_249) @[Cat.scala 20:58] - node T_251 = mux(T_150, T_200, T_250) @[CircuitMath.scala 29:21] - node T_252 = cat(T_150, T_251) @[Cat.scala 20:58] - node T_253 = mux(T_88, T_146, T_252) @[CircuitMath.scala 29:21] - node T_254 = cat(T_88, T_253) @[Cat.scala 20:58] - node T_255 = sub(UInt<7>("h049"), T_254) @[primitives.scala 79:25] - node estNormPos_dist = tail(T_255, 1) @[primitives.scala 79:25] - node T_256 = bits(sigSum, 33, 18) @[MulAddRecFN.scala 252:19] - node T_258 = neq(T_256, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] - node T_259 = bits(sigSum, 17, 0) @[MulAddRecFN.scala 255:19] - node T_261 = neq(T_259, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] - node firstReduceSigSum = cat(T_258, T_261) @[Cat.scala 20:58] - node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] - node T_262 = bits(complSigSum, 33, 18) @[MulAddRecFN.scala 259:24] - node T_264 = neq(T_262, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] - node T_265 = bits(complSigSum, 17, 0) @[MulAddRecFN.scala 262:24] - node T_267 = neq(T_265, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] - node firstReduceComplSigSum = cat(T_264, T_267) @[Cat.scala 20:58] - node T_268 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] - node T_270 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] - node T_271 = tail(T_270, 1) @[MulAddRecFN.scala 268:39] - node T_272 = bits(T_271, 4, 0) @[MulAddRecFN.scala 268:49] - node CDom_estNormDist = mux(T_268, io.fromPreMul.CAlignDist, T_272) @[MulAddRecFN.scala 266:12] - node T_274 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] - node T_275 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 271:46] - node T_277 = eq(T_275, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] - node T_278 = and(T_274, T_277) @[MulAddRecFN.scala 271:25] - node T_279 = bits(sigSum, 74, 34) @[MulAddRecFN.scala 272:23] - node T_281 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] - node T_282 = cat(T_279, T_281) @[Cat.scala 20:58] - node T_284 = mux(T_278, T_282, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] - node T_286 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] - node T_287 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 277:44] - node T_288 = and(T_286, T_287) @[MulAddRecFN.scala 277:25] - node T_289 = bits(sigSum, 58, 18) @[MulAddRecFN.scala 278:23] - node T_290 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] - node T_291 = cat(T_289, T_290) @[Cat.scala 20:58] - node T_293 = mux(T_288, T_291, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] - node T_294 = or(T_284, T_293) @[MulAddRecFN.scala 276:11] - node T_295 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 286:44] - node T_297 = eq(T_295, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] - node T_298 = and(doSubMags, T_297) @[MulAddRecFN.scala 286:23] - node T_299 = bits(complSigSum, 74, 34) @[MulAddRecFN.scala 287:28] - node T_301 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] - node T_302 = cat(T_299, T_301) @[Cat.scala 20:58] - node T_304 = mux(T_298, T_302, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] - node T_305 = or(T_294, T_304) @[MulAddRecFN.scala 285:11] - node T_306 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 292:42] - node T_307 = and(doSubMags, T_306) @[MulAddRecFN.scala 292:23] - node T_308 = bits(complSigSum, 58, 18) @[MulAddRecFN.scala 293:28] - node T_309 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] - node T_310 = cat(T_308, T_309) @[Cat.scala 20:58] - node T_312 = mux(T_307, T_310, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] - node CDom_firstNormAbsSigSum = or(T_305, T_312) @[MulAddRecFN.scala 291:11] - node T_313 = bits(sigSum, 50, 18) @[MulAddRecFN.scala 308:23] - node T_314 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] - node T_316 = eq(T_314, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] - node T_317 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] - node T_318 = mux(doSubMags, T_316, T_317) @[MulAddRecFN.scala 309:20] - node T_319 = cat(T_313, T_318) @[Cat.scala 20:58] - node T_320 = bits(sigSum, 42, 1) @[MulAddRecFN.scala 314:24] - node T_321 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 338:28] - node T_322 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 339:33] - node T_323 = bits(sigSum, 26, 1) @[MulAddRecFN.scala 340:28] - node T_324 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_327 = mux(T_324, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 33:12] - node T_328 = cat(T_323, T_327) @[Cat.scala 20:58] - node T_329 = mux(T_322, T_328, T_320) @[MulAddRecFN.scala 339:17] - node T_330 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 345:33] - node T_331 = bits(sigSum, 10, 1) @[MulAddRecFN.scala 347:28] - node T_332 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_335 = mux(T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_336 = cat(T_331, T_335) @[Cat.scala 20:58] - node T_337 = mux(T_330, T_319, T_336) @[MulAddRecFN.scala 345:17] - node notCDom_pos_firstNormAbsSigSum = mux(T_321, T_329, T_337) @[MulAddRecFN.scala 338:12] - node T_338 = bits(complSigSum, 49, 18) @[MulAddRecFN.scala 360:28] - node T_339 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] - node T_340 = cat(T_338, T_339) @[Cat.scala 20:58] - node T_341 = bits(complSigSum, 42, 1) @[MulAddRecFN.scala 363:29] - node T_342 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 379:28] - node T_343 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 380:33] - node T_344 = bits(complSigSum, 27, 1) @[MulAddRecFN.scala 381:29] - node T_345 = shl(T_344, 16) @[MulAddRecFN.scala 381:64] - node T_346 = mux(T_343, T_345, T_341) @[MulAddRecFN.scala 380:17] - node T_347 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 385:33] - node T_348 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 387:29] - node T_349 = shl(T_348, 32) @[MulAddRecFN.scala 387:64] - node T_350 = mux(T_347, T_340, T_349) @[MulAddRecFN.scala 385:17] - node notCDom_neg_cFirstNormAbsSigSum = mux(T_342, T_346, T_350) @[MulAddRecFN.scala 379:12] - node notCDom_signSigSum = bits(sigSum, 51, 51) @[MulAddRecFN.scala 392:36] - node T_352 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] - node T_353 = and(doSubMags, T_352) @[MulAddRecFN.scala 395:23] - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_353, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] - node T_354 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) @[MulAddRecFN.scala 401:16] - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_354) @[MulAddRecFN.scala 399:12] - node T_355 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] - node T_356 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_355, T_356) @[MulAddRecFN.scala 407:12] - node T_358 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] - node T_360 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] - node T_361 = and(T_358, T_360) @[MulAddRecFN.scala 418:37] - node doIncrSig = and(T_361, doSubMags) @[MulAddRecFN.scala 418:61] - node estNormDist_5 = bits(estNormDist, 3, 0) @[MulAddRecFN.scala 419:36] - node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] - node T_363 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) @[primitives.scala 68:52] - node T_364 = bits(T_363, 15, 1) @[primitives.scala 69:26] - node T_365 = bits(T_364, 7, 0) @[Bitwise.scala 65:18] - node T_368 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 58:47] - node T_369 = xor(UInt<8>("h0ff"), T_368) @[Bitwise.scala 58:21] - node T_370 = shr(T_365, 4) @[Bitwise.scala 59:21] - node T_371 = and(T_370, T_369) @[Bitwise.scala 59:31] - node T_372 = bits(T_365, 3, 0) @[Bitwise.scala 59:46] - node T_373 = shl(T_372, 4) @[Bitwise.scala 59:65] - node T_374 = not(T_369) @[Bitwise.scala 59:77] - node T_375 = and(T_373, T_374) @[Bitwise.scala 59:75] - node T_376 = or(T_371, T_375) @[Bitwise.scala 59:39] - node T_377 = bits(T_369, 5, 0) @[Bitwise.scala 58:28] - node T_378 = shl(T_377, 2) @[Bitwise.scala 58:47] - node T_379 = xor(T_369, T_378) @[Bitwise.scala 58:21] - node T_380 = shr(T_376, 2) @[Bitwise.scala 59:21] - node T_381 = and(T_380, T_379) @[Bitwise.scala 59:31] - node T_382 = bits(T_376, 5, 0) @[Bitwise.scala 59:46] - node T_383 = shl(T_382, 2) @[Bitwise.scala 59:65] - node T_384 = not(T_379) @[Bitwise.scala 59:77] - node T_385 = and(T_383, T_384) @[Bitwise.scala 59:75] - node T_386 = or(T_381, T_385) @[Bitwise.scala 59:39] - node T_387 = bits(T_379, 6, 0) @[Bitwise.scala 58:28] - node T_388 = shl(T_387, 1) @[Bitwise.scala 58:47] - node T_389 = xor(T_379, T_388) @[Bitwise.scala 58:21] - node T_390 = shr(T_386, 1) @[Bitwise.scala 59:21] - node T_391 = and(T_390, T_389) @[Bitwise.scala 59:31] - node T_392 = bits(T_386, 6, 0) @[Bitwise.scala 59:46] - node T_393 = shl(T_392, 1) @[Bitwise.scala 59:65] - node T_394 = not(T_389) @[Bitwise.scala 59:77] - node T_395 = and(T_393, T_394) @[Bitwise.scala 59:75] - node T_396 = or(T_391, T_395) @[Bitwise.scala 59:39] - node T_397 = bits(T_364, 14, 8) @[Bitwise.scala 65:44] - node T_398 = bits(T_397, 3, 0) @[Bitwise.scala 65:18] - node T_399 = bits(T_398, 1, 0) @[Bitwise.scala 65:18] - node T_400 = bits(T_399, 0, 0) @[Bitwise.scala 65:18] - node T_401 = bits(T_399, 1, 1) @[Bitwise.scala 65:44] - node T_402 = cat(T_400, T_401) @[Cat.scala 20:58] - node T_403 = bits(T_398, 3, 2) @[Bitwise.scala 65:44] - node T_404 = bits(T_403, 0, 0) @[Bitwise.scala 65:18] - node T_405 = bits(T_403, 1, 1) @[Bitwise.scala 65:44] - node T_406 = cat(T_404, T_405) @[Cat.scala 20:58] - node T_407 = cat(T_402, T_406) @[Cat.scala 20:58] - node T_408 = bits(T_397, 6, 4) @[Bitwise.scala 65:44] - node T_409 = bits(T_408, 1, 0) @[Bitwise.scala 65:18] - node T_410 = bits(T_409, 0, 0) @[Bitwise.scala 65:18] - node T_411 = bits(T_409, 1, 1) @[Bitwise.scala 65:44] - node T_412 = cat(T_410, T_411) @[Cat.scala 20:58] - node T_413 = bits(T_408, 2, 2) @[Bitwise.scala 65:44] - node T_414 = cat(T_412, T_413) @[Cat.scala 20:58] - node T_415 = cat(T_407, T_414) @[Cat.scala 20:58] - node T_416 = cat(T_396, T_415) @[Cat.scala 20:58] - node absSigSumExtraMask = cat(T_416, UInt<1>("h01")) @[Cat.scala 20:58] - node T_418 = bits(cFirstNormAbsSigSum, 42, 1) @[MulAddRecFN.scala 424:32] - node T_419 = dshr(T_418, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] - node T_420 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 427:39] - node T_421 = not(T_420) @[MulAddRecFN.scala 427:19] - node T_422 = and(T_421, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] - node T_424 = eq(T_422, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] - node T_425 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 430:38] - node T_426 = and(T_425, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] - node T_428 = neq(T_426, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] - node T_429 = mux(doIncrSig, T_424, T_428) @[MulAddRecFN.scala 426:16] - node T_430 = cat(T_419, T_429) @[Cat.scala 20:58] - node sigX3 = bits(T_430, 27, 0) @[MulAddRecFN.scala 434:10] - node T_431 = bits(sigX3, 27, 26) @[MulAddRecFN.scala 436:29] - node sigX3Shift1 = eq(T_431, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] - node T_433 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] - node sExpX3 = tail(T_433, 1) @[MulAddRecFN.scala 437:40] - node T_434 = bits(sigX3, 27, 25) @[MulAddRecFN.scala 439:25] - node isZeroY = eq(T_434, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] - node T_436 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_436) @[MulAddRecFN.scala 442:12] - node sExpX3_13 = bits(sExpX3, 9, 0) @[MulAddRecFN.scala 446:27] - node T_437 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 448:34] - node T_438 = bits(T_437, 0, 0) @[Bitwise.scala 33:15] - node T_441 = mux(T_438, UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 33:12] - node T_442 = not(sExpX3_13) @[primitives.scala 50:21] - node T_443 = bits(T_442, 9, 9) @[primitives.scala 56:25] - node T_444 = bits(T_442, 8, 0) @[primitives.scala 57:26] - node T_445 = bits(T_444, 8, 8) @[primitives.scala 56:25] - node T_446 = bits(T_444, 7, 0) @[primitives.scala 57:26] - node T_447 = bits(T_446, 7, 7) @[primitives.scala 56:25] - node T_448 = bits(T_446, 6, 0) @[primitives.scala 57:26] - node T_449 = bits(T_448, 6, 6) @[primitives.scala 56:25] - node T_450 = bits(T_448, 5, 0) @[primitives.scala 57:26] - node T_453 = dshr(asSInt(UInt<65>("h010000000000000000")), T_450) @[primitives.scala 68:52] - node T_454 = bits(T_453, 63, 43) @[primitives.scala 69:26] - node T_455 = bits(T_454, 15, 0) @[Bitwise.scala 65:18] - node T_458 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_459 = xor(UInt<16>("h0ffff"), T_458) @[Bitwise.scala 58:21] - node T_460 = shr(T_455, 8) @[Bitwise.scala 59:21] - node T_461 = and(T_460, T_459) @[Bitwise.scala 59:31] - node T_462 = bits(T_455, 7, 0) @[Bitwise.scala 59:46] - node T_463 = shl(T_462, 8) @[Bitwise.scala 59:65] - node T_464 = not(T_459) @[Bitwise.scala 59:77] - node T_465 = and(T_463, T_464) @[Bitwise.scala 59:75] - node T_466 = or(T_461, T_465) @[Bitwise.scala 59:39] - node T_467 = bits(T_459, 11, 0) @[Bitwise.scala 58:28] - node T_468 = shl(T_467, 4) @[Bitwise.scala 58:47] - node T_469 = xor(T_459, T_468) @[Bitwise.scala 58:21] - node T_470 = shr(T_466, 4) @[Bitwise.scala 59:21] - node T_471 = and(T_470, T_469) @[Bitwise.scala 59:31] - node T_472 = bits(T_466, 11, 0) @[Bitwise.scala 59:46] - node T_473 = shl(T_472, 4) @[Bitwise.scala 59:65] - node T_474 = not(T_469) @[Bitwise.scala 59:77] - node T_475 = and(T_473, T_474) @[Bitwise.scala 59:75] - node T_476 = or(T_471, T_475) @[Bitwise.scala 59:39] - node T_477 = bits(T_469, 13, 0) @[Bitwise.scala 58:28] - node T_478 = shl(T_477, 2) @[Bitwise.scala 58:47] - node T_479 = xor(T_469, T_478) @[Bitwise.scala 58:21] - node T_480 = shr(T_476, 2) @[Bitwise.scala 59:21] - node T_481 = and(T_480, T_479) @[Bitwise.scala 59:31] - node T_482 = bits(T_476, 13, 0) @[Bitwise.scala 59:46] - node T_483 = shl(T_482, 2) @[Bitwise.scala 59:65] - node T_484 = not(T_479) @[Bitwise.scala 59:77] - node T_485 = and(T_483, T_484) @[Bitwise.scala 59:75] - node T_486 = or(T_481, T_485) @[Bitwise.scala 59:39] - node T_487 = bits(T_479, 14, 0) @[Bitwise.scala 58:28] - node T_488 = shl(T_487, 1) @[Bitwise.scala 58:47] - node T_489 = xor(T_479, T_488) @[Bitwise.scala 58:21] - node T_490 = shr(T_486, 1) @[Bitwise.scala 59:21] - node T_491 = and(T_490, T_489) @[Bitwise.scala 59:31] - node T_492 = bits(T_486, 14, 0) @[Bitwise.scala 59:46] - node T_493 = shl(T_492, 1) @[Bitwise.scala 59:65] - node T_494 = not(T_489) @[Bitwise.scala 59:77] - node T_495 = and(T_493, T_494) @[Bitwise.scala 59:75] - node T_496 = or(T_491, T_495) @[Bitwise.scala 59:39] - node T_497 = bits(T_454, 20, 16) @[Bitwise.scala 65:44] - node T_498 = bits(T_497, 3, 0) @[Bitwise.scala 65:18] - node T_499 = bits(T_498, 1, 0) @[Bitwise.scala 65:18] - node T_500 = bits(T_499, 0, 0) @[Bitwise.scala 65:18] - node T_501 = bits(T_499, 1, 1) @[Bitwise.scala 65:44] - node T_502 = cat(T_500, T_501) @[Cat.scala 20:58] - node T_503 = bits(T_498, 3, 2) @[Bitwise.scala 65:44] - node T_504 = bits(T_503, 0, 0) @[Bitwise.scala 65:18] - node T_505 = bits(T_503, 1, 1) @[Bitwise.scala 65:44] - node T_506 = cat(T_504, T_505) @[Cat.scala 20:58] - node T_507 = cat(T_502, T_506) @[Cat.scala 20:58] - node T_508 = bits(T_497, 4, 4) @[Bitwise.scala 65:44] - node T_509 = cat(T_507, T_508) @[Cat.scala 20:58] - node T_510 = cat(T_496, T_509) @[Cat.scala 20:58] - node T_511 = not(T_510) @[primitives.scala 65:36] - node T_512 = mux(T_449, UInt<1>("h00"), T_511) @[primitives.scala 65:21] - node T_513 = not(T_512) @[primitives.scala 65:17] - node T_515 = cat(T_513, UInt<4>("h0f")) @[Cat.scala 20:58] - node T_516 = bits(T_448, 6, 6) @[primitives.scala 56:25] - node T_517 = bits(T_448, 5, 0) @[primitives.scala 57:26] - node T_519 = dshr(asSInt(UInt<65>("h010000000000000000")), T_517) @[primitives.scala 68:52] - node T_520 = bits(T_519, 3, 0) @[primitives.scala 69:26] - node T_521 = bits(T_520, 1, 0) @[Bitwise.scala 65:18] - node T_522 = bits(T_521, 0, 0) @[Bitwise.scala 65:18] - node T_523 = bits(T_521, 1, 1) @[Bitwise.scala 65:44] - node T_524 = cat(T_522, T_523) @[Cat.scala 20:58] - node T_525 = bits(T_520, 3, 2) @[Bitwise.scala 65:44] - node T_526 = bits(T_525, 0, 0) @[Bitwise.scala 65:18] - node T_527 = bits(T_525, 1, 1) @[Bitwise.scala 65:44] - node T_528 = cat(T_526, T_527) @[Cat.scala 20:58] - node T_529 = cat(T_524, T_528) @[Cat.scala 20:58] - node T_531 = mux(T_516, T_529, UInt<1>("h00")) @[primitives.scala 59:20] - node T_532 = mux(T_447, T_515, T_531) @[primitives.scala 61:20] - node T_534 = mux(T_445, T_532, UInt<1>("h00")) @[primitives.scala 59:20] - node T_536 = mux(T_443, T_534, UInt<1>("h00")) @[primitives.scala 59:20] - node T_537 = bits(sigX3, 26, 26) @[MulAddRecFN.scala 450:26] - node T_538 = or(T_536, T_537) @[MulAddRecFN.scala 449:75] - node T_540 = cat(T_538, UInt<2>("h03")) @[Cat.scala 20:58] - node roundMask = or(T_441, T_540) @[MulAddRecFN.scala 448:50] - node T_541 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] - node T_542 = not(T_541) @[MulAddRecFN.scala 454:24] - node roundPosMask = and(T_542, roundMask) @[MulAddRecFN.scala 454:40] - node T_543 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] - node roundPosBit = neq(T_543, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] - node T_545 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] - node T_546 = and(sigX3, T_545) @[MulAddRecFN.scala 456:34] - node anyRoundExtra = neq(T_546, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] - node T_548 = not(sigX3) @[MulAddRecFN.scala 457:27] - node T_549 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] - node T_550 = and(T_548, T_549) @[MulAddRecFN.scala 457:34] - node allRoundExtra = eq(T_550, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] - node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] - node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] - node T_553 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] - node T_554 = and(T_553, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] - node T_555 = and(T_554, roundPosBit) @[MulAddRecFN.scala 462:51] - node T_556 = and(T_555, anyRoundExtra) @[MulAddRecFN.scala 463:60] - node T_558 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] - node T_559 = and(T_558, roundDirectUp) @[MulAddRecFN.scala 464:22] - node T_560 = and(T_559, anyRound) @[MulAddRecFN.scala 464:49] - node T_561 = or(T_556, T_560) @[MulAddRecFN.scala 463:78] - node T_562 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] - node T_563 = or(T_561, T_562) @[MulAddRecFN.scala 464:65] - node T_564 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] - node T_565 = and(T_564, roundPosBit) @[MulAddRecFN.scala 466:49] - node T_566 = or(T_563, T_565) @[MulAddRecFN.scala 465:65] - node T_567 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] - node T_569 = and(T_567, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] - node roundUp = or(T_566, T_569) @[MulAddRecFN.scala 466:65] - node T_571 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] - node T_572 = and(roundingMode_nearest_even, T_571) @[MulAddRecFN.scala 470:39] - node T_573 = and(T_572, allRoundExtra) @[MulAddRecFN.scala 470:56] - node T_574 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] - node T_576 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] - node T_577 = and(T_574, T_576) @[MulAddRecFN.scala 471:56] - node roundEven = mux(doIncrSig, T_573, T_577) @[MulAddRecFN.scala 469:12] - node T_579 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] - node roundInexact = mux(doIncrSig, T_579, anyRound) @[MulAddRecFN.scala 473:27] - node T_580 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] - node T_581 = shr(T_580, 2) @[MulAddRecFN.scala 475:30] - node T_583 = add(T_581, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] - node T_584 = tail(T_583, 1) @[MulAddRecFN.scala 475:35] - node roundUp_sigY3 = bits(T_584, 25, 0) @[MulAddRecFN.scala 475:45] - node T_586 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] - node T_588 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] - node T_589 = and(T_586, T_588) @[MulAddRecFN.scala 477:23] - node T_590 = not(roundMask) @[MulAddRecFN.scala 477:48] - node T_591 = and(sigX3, T_590) @[MulAddRecFN.scala 477:46] - node T_592 = shr(T_591, 2) @[MulAddRecFN.scala 477:59] - node T_594 = mux(T_589, T_592, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] - node T_596 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] - node T_597 = or(T_594, T_596) @[MulAddRecFN.scala 477:79] - node T_598 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] - node T_599 = not(T_598) @[MulAddRecFN.scala 479:53] - node T_600 = and(roundUp_sigY3, T_599) @[MulAddRecFN.scala 479:51] - node T_602 = mux(roundEven, T_600, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] - node sigY3 = or(T_597, T_602) @[MulAddRecFN.scala 478:79] - node T_603 = bits(sigY3, 25, 25) @[MulAddRecFN.scala 482:18] - node T_605 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] - node T_606 = tail(T_605, 1) @[MulAddRecFN.scala 482:41] - node T_608 = mux(T_603, T_606, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] - node T_609 = bits(sigY3, 24, 24) @[MulAddRecFN.scala 483:18] - node T_611 = mux(T_609, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] - node T_612 = or(T_608, T_611) @[MulAddRecFN.scala 482:61] - node T_613 = bits(sigY3, 25, 24) @[MulAddRecFN.scala 484:19] - node T_615 = eq(T_613, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] - node T_617 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] - node T_618 = tail(T_617, 1) @[MulAddRecFN.scala 485:20] - node T_620 = mux(T_615, T_618, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] - node sExpY = or(T_612, T_620) @[MulAddRecFN.scala 483:61] - node expY = bits(sExpY, 8, 0) @[MulAddRecFN.scala 488:21] - node T_621 = bits(sigY3, 22, 0) @[MulAddRecFN.scala 490:31] - node T_622 = bits(sigY3, 23, 1) @[MulAddRecFN.scala 490:55] - node fractY = mux(sigX3Shift1, T_621, T_622) @[MulAddRecFN.scala 490:12] - node T_623 = bits(sExpY, 9, 7) @[MulAddRecFN.scala 492:27] - node overflowY = eq(T_623, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] - node T_626 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] - node T_627 = bits(sExpY, 9, 9) @[MulAddRecFN.scala 496:19] - node T_628 = bits(sExpY, 8, 0) @[MulAddRecFN.scala 496:43] - node T_630 = lt(T_628, UInt<7>("h06b")) @[MulAddRecFN.scala 496:57] - node T_631 = or(T_627, T_630) @[MulAddRecFN.scala 496:34] - node totalUnderflowY = and(T_626, T_631) @[MulAddRecFN.scala 495:19] - node T_632 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 499:20] - node T_635 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) @[MulAddRecFN.scala 501:26] - node T_636 = leq(sExpX3_13, T_635) @[MulAddRecFN.scala 500:29] - node T_637 = or(T_632, T_636) @[MulAddRecFN.scala 499:35] - node underflowY = and(roundInexact, T_637) @[MulAddRecFN.scala 498:22] - node T_638 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] - node T_640 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] - node T_641 = and(roundingMode_max, T_640) @[MulAddRecFN.scala 506:58] - node roundMagUp = or(T_638, T_641) @[MulAddRecFN.scala 506:37] - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] - node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] - node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] - node T_643 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] - node T_645 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] - node commonCase = and(T_643, T_645) @[MulAddRecFN.scala 514:35] - node T_646 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] - node T_647 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] - node T_648 = or(T_646, T_647) @[MulAddRecFN.scala 517:29] - node T_650 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] - node T_652 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] - node T_653 = and(T_650, T_652) @[MulAddRecFN.scala 518:23] - node T_654 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] - node T_655 = and(T_653, T_654) @[MulAddRecFN.scala 518:35] - node T_656 = and(T_655, isInfC) @[MulAddRecFN.scala 518:57] - node T_657 = and(T_656, doSubMags) @[MulAddRecFN.scala 518:67] - node notSigNaN_invalid = or(T_648, T_657) @[MulAddRecFN.scala 517:52] - node T_658 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] - node T_659 = or(T_658, isSigNaNC) @[MulAddRecFN.scala 519:42] - node invalid = or(T_659, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] - node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] - node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] - node T_660 = and(commonCase, roundInexact) @[MulAddRecFN.scala 522:43] - node inexact = or(overflow, T_660) @[MulAddRecFN.scala 522:28] - node T_661 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] - node notSpecial_isZeroOut = or(T_661, totalUnderflowY) @[MulAddRecFN.scala 525:40] - node T_662 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] - node pegMinFiniteMagOut = and(T_662, roundMagUp) @[MulAddRecFN.scala 526:60] - node T_664 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] - node pegMaxFiniteMagOut = and(overflow, T_664) @[MulAddRecFN.scala 527:39] - node T_665 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] - node T_666 = or(T_665, isInfC) @[MulAddRecFN.scala 529:26] - node T_667 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] - node notNaN_isInfOut = or(T_666, T_667) @[MulAddRecFN.scala 529:36] - node T_668 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] - node T_669 = or(T_668, isNaNC) @[MulAddRecFN.scala 530:37] - node isNaNOut = or(T_669, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] - node T_671 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] - node T_672 = and(T_671, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] - node T_674 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] - node T_675 = and(mulSpecial, T_674) @[MulAddRecFN.scala 534:21] - node T_676 = and(T_675, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] - node T_677 = or(T_672, T_676) @[MulAddRecFN.scala 533:78] - node T_679 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] - node T_680 = and(T_679, isSpecialC) @[MulAddRecFN.scala 535:23] - node T_681 = and(T_680, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] - node T_682 = or(T_677, T_681) @[MulAddRecFN.scala 534:78] - node T_684 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] - node T_685 = and(T_684, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] - node T_686 = and(T_685, doSubMags) @[MulAddRecFN.scala 536:46] - node T_687 = and(T_686, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] - node uncommonCaseSignOut = or(T_682, T_687) @[MulAddRecFN.scala 535:78] - node T_689 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] - node T_690 = and(T_689, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] - node T_691 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] - node signOut = or(T_690, T_691) @[MulAddRecFN.scala 538:55] - node T_694 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 541:18] - node T_695 = not(T_694) @[MulAddRecFN.scala 541:14] - node T_696 = and(expY, T_695) @[MulAddRecFN.scala 540:15] - node T_698 = not(UInt<9>("h06b")) @[MulAddRecFN.scala 546:19] - node T_700 = mux(pegMinFiniteMagOut, T_698, UInt<9>("h00")) @[MulAddRecFN.scala 545:18] - node T_701 = not(T_700) @[MulAddRecFN.scala 545:14] - node T_702 = and(T_696, T_701) @[MulAddRecFN.scala 544:17] - node T_705 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) @[MulAddRecFN.scala 549:18] - node T_706 = not(T_705) @[MulAddRecFN.scala 549:14] - node T_707 = and(T_702, T_706) @[MulAddRecFN.scala 548:17] - node T_710 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) @[MulAddRecFN.scala 553:18] - node T_711 = not(T_710) @[MulAddRecFN.scala 553:14] - node T_712 = and(T_707, T_711) @[MulAddRecFN.scala 552:17] - node T_715 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) @[MulAddRecFN.scala 557:16] - node T_716 = or(T_712, T_715) @[MulAddRecFN.scala 556:18] - node T_719 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) @[MulAddRecFN.scala 558:16] - node T_720 = or(T_716, T_719) @[MulAddRecFN.scala 557:74] - node T_723 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) @[MulAddRecFN.scala 562:16] - node T_724 = or(T_720, T_723) @[MulAddRecFN.scala 561:15] - node T_727 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 566:16] - node expOut = or(T_724, T_727) @[MulAddRecFN.scala 565:15] - node T_728 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] - node T_729 = or(T_728, isNaNOut) @[MulAddRecFN.scala 568:45] - node T_731 = shl(UInt<1>("h01"), 22) @[MulAddRecFN.scala 569:34] - node T_733 = mux(isNaNOut, T_731, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] - node T_734 = mux(T_729, T_733, fractY) @[MulAddRecFN.scala 568:12] - node T_735 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 33:15] - node T_738 = mux(T_735, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 33:12] - node fractOut = or(T_734, T_738) @[MulAddRecFN.scala 571:11] - node T_739 = cat(signOut, expOut) @[Cat.scala 20:58] - node T_740 = cat(T_739, fractOut) @[Cat.scala 20:58] - io.out <= T_740 @[MulAddRecFN.scala 574:12] - node T_742 = cat(underflow, inexact) @[Cat.scala 20:58] - node T_743 = cat(invalid, UInt<1>("h00")) @[Cat.scala 20:58] - node T_744 = cat(T_743, overflow) @[Cat.scala 20:58] - node T_745 = cat(T_744, T_742) @[Cat.scala 20:58] - io.exceptionFlags <= T_745 @[MulAddRecFN.scala 575:23] - - module MulAddRecFN : + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h0")) + node T_38 = bits(io.fromPreMul.highExpA, 2, 1) + node isSpecialA = eq(T_38, UInt<2>("h3")) + node T_40 = bits(io.fromPreMul.highExpA, 0, 0) + node T_42 = eq(T_40, UInt<1>("h0")) + node isInfA = and(isSpecialA, T_42) + node T_43 = bits(io.fromPreMul.highExpA, 0, 0) + node isNaNA = and(isSpecialA, T_43) + node T_45 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h0")) + node isSigNaNA = and(isNaNA, T_45) + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h0")) + node T_47 = bits(io.fromPreMul.highExpB, 2, 1) + node isSpecialB = eq(T_47, UInt<2>("h3")) + node T_49 = bits(io.fromPreMul.highExpB, 0, 0) + node T_51 = eq(T_49, UInt<1>("h0")) + node isInfB = and(isSpecialB, T_51) + node T_52 = bits(io.fromPreMul.highExpB, 0, 0) + node isNaNB = and(isSpecialB, T_52) + node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h0")) + node isSigNaNB = and(isNaNB, T_54) + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h0")) + node T_56 = bits(io.fromPreMul.highExpC, 2, 1) + node isSpecialC = eq(T_56, UInt<2>("h3")) + node T_58 = bits(io.fromPreMul.highExpC, 0, 0) + node T_60 = eq(T_58, UInt<1>("h0")) + node isInfC = and(isSpecialC, T_60) + node T_61 = bits(io.fromPreMul.highExpC, 0, 0) + node isNaNC = and(isSpecialC, T_61) + node T_63 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h0")) + node isSigNaNC = and(isNaNC, T_63) + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h0")) + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h1")) + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h2")) + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h3")) + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h1"), UInt<1>("h0")) + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) + node T_70 = bits(io.mulAddResult, 48, 48) + node T_72 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h1")) + node T_73 = tail(T_72, 1) + node T_74 = mux(T_70, T_73, io.fromPreMul.highAlignedNegSigC) + node T_75 = bits(io.mulAddResult, 47, 0) + node T_76 = cat(T_74, T_75) + node sigSum = cat(T_76, io.fromPreMul.bit0AlignedNegSigC) + node T_78 = bits(sigSum, 50, 1) + node T_79 = xor(UInt<50>("h0"), T_78) + node T_80 = or(UInt<50>("h0"), T_78) + node T_81 = shl(T_80, 1) + node T_82 = xor(T_79, T_81) + node T_84 = bits(T_82, 49, 0) + node T_85 = bits(T_84, 49, 32) + node T_86 = bits(T_84, 31, 0) + node T_88 = neq(T_85, UInt<1>("h0")) + node T_89 = bits(T_85, 17, 16) + node T_90 = bits(T_85, 15, 0) + node T_92 = neq(T_89, UInt<1>("h0")) + node T_93 = bits(T_89, 1, 1) + node T_94 = bits(T_90, 15, 8) + node T_95 = bits(T_90, 7, 0) + node T_97 = neq(T_94, UInt<1>("h0")) + node T_98 = bits(T_94, 7, 4) + node T_99 = bits(T_94, 3, 0) + node T_101 = neq(T_98, UInt<1>("h0")) + node T_102 = bits(T_98, 3, 3) + node T_104 = bits(T_98, 2, 2) + node T_106 = bits(T_98, 1, 1) + node T_107 = shl(T_106, 0) + node T_108 = mux(T_104, UInt<2>("h2"), T_107) + node T_109 = mux(T_102, UInt<2>("h3"), T_108) + node T_110 = bits(T_99, 3, 3) + node T_112 = bits(T_99, 2, 2) + node T_114 = bits(T_99, 1, 1) + node T_115 = shl(T_114, 0) + node T_116 = mux(T_112, UInt<2>("h2"), T_115) + node T_117 = mux(T_110, UInt<2>("h3"), T_116) + node T_118 = mux(T_101, T_109, T_117) + node T_119 = cat(T_101, T_118) + node T_120 = bits(T_95, 7, 4) + node T_121 = bits(T_95, 3, 0) + node T_123 = neq(T_120, UInt<1>("h0")) + node T_124 = bits(T_120, 3, 3) + node T_126 = bits(T_120, 2, 2) + node T_128 = bits(T_120, 1, 1) + node T_129 = shl(T_128, 0) + node T_130 = mux(T_126, UInt<2>("h2"), T_129) + node T_131 = mux(T_124, UInt<2>("h3"), T_130) + node T_132 = bits(T_121, 3, 3) + node T_134 = bits(T_121, 2, 2) + node T_136 = bits(T_121, 1, 1) + node T_137 = shl(T_136, 0) + node T_138 = mux(T_134, UInt<2>("h2"), T_137) + node T_139 = mux(T_132, UInt<2>("h3"), T_138) + node T_140 = mux(T_123, T_131, T_139) + node T_141 = cat(T_123, T_140) + node T_142 = mux(T_97, T_119, T_141) + node T_143 = cat(T_97, T_142) + node T_144 = shl(T_93, 0) + node T_145 = mux(T_92, T_144, T_143) + node T_146 = cat(T_92, T_145) + node T_147 = bits(T_86, 31, 16) + node T_148 = bits(T_86, 15, 0) + node T_150 = neq(T_147, UInt<1>("h0")) + node T_151 = bits(T_147, 15, 8) + node T_152 = bits(T_147, 7, 0) + node T_154 = neq(T_151, UInt<1>("h0")) + node T_155 = bits(T_151, 7, 4) + node T_156 = bits(T_151, 3, 0) + node T_158 = neq(T_155, UInt<1>("h0")) + node T_159 = bits(T_155, 3, 3) + node T_161 = bits(T_155, 2, 2) + node T_163 = bits(T_155, 1, 1) + node T_164 = shl(T_163, 0) + node T_165 = mux(T_161, UInt<2>("h2"), T_164) + node T_166 = mux(T_159, UInt<2>("h3"), T_165) + node T_167 = bits(T_156, 3, 3) + node T_169 = bits(T_156, 2, 2) + node T_171 = bits(T_156, 1, 1) + node T_172 = shl(T_171, 0) + node T_173 = mux(T_169, UInt<2>("h2"), T_172) + node T_174 = mux(T_167, UInt<2>("h3"), T_173) + node T_175 = mux(T_158, T_166, T_174) + node T_176 = cat(T_158, T_175) + node T_177 = bits(T_152, 7, 4) + node T_178 = bits(T_152, 3, 0) + node T_180 = neq(T_177, UInt<1>("h0")) + node T_181 = bits(T_177, 3, 3) + node T_183 = bits(T_177, 2, 2) + node T_185 = bits(T_177, 1, 1) + node T_186 = shl(T_185, 0) + node T_187 = mux(T_183, UInt<2>("h2"), T_186) + node T_188 = mux(T_181, UInt<2>("h3"), T_187) + node T_189 = bits(T_178, 3, 3) + node T_191 = bits(T_178, 2, 2) + node T_193 = bits(T_178, 1, 1) + node T_194 = shl(T_193, 0) + node T_195 = mux(T_191, UInt<2>("h2"), T_194) + node T_196 = mux(T_189, UInt<2>("h3"), T_195) + node T_197 = mux(T_180, T_188, T_196) + node T_198 = cat(T_180, T_197) + node T_199 = mux(T_154, T_176, T_198) + node T_200 = cat(T_154, T_199) + node T_201 = bits(T_148, 15, 8) + node T_202 = bits(T_148, 7, 0) + node T_204 = neq(T_201, UInt<1>("h0")) + node T_205 = bits(T_201, 7, 4) + node T_206 = bits(T_201, 3, 0) + node T_208 = neq(T_205, UInt<1>("h0")) + node T_209 = bits(T_205, 3, 3) + node T_211 = bits(T_205, 2, 2) + node T_213 = bits(T_205, 1, 1) + node T_214 = shl(T_213, 0) + node T_215 = mux(T_211, UInt<2>("h2"), T_214) + node T_216 = mux(T_209, UInt<2>("h3"), T_215) + node T_217 = bits(T_206, 3, 3) + node T_219 = bits(T_206, 2, 2) + node T_221 = bits(T_206, 1, 1) + node T_222 = shl(T_221, 0) + node T_223 = mux(T_219, UInt<2>("h2"), T_222) + node T_224 = mux(T_217, UInt<2>("h3"), T_223) + node T_225 = mux(T_208, T_216, T_224) + node T_226 = cat(T_208, T_225) + node T_227 = bits(T_202, 7, 4) + node T_228 = bits(T_202, 3, 0) + node T_230 = neq(T_227, UInt<1>("h0")) + node T_231 = bits(T_227, 3, 3) + node T_233 = bits(T_227, 2, 2) + node T_235 = bits(T_227, 1, 1) + node T_236 = shl(T_235, 0) + node T_237 = mux(T_233, UInt<2>("h2"), T_236) + node T_238 = mux(T_231, UInt<2>("h3"), T_237) + node T_239 = bits(T_228, 3, 3) + node T_241 = bits(T_228, 2, 2) + node T_243 = bits(T_228, 1, 1) + node T_244 = shl(T_243, 0) + node T_245 = mux(T_241, UInt<2>("h2"), T_244) + node T_246 = mux(T_239, UInt<2>("h3"), T_245) + node T_247 = mux(T_230, T_238, T_246) + node T_248 = cat(T_230, T_247) + node T_249 = mux(T_204, T_226, T_248) + node T_250 = cat(T_204, T_249) + node T_251 = mux(T_150, T_200, T_250) + node T_252 = cat(T_150, T_251) + node T_253 = mux(T_88, T_146, T_252) + node T_254 = cat(T_88, T_253) + node T_255 = sub(UInt<7>("h49"), T_254) + node estNormPos_dist = tail(T_255, 1) + node T_256 = bits(sigSum, 33, 18) + node T_258 = neq(T_256, UInt<1>("h0")) + node T_259 = bits(sigSum, 17, 0) + node T_261 = neq(T_259, UInt<1>("h0")) + node firstReduceSigSum = cat(T_258, T_261) + node complSigSum = not(sigSum) + node T_262 = bits(complSigSum, 33, 18) + node T_264 = neq(T_262, UInt<1>("h0")) + node T_265 = bits(complSigSum, 17, 0) + node T_267 = neq(T_265, UInt<1>("h0")) + node firstReduceComplSigSum = cat(T_264, T_267) + node T_268 = or(io.fromPreMul.CAlignDist_0, doSubMags) + node T_270 = sub(io.fromPreMul.CAlignDist, UInt<1>("h1")) + node T_271 = tail(T_270, 1) + node T_272 = bits(T_271, 4, 0) + node CDom_estNormDist = mux(T_268, io.fromPreMul.CAlignDist, T_272) + node T_274 = eq(doSubMags, UInt<1>("h0")) + node T_275 = bits(CDom_estNormDist, 4, 4) + node T_277 = eq(T_275, UInt<1>("h0")) + node T_278 = and(T_274, T_277) + node T_279 = bits(sigSum, 74, 34) + node T_281 = neq(firstReduceSigSum, UInt<1>("h0")) + node T_282 = cat(T_279, T_281) + node T_284 = mux(T_278, T_282, UInt<1>("h0")) + node T_286 = eq(doSubMags, UInt<1>("h0")) + node T_287 = bits(CDom_estNormDist, 4, 4) + node T_288 = and(T_286, T_287) + node T_289 = bits(sigSum, 58, 18) + node T_290 = bits(firstReduceSigSum, 0, 0) + node T_291 = cat(T_289, T_290) + node T_293 = mux(T_288, T_291, UInt<1>("h0")) + node T_294 = or(T_284, T_293) + node T_295 = bits(CDom_estNormDist, 4, 4) + node T_297 = eq(T_295, UInt<1>("h0")) + node T_298 = and(doSubMags, T_297) + node T_299 = bits(complSigSum, 74, 34) + node T_301 = neq(firstReduceComplSigSum, UInt<1>("h0")) + node T_302 = cat(T_299, T_301) + node T_304 = mux(T_298, T_302, UInt<1>("h0")) + node T_305 = or(T_294, T_304) + node T_306 = bits(CDom_estNormDist, 4, 4) + node T_307 = and(doSubMags, T_306) + node T_308 = bits(complSigSum, 58, 18) + node T_309 = bits(firstReduceComplSigSum, 0, 0) + node T_310 = cat(T_308, T_309) + node T_312 = mux(T_307, T_310, UInt<1>("h0")) + node CDom_firstNormAbsSigSum = or(T_305, T_312) + node T_313 = bits(sigSum, 50, 18) + node T_314 = bits(firstReduceComplSigSum, 0, 0) + node T_316 = eq(T_314, UInt<1>("h0")) + node T_317 = bits(firstReduceSigSum, 0, 0) + node T_318 = mux(doSubMags, T_316, T_317) + node T_319 = cat(T_313, T_318) + node T_320 = bits(sigSum, 42, 1) + node T_321 = bits(estNormPos_dist, 5, 5) + node T_322 = bits(estNormPos_dist, 4, 4) + node T_323 = bits(sigSum, 26, 1) + node T_324 = bits(doSubMags, 0, 0) + node T_327 = mux(T_324, UInt<16>("hffff"), UInt<16>("h0")) + node T_328 = cat(T_323, T_327) + node T_329 = mux(T_322, T_328, T_320) + node T_330 = bits(estNormPos_dist, 4, 4) + node T_331 = bits(sigSum, 10, 1) + node T_332 = bits(doSubMags, 0, 0) + node T_335 = mux(T_332, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_336 = cat(T_331, T_335) + node T_337 = mux(T_330, T_319, T_336) + node notCDom_pos_firstNormAbsSigSum = mux(T_321, T_329, T_337) + node T_338 = bits(complSigSum, 49, 18) + node T_339 = bits(firstReduceComplSigSum, 0, 0) + node T_340 = cat(T_338, T_339) + node T_341 = bits(complSigSum, 42, 1) + node T_342 = bits(estNormPos_dist, 5, 5) + node T_343 = bits(estNormPos_dist, 4, 4) + node T_344 = bits(complSigSum, 27, 1) + node T_345 = shl(T_344, 16) + node T_346 = mux(T_343, T_345, T_341) + node T_347 = bits(estNormPos_dist, 4, 4) + node T_348 = bits(complSigSum, 11, 1) + node T_349 = shl(T_348, 32) + node T_350 = mux(T_347, T_340, T_349) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_342, T_346, T_350) + node notCDom_signSigSum = bits(sigSum, 51, 51) + node T_352 = eq(isZeroC, UInt<1>("h0")) + node T_353 = and(doSubMags, T_352) + node doNegSignSum = mux(io.fromPreMul.isCDominant, T_353, notCDom_signSigSum) + node T_354 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_354) + node T_355 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_356 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_355, T_356) + node T_358 = eq(io.fromPreMul.isCDominant, UInt<1>("h0")) + node T_360 = eq(notCDom_signSigSum, UInt<1>("h0")) + node T_361 = and(T_358, T_360) + node doIncrSig = and(T_361, doSubMags) + node estNormDist_5 = bits(estNormDist, 3, 0) + node normTo2ShiftDist = not(estNormDist_5) + node T_363 = dshr(asSInt(UInt<17>("h10000")), normTo2ShiftDist) + node T_364 = bits(T_363, 15, 1) + node T_365 = bits(T_364, 7, 0) + node T_368 = shl(UInt<4>("hf"), 4) + node T_369 = xor(UInt<8>("hff"), T_368) + node T_370 = shr(T_365, 4) + node T_371 = and(T_370, T_369) + node T_372 = bits(T_365, 3, 0) + node T_373 = shl(T_372, 4) + node T_374 = not(T_369) + node T_375 = and(T_373, T_374) + node T_376 = or(T_371, T_375) + node T_377 = bits(T_369, 5, 0) + node T_378 = shl(T_377, 2) + node T_379 = xor(T_369, T_378) + node T_380 = shr(T_376, 2) + node T_381 = and(T_380, T_379) + node T_382 = bits(T_376, 5, 0) + node T_383 = shl(T_382, 2) + node T_384 = not(T_379) + node T_385 = and(T_383, T_384) + node T_386 = or(T_381, T_385) + node T_387 = bits(T_379, 6, 0) + node T_388 = shl(T_387, 1) + node T_389 = xor(T_379, T_388) + node T_390 = shr(T_386, 1) + node T_391 = and(T_390, T_389) + node T_392 = bits(T_386, 6, 0) + node T_393 = shl(T_392, 1) + node T_394 = not(T_389) + node T_395 = and(T_393, T_394) + node T_396 = or(T_391, T_395) + node T_397 = bits(T_364, 14, 8) + node T_398 = bits(T_397, 3, 0) + node T_399 = bits(T_398, 1, 0) + node T_400 = bits(T_399, 0, 0) + node T_401 = bits(T_399, 1, 1) + node T_402 = cat(T_400, T_401) + node T_403 = bits(T_398, 3, 2) + node T_404 = bits(T_403, 0, 0) + node T_405 = bits(T_403, 1, 1) + node T_406 = cat(T_404, T_405) + node T_407 = cat(T_402, T_406) + node T_408 = bits(T_397, 6, 4) + node T_409 = bits(T_408, 1, 0) + node T_410 = bits(T_409, 0, 0) + node T_411 = bits(T_409, 1, 1) + node T_412 = cat(T_410, T_411) + node T_413 = bits(T_408, 2, 2) + node T_414 = cat(T_412, T_413) + node T_415 = cat(T_407, T_414) + node T_416 = cat(T_396, T_415) + node absSigSumExtraMask = cat(T_416, UInt<1>("h1")) + node T_418 = bits(cFirstNormAbsSigSum, 42, 1) + node T_419 = dshr(T_418, normTo2ShiftDist) + node T_420 = bits(cFirstNormAbsSigSum, 15, 0) + node T_421 = not(T_420) + node T_422 = and(T_421, absSigSumExtraMask) + node T_424 = eq(T_422, UInt<1>("h0")) + node T_425 = bits(cFirstNormAbsSigSum, 15, 0) + node T_426 = and(T_425, absSigSumExtraMask) + node T_428 = neq(T_426, UInt<1>("h0")) + node T_429 = mux(doIncrSig, T_424, T_428) + node T_430 = cat(T_419, T_429) + node sigX3 = bits(T_430, 27, 0) + node T_431 = bits(sigX3, 27, 26) + node sigX3Shift1 = eq(T_431, UInt<1>("h0")) + node T_433 = sub(io.fromPreMul.sExpSum, estNormDist) + node sExpX3 = tail(T_433, 1) + node T_434 = bits(sigX3, 27, 25) + node isZeroY = eq(T_434, UInt<1>("h0")) + node T_436 = xor(io.fromPreMul.signProd, doNegSignSum) + node signY = mux(isZeroY, signZeroNotEqOpSigns, T_436) + node sExpX3_13 = bits(sExpX3, 9, 0) + node T_437 = bits(sExpX3, 10, 10) + node T_438 = bits(T_437, 0, 0) + node T_441 = mux(T_438, UInt<27>("h7ffffff"), UInt<27>("h0")) + node T_442 = not(sExpX3_13) + node T_443 = bits(T_442, 9, 9) + node T_444 = bits(T_442, 8, 0) + node T_445 = bits(T_444, 8, 8) + node T_446 = bits(T_444, 7, 0) + node T_447 = bits(T_446, 7, 7) + node T_448 = bits(T_446, 6, 0) + node T_449 = bits(T_448, 6, 6) + node T_450 = bits(T_448, 5, 0) + node T_453 = dshr(asSInt(UInt<65>("h10000000000000000")), T_450) + node T_454 = bits(T_453, 63, 43) + node T_455 = bits(T_454, 15, 0) + node T_458 = shl(UInt<8>("hff"), 8) + node T_459 = xor(UInt<16>("hffff"), T_458) + node T_460 = shr(T_455, 8) + node T_461 = and(T_460, T_459) + node T_462 = bits(T_455, 7, 0) + node T_463 = shl(T_462, 8) + node T_464 = not(T_459) + node T_465 = and(T_463, T_464) + node T_466 = or(T_461, T_465) + node T_467 = bits(T_459, 11, 0) + node T_468 = shl(T_467, 4) + node T_469 = xor(T_459, T_468) + node T_470 = shr(T_466, 4) + node T_471 = and(T_470, T_469) + node T_472 = bits(T_466, 11, 0) + node T_473 = shl(T_472, 4) + node T_474 = not(T_469) + node T_475 = and(T_473, T_474) + node T_476 = or(T_471, T_475) + node T_477 = bits(T_469, 13, 0) + node T_478 = shl(T_477, 2) + node T_479 = xor(T_469, T_478) + node T_480 = shr(T_476, 2) + node T_481 = and(T_480, T_479) + node T_482 = bits(T_476, 13, 0) + node T_483 = shl(T_482, 2) + node T_484 = not(T_479) + node T_485 = and(T_483, T_484) + node T_486 = or(T_481, T_485) + node T_487 = bits(T_479, 14, 0) + node T_488 = shl(T_487, 1) + node T_489 = xor(T_479, T_488) + node T_490 = shr(T_486, 1) + node T_491 = and(T_490, T_489) + node T_492 = bits(T_486, 14, 0) + node T_493 = shl(T_492, 1) + node T_494 = not(T_489) + node T_495 = and(T_493, T_494) + node T_496 = or(T_491, T_495) + node T_497 = bits(T_454, 20, 16) + node T_498 = bits(T_497, 3, 0) + node T_499 = bits(T_498, 1, 0) + node T_500 = bits(T_499, 0, 0) + node T_501 = bits(T_499, 1, 1) + node T_502 = cat(T_500, T_501) + node T_503 = bits(T_498, 3, 2) + node T_504 = bits(T_503, 0, 0) + node T_505 = bits(T_503, 1, 1) + node T_506 = cat(T_504, T_505) + node T_507 = cat(T_502, T_506) + node T_508 = bits(T_497, 4, 4) + node T_509 = cat(T_507, T_508) + node T_510 = cat(T_496, T_509) + node T_511 = not(T_510) + node T_512 = mux(T_449, UInt<1>("h0"), T_511) + node T_513 = not(T_512) + node T_515 = cat(T_513, UInt<4>("hf")) + node T_516 = bits(T_448, 6, 6) + node T_517 = bits(T_448, 5, 0) + node T_519 = dshr(asSInt(UInt<65>("h10000000000000000")), T_517) + node T_520 = bits(T_519, 3, 0) + node T_521 = bits(T_520, 1, 0) + node T_522 = bits(T_521, 0, 0) + node T_523 = bits(T_521, 1, 1) + node T_524 = cat(T_522, T_523) + node T_525 = bits(T_520, 3, 2) + node T_526 = bits(T_525, 0, 0) + node T_527 = bits(T_525, 1, 1) + node T_528 = cat(T_526, T_527) + node T_529 = cat(T_524, T_528) + node T_531 = mux(T_516, T_529, UInt<1>("h0")) + node T_532 = mux(T_447, T_515, T_531) + node T_534 = mux(T_445, T_532, UInt<1>("h0")) + node T_536 = mux(T_443, T_534, UInt<1>("h0")) + node T_537 = bits(sigX3, 26, 26) + node T_538 = or(T_536, T_537) + node T_540 = cat(T_538, UInt<2>("h3")) + node roundMask = or(T_441, T_540) + node T_541 = shr(roundMask, 1) + node T_542 = not(T_541) + node roundPosMask = and(T_542, roundMask) + node T_543 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_543, UInt<1>("h0")) + node T_545 = shr(roundMask, 1) + node T_546 = and(sigX3, T_545) + node anyRoundExtra = neq(T_546, UInt<1>("h0")) + node T_548 = not(sigX3) + node T_549 = shr(roundMask, 1) + node T_550 = and(T_548, T_549) + node allRoundExtra = eq(T_550, UInt<1>("h0")) + node anyRound = or(roundPosBit, anyRoundExtra) + node allRound = and(roundPosBit, allRoundExtra) + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) + node T_553 = eq(doIncrSig, UInt<1>("h0")) + node T_554 = and(T_553, roundingMode_nearest_even) + node T_555 = and(T_554, roundPosBit) + node T_556 = and(T_555, anyRoundExtra) + node T_558 = eq(doIncrSig, UInt<1>("h0")) + node T_559 = and(T_558, roundDirectUp) + node T_560 = and(T_559, anyRound) + node T_561 = or(T_556, T_560) + node T_562 = and(doIncrSig, allRound) + node T_563 = or(T_561, T_562) + node T_564 = and(doIncrSig, roundingMode_nearest_even) + node T_565 = and(T_564, roundPosBit) + node T_566 = or(T_563, T_565) + node T_567 = and(doIncrSig, roundDirectUp) + node T_569 = and(T_567, UInt<1>("h1")) + node roundUp = or(T_566, T_569) + node T_571 = eq(roundPosBit, UInt<1>("h0")) + node T_572 = and(roundingMode_nearest_even, T_571) + node T_573 = and(T_572, allRoundExtra) + node T_574 = and(roundingMode_nearest_even, roundPosBit) + node T_576 = eq(anyRoundExtra, UInt<1>("h0")) + node T_577 = and(T_574, T_576) + node roundEven = mux(doIncrSig, T_573, T_577) + node T_579 = eq(allRound, UInt<1>("h0")) + node roundInexact = mux(doIncrSig, T_579, anyRound) + node T_580 = or(sigX3, roundMask) + node T_581 = shr(T_580, 2) + node T_583 = add(T_581, UInt<1>("h1")) + node T_584 = tail(T_583, 1) + node roundUp_sigY3 = bits(T_584, 25, 0) + node T_586 = eq(roundUp, UInt<1>("h0")) + node T_588 = eq(roundEven, UInt<1>("h0")) + node T_589 = and(T_586, T_588) + node T_590 = not(roundMask) + node T_591 = and(sigX3, T_590) + node T_592 = shr(T_591, 2) + node T_594 = mux(T_589, T_592, UInt<1>("h0")) + node T_596 = mux(roundUp, roundUp_sigY3, UInt<1>("h0")) + node T_597 = or(T_594, T_596) + node T_598 = shr(roundMask, 1) + node T_599 = not(T_598) + node T_600 = and(roundUp_sigY3, T_599) + node T_602 = mux(roundEven, T_600, UInt<1>("h0")) + node sigY3 = or(T_597, T_602) + node T_603 = bits(sigY3, 25, 25) + node T_605 = add(sExpX3, UInt<1>("h1")) + node T_606 = tail(T_605, 1) + node T_608 = mux(T_603, T_606, UInt<1>("h0")) + node T_609 = bits(sigY3, 24, 24) + node T_611 = mux(T_609, sExpX3, UInt<1>("h0")) + node T_612 = or(T_608, T_611) + node T_613 = bits(sigY3, 25, 24) + node T_615 = eq(T_613, UInt<1>("h0")) + node T_617 = sub(sExpX3, UInt<1>("h1")) + node T_618 = tail(T_617, 1) + node T_620 = mux(T_615, T_618, UInt<1>("h0")) + node sExpY = or(T_612, T_620) + node expY = bits(sExpY, 8, 0) + node T_621 = bits(sigY3, 22, 0) + node T_622 = bits(sigY3, 23, 1) + node fractY = mux(sigX3Shift1, T_621, T_622) + node T_623 = bits(sExpY, 9, 7) + node overflowY = eq(T_623, UInt<2>("h3")) + node T_626 = eq(isZeroY, UInt<1>("h0")) + node T_627 = bits(sExpY, 9, 9) + node T_628 = bits(sExpY, 8, 0) + node T_630 = lt(T_628, UInt<7>("h6b")) + node T_631 = or(T_627, T_630) + node totalUnderflowY = and(T_626, T_631) + node T_632 = bits(sExpX3, 10, 10) + node T_635 = mux(sigX3Shift1, UInt<8>("h82"), UInt<8>("h81")) + node T_636 = leq(sExpX3_13, T_635) + node T_637 = or(T_632, T_636) + node underflowY = and(roundInexact, T_637) + node T_638 = and(roundingMode_min, signY) + node T_640 = eq(signY, UInt<1>("h0")) + node T_641 = and(roundingMode_max, T_640) + node roundMagUp = or(T_638, T_641) + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) + node mulSpecial = or(isSpecialA, isSpecialB) + node addSpecial = or(mulSpecial, isSpecialC) + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) + node T_643 = eq(addSpecial, UInt<1>("h0")) + node T_645 = eq(notSpecial_addZeros, UInt<1>("h0")) + node commonCase = and(T_643, T_645) + node T_646 = and(isInfA, isZeroB) + node T_647 = and(isZeroA, isInfB) + node T_648 = or(T_646, T_647) + node T_650 = eq(isNaNA, UInt<1>("h0")) + node T_652 = eq(isNaNB, UInt<1>("h0")) + node T_653 = and(T_650, T_652) + node T_654 = or(isInfA, isInfB) + node T_655 = and(T_653, T_654) + node T_656 = and(T_655, isInfC) + node T_657 = and(T_656, doSubMags) + node notSigNaN_invalid = or(T_648, T_657) + node T_658 = or(isSigNaNA, isSigNaNB) + node T_659 = or(T_658, isSigNaNC) + node invalid = or(T_659, notSigNaN_invalid) + node overflow = and(commonCase, overflowY) + node underflow = and(commonCase, underflowY) + node T_660 = and(commonCase, roundInexact) + node inexact = or(overflow, T_660) + node T_661 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_661, totalUnderflowY) + node T_662 = and(commonCase, totalUnderflowY) + node pegMinFiniteMagOut = and(T_662, roundMagUp) + node T_664 = eq(overflowY_roundMagUp, UInt<1>("h0")) + node pegMaxFiniteMagOut = and(overflow, T_664) + node T_665 = or(isInfA, isInfB) + node T_666 = or(T_665, isInfC) + node T_667 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_666, T_667) + node T_668 = or(isNaNA, isNaNB) + node T_669 = or(T_668, isNaNC) + node isNaNOut = or(T_669, notSigNaN_invalid) + node T_671 = eq(doSubMags, UInt<1>("h0")) + node T_672 = and(T_671, io.fromPreMul.opSignC) + node T_674 = eq(isSpecialC, UInt<1>("h0")) + node T_675 = and(mulSpecial, T_674) + node T_676 = and(T_675, io.fromPreMul.signProd) + node T_677 = or(T_672, T_676) + node T_679 = eq(mulSpecial, UInt<1>("h0")) + node T_680 = and(T_679, isSpecialC) + node T_681 = and(T_680, io.fromPreMul.opSignC) + node T_682 = or(T_677, T_681) + node T_684 = eq(mulSpecial, UInt<1>("h0")) + node T_685 = and(T_684, notSpecial_addZeros) + node T_686 = and(T_685, doSubMags) + node T_687 = and(T_686, signZeroNotEqOpSigns) + node uncommonCaseSignOut = or(T_682, T_687) + node T_689 = eq(isNaNOut, UInt<1>("h0")) + node T_690 = and(T_689, uncommonCaseSignOut) + node T_691 = and(commonCase, signY) + node signOut = or(T_690, T_691) + node T_694 = mux(notSpecial_isZeroOut, UInt<9>("h1c0"), UInt<9>("h0")) + node T_695 = not(T_694) + node T_696 = and(expY, T_695) + node T_698 = not(UInt<9>("h6b")) + node T_700 = mux(pegMinFiniteMagOut, T_698, UInt<9>("h0")) + node T_701 = not(T_700) + node T_702 = and(T_696, T_701) + node T_705 = mux(pegMaxFiniteMagOut, UInt<9>("h80"), UInt<9>("h0")) + node T_706 = not(T_705) + node T_707 = and(T_702, T_706) + node T_710 = mux(notNaN_isInfOut, UInt<7>("h40"), UInt<9>("h0")) + node T_711 = not(T_710) + node T_712 = and(T_707, T_711) + node T_715 = mux(pegMinFiniteMagOut, UInt<7>("h6b"), UInt<9>("h0")) + node T_716 = or(T_712, T_715) + node T_719 = mux(pegMaxFiniteMagOut, UInt<9>("h17f"), UInt<9>("h0")) + node T_720 = or(T_716, T_719) + node T_723 = mux(notNaN_isInfOut, UInt<9>("h180"), UInt<9>("h0")) + node T_724 = or(T_720, T_723) + node T_727 = mux(isNaNOut, UInt<9>("h1c0"), UInt<9>("h0")) + node expOut = or(T_724, T_727) + node T_728 = and(totalUnderflowY, roundMagUp) + node T_729 = or(T_728, isNaNOut) + node T_731 = shl(UInt<1>("h1"), 22) + node T_733 = mux(isNaNOut, T_731, UInt<1>("h0")) + node T_734 = mux(T_729, T_733, fractY) + node T_735 = bits(pegMaxFiniteMagOut, 0, 0) + node T_738 = mux(T_735, UInt<23>("h7fffff"), UInt<23>("h0")) + node fractOut = or(T_734, T_738) + node T_739 = cat(signOut, expOut) + node T_740 = cat(T_739, fractOut) + io.out <= T_740 + node T_742 = cat(underflow, inexact) + node T_743 = cat(invalid, UInt<1>("h0")) + node T_744 = cat(T_743, overflow) + node T_745 = cat(T_744, T_742) + io.exceptionFlags <= T_745 + + module MulAddRecFN : input clk : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul @[MulAddRecFN.scala 598:15] + inst mulAddRecFN_preMul of MulAddRecFN_preMul mulAddRecFN_preMul.io is invalid mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul @[MulAddRecFN.scala 600:15] + inst mulAddRecFN_postMul of MulAddRecFN_postMul mulAddRecFN_postMul.io is invalid mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] - mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] - mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] - mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] - node T_7 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] - node T_9 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 20:58] - node T_10 = add(T_7, T_9) @[MulAddRecFN.scala 610:71] - node T_11 = tail(T_10, 1) @[MulAddRecFN.scala 610:71] - mulAddRecFN_postMul.io.mulAddResult <= T_11 @[MulAddRecFN.scala 609:41] - io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] - - module FPUFMAPipe : + mulAddRecFN_preMul.io.op <= io.op + mulAddRecFN_preMul.io.a <= io.a + mulAddRecFN_preMul.io.b <= io.b + mulAddRecFN_preMul.io.c <= io.c + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul + node T_7 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) + node T_9 = cat(UInt<1>("h0"), mulAddRecFN_preMul.io.mulAddC) + node T_10 = add(T_7, T_9) + node T_11 = tail(T_10, 1) + mulAddRecFN_postMul.io.mulAddResult <= T_11 + io.out <= mulAddRecFN_postMul.io.out + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags + + module FPUFMAPipe : input clk : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - + output io : { flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} + io is invalid - node one = shl(UInt<1>("h01"), 31) @[fpu.scala 462:21] - node T_131 = bits(io.in.bits.in1, 32, 32) @[fpu.scala 463:29] - node T_132 = bits(io.in.bits.in2, 32, 32) @[fpu.scala 463:53] - node T_133 = xor(T_131, T_132) @[fpu.scala 463:37] - node zero = shl(T_133, 32) @[fpu.scala 463:62] - reg valid : UInt<1>, clk + node one = shl(UInt<1>("h1"), 31) + node T_131 = bits(io.in.bits.in1, 32, 32) + node T_132 = bits(io.in.bits.in2, 32, 32) + node T_133 = xor(T_131, T_132) + node zero = shl(T_133, 32) + reg valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), valid) valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : @[fpu.scala 467:22] - in <- io.in.bits @[fpu.scala 468:8] - node T_179 = bits(io.in.bits.cmd, 1, 1) @[fpu.scala 471:33] - node T_180 = or(io.in.bits.ren3, io.in.bits.swap23) @[fpu.scala 471:48] - node T_181 = and(T_179, T_180) @[fpu.scala 471:37] - node T_182 = bits(io.in.bits.cmd, 0, 0) @[fpu.scala 471:78] - node T_183 = cat(T_181, T_182) @[Cat.scala 20:58] - in.cmd <= T_183 @[fpu.scala 471:12] - when io.in.bits.swap23 : @[fpu.scala 472:23] - in.in2 <= one @[fpu.scala 472:32] - skip @[fpu.scala 472:23] - node T_184 = or(io.in.bits.ren3, io.in.bits.swap23) @[fpu.scala 473:21] - node T_186 = eq(T_184, UInt<1>("h00")) @[Conditional.scala 18:11] - when T_186 : @[Conditional.scala 18:15] - in.in3 <= zero @[fpu.scala 473:45] - skip @[Conditional.scala 18:15] - skip @[fpu.scala 467:22] - inst fma of MulAddRecFN @[fpu.scala 476:19] + reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : + reset => (UInt<1>("h0"), in) + when io.in.valid : + in <- io.in.bits + node T_179 = bits(io.in.bits.cmd, 1, 1) + node T_180 = or(io.in.bits.ren3, io.in.bits.swap23) + node T_181 = and(T_179, T_180) + node T_182 = bits(io.in.bits.cmd, 0, 0) + node T_183 = cat(T_181, T_182) + in.cmd <= T_183 + when io.in.bits.swap23 : + in.in2 <= one + node T_184 = or(io.in.bits.ren3, io.in.bits.swap23) + node T_186 = eq(T_184, UInt<1>("h0")) + when T_186 : + in.in3 <= zero + inst fma of MulAddRecFN fma.io is invalid fma.clk <= clk fma.reset <= reset - fma.io.op <= in.cmd @[fpu.scala 477:13] - fma.io.roundingMode <= in.rm @[fpu.scala 478:23] - fma.io.a <= in.in1 @[fpu.scala 479:12] - fma.io.b <= in.in2 @[fpu.scala 480:12] - fma.io.c <= in.in3 @[fpu.scala 481:12] - wire res : {data : UInt<65>, exc : UInt<5>} @[fpu.scala 483:17] - res is invalid @[fpu.scala 483:17] - node T_193 = cat(UInt<32>("h0ffffffff"), fma.io.out) @[Cat.scala 20:58] - res.data <= T_193 @[fpu.scala 484:12] - res.exc <= fma.io.exceptionFlags @[fpu.scala 485:11] - reg T_196 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + fma.io.op <= in.cmd + fma.io.roundingMode <= in.rm + fma.io.a <= in.in1 + fma.io.b <= in.in2 + fma.io.c <= in.in3 + wire res : { data : UInt<65>, exc : UInt<5>} + res is invalid + node T_193 = cat(UInt<32>("hffffffff"), fma.io.out) + res.data <= T_193 + res.exc <= fma.io.exceptionFlags + reg T_196 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_196 <= valid - reg T_197 : {data : UInt<65>, exc : UInt<5>}, clk - when valid : @[Reg.scala 29:19] - T_197 <- res @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg T_202 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_197 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_197) + when valid : + T_197 <- res + reg T_202 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_202 <= T_196 - reg T_203 : {data : UInt<65>, exc : UInt<5>}, clk - when T_196 : @[Reg.scala 29:19] - T_203 <- T_197 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire T_214 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 39:21] - T_214 is invalid @[Valid.scala 39:21] - T_214.valid <= T_202 @[Valid.scala 40:17] - T_214.bits <- T_203 @[Valid.scala 41:16] - io.out <- T_214 @[fpu.scala 486:10] - - module CompareRecFN : + reg T_203 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_203) + when T_196 : + T_203 <- T_197 + wire T_214 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} + T_214 is invalid + T_214.valid <= T_202 + T_214.bits <- T_203 + io.out <- T_214 + + module CompareRecFN : input clk : Clock input reset : UInt<1> - output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} - + output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} + io is invalid - node T_7 = bits(io.a, 63, 52) @[rawFNFromRecFN.scala 50:21] - node T_8 = bits(T_7, 11, 9) @[rawFNFromRecFN.scala 51:29] - node T_10 = eq(T_8, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] - node T_11 = bits(T_7, 11, 10) @[rawFNFromRecFN.scala 52:29] - node T_13 = eq(T_11, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] - wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] - rawA is invalid @[rawFNFromRecFN.scala 54:23] - node T_27 = bits(io.a, 64, 64) @[rawFNFromRecFN.scala 55:23] - rawA.sign <= T_27 @[rawFNFromRecFN.scala 55:18] - node T_28 = bits(T_7, 9, 9) @[rawFNFromRecFN.scala 56:40] - node T_29 = and(T_13, T_28) @[rawFNFromRecFN.scala 56:32] - rawA.isNaN <= T_29 @[rawFNFromRecFN.scala 56:19] - node T_30 = bits(T_7, 9, 9) @[rawFNFromRecFN.scala 57:40] - node T_32 = eq(T_30, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] - node T_33 = and(T_13, T_32) @[rawFNFromRecFN.scala 57:32] - rawA.isInf <= T_33 @[rawFNFromRecFN.scala 57:19] - rawA.isZero <= T_10 @[rawFNFromRecFN.scala 58:20] - node T_34 = cvt(T_7) @[rawFNFromRecFN.scala 59:25] - rawA.sExp <= T_34 @[rawFNFromRecFN.scala 59:18] - node T_37 = eq(T_10, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] - node T_38 = bits(io.a, 51, 0) @[rawFNFromRecFN.scala 60:48] - node T_40 = cat(T_38, UInt<2>("h00")) @[Cat.scala 20:58] - node T_41 = cat(UInt<1>("h00"), T_37) @[Cat.scala 20:58] - node T_42 = cat(T_41, T_40) @[Cat.scala 20:58] - rawA.sig <= T_42 @[rawFNFromRecFN.scala 60:17] - node T_43 = bits(io.b, 63, 52) @[rawFNFromRecFN.scala 50:21] - node T_44 = bits(T_43, 11, 9) @[rawFNFromRecFN.scala 51:29] - node T_46 = eq(T_44, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] - node T_47 = bits(T_43, 11, 10) @[rawFNFromRecFN.scala 52:29] - node T_49 = eq(T_47, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] - wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] - rawB is invalid @[rawFNFromRecFN.scala 54:23] - node T_63 = bits(io.b, 64, 64) @[rawFNFromRecFN.scala 55:23] - rawB.sign <= T_63 @[rawFNFromRecFN.scala 55:18] - node T_64 = bits(T_43, 9, 9) @[rawFNFromRecFN.scala 56:40] - node T_65 = and(T_49, T_64) @[rawFNFromRecFN.scala 56:32] - rawB.isNaN <= T_65 @[rawFNFromRecFN.scala 56:19] - node T_66 = bits(T_43, 9, 9) @[rawFNFromRecFN.scala 57:40] - node T_68 = eq(T_66, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] - node T_69 = and(T_49, T_68) @[rawFNFromRecFN.scala 57:32] - rawB.isInf <= T_69 @[rawFNFromRecFN.scala 57:19] - rawB.isZero <= T_46 @[rawFNFromRecFN.scala 58:20] - node T_70 = cvt(T_43) @[rawFNFromRecFN.scala 59:25] - rawB.sExp <= T_70 @[rawFNFromRecFN.scala 59:18] - node T_73 = eq(T_46, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] - node T_74 = bits(io.b, 51, 0) @[rawFNFromRecFN.scala 60:48] - node T_76 = cat(T_74, UInt<2>("h00")) @[Cat.scala 20:58] - node T_77 = cat(UInt<1>("h00"), T_73) @[Cat.scala 20:58] - node T_78 = cat(T_77, T_76) @[Cat.scala 20:58] - rawB.sig <= T_78 @[rawFNFromRecFN.scala 60:17] - node T_80 = eq(rawA.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:19] - node T_82 = eq(rawB.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:35] - node ordered = and(T_80, T_82) @[CompareRecFN.scala 57:32] - node bothInfs = and(rawA.isInf, rawB.isInf) @[CompareRecFN.scala 58:33] - node bothZeros = and(rawA.isZero, rawB.isZero) @[CompareRecFN.scala 59:33] - node eqExps = eq(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 60:29] - node T_83 = lt(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 62:20] - node T_84 = lt(rawA.sig, rawB.sig) @[CompareRecFN.scala 62:57] - node T_85 = and(eqExps, T_84) @[CompareRecFN.scala 62:44] - node common_ltMags = or(T_83, T_85) @[CompareRecFN.scala 62:33] - node T_86 = eq(rawA.sig, rawB.sig) @[CompareRecFN.scala 63:45] - node common_eqMags = and(eqExps, T_86) @[CompareRecFN.scala 63:32] - node T_88 = eq(bothZeros, UInt<1>("h00")) @[CompareRecFN.scala 66:9] - node T_90 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 67:28] - node T_91 = and(rawA.sign, T_90) @[CompareRecFN.scala 67:25] - node T_93 = eq(bothInfs, UInt<1>("h00")) @[CompareRecFN.scala 68:19] - node T_95 = eq(common_ltMags, UInt<1>("h00")) @[CompareRecFN.scala 69:38] - node T_96 = and(rawA.sign, T_95) @[CompareRecFN.scala 69:35] - node T_98 = eq(common_eqMags, UInt<1>("h00")) @[CompareRecFN.scala 69:57] - node T_99 = and(T_96, T_98) @[CompareRecFN.scala 69:54] - node T_101 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 70:29] - node T_102 = and(T_101, common_ltMags) @[CompareRecFN.scala 70:41] - node T_103 = or(T_99, T_102) @[CompareRecFN.scala 69:74] - node T_104 = and(T_93, T_103) @[CompareRecFN.scala 68:30] - node T_105 = or(T_91, T_104) @[CompareRecFN.scala 67:41] - node ordered_lt = and(T_88, T_105) @[CompareRecFN.scala 66:21] - node T_106 = eq(rawA.sign, rawB.sign) @[CompareRecFN.scala 72:34] - node T_107 = or(bothInfs, common_eqMags) @[CompareRecFN.scala 72:62] - node T_108 = and(T_106, T_107) @[CompareRecFN.scala 72:49] - node ordered_eq = or(bothZeros, T_108) @[CompareRecFN.scala 72:19] - node T_109 = bits(rawA.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] - node T_111 = eq(T_109, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] - node T_112 = and(rawA.isNaN, T_111) @[RoundRawFNToRecFN.scala 61:46] - node T_113 = bits(rawB.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] - node T_115 = eq(T_113, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] - node T_116 = and(rawB.isNaN, T_115) @[RoundRawFNToRecFN.scala 61:46] - node T_117 = or(T_112, T_116) @[CompareRecFN.scala 75:29] - node T_119 = eq(ordered, UInt<1>("h00")) @[CompareRecFN.scala 76:30] - node T_120 = and(io.signaling, T_119) @[CompareRecFN.scala 76:27] - node invalid = or(T_117, T_120) @[CompareRecFN.scala 75:52] - node T_121 = and(ordered, ordered_lt) @[CompareRecFN.scala 78:22] - io.lt <= T_121 @[CompareRecFN.scala 78:11] - node T_122 = and(ordered, ordered_eq) @[CompareRecFN.scala 79:22] - io.eq <= T_122 @[CompareRecFN.scala 79:11] - node T_124 = eq(ordered_lt, UInt<1>("h00")) @[CompareRecFN.scala 80:25] - node T_125 = and(ordered, T_124) @[CompareRecFN.scala 80:22] - node T_127 = eq(ordered_eq, UInt<1>("h00")) @[CompareRecFN.scala 80:41] - node T_128 = and(T_125, T_127) @[CompareRecFN.scala 80:38] - io.gt <= T_128 @[CompareRecFN.scala 80:11] - node T_130 = cat(invalid, UInt<4>("h00")) @[Cat.scala 20:58] - io.exceptionFlags <= T_130 @[CompareRecFN.scala 82:23] - - module RecFNToIN : + node T_7 = bits(io.a, 63, 52) + node T_8 = bits(T_7, 11, 9) + node T_10 = eq(T_8, UInt<1>("h0")) + node T_11 = bits(T_7, 11, 10) + node T_13 = eq(T_11, UInt<2>("h3")) + wire rawA : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} + rawA is invalid + node T_27 = bits(io.a, 64, 64) + rawA.sign <= T_27 + node T_28 = bits(T_7, 9, 9) + node T_29 = and(T_13, T_28) + rawA.isNaN <= T_29 + node T_30 = bits(T_7, 9, 9) + node T_32 = eq(T_30, UInt<1>("h0")) + node T_33 = and(T_13, T_32) + rawA.isInf <= T_33 + rawA.isZero <= T_10 + node T_34 = cvt(T_7) + rawA.sExp <= T_34 + node T_37 = eq(T_10, UInt<1>("h0")) + node T_38 = bits(io.a, 51, 0) + node T_40 = cat(T_38, UInt<2>("h0")) + node T_41 = cat(UInt<1>("h0"), T_37) + node T_42 = cat(T_41, T_40) + rawA.sig <= T_42 + node T_43 = bits(io.b, 63, 52) + node T_44 = bits(T_43, 11, 9) + node T_46 = eq(T_44, UInt<1>("h0")) + node T_47 = bits(T_43, 11, 10) + node T_49 = eq(T_47, UInt<2>("h3")) + wire rawB : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} + rawB is invalid + node T_63 = bits(io.b, 64, 64) + rawB.sign <= T_63 + node T_64 = bits(T_43, 9, 9) + node T_65 = and(T_49, T_64) + rawB.isNaN <= T_65 + node T_66 = bits(T_43, 9, 9) + node T_68 = eq(T_66, UInt<1>("h0")) + node T_69 = and(T_49, T_68) + rawB.isInf <= T_69 + rawB.isZero <= T_46 + node T_70 = cvt(T_43) + rawB.sExp <= T_70 + node T_73 = eq(T_46, UInt<1>("h0")) + node T_74 = bits(io.b, 51, 0) + node T_76 = cat(T_74, UInt<2>("h0")) + node T_77 = cat(UInt<1>("h0"), T_73) + node T_78 = cat(T_77, T_76) + rawB.sig <= T_78 + node T_80 = eq(rawA.isNaN, UInt<1>("h0")) + node T_82 = eq(rawB.isNaN, UInt<1>("h0")) + node ordered = and(T_80, T_82) + node bothInfs = and(rawA.isInf, rawB.isInf) + node bothZeros = and(rawA.isZero, rawB.isZero) + node eqExps = eq(rawA.sExp, rawB.sExp) + node T_83 = lt(rawA.sExp, rawB.sExp) + node T_84 = lt(rawA.sig, rawB.sig) + node T_85 = and(eqExps, T_84) + node common_ltMags = or(T_83, T_85) + node T_86 = eq(rawA.sig, rawB.sig) + node common_eqMags = and(eqExps, T_86) + node T_88 = eq(bothZeros, UInt<1>("h0")) + node T_90 = eq(rawB.sign, UInt<1>("h0")) + node T_91 = and(rawA.sign, T_90) + node T_93 = eq(bothInfs, UInt<1>("h0")) + node T_95 = eq(common_ltMags, UInt<1>("h0")) + node T_96 = and(rawA.sign, T_95) + node T_98 = eq(common_eqMags, UInt<1>("h0")) + node T_99 = and(T_96, T_98) + node T_101 = eq(rawB.sign, UInt<1>("h0")) + node T_102 = and(T_101, common_ltMags) + node T_103 = or(T_99, T_102) + node T_104 = and(T_93, T_103) + node T_105 = or(T_91, T_104) + node ordered_lt = and(T_88, T_105) + node T_106 = eq(rawA.sign, rawB.sign) + node T_107 = or(bothInfs, common_eqMags) + node T_108 = and(T_106, T_107) + node ordered_eq = or(bothZeros, T_108) + node T_109 = bits(rawA.sig, 53, 53) + node T_111 = eq(T_109, UInt<1>("h0")) + node T_112 = and(rawA.isNaN, T_111) + node T_113 = bits(rawB.sig, 53, 53) + node T_115 = eq(T_113, UInt<1>("h0")) + node T_116 = and(rawB.isNaN, T_115) + node T_117 = or(T_112, T_116) + node T_119 = eq(ordered, UInt<1>("h0")) + node T_120 = and(io.signaling, T_119) + node invalid = or(T_117, T_120) + node T_121 = and(ordered, ordered_lt) + io.lt <= T_121 + node T_122 = and(ordered, ordered_eq) + io.eq <= T_122 + node T_124 = eq(ordered_lt, UInt<1>("h0")) + node T_125 = and(ordered, T_124) + node T_127 = eq(ordered_eq, UInt<1>("h0")) + node T_128 = and(T_125, T_127) + io.gt <= T_128 + node T_130 = cat(invalid, UInt<4>("h0")) + io.exceptionFlags <= T_130 + + module RecFNToIN : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} - + output io : { flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} + io is invalid - node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] - node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] - node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] - node T_5 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] - node isZero = eq(T_5, UInt<1>("h00")) @[RecFNToIN.scala 58:47] - node T_7 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] - node isSpecial = eq(T_7, UInt<2>("h03")) @[RecFNToIN.scala 59:50] - node T_9 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] - node isNaN = and(isSpecial, T_9) @[RecFNToIN.scala 60:27] - node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] - node T_10 = cat(notSpecial_magGeOne, fract) @[Cat.scala 20:58] - node T_11 = bits(exp, 4, 0) @[RecFNToIN.scala 74:20] - node T_13 = mux(notSpecial_magGeOne, T_11, UInt<1>("h00")) @[RecFNToIN.scala 73:16] - node shiftedSig = dshl(T_10, T_13) @[RecFNToIN.scala 72:40] - node unroundedInt = bits(shiftedSig, 83, 52) @[RecFNToIN.scala 82:24] - node T_14 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] - node T_15 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] - node T_17 = neq(T_15, UInt<1>("h00")) @[RecFNToIN.scala 86:41] - node roundBits = cat(T_14, T_17) @[Cat.scala 20:58] - node T_18 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] - node T_20 = neq(T_18, UInt<1>("h00")) @[RecFNToIN.scala 88:65] - node T_22 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] - node roundInexact = mux(notSpecial_magGeOne, T_20, T_22) @[RecFNToIN.scala 88:27] - node T_23 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] - node T_24 = not(T_23) @[RecFNToIN.scala 91:29] - node T_26 = eq(T_24, UInt<1>("h00")) @[RecFNToIN.scala 91:29] - node T_27 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] - node T_28 = not(T_27) @[RecFNToIN.scala 91:53] - node T_30 = eq(T_28, UInt<1>("h00")) @[RecFNToIN.scala 91:53] - node T_31 = or(T_26, T_30) @[RecFNToIN.scala 91:34] - node T_32 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] - node T_33 = not(T_32) @[RecFNToIN.scala 92:38] - node T_35 = eq(T_33, UInt<1>("h00")) @[RecFNToIN.scala 92:38] - node T_36 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] - node T_38 = neq(T_36, UInt<1>("h00")) @[RecFNToIN.scala 92:60] - node T_40 = mux(T_35, T_38, UInt<1>("h00")) @[RecFNToIN.scala 92:16] - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_31, T_40) @[RecFNToIN.scala 90:12] - node T_41 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] - node T_42 = and(T_41, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] - node T_43 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] - node T_44 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] - node T_45 = and(T_43, T_44) @[RecFNToIN.scala 96:49] - node T_46 = or(T_42, T_45) @[RecFNToIN.scala 95:78] - node T_47 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] - node T_49 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] - node T_50 = and(T_49, roundInexact) @[RecFNToIN.scala 97:60] - node T_51 = and(T_47, T_50) @[RecFNToIN.scala 97:49] - node roundIncr = or(T_46, T_51) @[RecFNToIN.scala 96:78] - node T_52 = not(unroundedInt) @[RecFNToIN.scala 98:39] - node complUnroundedInt = mux(sign, T_52, unroundedInt) @[RecFNToIN.scala 98:32] - node T_53 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] - node T_55 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] - node T_56 = tail(T_55, 1) @[RecFNToIN.scala 100:49] - node roundedInt = mux(T_53, T_56, complUnroundedInt) @[RecFNToIN.scala 100:12] - node T_57 = bits(unroundedInt, 29, 0) @[RecFNToIN.scala 103:38] - node T_58 = not(T_57) @[RecFNToIN.scala 103:56] - node T_60 = eq(T_58, UInt<1>("h00")) @[RecFNToIN.scala 103:56] - node roundCarryBut2 = and(T_60, roundIncr) @[RecFNToIN.scala 103:61] - node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] - node T_62 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 108:21] - node T_64 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 109:26] - node T_66 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] - node T_67 = bits(unroundedInt, 30, 0) @[RecFNToIN.scala 110:45] - node T_69 = neq(T_67, UInt<1>("h00")) @[RecFNToIN.scala 110:63] - node T_70 = or(T_66, T_69) @[RecFNToIN.scala 110:30] - node T_71 = or(T_70, roundIncr) @[RecFNToIN.scala 111:27] - node T_72 = and(T_64, T_71) @[RecFNToIN.scala 109:50] - node T_73 = or(T_62, T_72) @[RecFNToIN.scala 108:40] - node T_75 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] - node T_77 = eq(posExp, UInt<5>("h01e")) @[RecFNToIN.scala 112:36] - node T_78 = and(T_75, T_77) @[RecFNToIN.scala 112:25] - node T_79 = and(T_78, roundCarryBut2) @[RecFNToIN.scala 112:60] - node T_80 = or(T_73, T_79) @[RecFNToIN.scala 111:42] - node overflow_signed = mux(notSpecial_magGeOne, T_80, UInt<1>("h00")) @[RecFNToIN.scala 107:12] - node T_83 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 117:29] - node T_84 = or(sign, T_83) @[RecFNToIN.scala 117:18] - node T_86 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 118:26] - node T_87 = bits(unroundedInt, 30, 30) @[RecFNToIN.scala 119:34] - node T_88 = and(T_86, T_87) @[RecFNToIN.scala 118:50] - node T_89 = and(T_88, roundCarryBut2) @[RecFNToIN.scala 119:49] - node T_90 = or(T_84, T_89) @[RecFNToIN.scala 117:48] - node T_91 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] - node overflow_unsigned = mux(notSpecial_magGeOne, T_90, T_91) @[RecFNToIN.scala 116:12] - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] - node T_93 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] - node excSign = and(sign, T_93) @[RecFNToIN.scala 124:24] - node T_94 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] - node T_96 = shl(UInt<1>("h01"), 31) @[RecFNToIN.scala 126:45] - node T_98 = mux(T_94, T_96, UInt<1>("h00")) @[RecFNToIN.scala 126:12] - node T_100 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] - node T_101 = and(io.signedOut, T_100) @[RecFNToIN.scala 127:26] - node T_104 = mux(T_101, UInt<31>("h07fffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] - node T_105 = or(T_98, T_104) @[RecFNToIN.scala 126:72] - node T_107 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] - node T_109 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] - node T_110 = and(T_107, T_109) @[RecFNToIN.scala 131:28] - node T_113 = mux(T_110, UInt<32>("h0ffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] - node excValue = or(T_105, T_113) @[RecFNToIN.scala 130:11] - node T_115 = eq(isSpecial, UInt<1>("h00")) @[RecFNToIN.scala 135:35] - node T_116 = and(roundInexact, T_115) @[RecFNToIN.scala 135:32] - node T_118 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] - node inexact = and(T_116, T_118) @[RecFNToIN.scala 135:45] - node T_119 = or(isSpecial, overflow) @[RecFNToIN.scala 137:27] - node T_120 = mux(T_119, excValue, roundedInt) @[RecFNToIN.scala 137:18] - io.out <= T_120 @[RecFNToIN.scala 137:12] - node T_121 = cat(isSpecial, overflow) @[Cat.scala 20:58] - node T_122 = cat(T_121, inexact) @[Cat.scala 20:58] - io.intExceptionFlags <= T_122 @[RecFNToIN.scala 138:26] - - module RecFNToIN_1 : + node sign = bits(io.in, 64, 64) + node exp = bits(io.in, 63, 52) + node fract = bits(io.in, 51, 0) + node T_5 = bits(exp, 11, 9) + node isZero = eq(T_5, UInt<1>("h0")) + node T_7 = bits(exp, 11, 10) + node isSpecial = eq(T_7, UInt<2>("h3")) + node T_9 = bits(exp, 9, 9) + node isNaN = and(isSpecial, T_9) + node notSpecial_magGeOne = bits(exp, 11, 11) + node T_10 = cat(notSpecial_magGeOne, fract) + node T_11 = bits(exp, 4, 0) + node T_13 = mux(notSpecial_magGeOne, T_11, UInt<1>("h0")) + node shiftedSig = dshl(T_10, T_13) + node unroundedInt = bits(shiftedSig, 83, 52) + node T_14 = bits(shiftedSig, 52, 51) + node T_15 = bits(shiftedSig, 50, 0) + node T_17 = neq(T_15, UInt<1>("h0")) + node roundBits = cat(T_14, T_17) + node T_18 = bits(roundBits, 1, 0) + node T_20 = neq(T_18, UInt<1>("h0")) + node T_22 = eq(isZero, UInt<1>("h0")) + node roundInexact = mux(notSpecial_magGeOne, T_20, T_22) + node T_23 = bits(roundBits, 2, 1) + node T_24 = not(T_23) + node T_26 = eq(T_24, UInt<1>("h0")) + node T_27 = bits(roundBits, 1, 0) + node T_28 = not(T_27) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = or(T_26, T_30) + node T_32 = bits(exp, 10, 0) + node T_33 = not(T_32) + node T_35 = eq(T_33, UInt<1>("h0")) + node T_36 = bits(roundBits, 1, 0) + node T_38 = neq(T_36, UInt<1>("h0")) + node T_40 = mux(T_35, T_38, UInt<1>("h0")) + node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_31, T_40) + node T_41 = eq(io.roundingMode, UInt<2>("h0")) + node T_42 = and(T_41, roundIncr_nearestEven) + node T_43 = eq(io.roundingMode, UInt<2>("h2")) + node T_44 = and(sign, roundInexact) + node T_45 = and(T_43, T_44) + node T_46 = or(T_42, T_45) + node T_47 = eq(io.roundingMode, UInt<2>("h3")) + node T_49 = eq(sign, UInt<1>("h0")) + node T_50 = and(T_49, roundInexact) + node T_51 = and(T_47, T_50) + node roundIncr = or(T_46, T_51) + node T_52 = not(unroundedInt) + node complUnroundedInt = mux(sign, T_52, unroundedInt) + node T_53 = xor(roundIncr, sign) + node T_55 = add(complUnroundedInt, UInt<1>("h1")) + node T_56 = tail(T_55, 1) + node roundedInt = mux(T_53, T_56, complUnroundedInt) + node T_57 = bits(unroundedInt, 29, 0) + node T_58 = not(T_57) + node T_60 = eq(T_58, UInt<1>("h0")) + node roundCarryBut2 = and(T_60, roundIncr) + node posExp = bits(exp, 10, 0) + node T_62 = geq(posExp, UInt<6>("h20")) + node T_64 = eq(posExp, UInt<5>("h1f")) + node T_66 = eq(sign, UInt<1>("h0")) + node T_67 = bits(unroundedInt, 30, 0) + node T_69 = neq(T_67, UInt<1>("h0")) + node T_70 = or(T_66, T_69) + node T_71 = or(T_70, roundIncr) + node T_72 = and(T_64, T_71) + node T_73 = or(T_62, T_72) + node T_75 = eq(sign, UInt<1>("h0")) + node T_77 = eq(posExp, UInt<5>("h1e")) + node T_78 = and(T_75, T_77) + node T_79 = and(T_78, roundCarryBut2) + node T_80 = or(T_73, T_79) + node overflow_signed = mux(notSpecial_magGeOne, T_80, UInt<1>("h0")) + node T_83 = geq(posExp, UInt<6>("h20")) + node T_84 = or(sign, T_83) + node T_86 = eq(posExp, UInt<5>("h1f")) + node T_87 = bits(unroundedInt, 30, 30) + node T_88 = and(T_86, T_87) + node T_89 = and(T_88, roundCarryBut2) + node T_90 = or(T_84, T_89) + node T_91 = and(sign, roundIncr) + node overflow_unsigned = mux(notSpecial_magGeOne, T_90, T_91) + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) + node T_93 = eq(isNaN, UInt<1>("h0")) + node excSign = and(sign, T_93) + node T_94 = and(io.signedOut, excSign) + node T_96 = shl(UInt<1>("h1"), 31) + node T_98 = mux(T_94, T_96, UInt<1>("h0")) + node T_100 = eq(excSign, UInt<1>("h0")) + node T_101 = and(io.signedOut, T_100) + node T_104 = mux(T_101, UInt<31>("h7fffffff"), UInt<1>("h0")) + node T_105 = or(T_98, T_104) + node T_107 = eq(io.signedOut, UInt<1>("h0")) + node T_109 = eq(excSign, UInt<1>("h0")) + node T_110 = and(T_107, T_109) + node T_113 = mux(T_110, UInt<32>("hffffffff"), UInt<1>("h0")) + node excValue = or(T_105, T_113) + node T_115 = eq(isSpecial, UInt<1>("h0")) + node T_116 = and(roundInexact, T_115) + node T_118 = eq(overflow, UInt<1>("h0")) + node inexact = and(T_116, T_118) + node T_119 = or(isSpecial, overflow) + node T_120 = mux(T_119, excValue, roundedInt) + io.out <= T_120 + node T_121 = cat(isSpecial, overflow) + node T_122 = cat(T_121, inexact) + io.intExceptionFlags <= T_122 + + module RecFNToIN_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} - + output io : { flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} + io is invalid - node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] - node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] - node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] - node T_5 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] - node isZero = eq(T_5, UInt<1>("h00")) @[RecFNToIN.scala 58:47] - node T_7 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] - node isSpecial = eq(T_7, UInt<2>("h03")) @[RecFNToIN.scala 59:50] - node T_9 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] - node isNaN = and(isSpecial, T_9) @[RecFNToIN.scala 60:27] - node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] - node T_10 = cat(notSpecial_magGeOne, fract) @[Cat.scala 20:58] - node T_11 = bits(exp, 5, 0) @[RecFNToIN.scala 74:20] - node T_13 = mux(notSpecial_magGeOne, T_11, UInt<1>("h00")) @[RecFNToIN.scala 73:16] - node shiftedSig = dshl(T_10, T_13) @[RecFNToIN.scala 72:40] - node unroundedInt = bits(shiftedSig, 115, 52) @[RecFNToIN.scala 82:24] - node T_14 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] - node T_15 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] - node T_17 = neq(T_15, UInt<1>("h00")) @[RecFNToIN.scala 86:41] - node roundBits = cat(T_14, T_17) @[Cat.scala 20:58] - node T_18 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] - node T_20 = neq(T_18, UInt<1>("h00")) @[RecFNToIN.scala 88:65] - node T_22 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] - node roundInexact = mux(notSpecial_magGeOne, T_20, T_22) @[RecFNToIN.scala 88:27] - node T_23 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] - node T_24 = not(T_23) @[RecFNToIN.scala 91:29] - node T_26 = eq(T_24, UInt<1>("h00")) @[RecFNToIN.scala 91:29] - node T_27 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] - node T_28 = not(T_27) @[RecFNToIN.scala 91:53] - node T_30 = eq(T_28, UInt<1>("h00")) @[RecFNToIN.scala 91:53] - node T_31 = or(T_26, T_30) @[RecFNToIN.scala 91:34] - node T_32 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] - node T_33 = not(T_32) @[RecFNToIN.scala 92:38] - node T_35 = eq(T_33, UInt<1>("h00")) @[RecFNToIN.scala 92:38] - node T_36 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] - node T_38 = neq(T_36, UInt<1>("h00")) @[RecFNToIN.scala 92:60] - node T_40 = mux(T_35, T_38, UInt<1>("h00")) @[RecFNToIN.scala 92:16] - node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_31, T_40) @[RecFNToIN.scala 90:12] - node T_41 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] - node T_42 = and(T_41, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] - node T_43 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] - node T_44 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] - node T_45 = and(T_43, T_44) @[RecFNToIN.scala 96:49] - node T_46 = or(T_42, T_45) @[RecFNToIN.scala 95:78] - node T_47 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] - node T_49 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] - node T_50 = and(T_49, roundInexact) @[RecFNToIN.scala 97:60] - node T_51 = and(T_47, T_50) @[RecFNToIN.scala 97:49] - node roundIncr = or(T_46, T_51) @[RecFNToIN.scala 96:78] - node T_52 = not(unroundedInt) @[RecFNToIN.scala 98:39] - node complUnroundedInt = mux(sign, T_52, unroundedInt) @[RecFNToIN.scala 98:32] - node T_53 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] - node T_55 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] - node T_56 = tail(T_55, 1) @[RecFNToIN.scala 100:49] - node roundedInt = mux(T_53, T_56, complUnroundedInt) @[RecFNToIN.scala 100:12] - node T_57 = bits(unroundedInt, 61, 0) @[RecFNToIN.scala 103:38] - node T_58 = not(T_57) @[RecFNToIN.scala 103:56] - node T_60 = eq(T_58, UInt<1>("h00")) @[RecFNToIN.scala 103:56] - node roundCarryBut2 = and(T_60, roundIncr) @[RecFNToIN.scala 103:61] - node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] - node T_62 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 108:21] - node T_64 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 109:26] - node T_66 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] - node T_67 = bits(unroundedInt, 62, 0) @[RecFNToIN.scala 110:45] - node T_69 = neq(T_67, UInt<1>("h00")) @[RecFNToIN.scala 110:63] - node T_70 = or(T_66, T_69) @[RecFNToIN.scala 110:30] - node T_71 = or(T_70, roundIncr) @[RecFNToIN.scala 111:27] - node T_72 = and(T_64, T_71) @[RecFNToIN.scala 109:50] - node T_73 = or(T_62, T_72) @[RecFNToIN.scala 108:40] - node T_75 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] - node T_77 = eq(posExp, UInt<6>("h03e")) @[RecFNToIN.scala 112:36] - node T_78 = and(T_75, T_77) @[RecFNToIN.scala 112:25] - node T_79 = and(T_78, roundCarryBut2) @[RecFNToIN.scala 112:60] - node T_80 = or(T_73, T_79) @[RecFNToIN.scala 111:42] - node overflow_signed = mux(notSpecial_magGeOne, T_80, UInt<1>("h00")) @[RecFNToIN.scala 107:12] - node T_83 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 117:29] - node T_84 = or(sign, T_83) @[RecFNToIN.scala 117:18] - node T_86 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 118:26] - node T_87 = bits(unroundedInt, 62, 62) @[RecFNToIN.scala 119:34] - node T_88 = and(T_86, T_87) @[RecFNToIN.scala 118:50] - node T_89 = and(T_88, roundCarryBut2) @[RecFNToIN.scala 119:49] - node T_90 = or(T_84, T_89) @[RecFNToIN.scala 117:48] - node T_91 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] - node overflow_unsigned = mux(notSpecial_magGeOne, T_90, T_91) @[RecFNToIN.scala 116:12] - node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] - node T_93 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] - node excSign = and(sign, T_93) @[RecFNToIN.scala 124:24] - node T_94 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] - node T_96 = shl(UInt<1>("h01"), 63) @[RecFNToIN.scala 126:45] - node T_98 = mux(T_94, T_96, UInt<1>("h00")) @[RecFNToIN.scala 126:12] - node T_100 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] - node T_101 = and(io.signedOut, T_100) @[RecFNToIN.scala 127:26] - node T_104 = mux(T_101, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] - node T_105 = or(T_98, T_104) @[RecFNToIN.scala 126:72] - node T_107 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] - node T_109 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] - node T_110 = and(T_107, T_109) @[RecFNToIN.scala 131:28] - node T_113 = mux(T_110, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] - node excValue = or(T_105, T_113) @[RecFNToIN.scala 130:11] - node T_115 = eq(isSpecial, UInt<1>("h00")) @[RecFNToIN.scala 135:35] - node T_116 = and(roundInexact, T_115) @[RecFNToIN.scala 135:32] - node T_118 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] - node inexact = and(T_116, T_118) @[RecFNToIN.scala 135:45] - node T_119 = or(isSpecial, overflow) @[RecFNToIN.scala 137:27] - node T_120 = mux(T_119, excValue, roundedInt) @[RecFNToIN.scala 137:18] - io.out <= T_120 @[RecFNToIN.scala 137:12] - node T_121 = cat(isSpecial, overflow) @[Cat.scala 20:58] - node T_122 = cat(T_121, inexact) @[Cat.scala 20:58] - io.intExceptionFlags <= T_122 @[RecFNToIN.scala 138:26] - - module FPToInt : + node sign = bits(io.in, 64, 64) + node exp = bits(io.in, 63, 52) + node fract = bits(io.in, 51, 0) + node T_5 = bits(exp, 11, 9) + node isZero = eq(T_5, UInt<1>("h0")) + node T_7 = bits(exp, 11, 10) + node isSpecial = eq(T_7, UInt<2>("h3")) + node T_9 = bits(exp, 9, 9) + node isNaN = and(isSpecial, T_9) + node notSpecial_magGeOne = bits(exp, 11, 11) + node T_10 = cat(notSpecial_magGeOne, fract) + node T_11 = bits(exp, 5, 0) + node T_13 = mux(notSpecial_magGeOne, T_11, UInt<1>("h0")) + node shiftedSig = dshl(T_10, T_13) + node unroundedInt = bits(shiftedSig, 115, 52) + node T_14 = bits(shiftedSig, 52, 51) + node T_15 = bits(shiftedSig, 50, 0) + node T_17 = neq(T_15, UInt<1>("h0")) + node roundBits = cat(T_14, T_17) + node T_18 = bits(roundBits, 1, 0) + node T_20 = neq(T_18, UInt<1>("h0")) + node T_22 = eq(isZero, UInt<1>("h0")) + node roundInexact = mux(notSpecial_magGeOne, T_20, T_22) + node T_23 = bits(roundBits, 2, 1) + node T_24 = not(T_23) + node T_26 = eq(T_24, UInt<1>("h0")) + node T_27 = bits(roundBits, 1, 0) + node T_28 = not(T_27) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = or(T_26, T_30) + node T_32 = bits(exp, 10, 0) + node T_33 = not(T_32) + node T_35 = eq(T_33, UInt<1>("h0")) + node T_36 = bits(roundBits, 1, 0) + node T_38 = neq(T_36, UInt<1>("h0")) + node T_40 = mux(T_35, T_38, UInt<1>("h0")) + node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_31, T_40) + node T_41 = eq(io.roundingMode, UInt<2>("h0")) + node T_42 = and(T_41, roundIncr_nearestEven) + node T_43 = eq(io.roundingMode, UInt<2>("h2")) + node T_44 = and(sign, roundInexact) + node T_45 = and(T_43, T_44) + node T_46 = or(T_42, T_45) + node T_47 = eq(io.roundingMode, UInt<2>("h3")) + node T_49 = eq(sign, UInt<1>("h0")) + node T_50 = and(T_49, roundInexact) + node T_51 = and(T_47, T_50) + node roundIncr = or(T_46, T_51) + node T_52 = not(unroundedInt) + node complUnroundedInt = mux(sign, T_52, unroundedInt) + node T_53 = xor(roundIncr, sign) + node T_55 = add(complUnroundedInt, UInt<1>("h1")) + node T_56 = tail(T_55, 1) + node roundedInt = mux(T_53, T_56, complUnroundedInt) + node T_57 = bits(unroundedInt, 61, 0) + node T_58 = not(T_57) + node T_60 = eq(T_58, UInt<1>("h0")) + node roundCarryBut2 = and(T_60, roundIncr) + node posExp = bits(exp, 10, 0) + node T_62 = geq(posExp, UInt<7>("h40")) + node T_64 = eq(posExp, UInt<6>("h3f")) + node T_66 = eq(sign, UInt<1>("h0")) + node T_67 = bits(unroundedInt, 62, 0) + node T_69 = neq(T_67, UInt<1>("h0")) + node T_70 = or(T_66, T_69) + node T_71 = or(T_70, roundIncr) + node T_72 = and(T_64, T_71) + node T_73 = or(T_62, T_72) + node T_75 = eq(sign, UInt<1>("h0")) + node T_77 = eq(posExp, UInt<6>("h3e")) + node T_78 = and(T_75, T_77) + node T_79 = and(T_78, roundCarryBut2) + node T_80 = or(T_73, T_79) + node overflow_signed = mux(notSpecial_magGeOne, T_80, UInt<1>("h0")) + node T_83 = geq(posExp, UInt<7>("h40")) + node T_84 = or(sign, T_83) + node T_86 = eq(posExp, UInt<6>("h3f")) + node T_87 = bits(unroundedInt, 62, 62) + node T_88 = and(T_86, T_87) + node T_89 = and(T_88, roundCarryBut2) + node T_90 = or(T_84, T_89) + node T_91 = and(sign, roundIncr) + node overflow_unsigned = mux(notSpecial_magGeOne, T_90, T_91) + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) + node T_93 = eq(isNaN, UInt<1>("h0")) + node excSign = and(sign, T_93) + node T_94 = and(io.signedOut, excSign) + node T_96 = shl(UInt<1>("h1"), 63) + node T_98 = mux(T_94, T_96, UInt<1>("h0")) + node T_100 = eq(excSign, UInt<1>("h0")) + node T_101 = and(io.signedOut, T_100) + node T_104 = mux(T_101, UInt<63>("h7fffffffffffffff"), UInt<1>("h0")) + node T_105 = or(T_98, T_104) + node T_107 = eq(io.signedOut, UInt<1>("h0")) + node T_109 = eq(excSign, UInt<1>("h0")) + node T_110 = and(T_107, T_109) + node T_113 = mux(T_110, UInt<64>("hffffffffffffffff"), UInt<1>("h0")) + node excValue = or(T_105, T_113) + node T_115 = eq(isSpecial, UInt<1>("h0")) + node T_116 = and(roundInexact, T_115) + node T_118 = eq(overflow, UInt<1>("h0")) + node inexact = and(T_116, T_118) + node T_119 = or(isSpecial, overflow) + node T_120 = mux(T_119, excValue, roundedInt) + io.out <= T_120 + node T_121 = cat(isSpecial, overflow) + node T_122 = cat(T_121, inexact) + io.intExceptionFlags <= T_122 + + module FPToInt : input clk : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} - + output io : { flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : { valid : UInt<1>, bits : { lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} + io is invalid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - reg valid : UInt<1>, clk + reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : + reset => (UInt<1>("h0"), in) + reg valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), valid) valid <= io.in.valid - when io.in.valid : @[fpu.scala 279:22] - in <- io.in.bits @[fpu.scala 280:8] - node T_228 = eq(io.in.bits.ldst, UInt<1>("h00")) @[fpu.scala 281:47] - node T_229 = and(io.in.bits.single, T_228) @[fpu.scala 281:44] - node T_232 = and(io.in.bits.cmd, UInt<4>("h0c")) @[fpu.scala 281:82] - node T_233 = eq(UInt<5>("h0c"), T_232) @[fpu.scala 281:82] - node T_235 = eq(T_233, UInt<1>("h00")) @[fpu.scala 281:82] - node T_236 = and(T_229, T_235) @[fpu.scala 281:64] - when T_236 : @[fpu.scala 281:98] - node T_237 = bits(io.in.bits.in1, 32, 32) @[fpu.scala 234:18] - node T_238 = bits(io.in.bits.in1, 22, 0) @[fpu.scala 235:21] - node T_239 = bits(io.in.bits.in1, 31, 23) @[fpu.scala 236:19] - node T_240 = shl(T_238, 53) @[fpu.scala 237:28] - node T_241 = shr(T_240, 24) @[fpu.scala 237:43] - node T_242 = bits(T_239, 8, 6) @[fpu.scala 239:26] - node T_244 = add(T_239, UInt<12>("h0800")) @[fpu.scala 240:31] - node T_245 = tail(T_244, 1) @[fpu.scala 240:31] - node T_247 = sub(T_245, UInt<9>("h0100")) @[fpu.scala 240:53] - node T_248 = tail(T_247, 1) @[fpu.scala 240:53] - node T_250 = eq(T_242, UInt<1>("h00")) @[fpu.scala 241:19] - node T_252 = geq(T_242, UInt<3>("h06")) @[fpu.scala 241:36] - node T_253 = or(T_250, T_252) @[fpu.scala 241:25] - node T_254 = bits(T_248, 8, 0) @[fpu.scala 241:65] - node T_255 = cat(T_242, T_254) @[Cat.scala 20:58] - node T_256 = bits(T_248, 11, 0) @[fpu.scala 242:52] - node T_257 = mux(T_253, T_255, T_256) @[fpu.scala 241:10] - node T_258 = cat(T_237, T_257) @[Cat.scala 20:58] - node T_259 = cat(T_258, T_241) @[Cat.scala 20:58] - in.in1 <= T_259 @[fpu.scala 282:14] - node T_260 = bits(io.in.bits.in2, 32, 32) @[fpu.scala 234:18] - node T_261 = bits(io.in.bits.in2, 22, 0) @[fpu.scala 235:21] - node T_262 = bits(io.in.bits.in2, 31, 23) @[fpu.scala 236:19] - node T_263 = shl(T_261, 53) @[fpu.scala 237:28] - node T_264 = shr(T_263, 24) @[fpu.scala 237:43] - node T_265 = bits(T_262, 8, 6) @[fpu.scala 239:26] - node T_267 = add(T_262, UInt<12>("h0800")) @[fpu.scala 240:31] - node T_268 = tail(T_267, 1) @[fpu.scala 240:31] - node T_270 = sub(T_268, UInt<9>("h0100")) @[fpu.scala 240:53] - node T_271 = tail(T_270, 1) @[fpu.scala 240:53] - node T_273 = eq(T_265, UInt<1>("h00")) @[fpu.scala 241:19] - node T_275 = geq(T_265, UInt<3>("h06")) @[fpu.scala 241:36] - node T_276 = or(T_273, T_275) @[fpu.scala 241:25] - node T_277 = bits(T_271, 8, 0) @[fpu.scala 241:65] - node T_278 = cat(T_265, T_277) @[Cat.scala 20:58] - node T_279 = bits(T_271, 11, 0) @[fpu.scala 242:52] - node T_280 = mux(T_276, T_278, T_279) @[fpu.scala 241:10] - node T_281 = cat(T_260, T_280) @[Cat.scala 20:58] - node T_282 = cat(T_281, T_264) @[Cat.scala 20:58] - in.in2 <= T_282 @[fpu.scala 283:14] - skip @[fpu.scala 281:98] - skip @[fpu.scala 279:22] - node T_283 = bits(in.in1, 32, 32) @[fNFromRecFN.scala 45:22] - node T_284 = bits(in.in1, 31, 23) @[fNFromRecFN.scala 46:23] - node T_285 = bits(in.in1, 22, 0) @[fNFromRecFN.scala 47:25] - node T_286 = bits(T_284, 6, 0) @[fNFromRecFN.scala 49:39] - node T_288 = lt(T_286, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] - node T_289 = bits(T_284, 8, 6) @[fNFromRecFN.scala 51:19] - node T_291 = eq(T_289, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] - node T_292 = bits(T_284, 8, 7) @[fNFromRecFN.scala 52:24] - node T_294 = eq(T_292, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] - node T_295 = and(T_294, T_288) @[fNFromRecFN.scala 52:62] - node T_296 = or(T_291, T_295) @[fNFromRecFN.scala 51:57] - node T_297 = bits(T_284, 8, 7) @[fNFromRecFN.scala 55:20] - node T_299 = eq(T_297, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] - node T_301 = eq(T_288, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] - node T_302 = and(T_299, T_301) @[fNFromRecFN.scala 55:58] - node T_303 = bits(T_284, 8, 7) @[fNFromRecFN.scala 57:23] - node T_305 = eq(T_303, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] - node T_306 = or(T_302, T_305) @[fNFromRecFN.scala 56:39] - node T_307 = bits(T_284, 8, 7) @[fNFromRecFN.scala 58:30] - node T_309 = eq(T_307, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] - node T_310 = bits(T_284, 6, 6) @[fNFromRecFN.scala 59:39] - node T_311 = and(T_309, T_310) @[fNFromRecFN.scala 59:31] - node T_313 = bits(T_284, 4, 0) @[fNFromRecFN.scala 61:46] - node T_314 = sub(UInt<2>("h02"), T_313) @[fNFromRecFN.scala 61:39] - node T_315 = tail(T_314, 1) @[fNFromRecFN.scala 61:39] - node T_317 = cat(UInt<1>("h01"), T_285) @[Cat.scala 20:58] - node T_318 = dshr(T_317, T_315) @[fNFromRecFN.scala 63:35] - node T_319 = bits(T_318, 22, 0) @[fNFromRecFN.scala 63:53] - node T_320 = bits(T_284, 7, 0) @[fNFromRecFN.scala 65:18] - node T_322 = sub(T_320, UInt<8>("h081")) @[fNFromRecFN.scala 65:36] - node T_323 = tail(T_322, 1) @[fNFromRecFN.scala 65:36] - node T_324 = bits(T_309, 0, 0) @[Bitwise.scala 33:15] - node T_327 = mux(T_324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_328 = mux(T_306, T_323, T_327) @[fNFromRecFN.scala 68:16] - node T_329 = or(T_306, T_311) @[fNFromRecFN.scala 70:26] - node T_331 = mux(T_296, T_319, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] - node T_332 = mux(T_329, T_285, T_331) @[fNFromRecFN.scala 70:16] - node T_333 = cat(T_283, T_328) @[Cat.scala 20:58] - node T_334 = cat(T_333, T_332) @[Cat.scala 20:58] - node T_335 = bits(T_334, 31, 31) @[util.scala 21:38] - node T_336 = bits(T_335, 0, 0) @[Bitwise.scala 33:15] - node T_339 = mux(T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node unrec_s = cat(T_339, T_334) @[Cat.scala 20:58] - node T_340 = bits(in.in1, 64, 64) @[fNFromRecFN.scala 45:22] - node T_341 = bits(in.in1, 63, 52) @[fNFromRecFN.scala 46:23] - node T_342 = bits(in.in1, 51, 0) @[fNFromRecFN.scala 47:25] - node T_343 = bits(T_341, 9, 0) @[fNFromRecFN.scala 49:39] - node T_345 = lt(T_343, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] - node T_346 = bits(T_341, 11, 9) @[fNFromRecFN.scala 51:19] - node T_348 = eq(T_346, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] - node T_349 = bits(T_341, 11, 10) @[fNFromRecFN.scala 52:24] - node T_351 = eq(T_349, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] - node T_352 = and(T_351, T_345) @[fNFromRecFN.scala 52:62] - node T_353 = or(T_348, T_352) @[fNFromRecFN.scala 51:57] - node T_354 = bits(T_341, 11, 10) @[fNFromRecFN.scala 55:20] - node T_356 = eq(T_354, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] - node T_358 = eq(T_345, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] - node T_359 = and(T_356, T_358) @[fNFromRecFN.scala 55:58] - node T_360 = bits(T_341, 11, 10) @[fNFromRecFN.scala 57:23] - node T_362 = eq(T_360, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] - node T_363 = or(T_359, T_362) @[fNFromRecFN.scala 56:39] - node T_364 = bits(T_341, 11, 10) @[fNFromRecFN.scala 58:30] - node T_366 = eq(T_364, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] - node T_367 = bits(T_341, 9, 9) @[fNFromRecFN.scala 59:39] - node T_368 = and(T_366, T_367) @[fNFromRecFN.scala 59:31] - node T_370 = bits(T_341, 5, 0) @[fNFromRecFN.scala 61:46] - node T_371 = sub(UInt<2>("h02"), T_370) @[fNFromRecFN.scala 61:39] - node T_372 = tail(T_371, 1) @[fNFromRecFN.scala 61:39] - node T_374 = cat(UInt<1>("h01"), T_342) @[Cat.scala 20:58] - node T_375 = dshr(T_374, T_372) @[fNFromRecFN.scala 63:35] - node T_376 = bits(T_375, 51, 0) @[fNFromRecFN.scala 63:53] - node T_377 = bits(T_341, 10, 0) @[fNFromRecFN.scala 65:18] - node T_379 = sub(T_377, UInt<11>("h0401")) @[fNFromRecFN.scala 65:36] - node T_380 = tail(T_379, 1) @[fNFromRecFN.scala 65:36] - node T_381 = bits(T_366, 0, 0) @[Bitwise.scala 33:15] - node T_384 = mux(T_381, UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 33:12] - node T_385 = mux(T_363, T_380, T_384) @[fNFromRecFN.scala 68:16] - node T_386 = or(T_363, T_368) @[fNFromRecFN.scala 70:26] - node T_388 = mux(T_353, T_376, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] - node T_389 = mux(T_386, T_342, T_388) @[fNFromRecFN.scala 70:16] - node T_390 = cat(T_340, T_385) @[Cat.scala 20:58] - node T_391 = cat(T_390, T_389) @[Cat.scala 20:58] - node unrec_mem = mux(in.single, unrec_s, T_391) @[fpu.scala 292:10] - node T_392 = bits(in.in1, 32, 32) @[fpu.scala 198:18] - node T_393 = bits(in.in1, 31, 23) @[fpu.scala 199:17] - node T_394 = bits(in.in1, 22, 0) @[fpu.scala 200:17] - node T_395 = bits(T_393, 8, 6) @[fpu.scala 202:26] - node T_396 = bits(T_395, 2, 1) @[fpu.scala 203:27] - node T_398 = eq(T_396, UInt<2>("h03")) @[fpu.scala 204:30] - node T_399 = bits(T_393, 6, 0) @[fpu.scala 206:32] - node T_401 = lt(T_399, UInt<2>("h02")) @[fpu.scala 206:48] - node T_403 = eq(T_395, UInt<1>("h01")) @[fpu.scala 207:28] - node T_405 = eq(T_396, UInt<1>("h01")) @[fpu.scala 207:50] - node T_406 = and(T_405, T_401) @[fpu.scala 207:62] - node T_407 = or(T_403, T_406) @[fpu.scala 207:40] - node T_409 = eq(T_396, UInt<1>("h01")) @[fpu.scala 208:27] - node T_411 = eq(T_401, UInt<1>("h00")) @[fpu.scala 208:42] - node T_412 = and(T_409, T_411) @[fpu.scala 208:39] - node T_414 = eq(T_396, UInt<2>("h02")) @[fpu.scala 208:71] - node T_415 = or(T_412, T_414) @[fpu.scala 208:61] - node T_417 = eq(T_395, UInt<1>("h00")) @[fpu.scala 209:23] - node T_418 = bits(T_393, 6, 6) @[fpu.scala 210:34] - node T_420 = eq(T_418, UInt<1>("h00")) @[fpu.scala 210:30] - node T_421 = and(T_398, T_420) @[fpu.scala 210:27] - node T_422 = not(T_395) @[fpu.scala 211:22] - node T_424 = eq(T_422, UInt<1>("h00")) @[fpu.scala 211:22] - node T_425 = bits(T_394, 22, 22) @[fpu.scala 212:31] - node T_427 = eq(T_425, UInt<1>("h00")) @[fpu.scala 212:27] - node T_428 = and(T_424, T_427) @[fpu.scala 212:24] - node T_429 = bits(T_394, 22, 22) @[fpu.scala 213:30] - node T_430 = and(T_424, T_429) @[fpu.scala 213:24] - node T_432 = eq(T_392, UInt<1>("h00")) @[fpu.scala 215:34] - node T_433 = and(T_421, T_432) @[fpu.scala 215:31] - node T_435 = eq(T_392, UInt<1>("h00")) @[fpu.scala 215:53] - node T_436 = and(T_415, T_435) @[fpu.scala 215:50] - node T_438 = eq(T_392, UInt<1>("h00")) @[fpu.scala 216:24] - node T_439 = and(T_407, T_438) @[fpu.scala 216:21] - node T_441 = eq(T_392, UInt<1>("h00")) @[fpu.scala 216:41] - node T_442 = and(T_417, T_441) @[fpu.scala 216:38] - node T_443 = and(T_417, T_392) @[fpu.scala 216:55] - node T_444 = and(T_407, T_392) @[fpu.scala 217:21] - node T_445 = and(T_415, T_392) @[fpu.scala 217:39] - node T_446 = and(T_421, T_392) @[fpu.scala 217:54] - node T_447 = cat(T_445, T_446) @[Cat.scala 20:58] - node T_448 = cat(T_442, T_443) @[Cat.scala 20:58] - node T_449 = cat(T_448, T_444) @[Cat.scala 20:58] - node T_450 = cat(T_449, T_447) @[Cat.scala 20:58] - node T_451 = cat(T_436, T_439) @[Cat.scala 20:58] - node T_452 = cat(T_430, T_428) @[Cat.scala 20:58] - node T_453 = cat(T_452, T_433) @[Cat.scala 20:58] - node T_454 = cat(T_453, T_451) @[Cat.scala 20:58] - node classify_s = cat(T_454, T_450) @[Cat.scala 20:58] - node T_455 = bits(in.in1, 64, 64) @[fpu.scala 198:18] - node T_456 = bits(in.in1, 63, 52) @[fpu.scala 199:17] - node T_457 = bits(in.in1, 51, 0) @[fpu.scala 200:17] - node T_458 = bits(T_456, 11, 9) @[fpu.scala 202:26] - node T_459 = bits(T_458, 2, 1) @[fpu.scala 203:27] - node T_461 = eq(T_459, UInt<2>("h03")) @[fpu.scala 204:30] - node T_462 = bits(T_456, 9, 0) @[fpu.scala 206:32] - node T_464 = lt(T_462, UInt<2>("h02")) @[fpu.scala 206:48] - node T_466 = eq(T_458, UInt<1>("h01")) @[fpu.scala 207:28] - node T_468 = eq(T_459, UInt<1>("h01")) @[fpu.scala 207:50] - node T_469 = and(T_468, T_464) @[fpu.scala 207:62] - node T_470 = or(T_466, T_469) @[fpu.scala 207:40] - node T_472 = eq(T_459, UInt<1>("h01")) @[fpu.scala 208:27] - node T_474 = eq(T_464, UInt<1>("h00")) @[fpu.scala 208:42] - node T_475 = and(T_472, T_474) @[fpu.scala 208:39] - node T_477 = eq(T_459, UInt<2>("h02")) @[fpu.scala 208:71] - node T_478 = or(T_475, T_477) @[fpu.scala 208:61] - node T_480 = eq(T_458, UInt<1>("h00")) @[fpu.scala 209:23] - node T_481 = bits(T_456, 9, 9) @[fpu.scala 210:34] - node T_483 = eq(T_481, UInt<1>("h00")) @[fpu.scala 210:30] - node T_484 = and(T_461, T_483) @[fpu.scala 210:27] - node T_485 = not(T_458) @[fpu.scala 211:22] - node T_487 = eq(T_485, UInt<1>("h00")) @[fpu.scala 211:22] - node T_488 = bits(T_457, 51, 51) @[fpu.scala 212:31] - node T_490 = eq(T_488, UInt<1>("h00")) @[fpu.scala 212:27] - node T_491 = and(T_487, T_490) @[fpu.scala 212:24] - node T_492 = bits(T_457, 51, 51) @[fpu.scala 213:30] - node T_493 = and(T_487, T_492) @[fpu.scala 213:24] - node T_495 = eq(T_455, UInt<1>("h00")) @[fpu.scala 215:34] - node T_496 = and(T_484, T_495) @[fpu.scala 215:31] - node T_498 = eq(T_455, UInt<1>("h00")) @[fpu.scala 215:53] - node T_499 = and(T_478, T_498) @[fpu.scala 215:50] - node T_501 = eq(T_455, UInt<1>("h00")) @[fpu.scala 216:24] - node T_502 = and(T_470, T_501) @[fpu.scala 216:21] - node T_504 = eq(T_455, UInt<1>("h00")) @[fpu.scala 216:41] - node T_505 = and(T_480, T_504) @[fpu.scala 216:38] - node T_506 = and(T_480, T_455) @[fpu.scala 216:55] - node T_507 = and(T_470, T_455) @[fpu.scala 217:21] - node T_508 = and(T_478, T_455) @[fpu.scala 217:39] - node T_509 = and(T_484, T_455) @[fpu.scala 217:54] - node T_510 = cat(T_508, T_509) @[Cat.scala 20:58] - node T_511 = cat(T_505, T_506) @[Cat.scala 20:58] - node T_512 = cat(T_511, T_507) @[Cat.scala 20:58] - node T_513 = cat(T_512, T_510) @[Cat.scala 20:58] - node T_514 = cat(T_499, T_502) @[Cat.scala 20:58] - node T_515 = cat(T_493, T_491) @[Cat.scala 20:58] - node T_516 = cat(T_515, T_496) @[Cat.scala 20:58] - node T_517 = cat(T_516, T_514) @[Cat.scala 20:58] - node T_518 = cat(T_517, T_513) @[Cat.scala 20:58] - node classify_out = mux(in.single, classify_s, T_518) @[fpu.scala 304:10] - inst dcmp of CompareRecFN @[fpu.scala 307:20] + when io.in.valid : + in <- io.in.bits + node T_228 = eq(io.in.bits.ldst, UInt<1>("h0")) + node T_229 = and(io.in.bits.single, T_228) + node T_232 = and(io.in.bits.cmd, UInt<4>("hc")) + node T_233 = eq(UInt<5>("hc"), T_232) + node T_235 = eq(T_233, UInt<1>("h0")) + node T_236 = and(T_229, T_235) + when T_236 : + node T_237 = bits(io.in.bits.in1, 32, 32) + node T_238 = bits(io.in.bits.in1, 22, 0) + node T_239 = bits(io.in.bits.in1, 31, 23) + node T_240 = shl(T_238, 53) + node T_241 = shr(T_240, 24) + node T_242 = bits(T_239, 8, 6) + node T_244 = add(T_239, UInt<12>("h800")) + node T_245 = tail(T_244, 1) + node T_247 = sub(T_245, UInt<9>("h100")) + node T_248 = tail(T_247, 1) + node T_250 = eq(T_242, UInt<1>("h0")) + node T_252 = geq(T_242, UInt<3>("h6")) + node T_253 = or(T_250, T_252) + node T_254 = bits(T_248, 8, 0) + node T_255 = cat(T_242, T_254) + node T_256 = bits(T_248, 11, 0) + node T_257 = mux(T_253, T_255, T_256) + node T_258 = cat(T_237, T_257) + node T_259 = cat(T_258, T_241) + in.in1 <= T_259 + node T_260 = bits(io.in.bits.in2, 32, 32) + node T_261 = bits(io.in.bits.in2, 22, 0) + node T_262 = bits(io.in.bits.in2, 31, 23) + node T_263 = shl(T_261, 53) + node T_264 = shr(T_263, 24) + node T_265 = bits(T_262, 8, 6) + node T_267 = add(T_262, UInt<12>("h800")) + node T_268 = tail(T_267, 1) + node T_270 = sub(T_268, UInt<9>("h100")) + node T_271 = tail(T_270, 1) + node T_273 = eq(T_265, UInt<1>("h0")) + node T_275 = geq(T_265, UInt<3>("h6")) + node T_276 = or(T_273, T_275) + node T_277 = bits(T_271, 8, 0) + node T_278 = cat(T_265, T_277) + node T_279 = bits(T_271, 11, 0) + node T_280 = mux(T_276, T_278, T_279) + node T_281 = cat(T_260, T_280) + node T_282 = cat(T_281, T_264) + in.in2 <= T_282 + node T_283 = bits(in.in1, 32, 32) + node T_284 = bits(in.in1, 31, 23) + node T_285 = bits(in.in1, 22, 0) + node T_286 = bits(T_284, 6, 0) + node T_288 = lt(T_286, UInt<2>("h2")) + node T_289 = bits(T_284, 8, 6) + node T_291 = eq(T_289, UInt<1>("h1")) + node T_292 = bits(T_284, 8, 7) + node T_294 = eq(T_292, UInt<1>("h1")) + node T_295 = and(T_294, T_288) + node T_296 = or(T_291, T_295) + node T_297 = bits(T_284, 8, 7) + node T_299 = eq(T_297, UInt<1>("h1")) + node T_301 = eq(T_288, UInt<1>("h0")) + node T_302 = and(T_299, T_301) + node T_303 = bits(T_284, 8, 7) + node T_305 = eq(T_303, UInt<2>("h2")) + node T_306 = or(T_302, T_305) + node T_307 = bits(T_284, 8, 7) + node T_309 = eq(T_307, UInt<2>("h3")) + node T_310 = bits(T_284, 6, 6) + node T_311 = and(T_309, T_310) + node T_313 = bits(T_284, 4, 0) + node T_314 = sub(UInt<2>("h2"), T_313) + node T_315 = tail(T_314, 1) + node T_317 = cat(UInt<1>("h1"), T_285) + node T_318 = dshr(T_317, T_315) + node T_319 = bits(T_318, 22, 0) + node T_320 = bits(T_284, 7, 0) + node T_322 = sub(T_320, UInt<8>("h81")) + node T_323 = tail(T_322, 1) + node T_324 = bits(T_309, 0, 0) + node T_327 = mux(T_324, UInt<8>("hff"), UInt<8>("h0")) + node T_328 = mux(T_306, T_323, T_327) + node T_329 = or(T_306, T_311) + node T_331 = mux(T_296, T_319, UInt<1>("h0")) + node T_332 = mux(T_329, T_285, T_331) + node T_333 = cat(T_283, T_328) + node T_334 = cat(T_333, T_332) + node T_335 = bits(T_334, 31, 31) + node T_336 = bits(T_335, 0, 0) + node T_339 = mux(T_336, UInt<32>("hffffffff"), UInt<32>("h0")) + node unrec_s = cat(T_339, T_334) + node T_340 = bits(in.in1, 64, 64) + node T_341 = bits(in.in1, 63, 52) + node T_342 = bits(in.in1, 51, 0) + node T_343 = bits(T_341, 9, 0) + node T_345 = lt(T_343, UInt<2>("h2")) + node T_346 = bits(T_341, 11, 9) + node T_348 = eq(T_346, UInt<1>("h1")) + node T_349 = bits(T_341, 11, 10) + node T_351 = eq(T_349, UInt<1>("h1")) + node T_352 = and(T_351, T_345) + node T_353 = or(T_348, T_352) + node T_354 = bits(T_341, 11, 10) + node T_356 = eq(T_354, UInt<1>("h1")) + node T_358 = eq(T_345, UInt<1>("h0")) + node T_359 = and(T_356, T_358) + node T_360 = bits(T_341, 11, 10) + node T_362 = eq(T_360, UInt<2>("h2")) + node T_363 = or(T_359, T_362) + node T_364 = bits(T_341, 11, 10) + node T_366 = eq(T_364, UInt<2>("h3")) + node T_367 = bits(T_341, 9, 9) + node T_368 = and(T_366, T_367) + node T_370 = bits(T_341, 5, 0) + node T_371 = sub(UInt<2>("h2"), T_370) + node T_372 = tail(T_371, 1) + node T_374 = cat(UInt<1>("h1"), T_342) + node T_375 = dshr(T_374, T_372) + node T_376 = bits(T_375, 51, 0) + node T_377 = bits(T_341, 10, 0) + node T_379 = sub(T_377, UInt<11>("h401")) + node T_380 = tail(T_379, 1) + node T_381 = bits(T_366, 0, 0) + node T_384 = mux(T_381, UInt<11>("h7ff"), UInt<11>("h0")) + node T_385 = mux(T_363, T_380, T_384) + node T_386 = or(T_363, T_368) + node T_388 = mux(T_353, T_376, UInt<1>("h0")) + node T_389 = mux(T_386, T_342, T_388) + node T_390 = cat(T_340, T_385) + node T_391 = cat(T_390, T_389) + node unrec_mem = mux(in.single, unrec_s, T_391) + node T_392 = bits(in.in1, 32, 32) + node T_393 = bits(in.in1, 31, 23) + node T_394 = bits(in.in1, 22, 0) + node T_395 = bits(T_393, 8, 6) + node T_396 = bits(T_395, 2, 1) + node T_398 = eq(T_396, UInt<2>("h3")) + node T_399 = bits(T_393, 6, 0) + node T_401 = lt(T_399, UInt<2>("h2")) + node T_403 = eq(T_395, UInt<1>("h1")) + node T_405 = eq(T_396, UInt<1>("h1")) + node T_406 = and(T_405, T_401) + node T_407 = or(T_403, T_406) + node T_409 = eq(T_396, UInt<1>("h1")) + node T_411 = eq(T_401, UInt<1>("h0")) + node T_412 = and(T_409, T_411) + node T_414 = eq(T_396, UInt<2>("h2")) + node T_415 = or(T_412, T_414) + node T_417 = eq(T_395, UInt<1>("h0")) + node T_418 = bits(T_393, 6, 6) + node T_420 = eq(T_418, UInt<1>("h0")) + node T_421 = and(T_398, T_420) + node T_422 = not(T_395) + node T_424 = eq(T_422, UInt<1>("h0")) + node T_425 = bits(T_394, 22, 22) + node T_427 = eq(T_425, UInt<1>("h0")) + node T_428 = and(T_424, T_427) + node T_429 = bits(T_394, 22, 22) + node T_430 = and(T_424, T_429) + node T_432 = eq(T_392, UInt<1>("h0")) + node T_433 = and(T_421, T_432) + node T_435 = eq(T_392, UInt<1>("h0")) + node T_436 = and(T_415, T_435) + node T_438 = eq(T_392, UInt<1>("h0")) + node T_439 = and(T_407, T_438) + node T_441 = eq(T_392, UInt<1>("h0")) + node T_442 = and(T_417, T_441) + node T_443 = and(T_417, T_392) + node T_444 = and(T_407, T_392) + node T_445 = and(T_415, T_392) + node T_446 = and(T_421, T_392) + node T_447 = cat(T_445, T_446) + node T_448 = cat(T_442, T_443) + node T_449 = cat(T_448, T_444) + node T_450 = cat(T_449, T_447) + node T_451 = cat(T_436, T_439) + node T_452 = cat(T_430, T_428) + node T_453 = cat(T_452, T_433) + node T_454 = cat(T_453, T_451) + node classify_s = cat(T_454, T_450) + node T_455 = bits(in.in1, 64, 64) + node T_456 = bits(in.in1, 63, 52) + node T_457 = bits(in.in1, 51, 0) + node T_458 = bits(T_456, 11, 9) + node T_459 = bits(T_458, 2, 1) + node T_461 = eq(T_459, UInt<2>("h3")) + node T_462 = bits(T_456, 9, 0) + node T_464 = lt(T_462, UInt<2>("h2")) + node T_466 = eq(T_458, UInt<1>("h1")) + node T_468 = eq(T_459, UInt<1>("h1")) + node T_469 = and(T_468, T_464) + node T_470 = or(T_466, T_469) + node T_472 = eq(T_459, UInt<1>("h1")) + node T_474 = eq(T_464, UInt<1>("h0")) + node T_475 = and(T_472, T_474) + node T_477 = eq(T_459, UInt<2>("h2")) + node T_478 = or(T_475, T_477) + node T_480 = eq(T_458, UInt<1>("h0")) + node T_481 = bits(T_456, 9, 9) + node T_483 = eq(T_481, UInt<1>("h0")) + node T_484 = and(T_461, T_483) + node T_485 = not(T_458) + node T_487 = eq(T_485, UInt<1>("h0")) + node T_488 = bits(T_457, 51, 51) + node T_490 = eq(T_488, UInt<1>("h0")) + node T_491 = and(T_487, T_490) + node T_492 = bits(T_457, 51, 51) + node T_493 = and(T_487, T_492) + node T_495 = eq(T_455, UInt<1>("h0")) + node T_496 = and(T_484, T_495) + node T_498 = eq(T_455, UInt<1>("h0")) + node T_499 = and(T_478, T_498) + node T_501 = eq(T_455, UInt<1>("h0")) + node T_502 = and(T_470, T_501) + node T_504 = eq(T_455, UInt<1>("h0")) + node T_505 = and(T_480, T_504) + node T_506 = and(T_480, T_455) + node T_507 = and(T_470, T_455) + node T_508 = and(T_478, T_455) + node T_509 = and(T_484, T_455) + node T_510 = cat(T_508, T_509) + node T_511 = cat(T_505, T_506) + node T_512 = cat(T_511, T_507) + node T_513 = cat(T_512, T_510) + node T_514 = cat(T_499, T_502) + node T_515 = cat(T_493, T_491) + node T_516 = cat(T_515, T_496) + node T_517 = cat(T_516, T_514) + node T_518 = cat(T_517, T_513) + node classify_out = mux(in.single, classify_s, T_518) + inst dcmp of CompareRecFN dcmp.io is invalid dcmp.clk <= clk dcmp.reset <= reset - dcmp.io.a <= in.in1 @[fpu.scala 308:13] - dcmp.io.b <= in.in2 @[fpu.scala 309:13] - dcmp.io.signaling <= UInt<1>("h01") @[fpu.scala 310:21] - node T_520 = not(in.rm) @[fpu.scala 311:19] - node T_521 = cat(dcmp.io.lt, dcmp.io.eq) @[Cat.scala 20:58] - node T_522 = and(T_520, T_521) @[fpu.scala 311:26] - node dcmp_out = neq(T_522, UInt<1>("h00")) @[fpu.scala 311:57] - node T_524 = bits(in.rm, 0, 0) @[fpu.scala 314:33] - node T_525 = mux(T_524, classify_out, unrec_mem) @[fpu.scala 314:27] - io.out.bits.toint <= T_525 @[fpu.scala 314:21] - io.out.bits.store <= unrec_mem @[fpu.scala 315:21] - io.out.bits.exc <= UInt<1>("h00") @[fpu.scala 316:19] - node T_529 = and(in.cmd, UInt<4>("h0c")) @[fpu.scala 318:16] - node T_530 = eq(UInt<5>("h04"), T_529) @[fpu.scala 318:16] - when T_530 : @[fpu.scala 318:30] - io.out.bits.toint <= dcmp_out @[fpu.scala 319:23] - io.out.bits.exc <= dcmp.io.exceptionFlags @[fpu.scala 320:21] - skip @[fpu.scala 318:30] - node T_533 = and(in.cmd, UInt<4>("h0c")) @[fpu.scala 322:16] - node T_534 = eq(UInt<5>("h08"), T_533) @[fpu.scala 322:16] - when T_534 : @[fpu.scala 322:33] - inst RecFNToIN_2 of RecFNToIN @[fpu.scala 326:24] + dcmp.io.a <= in.in1 + dcmp.io.b <= in.in2 + dcmp.io.signaling <= UInt<1>("h1") + node T_520 = not(in.rm) + node T_521 = cat(dcmp.io.lt, dcmp.io.eq) + node T_522 = and(T_520, T_521) + node dcmp_out = neq(T_522, UInt<1>("h0")) + node T_524 = bits(in.rm, 0, 0) + node T_525 = mux(T_524, classify_out, unrec_mem) + io.out.bits.toint <= T_525 + io.out.bits.store <= unrec_mem + io.out.bits.exc <= UInt<1>("h0") + node T_529 = and(in.cmd, UInt<4>("hc")) + node T_530 = eq(UInt<5>("h4"), T_529) + when T_530 : + io.out.bits.toint <= dcmp_out + io.out.bits.exc <= dcmp.io.exceptionFlags + node T_533 = and(in.cmd, UInt<4>("hc")) + node T_534 = eq(UInt<5>("h8"), T_533) + when T_534 : + inst RecFNToIN_2 of RecFNToIN RecFNToIN_2.io is invalid RecFNToIN_2.clk <= clk RecFNToIN_2.reset <= reset - RecFNToIN_2.io.in <= in.in1 @[fpu.scala 327:18] - RecFNToIN_2.io.roundingMode <= in.rm @[fpu.scala 328:28] - node T_535 = bits(in.typ, 0, 0) @[fpu.scala 329:35] - node T_536 = not(T_535) @[fpu.scala 329:28] - RecFNToIN_2.io.signedOut <= T_536 @[fpu.scala 329:25] - node T_537 = bits(in.typ, 1, 1) @[util.scala 25:13] - node T_539 = eq(T_537, UInt<1>("h00")) @[fpu.scala 330:44] - when T_539 : @[fpu.scala 330:51] - node T_540 = bits(RecFNToIN_2.io.out, 31, 31) @[util.scala 21:38] - node T_541 = bits(T_540, 0, 0) @[Bitwise.scala 33:15] - node T_544 = mux(T_541, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_545 = cat(T_544, RecFNToIN_2.io.out) @[Cat.scala 20:58] - io.out.bits.toint <= T_545 @[fpu.scala 331:27] - node T_546 = bits(RecFNToIN_2.io.intExceptionFlags, 2, 1) @[fpu.scala 332:57] - node T_548 = neq(T_546, UInt<1>("h00")) @[fpu.scala 332:64] - node T_550 = bits(RecFNToIN_2.io.intExceptionFlags, 0, 0) @[fpu.scala 332:106] - node T_551 = cat(T_548, UInt<3>("h00")) @[Cat.scala 20:58] - node T_552 = cat(T_551, T_550) @[Cat.scala 20:58] - io.out.bits.exc <= T_552 @[fpu.scala 332:25] - skip @[fpu.scala 330:51] - inst RecFNToIN_1_1 of RecFNToIN_1 @[fpu.scala 326:24] + RecFNToIN_2.io.in <= in.in1 + RecFNToIN_2.io.roundingMode <= in.rm + node T_535 = bits(in.typ, 0, 0) + node T_536 = not(T_535) + RecFNToIN_2.io.signedOut <= T_536 + node T_537 = bits(in.typ, 1, 1) + node T_539 = eq(T_537, UInt<1>("h0")) + when T_539 : + node T_540 = bits(RecFNToIN_2.io.out, 31, 31) + node T_541 = bits(T_540, 0, 0) + node T_544 = mux(T_541, UInt<32>("hffffffff"), UInt<32>("h0")) + node T_545 = cat(T_544, RecFNToIN_2.io.out) + io.out.bits.toint <= T_545 + node T_546 = bits(RecFNToIN_2.io.intExceptionFlags, 2, 1) + node T_548 = neq(T_546, UInt<1>("h0")) + node T_550 = bits(RecFNToIN_2.io.intExceptionFlags, 0, 0) + node T_551 = cat(T_548, UInt<3>("h0")) + node T_552 = cat(T_551, T_550) + io.out.bits.exc <= T_552 + inst RecFNToIN_1_1 of RecFNToIN_1 RecFNToIN_1_1.io is invalid RecFNToIN_1_1.clk <= clk RecFNToIN_1_1.reset <= reset - RecFNToIN_1_1.io.in <= in.in1 @[fpu.scala 327:18] - RecFNToIN_1_1.io.roundingMode <= in.rm @[fpu.scala 328:28] - node T_553 = bits(in.typ, 0, 0) @[fpu.scala 329:35] - node T_554 = not(T_553) @[fpu.scala 329:28] - RecFNToIN_1_1.io.signedOut <= T_554 @[fpu.scala 329:25] - node T_555 = bits(in.typ, 1, 1) @[util.scala 25:13] - node T_557 = eq(T_555, UInt<1>("h01")) @[fpu.scala 330:44] - when T_557 : @[fpu.scala 330:51] - io.out.bits.toint <= RecFNToIN_1_1.io.out @[fpu.scala 331:27] - node T_558 = bits(RecFNToIN_1_1.io.intExceptionFlags, 2, 1) @[fpu.scala 332:57] - node T_560 = neq(T_558, UInt<1>("h00")) @[fpu.scala 332:64] - node T_562 = bits(RecFNToIN_1_1.io.intExceptionFlags, 0, 0) @[fpu.scala 332:106] - node T_563 = cat(T_560, UInt<3>("h00")) @[Cat.scala 20:58] - node T_564 = cat(T_563, T_562) @[Cat.scala 20:58] - io.out.bits.exc <= T_564 @[fpu.scala 332:25] - skip @[fpu.scala 330:51] - skip @[fpu.scala 322:33] - io.out.valid <= valid @[fpu.scala 337:16] - io.out.bits.lt <= dcmp.io.lt @[fpu.scala 338:18] - io.as_double <- in @[fpu.scala 339:16] - - module INToRecFN : + RecFNToIN_1_1.io.in <= in.in1 + RecFNToIN_1_1.io.roundingMode <= in.rm + node T_553 = bits(in.typ, 0, 0) + node T_554 = not(T_553) + RecFNToIN_1_1.io.signedOut <= T_554 + node T_555 = bits(in.typ, 1, 1) + node T_557 = eq(T_555, UInt<1>("h1")) + when T_557 : + io.out.bits.toint <= RecFNToIN_1_1.io.out + node T_558 = bits(RecFNToIN_1_1.io.intExceptionFlags, 2, 1) + node T_560 = neq(T_558, UInt<1>("h0")) + node T_562 = bits(RecFNToIN_1_1.io.intExceptionFlags, 0, 0) + node T_563 = cat(T_560, UInt<3>("h0")) + node T_564 = cat(T_563, T_562) + io.out.bits.exc <= T_564 + io.out.valid <= valid + io.out.bits.lt <= dcmp.io.lt + io.as_double <- in + + module INToRecFN : input clk : Clock input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - node T_5 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] - node sign = and(io.signedIn, T_5) @[INToRecFN.scala 55:28] - node T_7 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] - node T_8 = tail(T_7, 1) @[INToRecFN.scala 56:27] - node absIn = mux(sign, T_8, io.in) @[INToRecFN.scala 56:20] - node T_9 = shl(absIn, 0) @[INToRecFN.scala 57:32] - node T_10 = bits(T_9, 63, 32) @[CircuitMath.scala 26:17] - node T_11 = bits(T_9, 31, 0) @[CircuitMath.scala 27:17] - node T_13 = neq(T_10, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_14 = bits(T_10, 31, 16) @[CircuitMath.scala 26:17] - node T_15 = bits(T_10, 15, 0) @[CircuitMath.scala 27:17] - node T_17 = neq(T_14, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_18 = bits(T_14, 15, 8) @[CircuitMath.scala 26:17] - node T_19 = bits(T_14, 7, 0) @[CircuitMath.scala 27:17] - node T_21 = neq(T_18, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_22 = bits(T_18, 7, 4) @[CircuitMath.scala 26:17] - node T_23 = bits(T_18, 3, 0) @[CircuitMath.scala 27:17] - node T_25 = neq(T_22, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_26 = bits(T_22, 3, 3) @[CircuitMath.scala 23:12] - node T_28 = bits(T_22, 2, 2) @[CircuitMath.scala 23:12] - node T_30 = bits(T_22, 1, 1) @[CircuitMath.scala 21:8] - node T_31 = shl(T_30, 0) @[CircuitMath.scala 23:10] - node T_32 = mux(T_28, UInt<2>("h02"), T_31) @[CircuitMath.scala 23:10] - node T_33 = mux(T_26, UInt<2>("h03"), T_32) @[CircuitMath.scala 23:10] - node T_34 = bits(T_23, 3, 3) @[CircuitMath.scala 23:12] - node T_36 = bits(T_23, 2, 2) @[CircuitMath.scala 23:12] - node T_38 = bits(T_23, 1, 1) @[CircuitMath.scala 21:8] - node T_39 = shl(T_38, 0) @[CircuitMath.scala 23:10] - node T_40 = mux(T_36, UInt<2>("h02"), T_39) @[CircuitMath.scala 23:10] - node T_41 = mux(T_34, UInt<2>("h03"), T_40) @[CircuitMath.scala 23:10] - node T_42 = mux(T_25, T_33, T_41) @[CircuitMath.scala 29:21] - node T_43 = cat(T_25, T_42) @[Cat.scala 20:58] - node T_44 = bits(T_19, 7, 4) @[CircuitMath.scala 26:17] - node T_45 = bits(T_19, 3, 0) @[CircuitMath.scala 27:17] - node T_47 = neq(T_44, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_48 = bits(T_44, 3, 3) @[CircuitMath.scala 23:12] - node T_50 = bits(T_44, 2, 2) @[CircuitMath.scala 23:12] - node T_52 = bits(T_44, 1, 1) @[CircuitMath.scala 21:8] - node T_53 = shl(T_52, 0) @[CircuitMath.scala 23:10] - node T_54 = mux(T_50, UInt<2>("h02"), T_53) @[CircuitMath.scala 23:10] - node T_55 = mux(T_48, UInt<2>("h03"), T_54) @[CircuitMath.scala 23:10] - node T_56 = bits(T_45, 3, 3) @[CircuitMath.scala 23:12] - node T_58 = bits(T_45, 2, 2) @[CircuitMath.scala 23:12] - node T_60 = bits(T_45, 1, 1) @[CircuitMath.scala 21:8] - node T_61 = shl(T_60, 0) @[CircuitMath.scala 23:10] - node T_62 = mux(T_58, UInt<2>("h02"), T_61) @[CircuitMath.scala 23:10] - node T_63 = mux(T_56, UInt<2>("h03"), T_62) @[CircuitMath.scala 23:10] - node T_64 = mux(T_47, T_55, T_63) @[CircuitMath.scala 29:21] - node T_65 = cat(T_47, T_64) @[Cat.scala 20:58] - node T_66 = mux(T_21, T_43, T_65) @[CircuitMath.scala 29:21] - node T_67 = cat(T_21, T_66) @[Cat.scala 20:58] - node T_68 = bits(T_15, 15, 8) @[CircuitMath.scala 26:17] - node T_69 = bits(T_15, 7, 0) @[CircuitMath.scala 27:17] - node T_71 = neq(T_68, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_72 = bits(T_68, 7, 4) @[CircuitMath.scala 26:17] - node T_73 = bits(T_68, 3, 0) @[CircuitMath.scala 27:17] - node T_75 = neq(T_72, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_76 = bits(T_72, 3, 3) @[CircuitMath.scala 23:12] - node T_78 = bits(T_72, 2, 2) @[CircuitMath.scala 23:12] - node T_80 = bits(T_72, 1, 1) @[CircuitMath.scala 21:8] - node T_81 = shl(T_80, 0) @[CircuitMath.scala 23:10] - node T_82 = mux(T_78, UInt<2>("h02"), T_81) @[CircuitMath.scala 23:10] - node T_83 = mux(T_76, UInt<2>("h03"), T_82) @[CircuitMath.scala 23:10] - node T_84 = bits(T_73, 3, 3) @[CircuitMath.scala 23:12] - node T_86 = bits(T_73, 2, 2) @[CircuitMath.scala 23:12] - node T_88 = bits(T_73, 1, 1) @[CircuitMath.scala 21:8] - node T_89 = shl(T_88, 0) @[CircuitMath.scala 23:10] - node T_90 = mux(T_86, UInt<2>("h02"), T_89) @[CircuitMath.scala 23:10] - node T_91 = mux(T_84, UInt<2>("h03"), T_90) @[CircuitMath.scala 23:10] - node T_92 = mux(T_75, T_83, T_91) @[CircuitMath.scala 29:21] - node T_93 = cat(T_75, T_92) @[Cat.scala 20:58] - node T_94 = bits(T_69, 7, 4) @[CircuitMath.scala 26:17] - node T_95 = bits(T_69, 3, 0) @[CircuitMath.scala 27:17] - node T_97 = neq(T_94, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_98 = bits(T_94, 3, 3) @[CircuitMath.scala 23:12] - node T_100 = bits(T_94, 2, 2) @[CircuitMath.scala 23:12] - node T_102 = bits(T_94, 1, 1) @[CircuitMath.scala 21:8] - node T_103 = shl(T_102, 0) @[CircuitMath.scala 23:10] - node T_104 = mux(T_100, UInt<2>("h02"), T_103) @[CircuitMath.scala 23:10] - node T_105 = mux(T_98, UInt<2>("h03"), T_104) @[CircuitMath.scala 23:10] - node T_106 = bits(T_95, 3, 3) @[CircuitMath.scala 23:12] - node T_108 = bits(T_95, 2, 2) @[CircuitMath.scala 23:12] - node T_110 = bits(T_95, 1, 1) @[CircuitMath.scala 21:8] - node T_111 = shl(T_110, 0) @[CircuitMath.scala 23:10] - node T_112 = mux(T_108, UInt<2>("h02"), T_111) @[CircuitMath.scala 23:10] - node T_113 = mux(T_106, UInt<2>("h03"), T_112) @[CircuitMath.scala 23:10] - node T_114 = mux(T_97, T_105, T_113) @[CircuitMath.scala 29:21] - node T_115 = cat(T_97, T_114) @[Cat.scala 20:58] - node T_116 = mux(T_71, T_93, T_115) @[CircuitMath.scala 29:21] - node T_117 = cat(T_71, T_116) @[Cat.scala 20:58] - node T_118 = mux(T_17, T_67, T_117) @[CircuitMath.scala 29:21] - node T_119 = cat(T_17, T_118) @[Cat.scala 20:58] - node T_120 = bits(T_11, 31, 16) @[CircuitMath.scala 26:17] - node T_121 = bits(T_11, 15, 0) @[CircuitMath.scala 27:17] - node T_123 = neq(T_120, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_124 = bits(T_120, 15, 8) @[CircuitMath.scala 26:17] - node T_125 = bits(T_120, 7, 0) @[CircuitMath.scala 27:17] - node T_127 = neq(T_124, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_128 = bits(T_124, 7, 4) @[CircuitMath.scala 26:17] - node T_129 = bits(T_124, 3, 0) @[CircuitMath.scala 27:17] - node T_131 = neq(T_128, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_132 = bits(T_128, 3, 3) @[CircuitMath.scala 23:12] - node T_134 = bits(T_128, 2, 2) @[CircuitMath.scala 23:12] - node T_136 = bits(T_128, 1, 1) @[CircuitMath.scala 21:8] - node T_137 = shl(T_136, 0) @[CircuitMath.scala 23:10] - node T_138 = mux(T_134, UInt<2>("h02"), T_137) @[CircuitMath.scala 23:10] - node T_139 = mux(T_132, UInt<2>("h03"), T_138) @[CircuitMath.scala 23:10] - node T_140 = bits(T_129, 3, 3) @[CircuitMath.scala 23:12] - node T_142 = bits(T_129, 2, 2) @[CircuitMath.scala 23:12] - node T_144 = bits(T_129, 1, 1) @[CircuitMath.scala 21:8] - node T_145 = shl(T_144, 0) @[CircuitMath.scala 23:10] - node T_146 = mux(T_142, UInt<2>("h02"), T_145) @[CircuitMath.scala 23:10] - node T_147 = mux(T_140, UInt<2>("h03"), T_146) @[CircuitMath.scala 23:10] - node T_148 = mux(T_131, T_139, T_147) @[CircuitMath.scala 29:21] - node T_149 = cat(T_131, T_148) @[Cat.scala 20:58] - node T_150 = bits(T_125, 7, 4) @[CircuitMath.scala 26:17] - node T_151 = bits(T_125, 3, 0) @[CircuitMath.scala 27:17] - node T_153 = neq(T_150, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_154 = bits(T_150, 3, 3) @[CircuitMath.scala 23:12] - node T_156 = bits(T_150, 2, 2) @[CircuitMath.scala 23:12] - node T_158 = bits(T_150, 1, 1) @[CircuitMath.scala 21:8] - node T_159 = shl(T_158, 0) @[CircuitMath.scala 23:10] - node T_160 = mux(T_156, UInt<2>("h02"), T_159) @[CircuitMath.scala 23:10] - node T_161 = mux(T_154, UInt<2>("h03"), T_160) @[CircuitMath.scala 23:10] - node T_162 = bits(T_151, 3, 3) @[CircuitMath.scala 23:12] - node T_164 = bits(T_151, 2, 2) @[CircuitMath.scala 23:12] - node T_166 = bits(T_151, 1, 1) @[CircuitMath.scala 21:8] - node T_167 = shl(T_166, 0) @[CircuitMath.scala 23:10] - node T_168 = mux(T_164, UInt<2>("h02"), T_167) @[CircuitMath.scala 23:10] - node T_169 = mux(T_162, UInt<2>("h03"), T_168) @[CircuitMath.scala 23:10] - node T_170 = mux(T_153, T_161, T_169) @[CircuitMath.scala 29:21] - node T_171 = cat(T_153, T_170) @[Cat.scala 20:58] - node T_172 = mux(T_127, T_149, T_171) @[CircuitMath.scala 29:21] - node T_173 = cat(T_127, T_172) @[Cat.scala 20:58] - node T_174 = bits(T_121, 15, 8) @[CircuitMath.scala 26:17] - node T_175 = bits(T_121, 7, 0) @[CircuitMath.scala 27:17] - node T_177 = neq(T_174, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_178 = bits(T_174, 7, 4) @[CircuitMath.scala 26:17] - node T_179 = bits(T_174, 3, 0) @[CircuitMath.scala 27:17] - node T_181 = neq(T_178, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_182 = bits(T_178, 3, 3) @[CircuitMath.scala 23:12] - node T_184 = bits(T_178, 2, 2) @[CircuitMath.scala 23:12] - node T_186 = bits(T_178, 1, 1) @[CircuitMath.scala 21:8] - node T_187 = shl(T_186, 0) @[CircuitMath.scala 23:10] - node T_188 = mux(T_184, UInt<2>("h02"), T_187) @[CircuitMath.scala 23:10] - node T_189 = mux(T_182, UInt<2>("h03"), T_188) @[CircuitMath.scala 23:10] - node T_190 = bits(T_179, 3, 3) @[CircuitMath.scala 23:12] - node T_192 = bits(T_179, 2, 2) @[CircuitMath.scala 23:12] - node T_194 = bits(T_179, 1, 1) @[CircuitMath.scala 21:8] - node T_195 = shl(T_194, 0) @[CircuitMath.scala 23:10] - node T_196 = mux(T_192, UInt<2>("h02"), T_195) @[CircuitMath.scala 23:10] - node T_197 = mux(T_190, UInt<2>("h03"), T_196) @[CircuitMath.scala 23:10] - node T_198 = mux(T_181, T_189, T_197) @[CircuitMath.scala 29:21] - node T_199 = cat(T_181, T_198) @[Cat.scala 20:58] - node T_200 = bits(T_175, 7, 4) @[CircuitMath.scala 26:17] - node T_201 = bits(T_175, 3, 0) @[CircuitMath.scala 27:17] - node T_203 = neq(T_200, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_204 = bits(T_200, 3, 3) @[CircuitMath.scala 23:12] - node T_206 = bits(T_200, 2, 2) @[CircuitMath.scala 23:12] - node T_208 = bits(T_200, 1, 1) @[CircuitMath.scala 21:8] - node T_209 = shl(T_208, 0) @[CircuitMath.scala 23:10] - node T_210 = mux(T_206, UInt<2>("h02"), T_209) @[CircuitMath.scala 23:10] - node T_211 = mux(T_204, UInt<2>("h03"), T_210) @[CircuitMath.scala 23:10] - node T_212 = bits(T_201, 3, 3) @[CircuitMath.scala 23:12] - node T_214 = bits(T_201, 2, 2) @[CircuitMath.scala 23:12] - node T_216 = bits(T_201, 1, 1) @[CircuitMath.scala 21:8] - node T_217 = shl(T_216, 0) @[CircuitMath.scala 23:10] - node T_218 = mux(T_214, UInt<2>("h02"), T_217) @[CircuitMath.scala 23:10] - node T_219 = mux(T_212, UInt<2>("h03"), T_218) @[CircuitMath.scala 23:10] - node T_220 = mux(T_203, T_211, T_219) @[CircuitMath.scala 29:21] - node T_221 = cat(T_203, T_220) @[Cat.scala 20:58] - node T_222 = mux(T_177, T_199, T_221) @[CircuitMath.scala 29:21] - node T_223 = cat(T_177, T_222) @[Cat.scala 20:58] - node T_224 = mux(T_123, T_173, T_223) @[CircuitMath.scala 29:21] - node T_225 = cat(T_123, T_224) @[Cat.scala 20:58] - node T_226 = mux(T_13, T_119, T_225) @[CircuitMath.scala 29:21] - node T_227 = cat(T_13, T_226) @[Cat.scala 20:58] - node normCount = not(T_227) @[INToRecFN.scala 57:21] - node T_228 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] - node normAbsIn = bits(T_228, 63, 0) @[INToRecFN.scala 58:39] - node T_230 = bits(normAbsIn, 40, 39) @[INToRecFN.scala 63:26] - node T_231 = bits(normAbsIn, 38, 0) @[INToRecFN.scala 64:26] - node T_233 = neq(T_231, UInt<1>("h00")) @[INToRecFN.scala 64:55] - node roundBits = cat(T_230, T_233) @[Cat.scala 20:58] - node T_234 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] - node roundInexact = neq(T_234, UInt<1>("h00")) @[INToRecFN.scala 72:40] - node T_236 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] - node T_237 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] - node T_238 = not(T_237) @[INToRecFN.scala 75:29] - node T_240 = eq(T_238, UInt<1>("h00")) @[INToRecFN.scala 75:29] - node T_241 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] - node T_242 = not(T_241) @[INToRecFN.scala 75:53] - node T_244 = eq(T_242, UInt<1>("h00")) @[INToRecFN.scala 75:53] - node T_245 = or(T_240, T_244) @[INToRecFN.scala 75:34] - node T_247 = mux(T_236, T_245, UInt<1>("h00")) @[INToRecFN.scala 74:12] - node T_248 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] - node T_249 = and(sign, roundInexact) @[INToRecFN.scala 79:18] - node T_251 = mux(T_248, T_249, UInt<1>("h00")) @[INToRecFN.scala 78:12] - node T_252 = or(T_247, T_251) @[INToRecFN.scala 77:11] - node T_253 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] - node T_255 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] - node T_256 = and(T_255, roundInexact) @[INToRecFN.scala 83:20] - node T_258 = mux(T_253, T_256, UInt<1>("h00")) @[INToRecFN.scala 82:12] - node round = or(T_252, T_258) @[INToRecFN.scala 81:11] - node T_260 = bits(normAbsIn, 63, 40) @[INToRecFN.scala 89:34] - node unroundedNorm = cat(UInt<1>("h00"), T_260) @[Cat.scala 20:58] - node T_263 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] - node T_264 = tail(T_263, 1) @[INToRecFN.scala 94:48] - node roundedNorm = mux(round, T_264, unroundedNorm) @[INToRecFN.scala 94:26] - node T_265 = not(normCount) @[INToRecFN.scala 97:24] - node unroundedExp = cat(UInt<1>("h00"), T_265) @[Cat.scala 20:58] - node T_268 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 20:58] - node T_269 = bits(roundedNorm, 24, 24) @[INToRecFN.scala 106:65] - node T_270 = add(T_268, T_269) @[INToRecFN.scala 106:52] - node roundedExp = tail(T_270, 1) @[INToRecFN.scala 106:52] - node T_271 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] - node T_273 = bits(roundedExp, 7, 0) @[INToRecFN.scala 115:27] - node T_274 = mux(UInt<1>("h00"), UInt<8>("h080"), T_273) @[INToRecFN.scala 113:16] - node expOut = cat(T_271, T_274) @[Cat.scala 20:58] - node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] - node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] - node T_275 = bits(roundedNorm, 22, 0) @[INToRecFN.scala 122:44] - node T_276 = cat(sign, expOut) @[Cat.scala 20:58] - node T_277 = cat(T_276, T_275) @[Cat.scala 20:58] - io.out <= T_277 @[INToRecFN.scala 122:12] - node T_280 = cat(UInt<1>("h00"), inexact) @[Cat.scala 20:58] - node T_281 = cat(UInt<2>("h00"), overflow) @[Cat.scala 20:58] - node T_282 = cat(T_281, T_280) @[Cat.scala 20:58] - io.exceptionFlags <= T_282 @[INToRecFN.scala 123:23] - - module INToRecFN_1 : + node T_5 = bits(io.in, 63, 63) + node sign = and(io.signedIn, T_5) + node T_7 = sub(UInt<1>("h0"), io.in) + node T_8 = tail(T_7, 1) + node absIn = mux(sign, T_8, io.in) + node T_9 = shl(absIn, 0) + node T_10 = bits(T_9, 63, 32) + node T_11 = bits(T_9, 31, 0) + node T_13 = neq(T_10, UInt<1>("h0")) + node T_14 = bits(T_10, 31, 16) + node T_15 = bits(T_10, 15, 0) + node T_17 = neq(T_14, UInt<1>("h0")) + node T_18 = bits(T_14, 15, 8) + node T_19 = bits(T_14, 7, 0) + node T_21 = neq(T_18, UInt<1>("h0")) + node T_22 = bits(T_18, 7, 4) + node T_23 = bits(T_18, 3, 0) + node T_25 = neq(T_22, UInt<1>("h0")) + node T_26 = bits(T_22, 3, 3) + node T_28 = bits(T_22, 2, 2) + node T_30 = bits(T_22, 1, 1) + node T_31 = shl(T_30, 0) + node T_32 = mux(T_28, UInt<2>("h2"), T_31) + node T_33 = mux(T_26, UInt<2>("h3"), T_32) + node T_34 = bits(T_23, 3, 3) + node T_36 = bits(T_23, 2, 2) + node T_38 = bits(T_23, 1, 1) + node T_39 = shl(T_38, 0) + node T_40 = mux(T_36, UInt<2>("h2"), T_39) + node T_41 = mux(T_34, UInt<2>("h3"), T_40) + node T_42 = mux(T_25, T_33, T_41) + node T_43 = cat(T_25, T_42) + node T_44 = bits(T_19, 7, 4) + node T_45 = bits(T_19, 3, 0) + node T_47 = neq(T_44, UInt<1>("h0")) + node T_48 = bits(T_44, 3, 3) + node T_50 = bits(T_44, 2, 2) + node T_52 = bits(T_44, 1, 1) + node T_53 = shl(T_52, 0) + node T_54 = mux(T_50, UInt<2>("h2"), T_53) + node T_55 = mux(T_48, UInt<2>("h3"), T_54) + node T_56 = bits(T_45, 3, 3) + node T_58 = bits(T_45, 2, 2) + node T_60 = bits(T_45, 1, 1) + node T_61 = shl(T_60, 0) + node T_62 = mux(T_58, UInt<2>("h2"), T_61) + node T_63 = mux(T_56, UInt<2>("h3"), T_62) + node T_64 = mux(T_47, T_55, T_63) + node T_65 = cat(T_47, T_64) + node T_66 = mux(T_21, T_43, T_65) + node T_67 = cat(T_21, T_66) + node T_68 = bits(T_15, 15, 8) + node T_69 = bits(T_15, 7, 0) + node T_71 = neq(T_68, UInt<1>("h0")) + node T_72 = bits(T_68, 7, 4) + node T_73 = bits(T_68, 3, 0) + node T_75 = neq(T_72, UInt<1>("h0")) + node T_76 = bits(T_72, 3, 3) + node T_78 = bits(T_72, 2, 2) + node T_80 = bits(T_72, 1, 1) + node T_81 = shl(T_80, 0) + node T_82 = mux(T_78, UInt<2>("h2"), T_81) + node T_83 = mux(T_76, UInt<2>("h3"), T_82) + node T_84 = bits(T_73, 3, 3) + node T_86 = bits(T_73, 2, 2) + node T_88 = bits(T_73, 1, 1) + node T_89 = shl(T_88, 0) + node T_90 = mux(T_86, UInt<2>("h2"), T_89) + node T_91 = mux(T_84, UInt<2>("h3"), T_90) + node T_92 = mux(T_75, T_83, T_91) + node T_93 = cat(T_75, T_92) + node T_94 = bits(T_69, 7, 4) + node T_95 = bits(T_69, 3, 0) + node T_97 = neq(T_94, UInt<1>("h0")) + node T_98 = bits(T_94, 3, 3) + node T_100 = bits(T_94, 2, 2) + node T_102 = bits(T_94, 1, 1) + node T_103 = shl(T_102, 0) + node T_104 = mux(T_100, UInt<2>("h2"), T_103) + node T_105 = mux(T_98, UInt<2>("h3"), T_104) + node T_106 = bits(T_95, 3, 3) + node T_108 = bits(T_95, 2, 2) + node T_110 = bits(T_95, 1, 1) + node T_111 = shl(T_110, 0) + node T_112 = mux(T_108, UInt<2>("h2"), T_111) + node T_113 = mux(T_106, UInt<2>("h3"), T_112) + node T_114 = mux(T_97, T_105, T_113) + node T_115 = cat(T_97, T_114) + node T_116 = mux(T_71, T_93, T_115) + node T_117 = cat(T_71, T_116) + node T_118 = mux(T_17, T_67, T_117) + node T_119 = cat(T_17, T_118) + node T_120 = bits(T_11, 31, 16) + node T_121 = bits(T_11, 15, 0) + node T_123 = neq(T_120, UInt<1>("h0")) + node T_124 = bits(T_120, 15, 8) + node T_125 = bits(T_120, 7, 0) + node T_127 = neq(T_124, UInt<1>("h0")) + node T_128 = bits(T_124, 7, 4) + node T_129 = bits(T_124, 3, 0) + node T_131 = neq(T_128, UInt<1>("h0")) + node T_132 = bits(T_128, 3, 3) + node T_134 = bits(T_128, 2, 2) + node T_136 = bits(T_128, 1, 1) + node T_137 = shl(T_136, 0) + node T_138 = mux(T_134, UInt<2>("h2"), T_137) + node T_139 = mux(T_132, UInt<2>("h3"), T_138) + node T_140 = bits(T_129, 3, 3) + node T_142 = bits(T_129, 2, 2) + node T_144 = bits(T_129, 1, 1) + node T_145 = shl(T_144, 0) + node T_146 = mux(T_142, UInt<2>("h2"), T_145) + node T_147 = mux(T_140, UInt<2>("h3"), T_146) + node T_148 = mux(T_131, T_139, T_147) + node T_149 = cat(T_131, T_148) + node T_150 = bits(T_125, 7, 4) + node T_151 = bits(T_125, 3, 0) + node T_153 = neq(T_150, UInt<1>("h0")) + node T_154 = bits(T_150, 3, 3) + node T_156 = bits(T_150, 2, 2) + node T_158 = bits(T_150, 1, 1) + node T_159 = shl(T_158, 0) + node T_160 = mux(T_156, UInt<2>("h2"), T_159) + node T_161 = mux(T_154, UInt<2>("h3"), T_160) + node T_162 = bits(T_151, 3, 3) + node T_164 = bits(T_151, 2, 2) + node T_166 = bits(T_151, 1, 1) + node T_167 = shl(T_166, 0) + node T_168 = mux(T_164, UInt<2>("h2"), T_167) + node T_169 = mux(T_162, UInt<2>("h3"), T_168) + node T_170 = mux(T_153, T_161, T_169) + node T_171 = cat(T_153, T_170) + node T_172 = mux(T_127, T_149, T_171) + node T_173 = cat(T_127, T_172) + node T_174 = bits(T_121, 15, 8) + node T_175 = bits(T_121, 7, 0) + node T_177 = neq(T_174, UInt<1>("h0")) + node T_178 = bits(T_174, 7, 4) + node T_179 = bits(T_174, 3, 0) + node T_181 = neq(T_178, UInt<1>("h0")) + node T_182 = bits(T_178, 3, 3) + node T_184 = bits(T_178, 2, 2) + node T_186 = bits(T_178, 1, 1) + node T_187 = shl(T_186, 0) + node T_188 = mux(T_184, UInt<2>("h2"), T_187) + node T_189 = mux(T_182, UInt<2>("h3"), T_188) + node T_190 = bits(T_179, 3, 3) + node T_192 = bits(T_179, 2, 2) + node T_194 = bits(T_179, 1, 1) + node T_195 = shl(T_194, 0) + node T_196 = mux(T_192, UInt<2>("h2"), T_195) + node T_197 = mux(T_190, UInt<2>("h3"), T_196) + node T_198 = mux(T_181, T_189, T_197) + node T_199 = cat(T_181, T_198) + node T_200 = bits(T_175, 7, 4) + node T_201 = bits(T_175, 3, 0) + node T_203 = neq(T_200, UInt<1>("h0")) + node T_204 = bits(T_200, 3, 3) + node T_206 = bits(T_200, 2, 2) + node T_208 = bits(T_200, 1, 1) + node T_209 = shl(T_208, 0) + node T_210 = mux(T_206, UInt<2>("h2"), T_209) + node T_211 = mux(T_204, UInt<2>("h3"), T_210) + node T_212 = bits(T_201, 3, 3) + node T_214 = bits(T_201, 2, 2) + node T_216 = bits(T_201, 1, 1) + node T_217 = shl(T_216, 0) + node T_218 = mux(T_214, UInt<2>("h2"), T_217) + node T_219 = mux(T_212, UInt<2>("h3"), T_218) + node T_220 = mux(T_203, T_211, T_219) + node T_221 = cat(T_203, T_220) + node T_222 = mux(T_177, T_199, T_221) + node T_223 = cat(T_177, T_222) + node T_224 = mux(T_123, T_173, T_223) + node T_225 = cat(T_123, T_224) + node T_226 = mux(T_13, T_119, T_225) + node T_227 = cat(T_13, T_226) + node normCount = not(T_227) + node T_228 = dshl(absIn, normCount) + node normAbsIn = bits(T_228, 63, 0) + node T_230 = bits(normAbsIn, 40, 39) + node T_231 = bits(normAbsIn, 38, 0) + node T_233 = neq(T_231, UInt<1>("h0")) + node roundBits = cat(T_230, T_233) + node T_234 = bits(roundBits, 1, 0) + node roundInexact = neq(T_234, UInt<1>("h0")) + node T_236 = eq(io.roundingMode, UInt<2>("h0")) + node T_237 = bits(roundBits, 2, 1) + node T_238 = not(T_237) + node T_240 = eq(T_238, UInt<1>("h0")) + node T_241 = bits(roundBits, 1, 0) + node T_242 = not(T_241) + node T_244 = eq(T_242, UInt<1>("h0")) + node T_245 = or(T_240, T_244) + node T_247 = mux(T_236, T_245, UInt<1>("h0")) + node T_248 = eq(io.roundingMode, UInt<2>("h2")) + node T_249 = and(sign, roundInexact) + node T_251 = mux(T_248, T_249, UInt<1>("h0")) + node T_252 = or(T_247, T_251) + node T_253 = eq(io.roundingMode, UInt<2>("h3")) + node T_255 = eq(sign, UInt<1>("h0")) + node T_256 = and(T_255, roundInexact) + node T_258 = mux(T_253, T_256, UInt<1>("h0")) + node round = or(T_252, T_258) + node T_260 = bits(normAbsIn, 63, 40) + node unroundedNorm = cat(UInt<1>("h0"), T_260) + node T_263 = add(unroundedNorm, UInt<1>("h1")) + node T_264 = tail(T_263, 1) + node roundedNorm = mux(round, T_264, unroundedNorm) + node T_265 = not(normCount) + node unroundedExp = cat(UInt<1>("h0"), T_265) + node T_268 = cat(UInt<1>("h0"), unroundedExp) + node T_269 = bits(roundedNorm, 24, 24) + node T_270 = add(T_268, T_269) + node roundedExp = tail(T_270, 1) + node T_271 = bits(normAbsIn, 63, 63) + node T_273 = bits(roundedExp, 7, 0) + node T_274 = mux(UInt<1>("h0"), UInt<8>("h80"), T_273) + node expOut = cat(T_271, T_274) + node overflow = or(UInt<1>("h0"), UInt<1>("h0")) + node inexact = or(roundInexact, overflow) + node T_275 = bits(roundedNorm, 22, 0) + node T_276 = cat(sign, expOut) + node T_277 = cat(T_276, T_275) + io.out <= T_277 + node T_280 = cat(UInt<1>("h0"), inexact) + node T_281 = cat(UInt<2>("h0"), overflow) + node T_282 = cat(T_281, T_280) + io.exceptionFlags <= T_282 + + module INToRecFN_1 : input clk : Clock input reset : UInt<1> - output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - + output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + io is invalid - node T_5 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] - node sign = and(io.signedIn, T_5) @[INToRecFN.scala 55:28] - node T_7 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] - node T_8 = tail(T_7, 1) @[INToRecFN.scala 56:27] - node absIn = mux(sign, T_8, io.in) @[INToRecFN.scala 56:20] - node T_9 = shl(absIn, 0) @[INToRecFN.scala 57:32] - node T_10 = bits(T_9, 63, 32) @[CircuitMath.scala 26:17] - node T_11 = bits(T_9, 31, 0) @[CircuitMath.scala 27:17] - node T_13 = neq(T_10, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_14 = bits(T_10, 31, 16) @[CircuitMath.scala 26:17] - node T_15 = bits(T_10, 15, 0) @[CircuitMath.scala 27:17] - node T_17 = neq(T_14, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_18 = bits(T_14, 15, 8) @[CircuitMath.scala 26:17] - node T_19 = bits(T_14, 7, 0) @[CircuitMath.scala 27:17] - node T_21 = neq(T_18, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_22 = bits(T_18, 7, 4) @[CircuitMath.scala 26:17] - node T_23 = bits(T_18, 3, 0) @[CircuitMath.scala 27:17] - node T_25 = neq(T_22, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_26 = bits(T_22, 3, 3) @[CircuitMath.scala 23:12] - node T_28 = bits(T_22, 2, 2) @[CircuitMath.scala 23:12] - node T_30 = bits(T_22, 1, 1) @[CircuitMath.scala 21:8] - node T_31 = shl(T_30, 0) @[CircuitMath.scala 23:10] - node T_32 = mux(T_28, UInt<2>("h02"), T_31) @[CircuitMath.scala 23:10] - node T_33 = mux(T_26, UInt<2>("h03"), T_32) @[CircuitMath.scala 23:10] - node T_34 = bits(T_23, 3, 3) @[CircuitMath.scala 23:12] - node T_36 = bits(T_23, 2, 2) @[CircuitMath.scala 23:12] - node T_38 = bits(T_23, 1, 1) @[CircuitMath.scala 21:8] - node T_39 = shl(T_38, 0) @[CircuitMath.scala 23:10] - node T_40 = mux(T_36, UInt<2>("h02"), T_39) @[CircuitMath.scala 23:10] - node T_41 = mux(T_34, UInt<2>("h03"), T_40) @[CircuitMath.scala 23:10] - node T_42 = mux(T_25, T_33, T_41) @[CircuitMath.scala 29:21] - node T_43 = cat(T_25, T_42) @[Cat.scala 20:58] - node T_44 = bits(T_19, 7, 4) @[CircuitMath.scala 26:17] - node T_45 = bits(T_19, 3, 0) @[CircuitMath.scala 27:17] - node T_47 = neq(T_44, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_48 = bits(T_44, 3, 3) @[CircuitMath.scala 23:12] - node T_50 = bits(T_44, 2, 2) @[CircuitMath.scala 23:12] - node T_52 = bits(T_44, 1, 1) @[CircuitMath.scala 21:8] - node T_53 = shl(T_52, 0) @[CircuitMath.scala 23:10] - node T_54 = mux(T_50, UInt<2>("h02"), T_53) @[CircuitMath.scala 23:10] - node T_55 = mux(T_48, UInt<2>("h03"), T_54) @[CircuitMath.scala 23:10] - node T_56 = bits(T_45, 3, 3) @[CircuitMath.scala 23:12] - node T_58 = bits(T_45, 2, 2) @[CircuitMath.scala 23:12] - node T_60 = bits(T_45, 1, 1) @[CircuitMath.scala 21:8] - node T_61 = shl(T_60, 0) @[CircuitMath.scala 23:10] - node T_62 = mux(T_58, UInt<2>("h02"), T_61) @[CircuitMath.scala 23:10] - node T_63 = mux(T_56, UInt<2>("h03"), T_62) @[CircuitMath.scala 23:10] - node T_64 = mux(T_47, T_55, T_63) @[CircuitMath.scala 29:21] - node T_65 = cat(T_47, T_64) @[Cat.scala 20:58] - node T_66 = mux(T_21, T_43, T_65) @[CircuitMath.scala 29:21] - node T_67 = cat(T_21, T_66) @[Cat.scala 20:58] - node T_68 = bits(T_15, 15, 8) @[CircuitMath.scala 26:17] - node T_69 = bits(T_15, 7, 0) @[CircuitMath.scala 27:17] - node T_71 = neq(T_68, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_72 = bits(T_68, 7, 4) @[CircuitMath.scala 26:17] - node T_73 = bits(T_68, 3, 0) @[CircuitMath.scala 27:17] - node T_75 = neq(T_72, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_76 = bits(T_72, 3, 3) @[CircuitMath.scala 23:12] - node T_78 = bits(T_72, 2, 2) @[CircuitMath.scala 23:12] - node T_80 = bits(T_72, 1, 1) @[CircuitMath.scala 21:8] - node T_81 = shl(T_80, 0) @[CircuitMath.scala 23:10] - node T_82 = mux(T_78, UInt<2>("h02"), T_81) @[CircuitMath.scala 23:10] - node T_83 = mux(T_76, UInt<2>("h03"), T_82) @[CircuitMath.scala 23:10] - node T_84 = bits(T_73, 3, 3) @[CircuitMath.scala 23:12] - node T_86 = bits(T_73, 2, 2) @[CircuitMath.scala 23:12] - node T_88 = bits(T_73, 1, 1) @[CircuitMath.scala 21:8] - node T_89 = shl(T_88, 0) @[CircuitMath.scala 23:10] - node T_90 = mux(T_86, UInt<2>("h02"), T_89) @[CircuitMath.scala 23:10] - node T_91 = mux(T_84, UInt<2>("h03"), T_90) @[CircuitMath.scala 23:10] - node T_92 = mux(T_75, T_83, T_91) @[CircuitMath.scala 29:21] - node T_93 = cat(T_75, T_92) @[Cat.scala 20:58] - node T_94 = bits(T_69, 7, 4) @[CircuitMath.scala 26:17] - node T_95 = bits(T_69, 3, 0) @[CircuitMath.scala 27:17] - node T_97 = neq(T_94, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_98 = bits(T_94, 3, 3) @[CircuitMath.scala 23:12] - node T_100 = bits(T_94, 2, 2) @[CircuitMath.scala 23:12] - node T_102 = bits(T_94, 1, 1) @[CircuitMath.scala 21:8] - node T_103 = shl(T_102, 0) @[CircuitMath.scala 23:10] - node T_104 = mux(T_100, UInt<2>("h02"), T_103) @[CircuitMath.scala 23:10] - node T_105 = mux(T_98, UInt<2>("h03"), T_104) @[CircuitMath.scala 23:10] - node T_106 = bits(T_95, 3, 3) @[CircuitMath.scala 23:12] - node T_108 = bits(T_95, 2, 2) @[CircuitMath.scala 23:12] - node T_110 = bits(T_95, 1, 1) @[CircuitMath.scala 21:8] - node T_111 = shl(T_110, 0) @[CircuitMath.scala 23:10] - node T_112 = mux(T_108, UInt<2>("h02"), T_111) @[CircuitMath.scala 23:10] - node T_113 = mux(T_106, UInt<2>("h03"), T_112) @[CircuitMath.scala 23:10] - node T_114 = mux(T_97, T_105, T_113) @[CircuitMath.scala 29:21] - node T_115 = cat(T_97, T_114) @[Cat.scala 20:58] - node T_116 = mux(T_71, T_93, T_115) @[CircuitMath.scala 29:21] - node T_117 = cat(T_71, T_116) @[Cat.scala 20:58] - node T_118 = mux(T_17, T_67, T_117) @[CircuitMath.scala 29:21] - node T_119 = cat(T_17, T_118) @[Cat.scala 20:58] - node T_120 = bits(T_11, 31, 16) @[CircuitMath.scala 26:17] - node T_121 = bits(T_11, 15, 0) @[CircuitMath.scala 27:17] - node T_123 = neq(T_120, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_124 = bits(T_120, 15, 8) @[CircuitMath.scala 26:17] - node T_125 = bits(T_120, 7, 0) @[CircuitMath.scala 27:17] - node T_127 = neq(T_124, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_128 = bits(T_124, 7, 4) @[CircuitMath.scala 26:17] - node T_129 = bits(T_124, 3, 0) @[CircuitMath.scala 27:17] - node T_131 = neq(T_128, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_132 = bits(T_128, 3, 3) @[CircuitMath.scala 23:12] - node T_134 = bits(T_128, 2, 2) @[CircuitMath.scala 23:12] - node T_136 = bits(T_128, 1, 1) @[CircuitMath.scala 21:8] - node T_137 = shl(T_136, 0) @[CircuitMath.scala 23:10] - node T_138 = mux(T_134, UInt<2>("h02"), T_137) @[CircuitMath.scala 23:10] - node T_139 = mux(T_132, UInt<2>("h03"), T_138) @[CircuitMath.scala 23:10] - node T_140 = bits(T_129, 3, 3) @[CircuitMath.scala 23:12] - node T_142 = bits(T_129, 2, 2) @[CircuitMath.scala 23:12] - node T_144 = bits(T_129, 1, 1) @[CircuitMath.scala 21:8] - node T_145 = shl(T_144, 0) @[CircuitMath.scala 23:10] - node T_146 = mux(T_142, UInt<2>("h02"), T_145) @[CircuitMath.scala 23:10] - node T_147 = mux(T_140, UInt<2>("h03"), T_146) @[CircuitMath.scala 23:10] - node T_148 = mux(T_131, T_139, T_147) @[CircuitMath.scala 29:21] - node T_149 = cat(T_131, T_148) @[Cat.scala 20:58] - node T_150 = bits(T_125, 7, 4) @[CircuitMath.scala 26:17] - node T_151 = bits(T_125, 3, 0) @[CircuitMath.scala 27:17] - node T_153 = neq(T_150, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_154 = bits(T_150, 3, 3) @[CircuitMath.scala 23:12] - node T_156 = bits(T_150, 2, 2) @[CircuitMath.scala 23:12] - node T_158 = bits(T_150, 1, 1) @[CircuitMath.scala 21:8] - node T_159 = shl(T_158, 0) @[CircuitMath.scala 23:10] - node T_160 = mux(T_156, UInt<2>("h02"), T_159) @[CircuitMath.scala 23:10] - node T_161 = mux(T_154, UInt<2>("h03"), T_160) @[CircuitMath.scala 23:10] - node T_162 = bits(T_151, 3, 3) @[CircuitMath.scala 23:12] - node T_164 = bits(T_151, 2, 2) @[CircuitMath.scala 23:12] - node T_166 = bits(T_151, 1, 1) @[CircuitMath.scala 21:8] - node T_167 = shl(T_166, 0) @[CircuitMath.scala 23:10] - node T_168 = mux(T_164, UInt<2>("h02"), T_167) @[CircuitMath.scala 23:10] - node T_169 = mux(T_162, UInt<2>("h03"), T_168) @[CircuitMath.scala 23:10] - node T_170 = mux(T_153, T_161, T_169) @[CircuitMath.scala 29:21] - node T_171 = cat(T_153, T_170) @[Cat.scala 20:58] - node T_172 = mux(T_127, T_149, T_171) @[CircuitMath.scala 29:21] - node T_173 = cat(T_127, T_172) @[Cat.scala 20:58] - node T_174 = bits(T_121, 15, 8) @[CircuitMath.scala 26:17] - node T_175 = bits(T_121, 7, 0) @[CircuitMath.scala 27:17] - node T_177 = neq(T_174, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_178 = bits(T_174, 7, 4) @[CircuitMath.scala 26:17] - node T_179 = bits(T_174, 3, 0) @[CircuitMath.scala 27:17] - node T_181 = neq(T_178, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_182 = bits(T_178, 3, 3) @[CircuitMath.scala 23:12] - node T_184 = bits(T_178, 2, 2) @[CircuitMath.scala 23:12] - node T_186 = bits(T_178, 1, 1) @[CircuitMath.scala 21:8] - node T_187 = shl(T_186, 0) @[CircuitMath.scala 23:10] - node T_188 = mux(T_184, UInt<2>("h02"), T_187) @[CircuitMath.scala 23:10] - node T_189 = mux(T_182, UInt<2>("h03"), T_188) @[CircuitMath.scala 23:10] - node T_190 = bits(T_179, 3, 3) @[CircuitMath.scala 23:12] - node T_192 = bits(T_179, 2, 2) @[CircuitMath.scala 23:12] - node T_194 = bits(T_179, 1, 1) @[CircuitMath.scala 21:8] - node T_195 = shl(T_194, 0) @[CircuitMath.scala 23:10] - node T_196 = mux(T_192, UInt<2>("h02"), T_195) @[CircuitMath.scala 23:10] - node T_197 = mux(T_190, UInt<2>("h03"), T_196) @[CircuitMath.scala 23:10] - node T_198 = mux(T_181, T_189, T_197) @[CircuitMath.scala 29:21] - node T_199 = cat(T_181, T_198) @[Cat.scala 20:58] - node T_200 = bits(T_175, 7, 4) @[CircuitMath.scala 26:17] - node T_201 = bits(T_175, 3, 0) @[CircuitMath.scala 27:17] - node T_203 = neq(T_200, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_204 = bits(T_200, 3, 3) @[CircuitMath.scala 23:12] - node T_206 = bits(T_200, 2, 2) @[CircuitMath.scala 23:12] - node T_208 = bits(T_200, 1, 1) @[CircuitMath.scala 21:8] - node T_209 = shl(T_208, 0) @[CircuitMath.scala 23:10] - node T_210 = mux(T_206, UInt<2>("h02"), T_209) @[CircuitMath.scala 23:10] - node T_211 = mux(T_204, UInt<2>("h03"), T_210) @[CircuitMath.scala 23:10] - node T_212 = bits(T_201, 3, 3) @[CircuitMath.scala 23:12] - node T_214 = bits(T_201, 2, 2) @[CircuitMath.scala 23:12] - node T_216 = bits(T_201, 1, 1) @[CircuitMath.scala 21:8] - node T_217 = shl(T_216, 0) @[CircuitMath.scala 23:10] - node T_218 = mux(T_214, UInt<2>("h02"), T_217) @[CircuitMath.scala 23:10] - node T_219 = mux(T_212, UInt<2>("h03"), T_218) @[CircuitMath.scala 23:10] - node T_220 = mux(T_203, T_211, T_219) @[CircuitMath.scala 29:21] - node T_221 = cat(T_203, T_220) @[Cat.scala 20:58] - node T_222 = mux(T_177, T_199, T_221) @[CircuitMath.scala 29:21] - node T_223 = cat(T_177, T_222) @[Cat.scala 20:58] - node T_224 = mux(T_123, T_173, T_223) @[CircuitMath.scala 29:21] - node T_225 = cat(T_123, T_224) @[Cat.scala 20:58] - node T_226 = mux(T_13, T_119, T_225) @[CircuitMath.scala 29:21] - node T_227 = cat(T_13, T_226) @[Cat.scala 20:58] - node normCount = not(T_227) @[INToRecFN.scala 57:21] - node T_228 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] - node normAbsIn = bits(T_228, 63, 0) @[INToRecFN.scala 58:39] - node T_230 = bits(normAbsIn, 11, 10) @[INToRecFN.scala 63:26] - node T_231 = bits(normAbsIn, 9, 0) @[INToRecFN.scala 64:26] - node T_233 = neq(T_231, UInt<1>("h00")) @[INToRecFN.scala 64:55] - node roundBits = cat(T_230, T_233) @[Cat.scala 20:58] - node T_234 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] - node roundInexact = neq(T_234, UInt<1>("h00")) @[INToRecFN.scala 72:40] - node T_236 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] - node T_237 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] - node T_238 = not(T_237) @[INToRecFN.scala 75:29] - node T_240 = eq(T_238, UInt<1>("h00")) @[INToRecFN.scala 75:29] - node T_241 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] - node T_242 = not(T_241) @[INToRecFN.scala 75:53] - node T_244 = eq(T_242, UInt<1>("h00")) @[INToRecFN.scala 75:53] - node T_245 = or(T_240, T_244) @[INToRecFN.scala 75:34] - node T_247 = mux(T_236, T_245, UInt<1>("h00")) @[INToRecFN.scala 74:12] - node T_248 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] - node T_249 = and(sign, roundInexact) @[INToRecFN.scala 79:18] - node T_251 = mux(T_248, T_249, UInt<1>("h00")) @[INToRecFN.scala 78:12] - node T_252 = or(T_247, T_251) @[INToRecFN.scala 77:11] - node T_253 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] - node T_255 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] - node T_256 = and(T_255, roundInexact) @[INToRecFN.scala 83:20] - node T_258 = mux(T_253, T_256, UInt<1>("h00")) @[INToRecFN.scala 82:12] - node round = or(T_252, T_258) @[INToRecFN.scala 81:11] - node T_260 = bits(normAbsIn, 63, 11) @[INToRecFN.scala 89:34] - node unroundedNorm = cat(UInt<1>("h00"), T_260) @[Cat.scala 20:58] - node T_263 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] - node T_264 = tail(T_263, 1) @[INToRecFN.scala 94:48] - node roundedNorm = mux(round, T_264, unroundedNorm) @[INToRecFN.scala 94:26] - node T_265 = not(normCount) @[INToRecFN.scala 97:24] - node unroundedExp = cat(UInt<4>("h00"), T_265) @[Cat.scala 20:58] - node T_268 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 20:58] - node T_269 = bits(roundedNorm, 53, 53) @[INToRecFN.scala 106:65] - node T_270 = add(T_268, T_269) @[INToRecFN.scala 106:52] - node roundedExp = tail(T_270, 1) @[INToRecFN.scala 106:52] - node T_271 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] - node T_273 = bits(roundedExp, 10, 0) @[INToRecFN.scala 115:27] - node T_274 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_273) @[INToRecFN.scala 113:16] - node expOut = cat(T_271, T_274) @[Cat.scala 20:58] - node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] - node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] - node T_275 = bits(roundedNorm, 51, 0) @[INToRecFN.scala 122:44] - node T_276 = cat(sign, expOut) @[Cat.scala 20:58] - node T_277 = cat(T_276, T_275) @[Cat.scala 20:58] - io.out <= T_277 @[INToRecFN.scala 122:12] - node T_280 = cat(UInt<1>("h00"), inexact) @[Cat.scala 20:58] - node T_281 = cat(UInt<2>("h00"), overflow) @[Cat.scala 20:58] - node T_282 = cat(T_281, T_280) @[Cat.scala 20:58] - io.exceptionFlags <= T_282 @[INToRecFN.scala 123:23] - - module IntToFP : + node T_5 = bits(io.in, 63, 63) + node sign = and(io.signedIn, T_5) + node T_7 = sub(UInt<1>("h0"), io.in) + node T_8 = tail(T_7, 1) + node absIn = mux(sign, T_8, io.in) + node T_9 = shl(absIn, 0) + node T_10 = bits(T_9, 63, 32) + node T_11 = bits(T_9, 31, 0) + node T_13 = neq(T_10, UInt<1>("h0")) + node T_14 = bits(T_10, 31, 16) + node T_15 = bits(T_10, 15, 0) + node T_17 = neq(T_14, UInt<1>("h0")) + node T_18 = bits(T_14, 15, 8) + node T_19 = bits(T_14, 7, 0) + node T_21 = neq(T_18, UInt<1>("h0")) + node T_22 = bits(T_18, 7, 4) + node T_23 = bits(T_18, 3, 0) + node T_25 = neq(T_22, UInt<1>("h0")) + node T_26 = bits(T_22, 3, 3) + node T_28 = bits(T_22, 2, 2) + node T_30 = bits(T_22, 1, 1) + node T_31 = shl(T_30, 0) + node T_32 = mux(T_28, UInt<2>("h2"), T_31) + node T_33 = mux(T_26, UInt<2>("h3"), T_32) + node T_34 = bits(T_23, 3, 3) + node T_36 = bits(T_23, 2, 2) + node T_38 = bits(T_23, 1, 1) + node T_39 = shl(T_38, 0) + node T_40 = mux(T_36, UInt<2>("h2"), T_39) + node T_41 = mux(T_34, UInt<2>("h3"), T_40) + node T_42 = mux(T_25, T_33, T_41) + node T_43 = cat(T_25, T_42) + node T_44 = bits(T_19, 7, 4) + node T_45 = bits(T_19, 3, 0) + node T_47 = neq(T_44, UInt<1>("h0")) + node T_48 = bits(T_44, 3, 3) + node T_50 = bits(T_44, 2, 2) + node T_52 = bits(T_44, 1, 1) + node T_53 = shl(T_52, 0) + node T_54 = mux(T_50, UInt<2>("h2"), T_53) + node T_55 = mux(T_48, UInt<2>("h3"), T_54) + node T_56 = bits(T_45, 3, 3) + node T_58 = bits(T_45, 2, 2) + node T_60 = bits(T_45, 1, 1) + node T_61 = shl(T_60, 0) + node T_62 = mux(T_58, UInt<2>("h2"), T_61) + node T_63 = mux(T_56, UInt<2>("h3"), T_62) + node T_64 = mux(T_47, T_55, T_63) + node T_65 = cat(T_47, T_64) + node T_66 = mux(T_21, T_43, T_65) + node T_67 = cat(T_21, T_66) + node T_68 = bits(T_15, 15, 8) + node T_69 = bits(T_15, 7, 0) + node T_71 = neq(T_68, UInt<1>("h0")) + node T_72 = bits(T_68, 7, 4) + node T_73 = bits(T_68, 3, 0) + node T_75 = neq(T_72, UInt<1>("h0")) + node T_76 = bits(T_72, 3, 3) + node T_78 = bits(T_72, 2, 2) + node T_80 = bits(T_72, 1, 1) + node T_81 = shl(T_80, 0) + node T_82 = mux(T_78, UInt<2>("h2"), T_81) + node T_83 = mux(T_76, UInt<2>("h3"), T_82) + node T_84 = bits(T_73, 3, 3) + node T_86 = bits(T_73, 2, 2) + node T_88 = bits(T_73, 1, 1) + node T_89 = shl(T_88, 0) + node T_90 = mux(T_86, UInt<2>("h2"), T_89) + node T_91 = mux(T_84, UInt<2>("h3"), T_90) + node T_92 = mux(T_75, T_83, T_91) + node T_93 = cat(T_75, T_92) + node T_94 = bits(T_69, 7, 4) + node T_95 = bits(T_69, 3, 0) + node T_97 = neq(T_94, UInt<1>("h0")) + node T_98 = bits(T_94, 3, 3) + node T_100 = bits(T_94, 2, 2) + node T_102 = bits(T_94, 1, 1) + node T_103 = shl(T_102, 0) + node T_104 = mux(T_100, UInt<2>("h2"), T_103) + node T_105 = mux(T_98, UInt<2>("h3"), T_104) + node T_106 = bits(T_95, 3, 3) + node T_108 = bits(T_95, 2, 2) + node T_110 = bits(T_95, 1, 1) + node T_111 = shl(T_110, 0) + node T_112 = mux(T_108, UInt<2>("h2"), T_111) + node T_113 = mux(T_106, UInt<2>("h3"), T_112) + node T_114 = mux(T_97, T_105, T_113) + node T_115 = cat(T_97, T_114) + node T_116 = mux(T_71, T_93, T_115) + node T_117 = cat(T_71, T_116) + node T_118 = mux(T_17, T_67, T_117) + node T_119 = cat(T_17, T_118) + node T_120 = bits(T_11, 31, 16) + node T_121 = bits(T_11, 15, 0) + node T_123 = neq(T_120, UInt<1>("h0")) + node T_124 = bits(T_120, 15, 8) + node T_125 = bits(T_120, 7, 0) + node T_127 = neq(T_124, UInt<1>("h0")) + node T_128 = bits(T_124, 7, 4) + node T_129 = bits(T_124, 3, 0) + node T_131 = neq(T_128, UInt<1>("h0")) + node T_132 = bits(T_128, 3, 3) + node T_134 = bits(T_128, 2, 2) + node T_136 = bits(T_128, 1, 1) + node T_137 = shl(T_136, 0) + node T_138 = mux(T_134, UInt<2>("h2"), T_137) + node T_139 = mux(T_132, UInt<2>("h3"), T_138) + node T_140 = bits(T_129, 3, 3) + node T_142 = bits(T_129, 2, 2) + node T_144 = bits(T_129, 1, 1) + node T_145 = shl(T_144, 0) + node T_146 = mux(T_142, UInt<2>("h2"), T_145) + node T_147 = mux(T_140, UInt<2>("h3"), T_146) + node T_148 = mux(T_131, T_139, T_147) + node T_149 = cat(T_131, T_148) + node T_150 = bits(T_125, 7, 4) + node T_151 = bits(T_125, 3, 0) + node T_153 = neq(T_150, UInt<1>("h0")) + node T_154 = bits(T_150, 3, 3) + node T_156 = bits(T_150, 2, 2) + node T_158 = bits(T_150, 1, 1) + node T_159 = shl(T_158, 0) + node T_160 = mux(T_156, UInt<2>("h2"), T_159) + node T_161 = mux(T_154, UInt<2>("h3"), T_160) + node T_162 = bits(T_151, 3, 3) + node T_164 = bits(T_151, 2, 2) + node T_166 = bits(T_151, 1, 1) + node T_167 = shl(T_166, 0) + node T_168 = mux(T_164, UInt<2>("h2"), T_167) + node T_169 = mux(T_162, UInt<2>("h3"), T_168) + node T_170 = mux(T_153, T_161, T_169) + node T_171 = cat(T_153, T_170) + node T_172 = mux(T_127, T_149, T_171) + node T_173 = cat(T_127, T_172) + node T_174 = bits(T_121, 15, 8) + node T_175 = bits(T_121, 7, 0) + node T_177 = neq(T_174, UInt<1>("h0")) + node T_178 = bits(T_174, 7, 4) + node T_179 = bits(T_174, 3, 0) + node T_181 = neq(T_178, UInt<1>("h0")) + node T_182 = bits(T_178, 3, 3) + node T_184 = bits(T_178, 2, 2) + node T_186 = bits(T_178, 1, 1) + node T_187 = shl(T_186, 0) + node T_188 = mux(T_184, UInt<2>("h2"), T_187) + node T_189 = mux(T_182, UInt<2>("h3"), T_188) + node T_190 = bits(T_179, 3, 3) + node T_192 = bits(T_179, 2, 2) + node T_194 = bits(T_179, 1, 1) + node T_195 = shl(T_194, 0) + node T_196 = mux(T_192, UInt<2>("h2"), T_195) + node T_197 = mux(T_190, UInt<2>("h3"), T_196) + node T_198 = mux(T_181, T_189, T_197) + node T_199 = cat(T_181, T_198) + node T_200 = bits(T_175, 7, 4) + node T_201 = bits(T_175, 3, 0) + node T_203 = neq(T_200, UInt<1>("h0")) + node T_204 = bits(T_200, 3, 3) + node T_206 = bits(T_200, 2, 2) + node T_208 = bits(T_200, 1, 1) + node T_209 = shl(T_208, 0) + node T_210 = mux(T_206, UInt<2>("h2"), T_209) + node T_211 = mux(T_204, UInt<2>("h3"), T_210) + node T_212 = bits(T_201, 3, 3) + node T_214 = bits(T_201, 2, 2) + node T_216 = bits(T_201, 1, 1) + node T_217 = shl(T_216, 0) + node T_218 = mux(T_214, UInt<2>("h2"), T_217) + node T_219 = mux(T_212, UInt<2>("h3"), T_218) + node T_220 = mux(T_203, T_211, T_219) + node T_221 = cat(T_203, T_220) + node T_222 = mux(T_177, T_199, T_221) + node T_223 = cat(T_177, T_222) + node T_224 = mux(T_123, T_173, T_223) + node T_225 = cat(T_123, T_224) + node T_226 = mux(T_13, T_119, T_225) + node T_227 = cat(T_13, T_226) + node normCount = not(T_227) + node T_228 = dshl(absIn, normCount) + node normAbsIn = bits(T_228, 63, 0) + node T_230 = bits(normAbsIn, 11, 10) + node T_231 = bits(normAbsIn, 9, 0) + node T_233 = neq(T_231, UInt<1>("h0")) + node roundBits = cat(T_230, T_233) + node T_234 = bits(roundBits, 1, 0) + node roundInexact = neq(T_234, UInt<1>("h0")) + node T_236 = eq(io.roundingMode, UInt<2>("h0")) + node T_237 = bits(roundBits, 2, 1) + node T_238 = not(T_237) + node T_240 = eq(T_238, UInt<1>("h0")) + node T_241 = bits(roundBits, 1, 0) + node T_242 = not(T_241) + node T_244 = eq(T_242, UInt<1>("h0")) + node T_245 = or(T_240, T_244) + node T_247 = mux(T_236, T_245, UInt<1>("h0")) + node T_248 = eq(io.roundingMode, UInt<2>("h2")) + node T_249 = and(sign, roundInexact) + node T_251 = mux(T_248, T_249, UInt<1>("h0")) + node T_252 = or(T_247, T_251) + node T_253 = eq(io.roundingMode, UInt<2>("h3")) + node T_255 = eq(sign, UInt<1>("h0")) + node T_256 = and(T_255, roundInexact) + node T_258 = mux(T_253, T_256, UInt<1>("h0")) + node round = or(T_252, T_258) + node T_260 = bits(normAbsIn, 63, 11) + node unroundedNorm = cat(UInt<1>("h0"), T_260) + node T_263 = add(unroundedNorm, UInt<1>("h1")) + node T_264 = tail(T_263, 1) + node roundedNorm = mux(round, T_264, unroundedNorm) + node T_265 = not(normCount) + node unroundedExp = cat(UInt<4>("h0"), T_265) + node T_268 = cat(UInt<1>("h0"), unroundedExp) + node T_269 = bits(roundedNorm, 53, 53) + node T_270 = add(T_268, T_269) + node roundedExp = tail(T_270, 1) + node T_271 = bits(normAbsIn, 63, 63) + node T_273 = bits(roundedExp, 10, 0) + node T_274 = mux(UInt<1>("h0"), UInt<11>("h400"), T_273) + node expOut = cat(T_271, T_274) + node overflow = or(UInt<1>("h0"), UInt<1>("h0")) + node inexact = or(roundInexact, overflow) + node T_275 = bits(roundedNorm, 51, 0) + node T_276 = cat(sign, expOut) + node T_277 = cat(T_276, T_275) + io.out <= T_277 + node T_280 = cat(UInt<1>("h0"), inexact) + node T_281 = cat(UInt<2>("h0"), overflow) + node T_282 = cat(T_281, T_280) + io.exceptionFlags <= T_282 + + module IntToFP : input clk : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - + output io : { flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} + io is invalid - reg T_132 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_132 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_132 <= io.in.valid - reg T_133 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : @[Reg.scala 29:19] - T_133 <- io.in.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 39:21] - in is invalid @[Valid.scala 39:21] - in.valid <= T_132 @[Valid.scala 40:17] - in.bits <- T_133 @[Valid.scala 41:16] - wire mux : {data : UInt<65>, exc : UInt<5>} @[fpu.scala 350:17] - mux is invalid @[fpu.scala 350:17] - mux.exc <= UInt<1>("h00") @[fpu.scala 351:11] - node T_257 = bits(in.bits.in1, 31, 31) @[recFNFromFN.scala 47:22] - node T_258 = bits(in.bits.in1, 30, 23) @[recFNFromFN.scala 48:23] - node T_259 = bits(in.bits.in1, 22, 0) @[recFNFromFN.scala 49:25] - node T_261 = eq(T_258, UInt<1>("h00")) @[recFNFromFN.scala 51:34] - node T_263 = eq(T_259, UInt<1>("h00")) @[recFNFromFN.scala 52:38] - node T_264 = and(T_261, T_263) @[recFNFromFN.scala 53:34] - node T_265 = shl(T_259, 9) @[recFNFromFN.scala 56:26] - node T_266 = bits(T_265, 31, 16) @[CircuitMath.scala 26:17] - node T_267 = bits(T_265, 15, 0) @[CircuitMath.scala 27:17] - node T_269 = neq(T_266, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_270 = bits(T_266, 15, 8) @[CircuitMath.scala 26:17] - node T_271 = bits(T_266, 7, 0) @[CircuitMath.scala 27:17] - node T_273 = neq(T_270, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_274 = bits(T_270, 7, 4) @[CircuitMath.scala 26:17] - node T_275 = bits(T_270, 3, 0) @[CircuitMath.scala 27:17] - node T_277 = neq(T_274, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_278 = bits(T_274, 3, 3) @[CircuitMath.scala 23:12] - node T_280 = bits(T_274, 2, 2) @[CircuitMath.scala 23:12] - node T_282 = bits(T_274, 1, 1) @[CircuitMath.scala 21:8] - node T_283 = shl(T_282, 0) @[CircuitMath.scala 23:10] - node T_284 = mux(T_280, UInt<2>("h02"), T_283) @[CircuitMath.scala 23:10] - node T_285 = mux(T_278, UInt<2>("h03"), T_284) @[CircuitMath.scala 23:10] - node T_286 = bits(T_275, 3, 3) @[CircuitMath.scala 23:12] - node T_288 = bits(T_275, 2, 2) @[CircuitMath.scala 23:12] - node T_290 = bits(T_275, 1, 1) @[CircuitMath.scala 21:8] - node T_291 = shl(T_290, 0) @[CircuitMath.scala 23:10] - node T_292 = mux(T_288, UInt<2>("h02"), T_291) @[CircuitMath.scala 23:10] - node T_293 = mux(T_286, UInt<2>("h03"), T_292) @[CircuitMath.scala 23:10] - node T_294 = mux(T_277, T_285, T_293) @[CircuitMath.scala 29:21] - node T_295 = cat(T_277, T_294) @[Cat.scala 20:58] - node T_296 = bits(T_271, 7, 4) @[CircuitMath.scala 26:17] - node T_297 = bits(T_271, 3, 0) @[CircuitMath.scala 27:17] - node T_299 = neq(T_296, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_300 = bits(T_296, 3, 3) @[CircuitMath.scala 23:12] - node T_302 = bits(T_296, 2, 2) @[CircuitMath.scala 23:12] - node T_304 = bits(T_296, 1, 1) @[CircuitMath.scala 21:8] - node T_305 = shl(T_304, 0) @[CircuitMath.scala 23:10] - node T_306 = mux(T_302, UInt<2>("h02"), T_305) @[CircuitMath.scala 23:10] - node T_307 = mux(T_300, UInt<2>("h03"), T_306) @[CircuitMath.scala 23:10] - node T_308 = bits(T_297, 3, 3) @[CircuitMath.scala 23:12] - node T_310 = bits(T_297, 2, 2) @[CircuitMath.scala 23:12] - node T_312 = bits(T_297, 1, 1) @[CircuitMath.scala 21:8] - node T_313 = shl(T_312, 0) @[CircuitMath.scala 23:10] - node T_314 = mux(T_310, UInt<2>("h02"), T_313) @[CircuitMath.scala 23:10] - node T_315 = mux(T_308, UInt<2>("h03"), T_314) @[CircuitMath.scala 23:10] - node T_316 = mux(T_299, T_307, T_315) @[CircuitMath.scala 29:21] - node T_317 = cat(T_299, T_316) @[Cat.scala 20:58] - node T_318 = mux(T_273, T_295, T_317) @[CircuitMath.scala 29:21] - node T_319 = cat(T_273, T_318) @[Cat.scala 20:58] - node T_320 = bits(T_267, 15, 8) @[CircuitMath.scala 26:17] - node T_321 = bits(T_267, 7, 0) @[CircuitMath.scala 27:17] - node T_323 = neq(T_320, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_324 = bits(T_320, 7, 4) @[CircuitMath.scala 26:17] - node T_325 = bits(T_320, 3, 0) @[CircuitMath.scala 27:17] - node T_327 = neq(T_324, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_328 = bits(T_324, 3, 3) @[CircuitMath.scala 23:12] - node T_330 = bits(T_324, 2, 2) @[CircuitMath.scala 23:12] - node T_332 = bits(T_324, 1, 1) @[CircuitMath.scala 21:8] - node T_333 = shl(T_332, 0) @[CircuitMath.scala 23:10] - node T_334 = mux(T_330, UInt<2>("h02"), T_333) @[CircuitMath.scala 23:10] - node T_335 = mux(T_328, UInt<2>("h03"), T_334) @[CircuitMath.scala 23:10] - node T_336 = bits(T_325, 3, 3) @[CircuitMath.scala 23:12] - node T_338 = bits(T_325, 2, 2) @[CircuitMath.scala 23:12] - node T_340 = bits(T_325, 1, 1) @[CircuitMath.scala 21:8] - node T_341 = shl(T_340, 0) @[CircuitMath.scala 23:10] - node T_342 = mux(T_338, UInt<2>("h02"), T_341) @[CircuitMath.scala 23:10] - node T_343 = mux(T_336, UInt<2>("h03"), T_342) @[CircuitMath.scala 23:10] - node T_344 = mux(T_327, T_335, T_343) @[CircuitMath.scala 29:21] - node T_345 = cat(T_327, T_344) @[Cat.scala 20:58] - node T_346 = bits(T_321, 7, 4) @[CircuitMath.scala 26:17] - node T_347 = bits(T_321, 3, 0) @[CircuitMath.scala 27:17] - node T_349 = neq(T_346, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_350 = bits(T_346, 3, 3) @[CircuitMath.scala 23:12] - node T_352 = bits(T_346, 2, 2) @[CircuitMath.scala 23:12] - node T_354 = bits(T_346, 1, 1) @[CircuitMath.scala 21:8] - node T_355 = shl(T_354, 0) @[CircuitMath.scala 23:10] - node T_356 = mux(T_352, UInt<2>("h02"), T_355) @[CircuitMath.scala 23:10] - node T_357 = mux(T_350, UInt<2>("h03"), T_356) @[CircuitMath.scala 23:10] - node T_358 = bits(T_347, 3, 3) @[CircuitMath.scala 23:12] - node T_360 = bits(T_347, 2, 2) @[CircuitMath.scala 23:12] - node T_362 = bits(T_347, 1, 1) @[CircuitMath.scala 21:8] - node T_363 = shl(T_362, 0) @[CircuitMath.scala 23:10] - node T_364 = mux(T_360, UInt<2>("h02"), T_363) @[CircuitMath.scala 23:10] - node T_365 = mux(T_358, UInt<2>("h03"), T_364) @[CircuitMath.scala 23:10] - node T_366 = mux(T_349, T_357, T_365) @[CircuitMath.scala 29:21] - node T_367 = cat(T_349, T_366) @[Cat.scala 20:58] - node T_368 = mux(T_323, T_345, T_367) @[CircuitMath.scala 29:21] - node T_369 = cat(T_323, T_368) @[Cat.scala 20:58] - node T_370 = mux(T_269, T_319, T_369) @[CircuitMath.scala 29:21] - node T_371 = cat(T_269, T_370) @[Cat.scala 20:58] - node T_372 = not(T_371) @[recFNFromFN.scala 56:13] - node T_373 = dshl(T_259, T_372) @[recFNFromFN.scala 58:25] - node T_374 = bits(T_373, 21, 0) @[recFNFromFN.scala 58:37] - node T_376 = cat(T_374, UInt<1>("h00")) @[Cat.scala 20:58] - node T_381 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 33:12] - node T_382 = xor(T_372, T_381) @[recFNFromFN.scala 62:27] - node T_383 = mux(T_261, T_382, T_258) @[recFNFromFN.scala 61:16] - node T_387 = mux(T_261, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] - node T_388 = or(UInt<8>("h080"), T_387) @[recFNFromFN.scala 64:42] - node T_389 = add(T_383, T_388) @[recFNFromFN.scala 64:15] - node T_390 = tail(T_389, 1) @[recFNFromFN.scala 64:15] - node T_391 = bits(T_390, 8, 7) @[recFNFromFN.scala 67:25] - node T_393 = eq(T_391, UInt<2>("h03")) @[recFNFromFN.scala 67:50] - node T_395 = eq(T_263, UInt<1>("h00")) @[recFNFromFN.scala 68:17] - node T_396 = and(T_393, T_395) @[recFNFromFN.scala 67:63] - node T_397 = bits(T_264, 0, 0) @[Bitwise.scala 33:15] - node T_400 = mux(T_397, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_401 = shl(T_400, 6) @[recFNFromFN.scala 71:45] - node T_402 = not(T_401) @[recFNFromFN.scala 71:28] - node T_403 = and(T_390, T_402) @[recFNFromFN.scala 71:26] - node T_404 = shl(T_396, 6) @[recFNFromFN.scala 72:22] - node T_405 = or(T_403, T_404) @[recFNFromFN.scala 71:64] - node T_406 = mux(T_261, T_376, T_259) @[recFNFromFN.scala 73:27] - node T_407 = cat(T_257, T_405) @[Cat.scala 20:58] - node T_408 = cat(T_407, T_406) @[Cat.scala 20:58] - mux.data <= T_408 @[fpu.scala 352:12] - node T_410 = eq(in.bits.single, UInt<1>("h00")) @[fpu.scala 353:24] - when T_410 : @[fpu.scala 353:41] - node T_411 = bits(in.bits.in1, 63, 63) @[recFNFromFN.scala 47:22] - node T_412 = bits(in.bits.in1, 62, 52) @[recFNFromFN.scala 48:23] - node T_413 = bits(in.bits.in1, 51, 0) @[recFNFromFN.scala 49:25] - node T_415 = eq(T_412, UInt<1>("h00")) @[recFNFromFN.scala 51:34] - node T_417 = eq(T_413, UInt<1>("h00")) @[recFNFromFN.scala 52:38] - node T_418 = and(T_415, T_417) @[recFNFromFN.scala 53:34] - node T_419 = shl(T_413, 12) @[recFNFromFN.scala 56:26] - node T_420 = bits(T_419, 63, 32) @[CircuitMath.scala 26:17] - node T_421 = bits(T_419, 31, 0) @[CircuitMath.scala 27:17] - node T_423 = neq(T_420, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_424 = bits(T_420, 31, 16) @[CircuitMath.scala 26:17] - node T_425 = bits(T_420, 15, 0) @[CircuitMath.scala 27:17] - node T_427 = neq(T_424, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_428 = bits(T_424, 15, 8) @[CircuitMath.scala 26:17] - node T_429 = bits(T_424, 7, 0) @[CircuitMath.scala 27:17] - node T_431 = neq(T_428, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_432 = bits(T_428, 7, 4) @[CircuitMath.scala 26:17] - node T_433 = bits(T_428, 3, 0) @[CircuitMath.scala 27:17] - node T_435 = neq(T_432, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_436 = bits(T_432, 3, 3) @[CircuitMath.scala 23:12] - node T_438 = bits(T_432, 2, 2) @[CircuitMath.scala 23:12] - node T_440 = bits(T_432, 1, 1) @[CircuitMath.scala 21:8] - node T_441 = shl(T_440, 0) @[CircuitMath.scala 23:10] - node T_442 = mux(T_438, UInt<2>("h02"), T_441) @[CircuitMath.scala 23:10] - node T_443 = mux(T_436, UInt<2>("h03"), T_442) @[CircuitMath.scala 23:10] - node T_444 = bits(T_433, 3, 3) @[CircuitMath.scala 23:12] - node T_446 = bits(T_433, 2, 2) @[CircuitMath.scala 23:12] - node T_448 = bits(T_433, 1, 1) @[CircuitMath.scala 21:8] - node T_449 = shl(T_448, 0) @[CircuitMath.scala 23:10] - node T_450 = mux(T_446, UInt<2>("h02"), T_449) @[CircuitMath.scala 23:10] - node T_451 = mux(T_444, UInt<2>("h03"), T_450) @[CircuitMath.scala 23:10] - node T_452 = mux(T_435, T_443, T_451) @[CircuitMath.scala 29:21] - node T_453 = cat(T_435, T_452) @[Cat.scala 20:58] - node T_454 = bits(T_429, 7, 4) @[CircuitMath.scala 26:17] - node T_455 = bits(T_429, 3, 0) @[CircuitMath.scala 27:17] - node T_457 = neq(T_454, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_458 = bits(T_454, 3, 3) @[CircuitMath.scala 23:12] - node T_460 = bits(T_454, 2, 2) @[CircuitMath.scala 23:12] - node T_462 = bits(T_454, 1, 1) @[CircuitMath.scala 21:8] - node T_463 = shl(T_462, 0) @[CircuitMath.scala 23:10] - node T_464 = mux(T_460, UInt<2>("h02"), T_463) @[CircuitMath.scala 23:10] - node T_465 = mux(T_458, UInt<2>("h03"), T_464) @[CircuitMath.scala 23:10] - node T_466 = bits(T_455, 3, 3) @[CircuitMath.scala 23:12] - node T_468 = bits(T_455, 2, 2) @[CircuitMath.scala 23:12] - node T_470 = bits(T_455, 1, 1) @[CircuitMath.scala 21:8] - node T_471 = shl(T_470, 0) @[CircuitMath.scala 23:10] - node T_472 = mux(T_468, UInt<2>("h02"), T_471) @[CircuitMath.scala 23:10] - node T_473 = mux(T_466, UInt<2>("h03"), T_472) @[CircuitMath.scala 23:10] - node T_474 = mux(T_457, T_465, T_473) @[CircuitMath.scala 29:21] - node T_475 = cat(T_457, T_474) @[Cat.scala 20:58] - node T_476 = mux(T_431, T_453, T_475) @[CircuitMath.scala 29:21] - node T_477 = cat(T_431, T_476) @[Cat.scala 20:58] - node T_478 = bits(T_425, 15, 8) @[CircuitMath.scala 26:17] - node T_479 = bits(T_425, 7, 0) @[CircuitMath.scala 27:17] - node T_481 = neq(T_478, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_482 = bits(T_478, 7, 4) @[CircuitMath.scala 26:17] - node T_483 = bits(T_478, 3, 0) @[CircuitMath.scala 27:17] - node T_485 = neq(T_482, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_486 = bits(T_482, 3, 3) @[CircuitMath.scala 23:12] - node T_488 = bits(T_482, 2, 2) @[CircuitMath.scala 23:12] - node T_490 = bits(T_482, 1, 1) @[CircuitMath.scala 21:8] - node T_491 = shl(T_490, 0) @[CircuitMath.scala 23:10] - node T_492 = mux(T_488, UInt<2>("h02"), T_491) @[CircuitMath.scala 23:10] - node T_493 = mux(T_486, UInt<2>("h03"), T_492) @[CircuitMath.scala 23:10] - node T_494 = bits(T_483, 3, 3) @[CircuitMath.scala 23:12] - node T_496 = bits(T_483, 2, 2) @[CircuitMath.scala 23:12] - node T_498 = bits(T_483, 1, 1) @[CircuitMath.scala 21:8] - node T_499 = shl(T_498, 0) @[CircuitMath.scala 23:10] - node T_500 = mux(T_496, UInt<2>("h02"), T_499) @[CircuitMath.scala 23:10] - node T_501 = mux(T_494, UInt<2>("h03"), T_500) @[CircuitMath.scala 23:10] - node T_502 = mux(T_485, T_493, T_501) @[CircuitMath.scala 29:21] - node T_503 = cat(T_485, T_502) @[Cat.scala 20:58] - node T_504 = bits(T_479, 7, 4) @[CircuitMath.scala 26:17] - node T_505 = bits(T_479, 3, 0) @[CircuitMath.scala 27:17] - node T_507 = neq(T_504, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_508 = bits(T_504, 3, 3) @[CircuitMath.scala 23:12] - node T_510 = bits(T_504, 2, 2) @[CircuitMath.scala 23:12] - node T_512 = bits(T_504, 1, 1) @[CircuitMath.scala 21:8] - node T_513 = shl(T_512, 0) @[CircuitMath.scala 23:10] - node T_514 = mux(T_510, UInt<2>("h02"), T_513) @[CircuitMath.scala 23:10] - node T_515 = mux(T_508, UInt<2>("h03"), T_514) @[CircuitMath.scala 23:10] - node T_516 = bits(T_505, 3, 3) @[CircuitMath.scala 23:12] - node T_518 = bits(T_505, 2, 2) @[CircuitMath.scala 23:12] - node T_520 = bits(T_505, 1, 1) @[CircuitMath.scala 21:8] - node T_521 = shl(T_520, 0) @[CircuitMath.scala 23:10] - node T_522 = mux(T_518, UInt<2>("h02"), T_521) @[CircuitMath.scala 23:10] - node T_523 = mux(T_516, UInt<2>("h03"), T_522) @[CircuitMath.scala 23:10] - node T_524 = mux(T_507, T_515, T_523) @[CircuitMath.scala 29:21] - node T_525 = cat(T_507, T_524) @[Cat.scala 20:58] - node T_526 = mux(T_481, T_503, T_525) @[CircuitMath.scala 29:21] - node T_527 = cat(T_481, T_526) @[Cat.scala 20:58] - node T_528 = mux(T_427, T_477, T_527) @[CircuitMath.scala 29:21] - node T_529 = cat(T_427, T_528) @[Cat.scala 20:58] - node T_530 = bits(T_421, 31, 16) @[CircuitMath.scala 26:17] - node T_531 = bits(T_421, 15, 0) @[CircuitMath.scala 27:17] - node T_533 = neq(T_530, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_534 = bits(T_530, 15, 8) @[CircuitMath.scala 26:17] - node T_535 = bits(T_530, 7, 0) @[CircuitMath.scala 27:17] - node T_537 = neq(T_534, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_538 = bits(T_534, 7, 4) @[CircuitMath.scala 26:17] - node T_539 = bits(T_534, 3, 0) @[CircuitMath.scala 27:17] - node T_541 = neq(T_538, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_542 = bits(T_538, 3, 3) @[CircuitMath.scala 23:12] - node T_544 = bits(T_538, 2, 2) @[CircuitMath.scala 23:12] - node T_546 = bits(T_538, 1, 1) @[CircuitMath.scala 21:8] - node T_547 = shl(T_546, 0) @[CircuitMath.scala 23:10] - node T_548 = mux(T_544, UInt<2>("h02"), T_547) @[CircuitMath.scala 23:10] - node T_549 = mux(T_542, UInt<2>("h03"), T_548) @[CircuitMath.scala 23:10] - node T_550 = bits(T_539, 3, 3) @[CircuitMath.scala 23:12] - node T_552 = bits(T_539, 2, 2) @[CircuitMath.scala 23:12] - node T_554 = bits(T_539, 1, 1) @[CircuitMath.scala 21:8] - node T_555 = shl(T_554, 0) @[CircuitMath.scala 23:10] - node T_556 = mux(T_552, UInt<2>("h02"), T_555) @[CircuitMath.scala 23:10] - node T_557 = mux(T_550, UInt<2>("h03"), T_556) @[CircuitMath.scala 23:10] - node T_558 = mux(T_541, T_549, T_557) @[CircuitMath.scala 29:21] - node T_559 = cat(T_541, T_558) @[Cat.scala 20:58] - node T_560 = bits(T_535, 7, 4) @[CircuitMath.scala 26:17] - node T_561 = bits(T_535, 3, 0) @[CircuitMath.scala 27:17] - node T_563 = neq(T_560, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_564 = bits(T_560, 3, 3) @[CircuitMath.scala 23:12] - node T_566 = bits(T_560, 2, 2) @[CircuitMath.scala 23:12] - node T_568 = bits(T_560, 1, 1) @[CircuitMath.scala 21:8] - node T_569 = shl(T_568, 0) @[CircuitMath.scala 23:10] - node T_570 = mux(T_566, UInt<2>("h02"), T_569) @[CircuitMath.scala 23:10] - node T_571 = mux(T_564, UInt<2>("h03"), T_570) @[CircuitMath.scala 23:10] - node T_572 = bits(T_561, 3, 3) @[CircuitMath.scala 23:12] - node T_574 = bits(T_561, 2, 2) @[CircuitMath.scala 23:12] - node T_576 = bits(T_561, 1, 1) @[CircuitMath.scala 21:8] - node T_577 = shl(T_576, 0) @[CircuitMath.scala 23:10] - node T_578 = mux(T_574, UInt<2>("h02"), T_577) @[CircuitMath.scala 23:10] - node T_579 = mux(T_572, UInt<2>("h03"), T_578) @[CircuitMath.scala 23:10] - node T_580 = mux(T_563, T_571, T_579) @[CircuitMath.scala 29:21] - node T_581 = cat(T_563, T_580) @[Cat.scala 20:58] - node T_582 = mux(T_537, T_559, T_581) @[CircuitMath.scala 29:21] - node T_583 = cat(T_537, T_582) @[Cat.scala 20:58] - node T_584 = bits(T_531, 15, 8) @[CircuitMath.scala 26:17] - node T_585 = bits(T_531, 7, 0) @[CircuitMath.scala 27:17] - node T_587 = neq(T_584, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_588 = bits(T_584, 7, 4) @[CircuitMath.scala 26:17] - node T_589 = bits(T_584, 3, 0) @[CircuitMath.scala 27:17] - node T_591 = neq(T_588, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_592 = bits(T_588, 3, 3) @[CircuitMath.scala 23:12] - node T_594 = bits(T_588, 2, 2) @[CircuitMath.scala 23:12] - node T_596 = bits(T_588, 1, 1) @[CircuitMath.scala 21:8] - node T_597 = shl(T_596, 0) @[CircuitMath.scala 23:10] - node T_598 = mux(T_594, UInt<2>("h02"), T_597) @[CircuitMath.scala 23:10] - node T_599 = mux(T_592, UInt<2>("h03"), T_598) @[CircuitMath.scala 23:10] - node T_600 = bits(T_589, 3, 3) @[CircuitMath.scala 23:12] - node T_602 = bits(T_589, 2, 2) @[CircuitMath.scala 23:12] - node T_604 = bits(T_589, 1, 1) @[CircuitMath.scala 21:8] - node T_605 = shl(T_604, 0) @[CircuitMath.scala 23:10] - node T_606 = mux(T_602, UInt<2>("h02"), T_605) @[CircuitMath.scala 23:10] - node T_607 = mux(T_600, UInt<2>("h03"), T_606) @[CircuitMath.scala 23:10] - node T_608 = mux(T_591, T_599, T_607) @[CircuitMath.scala 29:21] - node T_609 = cat(T_591, T_608) @[Cat.scala 20:58] - node T_610 = bits(T_585, 7, 4) @[CircuitMath.scala 26:17] - node T_611 = bits(T_585, 3, 0) @[CircuitMath.scala 27:17] - node T_613 = neq(T_610, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_614 = bits(T_610, 3, 3) @[CircuitMath.scala 23:12] - node T_616 = bits(T_610, 2, 2) @[CircuitMath.scala 23:12] - node T_618 = bits(T_610, 1, 1) @[CircuitMath.scala 21:8] - node T_619 = shl(T_618, 0) @[CircuitMath.scala 23:10] - node T_620 = mux(T_616, UInt<2>("h02"), T_619) @[CircuitMath.scala 23:10] - node T_621 = mux(T_614, UInt<2>("h03"), T_620) @[CircuitMath.scala 23:10] - node T_622 = bits(T_611, 3, 3) @[CircuitMath.scala 23:12] - node T_624 = bits(T_611, 2, 2) @[CircuitMath.scala 23:12] - node T_626 = bits(T_611, 1, 1) @[CircuitMath.scala 21:8] - node T_627 = shl(T_626, 0) @[CircuitMath.scala 23:10] - node T_628 = mux(T_624, UInt<2>("h02"), T_627) @[CircuitMath.scala 23:10] - node T_629 = mux(T_622, UInt<2>("h03"), T_628) @[CircuitMath.scala 23:10] - node T_630 = mux(T_613, T_621, T_629) @[CircuitMath.scala 29:21] - node T_631 = cat(T_613, T_630) @[Cat.scala 20:58] - node T_632 = mux(T_587, T_609, T_631) @[CircuitMath.scala 29:21] - node T_633 = cat(T_587, T_632) @[Cat.scala 20:58] - node T_634 = mux(T_533, T_583, T_633) @[CircuitMath.scala 29:21] - node T_635 = cat(T_533, T_634) @[Cat.scala 20:58] - node T_636 = mux(T_423, T_529, T_635) @[CircuitMath.scala 29:21] - node T_637 = cat(T_423, T_636) @[Cat.scala 20:58] - node T_638 = not(T_637) @[recFNFromFN.scala 56:13] - node T_639 = dshl(T_413, T_638) @[recFNFromFN.scala 58:25] - node T_640 = bits(T_639, 50, 0) @[recFNFromFN.scala 58:37] - node T_642 = cat(T_640, UInt<1>("h00")) @[Cat.scala 20:58] - node T_647 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 33:12] - node T_648 = xor(T_638, T_647) @[recFNFromFN.scala 62:27] - node T_649 = mux(T_415, T_648, T_412) @[recFNFromFN.scala 61:16] - node T_653 = mux(T_415, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] - node T_654 = or(UInt<11>("h0400"), T_653) @[recFNFromFN.scala 64:42] - node T_655 = add(T_649, T_654) @[recFNFromFN.scala 64:15] - node T_656 = tail(T_655, 1) @[recFNFromFN.scala 64:15] - node T_657 = bits(T_656, 11, 10) @[recFNFromFN.scala 67:25] - node T_659 = eq(T_657, UInt<2>("h03")) @[recFNFromFN.scala 67:50] - node T_661 = eq(T_417, UInt<1>("h00")) @[recFNFromFN.scala 68:17] - node T_662 = and(T_659, T_661) @[recFNFromFN.scala 67:63] - node T_663 = bits(T_418, 0, 0) @[Bitwise.scala 33:15] - node T_666 = mux(T_663, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_667 = shl(T_666, 9) @[recFNFromFN.scala 71:45] - node T_668 = not(T_667) @[recFNFromFN.scala 71:28] - node T_669 = and(T_656, T_668) @[recFNFromFN.scala 71:26] - node T_670 = shl(T_662, 9) @[recFNFromFN.scala 72:22] - node T_671 = or(T_669, T_670) @[recFNFromFN.scala 71:64] - node T_672 = mux(T_415, T_642, T_413) @[recFNFromFN.scala 73:27] - node T_673 = cat(T_411, T_671) @[Cat.scala 20:58] - node T_674 = cat(T_673, T_672) @[Cat.scala 20:58] - mux.data <= T_674 @[fpu.scala 354:14] - skip @[fpu.scala 353:41] - node T_675 = asSInt(in.bits.in1) @[fpu.scala 360:39] + reg T_133 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : + reset => (UInt<1>("h0"), T_133) + when io.in.valid : + T_133 <- io.in.bits + wire in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + in is invalid + in.valid <= T_132 + in.bits <- T_133 + wire mux : { data : UInt<65>, exc : UInt<5>} + mux is invalid + mux.exc <= UInt<1>("h0") + node T_257 = bits(in.bits.in1, 31, 31) + node T_258 = bits(in.bits.in1, 30, 23) + node T_259 = bits(in.bits.in1, 22, 0) + node T_261 = eq(T_258, UInt<1>("h0")) + node T_263 = eq(T_259, UInt<1>("h0")) + node T_264 = and(T_261, T_263) + node T_265 = shl(T_259, 9) + node T_266 = bits(T_265, 31, 16) + node T_267 = bits(T_265, 15, 0) + node T_269 = neq(T_266, UInt<1>("h0")) + node T_270 = bits(T_266, 15, 8) + node T_271 = bits(T_266, 7, 0) + node T_273 = neq(T_270, UInt<1>("h0")) + node T_274 = bits(T_270, 7, 4) + node T_275 = bits(T_270, 3, 0) + node T_277 = neq(T_274, UInt<1>("h0")) + node T_278 = bits(T_274, 3, 3) + node T_280 = bits(T_274, 2, 2) + node T_282 = bits(T_274, 1, 1) + node T_283 = shl(T_282, 0) + node T_284 = mux(T_280, UInt<2>("h2"), T_283) + node T_285 = mux(T_278, UInt<2>("h3"), T_284) + node T_286 = bits(T_275, 3, 3) + node T_288 = bits(T_275, 2, 2) + node T_290 = bits(T_275, 1, 1) + node T_291 = shl(T_290, 0) + node T_292 = mux(T_288, UInt<2>("h2"), T_291) + node T_293 = mux(T_286, UInt<2>("h3"), T_292) + node T_294 = mux(T_277, T_285, T_293) + node T_295 = cat(T_277, T_294) + node T_296 = bits(T_271, 7, 4) + node T_297 = bits(T_271, 3, 0) + node T_299 = neq(T_296, UInt<1>("h0")) + node T_300 = bits(T_296, 3, 3) + node T_302 = bits(T_296, 2, 2) + node T_304 = bits(T_296, 1, 1) + node T_305 = shl(T_304, 0) + node T_306 = mux(T_302, UInt<2>("h2"), T_305) + node T_307 = mux(T_300, UInt<2>("h3"), T_306) + node T_308 = bits(T_297, 3, 3) + node T_310 = bits(T_297, 2, 2) + node T_312 = bits(T_297, 1, 1) + node T_313 = shl(T_312, 0) + node T_314 = mux(T_310, UInt<2>("h2"), T_313) + node T_315 = mux(T_308, UInt<2>("h3"), T_314) + node T_316 = mux(T_299, T_307, T_315) + node T_317 = cat(T_299, T_316) + node T_318 = mux(T_273, T_295, T_317) + node T_319 = cat(T_273, T_318) + node T_320 = bits(T_267, 15, 8) + node T_321 = bits(T_267, 7, 0) + node T_323 = neq(T_320, UInt<1>("h0")) + node T_324 = bits(T_320, 7, 4) + node T_325 = bits(T_320, 3, 0) + node T_327 = neq(T_324, UInt<1>("h0")) + node T_328 = bits(T_324, 3, 3) + node T_330 = bits(T_324, 2, 2) + node T_332 = bits(T_324, 1, 1) + node T_333 = shl(T_332, 0) + node T_334 = mux(T_330, UInt<2>("h2"), T_333) + node T_335 = mux(T_328, UInt<2>("h3"), T_334) + node T_336 = bits(T_325, 3, 3) + node T_338 = bits(T_325, 2, 2) + node T_340 = bits(T_325, 1, 1) + node T_341 = shl(T_340, 0) + node T_342 = mux(T_338, UInt<2>("h2"), T_341) + node T_343 = mux(T_336, UInt<2>("h3"), T_342) + node T_344 = mux(T_327, T_335, T_343) + node T_345 = cat(T_327, T_344) + node T_346 = bits(T_321, 7, 4) + node T_347 = bits(T_321, 3, 0) + node T_349 = neq(T_346, UInt<1>("h0")) + node T_350 = bits(T_346, 3, 3) + node T_352 = bits(T_346, 2, 2) + node T_354 = bits(T_346, 1, 1) + node T_355 = shl(T_354, 0) + node T_356 = mux(T_352, UInt<2>("h2"), T_355) + node T_357 = mux(T_350, UInt<2>("h3"), T_356) + node T_358 = bits(T_347, 3, 3) + node T_360 = bits(T_347, 2, 2) + node T_362 = bits(T_347, 1, 1) + node T_363 = shl(T_362, 0) + node T_364 = mux(T_360, UInt<2>("h2"), T_363) + node T_365 = mux(T_358, UInt<2>("h3"), T_364) + node T_366 = mux(T_349, T_357, T_365) + node T_367 = cat(T_349, T_366) + node T_368 = mux(T_323, T_345, T_367) + node T_369 = cat(T_323, T_368) + node T_370 = mux(T_269, T_319, T_369) + node T_371 = cat(T_269, T_370) + node T_372 = not(T_371) + node T_373 = dshl(T_259, T_372) + node T_374 = bits(T_373, 21, 0) + node T_376 = cat(T_374, UInt<1>("h0")) + node T_381 = mux(UInt<1>("h1"), UInt<9>("h1ff"), UInt<9>("h0")) + node T_382 = xor(T_372, T_381) + node T_383 = mux(T_261, T_382, T_258) + node T_387 = mux(T_261, UInt<2>("h2"), UInt<1>("h1")) + node T_388 = or(UInt<8>("h80"), T_387) + node T_389 = add(T_383, T_388) + node T_390 = tail(T_389, 1) + node T_391 = bits(T_390, 8, 7) + node T_393 = eq(T_391, UInt<2>("h3")) + node T_395 = eq(T_263, UInt<1>("h0")) + node T_396 = and(T_393, T_395) + node T_397 = bits(T_264, 0, 0) + node T_400 = mux(T_397, UInt<3>("h7"), UInt<3>("h0")) + node T_401 = shl(T_400, 6) + node T_402 = not(T_401) + node T_403 = and(T_390, T_402) + node T_404 = shl(T_396, 6) + node T_405 = or(T_403, T_404) + node T_406 = mux(T_261, T_376, T_259) + node T_407 = cat(T_257, T_405) + node T_408 = cat(T_407, T_406) + mux.data <= T_408 + node T_410 = eq(in.bits.single, UInt<1>("h0")) + when T_410 : + node T_411 = bits(in.bits.in1, 63, 63) + node T_412 = bits(in.bits.in1, 62, 52) + node T_413 = bits(in.bits.in1, 51, 0) + node T_415 = eq(T_412, UInt<1>("h0")) + node T_417 = eq(T_413, UInt<1>("h0")) + node T_418 = and(T_415, T_417) + node T_419 = shl(T_413, 12) + node T_420 = bits(T_419, 63, 32) + node T_421 = bits(T_419, 31, 0) + node T_423 = neq(T_420, UInt<1>("h0")) + node T_424 = bits(T_420, 31, 16) + node T_425 = bits(T_420, 15, 0) + node T_427 = neq(T_424, UInt<1>("h0")) + node T_428 = bits(T_424, 15, 8) + node T_429 = bits(T_424, 7, 0) + node T_431 = neq(T_428, UInt<1>("h0")) + node T_432 = bits(T_428, 7, 4) + node T_433 = bits(T_428, 3, 0) + node T_435 = neq(T_432, UInt<1>("h0")) + node T_436 = bits(T_432, 3, 3) + node T_438 = bits(T_432, 2, 2) + node T_440 = bits(T_432, 1, 1) + node T_441 = shl(T_440, 0) + node T_442 = mux(T_438, UInt<2>("h2"), T_441) + node T_443 = mux(T_436, UInt<2>("h3"), T_442) + node T_444 = bits(T_433, 3, 3) + node T_446 = bits(T_433, 2, 2) + node T_448 = bits(T_433, 1, 1) + node T_449 = shl(T_448, 0) + node T_450 = mux(T_446, UInt<2>("h2"), T_449) + node T_451 = mux(T_444, UInt<2>("h3"), T_450) + node T_452 = mux(T_435, T_443, T_451) + node T_453 = cat(T_435, T_452) + node T_454 = bits(T_429, 7, 4) + node T_455 = bits(T_429, 3, 0) + node T_457 = neq(T_454, UInt<1>("h0")) + node T_458 = bits(T_454, 3, 3) + node T_460 = bits(T_454, 2, 2) + node T_462 = bits(T_454, 1, 1) + node T_463 = shl(T_462, 0) + node T_464 = mux(T_460, UInt<2>("h2"), T_463) + node T_465 = mux(T_458, UInt<2>("h3"), T_464) + node T_466 = bits(T_455, 3, 3) + node T_468 = bits(T_455, 2, 2) + node T_470 = bits(T_455, 1, 1) + node T_471 = shl(T_470, 0) + node T_472 = mux(T_468, UInt<2>("h2"), T_471) + node T_473 = mux(T_466, UInt<2>("h3"), T_472) + node T_474 = mux(T_457, T_465, T_473) + node T_475 = cat(T_457, T_474) + node T_476 = mux(T_431, T_453, T_475) + node T_477 = cat(T_431, T_476) + node T_478 = bits(T_425, 15, 8) + node T_479 = bits(T_425, 7, 0) + node T_481 = neq(T_478, UInt<1>("h0")) + node T_482 = bits(T_478, 7, 4) + node T_483 = bits(T_478, 3, 0) + node T_485 = neq(T_482, UInt<1>("h0")) + node T_486 = bits(T_482, 3, 3) + node T_488 = bits(T_482, 2, 2) + node T_490 = bits(T_482, 1, 1) + node T_491 = shl(T_490, 0) + node T_492 = mux(T_488, UInt<2>("h2"), T_491) + node T_493 = mux(T_486, UInt<2>("h3"), T_492) + node T_494 = bits(T_483, 3, 3) + node T_496 = bits(T_483, 2, 2) + node T_498 = bits(T_483, 1, 1) + node T_499 = shl(T_498, 0) + node T_500 = mux(T_496, UInt<2>("h2"), T_499) + node T_501 = mux(T_494, UInt<2>("h3"), T_500) + node T_502 = mux(T_485, T_493, T_501) + node T_503 = cat(T_485, T_502) + node T_504 = bits(T_479, 7, 4) + node T_505 = bits(T_479, 3, 0) + node T_507 = neq(T_504, UInt<1>("h0")) + node T_508 = bits(T_504, 3, 3) + node T_510 = bits(T_504, 2, 2) + node T_512 = bits(T_504, 1, 1) + node T_513 = shl(T_512, 0) + node T_514 = mux(T_510, UInt<2>("h2"), T_513) + node T_515 = mux(T_508, UInt<2>("h3"), T_514) + node T_516 = bits(T_505, 3, 3) + node T_518 = bits(T_505, 2, 2) + node T_520 = bits(T_505, 1, 1) + node T_521 = shl(T_520, 0) + node T_522 = mux(T_518, UInt<2>("h2"), T_521) + node T_523 = mux(T_516, UInt<2>("h3"), T_522) + node T_524 = mux(T_507, T_515, T_523) + node T_525 = cat(T_507, T_524) + node T_526 = mux(T_481, T_503, T_525) + node T_527 = cat(T_481, T_526) + node T_528 = mux(T_427, T_477, T_527) + node T_529 = cat(T_427, T_528) + node T_530 = bits(T_421, 31, 16) + node T_531 = bits(T_421, 15, 0) + node T_533 = neq(T_530, UInt<1>("h0")) + node T_534 = bits(T_530, 15, 8) + node T_535 = bits(T_530, 7, 0) + node T_537 = neq(T_534, UInt<1>("h0")) + node T_538 = bits(T_534, 7, 4) + node T_539 = bits(T_534, 3, 0) + node T_541 = neq(T_538, UInt<1>("h0")) + node T_542 = bits(T_538, 3, 3) + node T_544 = bits(T_538, 2, 2) + node T_546 = bits(T_538, 1, 1) + node T_547 = shl(T_546, 0) + node T_548 = mux(T_544, UInt<2>("h2"), T_547) + node T_549 = mux(T_542, UInt<2>("h3"), T_548) + node T_550 = bits(T_539, 3, 3) + node T_552 = bits(T_539, 2, 2) + node T_554 = bits(T_539, 1, 1) + node T_555 = shl(T_554, 0) + node T_556 = mux(T_552, UInt<2>("h2"), T_555) + node T_557 = mux(T_550, UInt<2>("h3"), T_556) + node T_558 = mux(T_541, T_549, T_557) + node T_559 = cat(T_541, T_558) + node T_560 = bits(T_535, 7, 4) + node T_561 = bits(T_535, 3, 0) + node T_563 = neq(T_560, UInt<1>("h0")) + node T_564 = bits(T_560, 3, 3) + node T_566 = bits(T_560, 2, 2) + node T_568 = bits(T_560, 1, 1) + node T_569 = shl(T_568, 0) + node T_570 = mux(T_566, UInt<2>("h2"), T_569) + node T_571 = mux(T_564, UInt<2>("h3"), T_570) + node T_572 = bits(T_561, 3, 3) + node T_574 = bits(T_561, 2, 2) + node T_576 = bits(T_561, 1, 1) + node T_577 = shl(T_576, 0) + node T_578 = mux(T_574, UInt<2>("h2"), T_577) + node T_579 = mux(T_572, UInt<2>("h3"), T_578) + node T_580 = mux(T_563, T_571, T_579) + node T_581 = cat(T_563, T_580) + node T_582 = mux(T_537, T_559, T_581) + node T_583 = cat(T_537, T_582) + node T_584 = bits(T_531, 15, 8) + node T_585 = bits(T_531, 7, 0) + node T_587 = neq(T_584, UInt<1>("h0")) + node T_588 = bits(T_584, 7, 4) + node T_589 = bits(T_584, 3, 0) + node T_591 = neq(T_588, UInt<1>("h0")) + node T_592 = bits(T_588, 3, 3) + node T_594 = bits(T_588, 2, 2) + node T_596 = bits(T_588, 1, 1) + node T_597 = shl(T_596, 0) + node T_598 = mux(T_594, UInt<2>("h2"), T_597) + node T_599 = mux(T_592, UInt<2>("h3"), T_598) + node T_600 = bits(T_589, 3, 3) + node T_602 = bits(T_589, 2, 2) + node T_604 = bits(T_589, 1, 1) + node T_605 = shl(T_604, 0) + node T_606 = mux(T_602, UInt<2>("h2"), T_605) + node T_607 = mux(T_600, UInt<2>("h3"), T_606) + node T_608 = mux(T_591, T_599, T_607) + node T_609 = cat(T_591, T_608) + node T_610 = bits(T_585, 7, 4) + node T_611 = bits(T_585, 3, 0) + node T_613 = neq(T_610, UInt<1>("h0")) + node T_614 = bits(T_610, 3, 3) + node T_616 = bits(T_610, 2, 2) + node T_618 = bits(T_610, 1, 1) + node T_619 = shl(T_618, 0) + node T_620 = mux(T_616, UInt<2>("h2"), T_619) + node T_621 = mux(T_614, UInt<2>("h3"), T_620) + node T_622 = bits(T_611, 3, 3) + node T_624 = bits(T_611, 2, 2) + node T_626 = bits(T_611, 1, 1) + node T_627 = shl(T_626, 0) + node T_628 = mux(T_624, UInt<2>("h2"), T_627) + node T_629 = mux(T_622, UInt<2>("h3"), T_628) + node T_630 = mux(T_613, T_621, T_629) + node T_631 = cat(T_613, T_630) + node T_632 = mux(T_587, T_609, T_631) + node T_633 = cat(T_587, T_632) + node T_634 = mux(T_533, T_583, T_633) + node T_635 = cat(T_533, T_634) + node T_636 = mux(T_423, T_529, T_635) + node T_637 = cat(T_423, T_636) + node T_638 = not(T_637) + node T_639 = dshl(T_413, T_638) + node T_640 = bits(T_639, 50, 0) + node T_642 = cat(T_640, UInt<1>("h0")) + node T_647 = mux(UInt<1>("h1"), UInt<12>("hfff"), UInt<12>("h0")) + node T_648 = xor(T_638, T_647) + node T_649 = mux(T_415, T_648, T_412) + node T_653 = mux(T_415, UInt<2>("h2"), UInt<1>("h1")) + node T_654 = or(UInt<11>("h400"), T_653) + node T_655 = add(T_649, T_654) + node T_656 = tail(T_655, 1) + node T_657 = bits(T_656, 11, 10) + node T_659 = eq(T_657, UInt<2>("h3")) + node T_661 = eq(T_417, UInt<1>("h0")) + node T_662 = and(T_659, T_661) + node T_663 = bits(T_418, 0, 0) + node T_666 = mux(T_663, UInt<3>("h7"), UInt<3>("h0")) + node T_667 = shl(T_666, 9) + node T_668 = not(T_667) + node T_669 = and(T_656, T_668) + node T_670 = shl(T_662, 9) + node T_671 = or(T_669, T_670) + node T_672 = mux(T_415, T_642, T_413) + node T_673 = cat(T_411, T_671) + node T_674 = cat(T_673, T_672) + mux.data <= T_674 + node T_675 = asSInt(in.bits.in1) wire T_676 : SInt T_676 is invalid T_676 <= T_675 - node T_677 = bits(in.bits.in1, 31, 0) @[fpu.scala 362:33] - node T_678 = bits(in.bits.typ, 1, 1) @[util.scala 25:13] - node T_680 = eq(T_678, UInt<1>("h00")) @[fpu.scala 363:49] - when T_680 : @[fpu.scala 363:56] - node T_681 = bits(in.bits.typ, 0, 0) @[fpu.scala 364:31] - node T_682 = cvt(T_677) @[fpu.scala 364:45] - node T_683 = asSInt(T_677) @[fpu.scala 364:60] - node T_684 = mux(T_681, T_682, T_683) @[fpu.scala 364:19] - T_676 <= T_684 @[fpu.scala 364:13] - skip @[fpu.scala 363:56] - node intValue = asUInt(T_676) @[fpu.scala 367:9] - node T_687 = and(in.bits.cmd, UInt<3>("h04")) @[fpu.scala 370:21] - node T_688 = eq(UInt<5>("h00"), T_687) @[fpu.scala 370:21] - when T_688 : @[fpu.scala 370:38] - inst INToRecFN_2 of INToRecFN @[fpu.scala 371:21] + node T_677 = bits(in.bits.in1, 31, 0) + node T_678 = bits(in.bits.typ, 1, 1) + node T_680 = eq(T_678, UInt<1>("h0")) + when T_680 : + node T_681 = bits(in.bits.typ, 0, 0) + node T_682 = cvt(T_677) + node T_683 = asSInt(T_677) + node T_684 = mux(T_681, T_682, T_683) + T_676 <= T_684 + node intValue = asUInt(T_676) + node T_687 = and(in.bits.cmd, UInt<3>("h4")) + node T_688 = eq(UInt<5>("h0"), T_687) + when T_688 : + inst INToRecFN_2 of INToRecFN INToRecFN_2.io is invalid INToRecFN_2.clk <= clk INToRecFN_2.reset <= reset - node T_689 = bits(in.bits.typ, 0, 0) @[fpu.scala 372:36] - node T_690 = not(T_689) @[fpu.scala 372:24] - INToRecFN_2.io.signedIn <= T_690 @[fpu.scala 372:21] - INToRecFN_2.io.in <= intValue @[fpu.scala 373:15] - INToRecFN_2.io.roundingMode <= in.bits.rm @[fpu.scala 374:25] - node T_692 = cat(UInt<32>("h0ffffffff"), INToRecFN_2.io.out) @[Cat.scala 20:58] - mux.data <= T_692 @[fpu.scala 375:14] - mux.exc <= INToRecFN_2.io.exceptionFlags @[fpu.scala 376:13] - inst INToRecFN_1_1 of INToRecFN_1 @[fpu.scala 381:25] + node T_689 = bits(in.bits.typ, 0, 0) + node T_690 = not(T_689) + INToRecFN_2.io.signedIn <= T_690 + INToRecFN_2.io.in <= intValue + INToRecFN_2.io.roundingMode <= in.bits.rm + node T_692 = cat(UInt<32>("hffffffff"), INToRecFN_2.io.out) + mux.data <= T_692 + mux.exc <= INToRecFN_2.io.exceptionFlags + inst INToRecFN_1_1 of INToRecFN_1 INToRecFN_1_1.io is invalid INToRecFN_1_1.clk <= clk INToRecFN_1_1.reset <= reset - node T_693 = bits(in.bits.typ, 0, 0) @[fpu.scala 382:40] - node T_694 = not(T_693) @[fpu.scala 382:28] - INToRecFN_1_1.io.signedIn <= T_694 @[fpu.scala 382:25] - INToRecFN_1_1.io.in <= intValue @[fpu.scala 383:19] - INToRecFN_1_1.io.roundingMode <= in.bits.rm @[fpu.scala 384:29] - node T_696 = eq(in.bits.single, UInt<1>("h00")) @[fpu.scala 385:15] - when T_696 : @[fpu.scala 385:32] - node T_698 = cat(UInt<1>("h00"), INToRecFN_1_1.io.out) @[Cat.scala 20:58] - mux.data <= T_698 @[fpu.scala 386:22] - mux.exc <= INToRecFN_1_1.io.exceptionFlags @[fpu.scala 387:21] - skip @[fpu.scala 385:32] - skip @[fpu.scala 370:38] - reg T_701 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_693 = bits(in.bits.typ, 0, 0) + node T_694 = not(T_693) + INToRecFN_1_1.io.signedIn <= T_694 + INToRecFN_1_1.io.in <= intValue + INToRecFN_1_1.io.roundingMode <= in.bits.rm + node T_696 = eq(in.bits.single, UInt<1>("h0")) + when T_696 : + node T_698 = cat(UInt<1>("h0"), INToRecFN_1_1.io.out) + mux.data <= T_698 + mux.exc <= INToRecFN_1_1.io.exceptionFlags + reg T_701 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_701 <= in.valid - reg T_702 : {data : UInt<65>, exc : UInt<5>}, clk - when in.valid : @[Reg.scala 29:19] - T_702 <- mux @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire T_713 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 39:21] - T_713 is invalid @[Valid.scala 39:21] - T_713.valid <= T_701 @[Valid.scala 40:17] - T_713.bits <- T_702 @[Valid.scala 41:16] - io.out <- T_713 @[fpu.scala 392:12] - - module RoundRawFNToRecFN : + reg T_702 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_702) + when in.valid : + T_702 <- mux + wire T_713 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} + T_713 is invalid + T_713.valid <= T_701 + T_713.bits <- T_702 + io.out <- T_713 + + module RoundRawFNToRecFN : input clk : Clock input reset : UInt<1> - output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) @[RoundRawFNToRecFN.scala 88:54] - node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) @[RoundRawFNToRecFN.scala 89:54] - node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @[RoundRawFNToRecFN.scala 90:54] - node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) @[RoundRawFNToRecFN.scala 91:54] - node T_19 = and(roundingMode_min, io.in.sign) @[RoundRawFNToRecFN.scala 94:27] - node T_21 = eq(io.in.sign, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 94:66] - node T_22 = and(roundingMode_max, T_21) @[RoundRawFNToRecFN.scala 94:63] - node roundMagUp = or(T_19, T_22) @[RoundRawFNToRecFN.scala 94:42] - node doShiftSigDown1 = bits(io.in.sig, 26, 26) @[RoundRawFNToRecFN.scala 98:36] - node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h00"))) @[RoundRawFNToRecFN.scala 99:32] - node T_24 = bits(isNegExp, 0, 0) @[Bitwise.scala 33:15] - node T_27 = mux(T_24, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 33:12] - node T_28 = bits(io.in.sExp, 8, 0) @[RoundRawFNToRecFN.scala 103:31] - node T_29 = not(T_28) @[primitives.scala 50:21] - node T_30 = bits(T_29, 8, 8) @[primitives.scala 56:25] - node T_31 = bits(T_29, 7, 0) @[primitives.scala 57:26] - node T_32 = bits(T_31, 7, 7) @[primitives.scala 56:25] - node T_33 = bits(T_31, 6, 0) @[primitives.scala 57:26] - node T_34 = bits(T_33, 6, 6) @[primitives.scala 56:25] - node T_35 = bits(T_33, 5, 0) @[primitives.scala 57:26] - node T_38 = dshr(asSInt(UInt<65>("h010000000000000000")), T_35) @[primitives.scala 68:52] - node T_39 = bits(T_38, 63, 42) @[primitives.scala 69:26] - node T_40 = bits(T_39, 15, 0) @[Bitwise.scala 65:18] - node T_43 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_44 = xor(UInt<16>("h0ffff"), T_43) @[Bitwise.scala 58:21] - node T_45 = shr(T_40, 8) @[Bitwise.scala 59:21] - node T_46 = and(T_45, T_44) @[Bitwise.scala 59:31] - node T_47 = bits(T_40, 7, 0) @[Bitwise.scala 59:46] - node T_48 = shl(T_47, 8) @[Bitwise.scala 59:65] - node T_49 = not(T_44) @[Bitwise.scala 59:77] - node T_50 = and(T_48, T_49) @[Bitwise.scala 59:75] - node T_51 = or(T_46, T_50) @[Bitwise.scala 59:39] - node T_52 = bits(T_44, 11, 0) @[Bitwise.scala 58:28] - node T_53 = shl(T_52, 4) @[Bitwise.scala 58:47] - node T_54 = xor(T_44, T_53) @[Bitwise.scala 58:21] - node T_55 = shr(T_51, 4) @[Bitwise.scala 59:21] - node T_56 = and(T_55, T_54) @[Bitwise.scala 59:31] - node T_57 = bits(T_51, 11, 0) @[Bitwise.scala 59:46] - node T_58 = shl(T_57, 4) @[Bitwise.scala 59:65] - node T_59 = not(T_54) @[Bitwise.scala 59:77] - node T_60 = and(T_58, T_59) @[Bitwise.scala 59:75] - node T_61 = or(T_56, T_60) @[Bitwise.scala 59:39] - node T_62 = bits(T_54, 13, 0) @[Bitwise.scala 58:28] - node T_63 = shl(T_62, 2) @[Bitwise.scala 58:47] - node T_64 = xor(T_54, T_63) @[Bitwise.scala 58:21] - node T_65 = shr(T_61, 2) @[Bitwise.scala 59:21] - node T_66 = and(T_65, T_64) @[Bitwise.scala 59:31] - node T_67 = bits(T_61, 13, 0) @[Bitwise.scala 59:46] - node T_68 = shl(T_67, 2) @[Bitwise.scala 59:65] - node T_69 = not(T_64) @[Bitwise.scala 59:77] - node T_70 = and(T_68, T_69) @[Bitwise.scala 59:75] - node T_71 = or(T_66, T_70) @[Bitwise.scala 59:39] - node T_72 = bits(T_64, 14, 0) @[Bitwise.scala 58:28] - node T_73 = shl(T_72, 1) @[Bitwise.scala 58:47] - node T_74 = xor(T_64, T_73) @[Bitwise.scala 58:21] - node T_75 = shr(T_71, 1) @[Bitwise.scala 59:21] - node T_76 = and(T_75, T_74) @[Bitwise.scala 59:31] - node T_77 = bits(T_71, 14, 0) @[Bitwise.scala 59:46] - node T_78 = shl(T_77, 1) @[Bitwise.scala 59:65] - node T_79 = not(T_74) @[Bitwise.scala 59:77] - node T_80 = and(T_78, T_79) @[Bitwise.scala 59:75] - node T_81 = or(T_76, T_80) @[Bitwise.scala 59:39] - node T_82 = bits(T_39, 21, 16) @[Bitwise.scala 65:44] - node T_83 = bits(T_82, 3, 0) @[Bitwise.scala 65:18] - node T_84 = bits(T_83, 1, 0) @[Bitwise.scala 65:18] - node T_85 = bits(T_84, 0, 0) @[Bitwise.scala 65:18] - node T_86 = bits(T_84, 1, 1) @[Bitwise.scala 65:44] - node T_87 = cat(T_85, T_86) @[Cat.scala 20:58] - node T_88 = bits(T_83, 3, 2) @[Bitwise.scala 65:44] - node T_89 = bits(T_88, 0, 0) @[Bitwise.scala 65:18] - node T_90 = bits(T_88, 1, 1) @[Bitwise.scala 65:44] - node T_91 = cat(T_89, T_90) @[Cat.scala 20:58] - node T_92 = cat(T_87, T_91) @[Cat.scala 20:58] - node T_93 = bits(T_82, 5, 4) @[Bitwise.scala 65:44] - node T_94 = bits(T_93, 0, 0) @[Bitwise.scala 65:18] - node T_95 = bits(T_93, 1, 1) @[Bitwise.scala 65:44] - node T_96 = cat(T_94, T_95) @[Cat.scala 20:58] - node T_97 = cat(T_92, T_96) @[Cat.scala 20:58] - node T_98 = cat(T_81, T_97) @[Cat.scala 20:58] - node T_99 = not(T_98) @[primitives.scala 65:36] - node T_100 = mux(T_34, UInt<1>("h00"), T_99) @[primitives.scala 65:21] - node T_101 = not(T_100) @[primitives.scala 65:17] - node T_103 = cat(T_101, UInt<3>("h07")) @[Cat.scala 20:58] - node T_104 = bits(T_33, 6, 6) @[primitives.scala 56:25] - node T_105 = bits(T_33, 5, 0) @[primitives.scala 57:26] - node T_107 = dshr(asSInt(UInt<65>("h010000000000000000")), T_105) @[primitives.scala 68:52] - node T_108 = bits(T_107, 2, 0) @[primitives.scala 69:26] - node T_109 = bits(T_108, 1, 0) @[Bitwise.scala 65:18] - node T_110 = bits(T_109, 0, 0) @[Bitwise.scala 65:18] - node T_111 = bits(T_109, 1, 1) @[Bitwise.scala 65:44] - node T_112 = cat(T_110, T_111) @[Cat.scala 20:58] - node T_113 = bits(T_108, 2, 2) @[Bitwise.scala 65:44] - node T_114 = cat(T_112, T_113) @[Cat.scala 20:58] - node T_116 = mux(T_104, T_114, UInt<1>("h00")) @[primitives.scala 59:20] - node T_117 = mux(T_32, T_103, T_116) @[primitives.scala 61:20] - node T_119 = mux(T_30, T_117, UInt<1>("h00")) @[primitives.scala 59:20] - node T_120 = or(T_27, T_119) @[RoundRawFNToRecFN.scala 101:42] - node T_121 = or(T_120, doShiftSigDown1) @[RoundRawFNToRecFN.scala 106:19] - node roundMask = cat(T_121, UInt<2>("h03")) @[Cat.scala 20:58] - node T_123 = cat(isNegExp, roundMask) @[Cat.scala 20:58] - node shiftedRoundMask = shr(T_123, 1) @[RoundRawFNToRecFN.scala 109:52] - node T_124 = not(shiftedRoundMask) @[RoundRawFNToRecFN.scala 110:24] - node roundPosMask = and(T_124, roundMask) @[RoundRawFNToRecFN.scala 110:42] - node T_125 = and(io.in.sig, roundPosMask) @[RoundRawFNToRecFN.scala 111:34] - node roundPosBit = neq(T_125, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 111:50] - node T_127 = and(io.in.sig, shiftedRoundMask) @[RoundRawFNToRecFN.scala 112:36] - node anyRoundExtra = neq(T_127, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 112:56] - node common_inexact = or(roundPosBit, anyRoundExtra) @[RoundRawFNToRecFN.scala 113:32] - node T_129 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 116:40] - node T_130 = and(roundMagUp, common_inexact) @[RoundRawFNToRecFN.scala 117:29] - node T_131 = or(T_129, T_130) @[RoundRawFNToRecFN.scala 116:56] - node T_132 = or(io.in.sig, roundMask) @[RoundRawFNToRecFN.scala 118:26] - node T_133 = shr(T_132, 2) @[RoundRawFNToRecFN.scala 118:38] - node T_135 = add(T_133, UInt<1>("h01")) @[RoundRawFNToRecFN.scala 118:43] - node T_136 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 119:48] - node T_138 = eq(anyRoundExtra, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 120:26] - node T_139 = and(T_136, T_138) @[RoundRawFNToRecFN.scala 119:63] - node T_140 = shr(roundMask, 1) @[RoundRawFNToRecFN.scala 121:31] - node T_142 = mux(T_139, T_140, UInt<26>("h00")) @[RoundRawFNToRecFN.scala 119:21] - node T_143 = not(T_142) @[RoundRawFNToRecFN.scala 119:17] - node T_144 = and(T_135, T_143) @[RoundRawFNToRecFN.scala 118:55] - node T_145 = not(roundMask) @[RoundRawFNToRecFN.scala 124:26] - node T_146 = and(io.in.sig, T_145) @[RoundRawFNToRecFN.scala 124:24] - node T_147 = shr(T_146, 2) @[RoundRawFNToRecFN.scala 124:37] - node roundedSig = mux(T_131, T_144, T_147) @[RoundRawFNToRecFN.scala 116:12] - node T_148 = shr(roundedSig, 24) @[RoundRawFNToRecFN.scala 127:48] - node T_149 = cvt(T_148) @[RoundRawFNToRecFN.scala 127:60] - node sRoundedExp = add(io.in.sExp, T_149) @[RoundRawFNToRecFN.scala 127:34] - node common_expOut = bits(sRoundedExp, 8, 0) @[RoundRawFNToRecFN.scala 129:36] - node T_150 = bits(roundedSig, 23, 1) @[RoundRawFNToRecFN.scala 132:23] - node T_151 = bits(roundedSig, 22, 0) @[RoundRawFNToRecFN.scala 133:23] - node common_fractOut = mux(doShiftSigDown1, T_150, T_151) @[RoundRawFNToRecFN.scala 131:12] - node T_152 = shr(sRoundedExp, 7) @[RoundRawFNToRecFN.scala 136:39] - node common_overflow = geq(T_152, asSInt(UInt<3>("h03"))) @[RoundRawFNToRecFN.scala 136:56] - node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) @[RoundRawFNToRecFN.scala 138:46] - node T_157 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) @[RoundRawFNToRecFN.scala 142:21] - node T_158 = lt(io.in.sExp, T_157) @[RoundRawFNToRecFN.scala 141:25] - node common_underflow = and(common_inexact, T_158) @[RoundRawFNToRecFN.scala 140:18] - node isNaNOut = or(io.invalidExc, io.in.isNaN) @[RoundRawFNToRecFN.scala 147:34] - node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[RoundRawFNToRecFN.scala 148:49] - node T_160 = eq(isNaNOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:22] - node T_162 = eq(notNaN_isSpecialInfOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:36] - node T_163 = and(T_160, T_162) @[RoundRawFNToRecFN.scala 149:33] - node T_165 = eq(io.in.isZero, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:64] - node commonCase = and(T_163, T_165) @[RoundRawFNToRecFN.scala 149:61] - node overflow = and(commonCase, common_overflow) @[RoundRawFNToRecFN.scala 150:32] - node underflow = and(commonCase, common_underflow) @[RoundRawFNToRecFN.scala 151:32] - node T_166 = and(commonCase, common_inexact) @[RoundRawFNToRecFN.scala 152:43] - node inexact = or(overflow, T_166) @[RoundRawFNToRecFN.scala 152:28] - node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[RoundRawFNToRecFN.scala 154:57] - node T_167 = and(commonCase, common_totalUnderflow) @[RoundRawFNToRecFN.scala 155:42] - node pegMinNonzeroMagOut = and(T_167, roundMagUp) @[RoundRawFNToRecFN.scala 155:67] - node T_168 = and(commonCase, overflow) @[RoundRawFNToRecFN.scala 156:41] - node T_170 = eq(overflow_roundMagUp, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 156:56] - node pegMaxFiniteMagOut = and(T_168, T_170) @[RoundRawFNToRecFN.scala 156:53] - node T_171 = and(overflow, overflow_roundMagUp) @[RoundRawFNToRecFN.scala 158:45] - node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_171) @[RoundRawFNToRecFN.scala 158:32] - node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) @[RoundRawFNToRecFN.scala 160:22] - node T_173 = or(io.in.isZero, common_totalUnderflow) @[RoundRawFNToRecFN.scala 163:32] - node T_176 = mux(T_173, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 163:18] - node T_177 = not(T_176) @[RoundRawFNToRecFN.scala 163:14] - node T_178 = and(common_expOut, T_177) @[RoundRawFNToRecFN.scala 162:24] - node T_180 = not(UInt<9>("h06b")) @[RoundRawFNToRecFN.scala 168:19] - node T_182 = mux(pegMinNonzeroMagOut, T_180, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 167:18] - node T_183 = not(T_182) @[RoundRawFNToRecFN.scala 167:14] - node T_184 = and(T_178, T_183) @[RoundRawFNToRecFN.scala 166:17] - node T_187 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 171:18] - node T_188 = not(T_187) @[RoundRawFNToRecFN.scala 171:14] - node T_189 = and(T_184, T_188) @[RoundRawFNToRecFN.scala 170:17] - node T_192 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 175:18] - node T_193 = not(T_192) @[RoundRawFNToRecFN.scala 175:14] - node T_194 = and(T_189, T_193) @[RoundRawFNToRecFN.scala 174:17] - node T_197 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 179:16] - node T_198 = or(T_194, T_197) @[RoundRawFNToRecFN.scala 178:18] - node T_201 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 183:16] - node T_202 = or(T_198, T_201) @[RoundRawFNToRecFN.scala 182:15] - node T_205 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 187:16] - node T_206 = or(T_202, T_205) @[RoundRawFNToRecFN.scala 186:15] - node T_209 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 188:16] - node expOut = or(T_206, T_209) @[RoundRawFNToRecFN.scala 187:71] - node T_210 = or(common_totalUnderflow, isNaNOut) @[RoundRawFNToRecFN.scala 190:35] - node T_212 = shl(UInt<1>("h01"), 22) @[RoundRawFNToRecFN.scala 191:34] - node T_214 = mux(isNaNOut, T_212, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 191:16] - node T_215 = mux(T_210, T_214, common_fractOut) @[RoundRawFNToRecFN.scala 190:12] - node T_216 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 33:15] - node T_219 = mux(T_216, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 33:12] - node fractOut = or(T_215, T_219) @[RoundRawFNToRecFN.scala 193:11] - node T_220 = cat(signOut, expOut) @[Cat.scala 20:58] - node T_221 = cat(T_220, fractOut) @[Cat.scala 20:58] - io.out <= T_221 @[RoundRawFNToRecFN.scala 196:12] - node T_222 = cat(underflow, inexact) @[Cat.scala 20:58] - node T_223 = cat(io.invalidExc, io.infiniteExc) @[Cat.scala 20:58] - node T_224 = cat(T_223, overflow) @[Cat.scala 20:58] - node T_225 = cat(T_224, T_222) @[Cat.scala 20:58] - io.exceptionFlags <= T_225 @[RoundRawFNToRecFN.scala 197:23] - - module RecFNToRecFN : + node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h0")) + node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h1")) + node roundingMode_min = eq(io.roundingMode, UInt<2>("h2")) + node roundingMode_max = eq(io.roundingMode, UInt<2>("h3")) + node T_19 = and(roundingMode_min, io.in.sign) + node T_21 = eq(io.in.sign, UInt<1>("h0")) + node T_22 = and(roundingMode_max, T_21) + node roundMagUp = or(T_19, T_22) + node doShiftSigDown1 = bits(io.in.sig, 26, 26) + node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h0"))) + node T_24 = bits(isNegExp, 0, 0) + node T_27 = mux(T_24, UInt<25>("h1ffffff"), UInt<25>("h0")) + node T_28 = bits(io.in.sExp, 8, 0) + node T_29 = not(T_28) + node T_30 = bits(T_29, 8, 8) + node T_31 = bits(T_29, 7, 0) + node T_32 = bits(T_31, 7, 7) + node T_33 = bits(T_31, 6, 0) + node T_34 = bits(T_33, 6, 6) + node T_35 = bits(T_33, 5, 0) + node T_38 = dshr(asSInt(UInt<65>("h10000000000000000")), T_35) + node T_39 = bits(T_38, 63, 42) + node T_40 = bits(T_39, 15, 0) + node T_43 = shl(UInt<8>("hff"), 8) + node T_44 = xor(UInt<16>("hffff"), T_43) + node T_45 = shr(T_40, 8) + node T_46 = and(T_45, T_44) + node T_47 = bits(T_40, 7, 0) + node T_48 = shl(T_47, 8) + node T_49 = not(T_44) + node T_50 = and(T_48, T_49) + node T_51 = or(T_46, T_50) + node T_52 = bits(T_44, 11, 0) + node T_53 = shl(T_52, 4) + node T_54 = xor(T_44, T_53) + node T_55 = shr(T_51, 4) + node T_56 = and(T_55, T_54) + node T_57 = bits(T_51, 11, 0) + node T_58 = shl(T_57, 4) + node T_59 = not(T_54) + node T_60 = and(T_58, T_59) + node T_61 = or(T_56, T_60) + node T_62 = bits(T_54, 13, 0) + node T_63 = shl(T_62, 2) + node T_64 = xor(T_54, T_63) + node T_65 = shr(T_61, 2) + node T_66 = and(T_65, T_64) + node T_67 = bits(T_61, 13, 0) + node T_68 = shl(T_67, 2) + node T_69 = not(T_64) + node T_70 = and(T_68, T_69) + node T_71 = or(T_66, T_70) + node T_72 = bits(T_64, 14, 0) + node T_73 = shl(T_72, 1) + node T_74 = xor(T_64, T_73) + node T_75 = shr(T_71, 1) + node T_76 = and(T_75, T_74) + node T_77 = bits(T_71, 14, 0) + node T_78 = shl(T_77, 1) + node T_79 = not(T_74) + node T_80 = and(T_78, T_79) + node T_81 = or(T_76, T_80) + node T_82 = bits(T_39, 21, 16) + node T_83 = bits(T_82, 3, 0) + node T_84 = bits(T_83, 1, 0) + node T_85 = bits(T_84, 0, 0) + node T_86 = bits(T_84, 1, 1) + node T_87 = cat(T_85, T_86) + node T_88 = bits(T_83, 3, 2) + node T_89 = bits(T_88, 0, 0) + node T_90 = bits(T_88, 1, 1) + node T_91 = cat(T_89, T_90) + node T_92 = cat(T_87, T_91) + node T_93 = bits(T_82, 5, 4) + node T_94 = bits(T_93, 0, 0) + node T_95 = bits(T_93, 1, 1) + node T_96 = cat(T_94, T_95) + node T_97 = cat(T_92, T_96) + node T_98 = cat(T_81, T_97) + node T_99 = not(T_98) + node T_100 = mux(T_34, UInt<1>("h0"), T_99) + node T_101 = not(T_100) + node T_103 = cat(T_101, UInt<3>("h7")) + node T_104 = bits(T_33, 6, 6) + node T_105 = bits(T_33, 5, 0) + node T_107 = dshr(asSInt(UInt<65>("h10000000000000000")), T_105) + node T_108 = bits(T_107, 2, 0) + node T_109 = bits(T_108, 1, 0) + node T_110 = bits(T_109, 0, 0) + node T_111 = bits(T_109, 1, 1) + node T_112 = cat(T_110, T_111) + node T_113 = bits(T_108, 2, 2) + node T_114 = cat(T_112, T_113) + node T_116 = mux(T_104, T_114, UInt<1>("h0")) + node T_117 = mux(T_32, T_103, T_116) + node T_119 = mux(T_30, T_117, UInt<1>("h0")) + node T_120 = or(T_27, T_119) + node T_121 = or(T_120, doShiftSigDown1) + node roundMask = cat(T_121, UInt<2>("h3")) + node T_123 = cat(isNegExp, roundMask) + node shiftedRoundMask = shr(T_123, 1) + node T_124 = not(shiftedRoundMask) + node roundPosMask = and(T_124, roundMask) + node T_125 = and(io.in.sig, roundPosMask) + node roundPosBit = neq(T_125, UInt<1>("h0")) + node T_127 = and(io.in.sig, shiftedRoundMask) + node anyRoundExtra = neq(T_127, UInt<1>("h0")) + node common_inexact = or(roundPosBit, anyRoundExtra) + node T_129 = and(roundingMode_nearest_even, roundPosBit) + node T_130 = and(roundMagUp, common_inexact) + node T_131 = or(T_129, T_130) + node T_132 = or(io.in.sig, roundMask) + node T_133 = shr(T_132, 2) + node T_135 = add(T_133, UInt<1>("h1")) + node T_136 = and(roundingMode_nearest_even, roundPosBit) + node T_138 = eq(anyRoundExtra, UInt<1>("h0")) + node T_139 = and(T_136, T_138) + node T_140 = shr(roundMask, 1) + node T_142 = mux(T_139, T_140, UInt<26>("h0")) + node T_143 = not(T_142) + node T_144 = and(T_135, T_143) + node T_145 = not(roundMask) + node T_146 = and(io.in.sig, T_145) + node T_147 = shr(T_146, 2) + node roundedSig = mux(T_131, T_144, T_147) + node T_148 = shr(roundedSig, 24) + node T_149 = cvt(T_148) + node sRoundedExp = add(io.in.sExp, T_149) + node common_expOut = bits(sRoundedExp, 8, 0) + node T_150 = bits(roundedSig, 23, 1) + node T_151 = bits(roundedSig, 22, 0) + node common_fractOut = mux(doShiftSigDown1, T_150, T_151) + node T_152 = shr(sRoundedExp, 7) + node common_overflow = geq(T_152, asSInt(UInt<3>("h3"))) + node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h6b"))) + node T_157 = mux(doShiftSigDown1, asSInt(UInt<9>("h81")), asSInt(UInt<9>("h82"))) + node T_158 = lt(io.in.sExp, T_157) + node common_underflow = and(common_inexact, T_158) + node isNaNOut = or(io.invalidExc, io.in.isNaN) + node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) + node T_160 = eq(isNaNOut, UInt<1>("h0")) + node T_162 = eq(notNaN_isSpecialInfOut, UInt<1>("h0")) + node T_163 = and(T_160, T_162) + node T_165 = eq(io.in.isZero, UInt<1>("h0")) + node commonCase = and(T_163, T_165) + node overflow = and(commonCase, common_overflow) + node underflow = and(commonCase, common_underflow) + node T_166 = and(commonCase, common_inexact) + node inexact = or(overflow, T_166) + node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) + node T_167 = and(commonCase, common_totalUnderflow) + node pegMinNonzeroMagOut = and(T_167, roundMagUp) + node T_168 = and(commonCase, overflow) + node T_170 = eq(overflow_roundMagUp, UInt<1>("h0")) + node pegMaxFiniteMagOut = and(T_168, T_170) + node T_171 = and(overflow, overflow_roundMagUp) + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_171) + node signOut = mux(isNaNOut, UInt<1>("h0"), io.in.sign) + node T_173 = or(io.in.isZero, common_totalUnderflow) + node T_176 = mux(T_173, UInt<9>("h1c0"), UInt<1>("h0")) + node T_177 = not(T_176) + node T_178 = and(common_expOut, T_177) + node T_180 = not(UInt<9>("h6b")) + node T_182 = mux(pegMinNonzeroMagOut, T_180, UInt<1>("h0")) + node T_183 = not(T_182) + node T_184 = and(T_178, T_183) + node T_187 = mux(pegMaxFiniteMagOut, UInt<9>("h80"), UInt<1>("h0")) + node T_188 = not(T_187) + node T_189 = and(T_184, T_188) + node T_192 = mux(notNaN_isInfOut, UInt<9>("h40"), UInt<1>("h0")) + node T_193 = not(T_192) + node T_194 = and(T_189, T_193) + node T_197 = mux(pegMinNonzeroMagOut, UInt<9>("h6b"), UInt<1>("h0")) + node T_198 = or(T_194, T_197) + node T_201 = mux(pegMaxFiniteMagOut, UInt<9>("h17f"), UInt<1>("h0")) + node T_202 = or(T_198, T_201) + node T_205 = mux(notNaN_isInfOut, UInt<9>("h180"), UInt<1>("h0")) + node T_206 = or(T_202, T_205) + node T_209 = mux(isNaNOut, UInt<9>("h1c0"), UInt<1>("h0")) + node expOut = or(T_206, T_209) + node T_210 = or(common_totalUnderflow, isNaNOut) + node T_212 = shl(UInt<1>("h1"), 22) + node T_214 = mux(isNaNOut, T_212, UInt<1>("h0")) + node T_215 = mux(T_210, T_214, common_fractOut) + node T_216 = bits(pegMaxFiniteMagOut, 0, 0) + node T_219 = mux(T_216, UInt<23>("h7fffff"), UInt<23>("h0")) + node fractOut = or(T_215, T_219) + node T_220 = cat(signOut, expOut) + node T_221 = cat(T_220, fractOut) + io.out <= T_221 + node T_222 = cat(underflow, inexact) + node T_223 = cat(io.invalidExc, io.infiniteExc) + node T_224 = cat(T_223, overflow) + node T_225 = cat(T_224, T_222) + io.exceptionFlags <= T_225 + + module RecFNToRecFN : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - node T_4 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] - node T_5 = bits(T_4, 11, 9) @[rawFNFromRecFN.scala 51:29] - node T_7 = eq(T_5, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] - node T_8 = bits(T_4, 11, 10) @[rawFNFromRecFN.scala 52:29] - node T_10 = eq(T_8, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] - wire T_18 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] - T_18 is invalid @[rawFNFromRecFN.scala 54:23] - node T_25 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] - T_18.sign <= T_25 @[rawFNFromRecFN.scala 55:18] - node T_26 = bits(T_4, 9, 9) @[rawFNFromRecFN.scala 56:40] - node T_27 = and(T_10, T_26) @[rawFNFromRecFN.scala 56:32] - T_18.isNaN <= T_27 @[rawFNFromRecFN.scala 56:19] - node T_28 = bits(T_4, 9, 9) @[rawFNFromRecFN.scala 57:40] - node T_30 = eq(T_28, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] - node T_31 = and(T_10, T_30) @[rawFNFromRecFN.scala 57:32] - T_18.isInf <= T_31 @[rawFNFromRecFN.scala 57:19] - T_18.isZero <= T_7 @[rawFNFromRecFN.scala 58:20] - node T_32 = cvt(T_4) @[rawFNFromRecFN.scala 59:25] - T_18.sExp <= T_32 @[rawFNFromRecFN.scala 59:18] - node T_35 = eq(T_7, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] - node T_36 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] - node T_38 = cat(T_36, UInt<2>("h00")) @[Cat.scala 20:58] - node T_39 = cat(UInt<1>("h00"), T_35) @[Cat.scala 20:58] - node T_40 = cat(T_39, T_38) @[Cat.scala 20:58] - T_18.sig <= T_40 @[rawFNFromRecFN.scala 60:17] - node T_42 = add(T_18.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] - wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] - outRawFloat is invalid @[resizeRawFN.scala 51:23] - outRawFloat.sign <= T_18.sign @[resizeRawFN.scala 52:20] - outRawFloat.isNaN <= T_18.isNaN @[resizeRawFN.scala 53:20] - outRawFloat.isInf <= T_18.isInf @[resizeRawFN.scala 54:20] - outRawFloat.isZero <= T_18.isZero @[resizeRawFN.scala 55:20] - node T_57 = lt(T_42, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] - node T_58 = bits(T_42, 12, 9) @[resizeRawFN.scala 61:33] - node T_60 = neq(T_58, UInt<1>("h00")) @[resizeRawFN.scala 61:65] - node T_65 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_67 = cat(T_65, UInt<2>("h00")) @[Cat.scala 20:58] - node T_68 = bits(T_42, 8, 0) @[resizeRawFN.scala 63:33] - node T_69 = mux(T_60, T_67, T_68) @[resizeRawFN.scala 61:25] - node T_70 = cat(T_57, T_69) @[Cat.scala 20:58] - node T_71 = asSInt(T_70) @[resizeRawFN.scala 65:20] - outRawFloat.sExp <= T_71 @[resizeRawFN.scala 56:18] - node T_72 = bits(T_18.sig, 55, 30) @[resizeRawFN.scala 71:28] - node T_73 = bits(T_18.sig, 29, 0) @[resizeRawFN.scala 72:28] - node T_75 = neq(T_73, UInt<1>("h00")) @[resizeRawFN.scala 72:56] - node T_76 = cat(T_72, T_75) @[Cat.scala 20:58] - outRawFloat.sig <= T_76 @[resizeRawFN.scala 67:17] - node T_77 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] - node T_79 = eq(T_77, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] - node invalidExc = and(outRawFloat.isNaN, T_79) @[RoundRawFNToRecFN.scala 61:46] - inst RoundRawFNToRecFN_1 of RoundRawFNToRecFN @[RecFNToRecFN.scala 102:19] + node T_4 = bits(io.in, 63, 52) + node T_5 = bits(T_4, 11, 9) + node T_7 = eq(T_5, UInt<1>("h0")) + node T_8 = bits(T_4, 11, 10) + node T_10 = eq(T_8, UInt<2>("h3")) + wire T_18 : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} + T_18 is invalid + node T_25 = bits(io.in, 64, 64) + T_18.sign <= T_25 + node T_26 = bits(T_4, 9, 9) + node T_27 = and(T_10, T_26) + T_18.isNaN <= T_27 + node T_28 = bits(T_4, 9, 9) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = and(T_10, T_30) + T_18.isInf <= T_31 + T_18.isZero <= T_7 + node T_32 = cvt(T_4) + T_18.sExp <= T_32 + node T_35 = eq(T_7, UInt<1>("h0")) + node T_36 = bits(io.in, 51, 0) + node T_38 = cat(T_36, UInt<2>("h0")) + node T_39 = cat(UInt<1>("h0"), T_35) + node T_40 = cat(T_39, T_38) + T_18.sig <= T_40 + node T_42 = add(T_18.sExp, asSInt(UInt<12>("h900"))) + wire outRawFloat : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} + outRawFloat is invalid + outRawFloat.sign <= T_18.sign + outRawFloat.isNaN <= T_18.isNaN + outRawFloat.isInf <= T_18.isInf + outRawFloat.isZero <= T_18.isZero + node T_57 = lt(T_42, asSInt(UInt<1>("h0"))) + node T_58 = bits(T_42, 12, 9) + node T_60 = neq(T_58, UInt<1>("h0")) + node T_65 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_67 = cat(T_65, UInt<2>("h0")) + node T_68 = bits(T_42, 8, 0) + node T_69 = mux(T_60, T_67, T_68) + node T_70 = cat(T_57, T_69) + node T_71 = asSInt(T_70) + outRawFloat.sExp <= T_71 + node T_72 = bits(T_18.sig, 55, 30) + node T_73 = bits(T_18.sig, 29, 0) + node T_75 = neq(T_73, UInt<1>("h0")) + node T_76 = cat(T_72, T_75) + outRawFloat.sig <= T_76 + node T_77 = bits(outRawFloat.sig, 24, 24) + node T_79 = eq(T_77, UInt<1>("h0")) + node invalidExc = and(outRawFloat.isNaN, T_79) + inst RoundRawFNToRecFN_1 of RoundRawFNToRecFN RoundRawFNToRecFN_1.io is invalid RoundRawFNToRecFN_1.clk <= clk RoundRawFNToRecFN_1.reset <= reset - RoundRawFNToRecFN_1.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] - RoundRawFNToRecFN_1.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] - RoundRawFNToRecFN_1.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] - RoundRawFNToRecFN_1.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] - io.out <= RoundRawFNToRecFN_1.io.out @[RecFNToRecFN.scala 107:16] - io.exceptionFlags <= RoundRawFNToRecFN_1.io.exceptionFlags @[RecFNToRecFN.scala 108:27] - - module RecFNToRecFN_1 : + RoundRawFNToRecFN_1.io.invalidExc <= invalidExc + RoundRawFNToRecFN_1.io.infiniteExc <= UInt<1>("h0") + RoundRawFNToRecFN_1.io.in <- outRawFloat + RoundRawFNToRecFN_1.io.roundingMode <= io.roundingMode + io.out <= RoundRawFNToRecFN_1.io.out + io.exceptionFlags <= RoundRawFNToRecFN_1.io.exceptionFlags + + module RecFNToRecFN_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - + output io : { flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + io is invalid - node T_4 = bits(io.in, 31, 23) @[rawFNFromRecFN.scala 50:21] - node T_5 = bits(T_4, 8, 6) @[rawFNFromRecFN.scala 51:29] - node T_7 = eq(T_5, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] - node T_8 = bits(T_4, 8, 7) @[rawFNFromRecFN.scala 52:29] - node T_10 = eq(T_8, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] - wire T_18 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[rawFNFromRecFN.scala 54:23] - T_18 is invalid @[rawFNFromRecFN.scala 54:23] - node T_25 = bits(io.in, 32, 32) @[rawFNFromRecFN.scala 55:23] - T_18.sign <= T_25 @[rawFNFromRecFN.scala 55:18] - node T_26 = bits(T_4, 6, 6) @[rawFNFromRecFN.scala 56:40] - node T_27 = and(T_10, T_26) @[rawFNFromRecFN.scala 56:32] - T_18.isNaN <= T_27 @[rawFNFromRecFN.scala 56:19] - node T_28 = bits(T_4, 6, 6) @[rawFNFromRecFN.scala 57:40] - node T_30 = eq(T_28, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] - node T_31 = and(T_10, T_30) @[rawFNFromRecFN.scala 57:32] - T_18.isInf <= T_31 @[rawFNFromRecFN.scala 57:19] - T_18.isZero <= T_7 @[rawFNFromRecFN.scala 58:20] - node T_32 = cvt(T_4) @[rawFNFromRecFN.scala 59:25] - T_18.sExp <= T_32 @[rawFNFromRecFN.scala 59:18] - node T_35 = eq(T_7, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] - node T_36 = bits(io.in, 22, 0) @[rawFNFromRecFN.scala 60:48] - node T_38 = cat(T_36, UInt<2>("h00")) @[Cat.scala 20:58] - node T_39 = cat(UInt<1>("h00"), T_35) @[Cat.scala 20:58] - node T_40 = cat(T_39, T_38) @[Cat.scala 20:58] - T_18.sig <= T_40 @[rawFNFromRecFN.scala 60:17] - node T_42 = add(T_18.sExp, asSInt(UInt<12>("h0700"))) @[resizeRawFN.scala 49:31] - wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[resizeRawFN.scala 51:23] - outRawFloat is invalid @[resizeRawFN.scala 51:23] - outRawFloat.sign <= T_18.sign @[resizeRawFN.scala 52:20] - outRawFloat.isNaN <= T_18.isNaN @[resizeRawFN.scala 53:20] - outRawFloat.isInf <= T_18.isInf @[resizeRawFN.scala 54:20] - outRawFloat.isZero <= T_18.isZero @[resizeRawFN.scala 55:20] - outRawFloat.sExp <= T_42 @[resizeRawFN.scala 56:18] - node T_56 = shl(T_18.sig, 29) @[resizeRawFN.scala 69:24] - outRawFloat.sig <= T_56 @[resizeRawFN.scala 67:17] - node T_57 = bits(outRawFloat.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] - node T_59 = eq(T_57, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] - node invalidExc = and(outRawFloat.isNaN, T_59) @[RoundRawFNToRecFN.scala 61:46] - node T_61 = eq(outRawFloat.isNaN, UInt<1>("h00")) @[RecFNToRecFN.scala 69:40] - node T_62 = and(outRawFloat.sign, T_61) @[RecFNToRecFN.scala 69:37] - node T_63 = bits(outRawFloat.sExp, 11, 0) @[RecFNToRecFN.scala 71:30] - node T_66 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 72:22] - node T_67 = not(T_66) @[RecFNToRecFN.scala 72:18] - node T_68 = and(T_63, T_67) @[RecFNToRecFN.scala 71:47] - node T_69 = or(outRawFloat.isZero, outRawFloat.isInf) @[RecFNToRecFN.scala 76:42] - node T_72 = mux(T_69, UInt<12>("h0200"), UInt<1>("h00")) @[RecFNToRecFN.scala 76:22] - node T_73 = not(T_72) @[RecFNToRecFN.scala 76:18] - node T_74 = and(T_68, T_73) @[RecFNToRecFN.scala 75:21] - node T_77 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 80:20] - node T_78 = or(T_74, T_77) @[RecFNToRecFN.scala 79:22] - node T_81 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) @[RecFNToRecFN.scala 84:20] - node T_82 = or(T_78, T_81) @[RecFNToRecFN.scala 83:19] - node T_84 = shl(UInt<1>("h01"), 51) @[RecFNToRecFN.scala 90:24] - node T_85 = bits(outRawFloat.sig, 53, 2) @[RecFNToRecFN.scala 91:32] - node T_86 = mux(outRawFloat.isNaN, T_84, T_85) @[RecFNToRecFN.scala 89:16] - node T_87 = cat(T_62, T_82) @[Cat.scala 20:58] - node T_88 = cat(T_87, T_86) @[Cat.scala 20:58] - io.out <= T_88 @[RecFNToRecFN.scala 93:16] - node T_90 = cat(invalidExc, UInt<4>("h00")) @[Cat.scala 20:58] - io.exceptionFlags <= T_90 @[RecFNToRecFN.scala 94:27] - - module FPToFP : + node T_4 = bits(io.in, 31, 23) + node T_5 = bits(T_4, 8, 6) + node T_7 = eq(T_5, UInt<1>("h0")) + node T_8 = bits(T_4, 8, 7) + node T_10 = eq(T_8, UInt<2>("h3")) + wire T_18 : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} + T_18 is invalid + node T_25 = bits(io.in, 32, 32) + T_18.sign <= T_25 + node T_26 = bits(T_4, 6, 6) + node T_27 = and(T_10, T_26) + T_18.isNaN <= T_27 + node T_28 = bits(T_4, 6, 6) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = and(T_10, T_30) + T_18.isInf <= T_31 + T_18.isZero <= T_7 + node T_32 = cvt(T_4) + T_18.sExp <= T_32 + node T_35 = eq(T_7, UInt<1>("h0")) + node T_36 = bits(io.in, 22, 0) + node T_38 = cat(T_36, UInt<2>("h0")) + node T_39 = cat(UInt<1>("h0"), T_35) + node T_40 = cat(T_39, T_38) + T_18.sig <= T_40 + node T_42 = add(T_18.sExp, asSInt(UInt<12>("h700"))) + wire outRawFloat : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} + outRawFloat is invalid + outRawFloat.sign <= T_18.sign + outRawFloat.isNaN <= T_18.isNaN + outRawFloat.isInf <= T_18.isInf + outRawFloat.isZero <= T_18.isZero + outRawFloat.sExp <= T_42 + node T_56 = shl(T_18.sig, 29) + outRawFloat.sig <= T_56 + node T_57 = bits(outRawFloat.sig, 53, 53) + node T_59 = eq(T_57, UInt<1>("h0")) + node invalidExc = and(outRawFloat.isNaN, T_59) + node T_61 = eq(outRawFloat.isNaN, UInt<1>("h0")) + node T_62 = and(outRawFloat.sign, T_61) + node T_63 = bits(outRawFloat.sExp, 11, 0) + node T_66 = mux(outRawFloat.isZero, UInt<12>("hc00"), UInt<1>("h0")) + node T_67 = not(T_66) + node T_68 = and(T_63, T_67) + node T_69 = or(outRawFloat.isZero, outRawFloat.isInf) + node T_72 = mux(T_69, UInt<12>("h200"), UInt<1>("h0")) + node T_73 = not(T_72) + node T_74 = and(T_68, T_73) + node T_77 = mux(outRawFloat.isInf, UInt<12>("hc00"), UInt<1>("h0")) + node T_78 = or(T_74, T_77) + node T_81 = mux(outRawFloat.isNaN, UInt<12>("he00"), UInt<1>("h0")) + node T_82 = or(T_78, T_81) + node T_84 = shl(UInt<1>("h1"), 51) + node T_85 = bits(outRawFloat.sig, 53, 2) + node T_86 = mux(outRawFloat.isNaN, T_84, T_85) + node T_87 = cat(T_62, T_82) + node T_88 = cat(T_87, T_86) + io.out <= T_88 + node T_90 = cat(invalidExc, UInt<4>("h0")) + io.exceptionFlags <= T_90 + + module FPToFP : input clk : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} - + output io : { flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} + io is invalid - reg T_133 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_133 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_133 <= io.in.valid - reg T_134 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : @[Reg.scala 29:19] - T_134 <- io.in.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 39:21] - in is invalid @[Valid.scala 39:21] - in.valid <= T_133 @[Valid.scala 40:17] - in.bits <- T_134 @[Valid.scala 41:16] - node T_252 = bits(in.bits.rm, 1, 1) @[fpu.scala 404:33] - node T_253 = xor(in.bits.in1, in.bits.in2) @[fpu.scala 404:50] - node T_254 = bits(in.bits.rm, 0, 0) @[fpu.scala 404:79] - node T_255 = not(in.bits.in2) @[fpu.scala 404:84] - node T_256 = mux(T_254, T_255, in.bits.in2) @[fpu.scala 404:68] - node signNum = mux(T_252, T_253, T_256) @[fpu.scala 404:22] - node T_257 = bits(signNum, 32, 32) @[fpu.scala 405:30] - node T_258 = bits(in.bits.in1, 31, 0) @[fpu.scala 405:47] - node fsgnj_s = cat(T_257, T_258) @[Cat.scala 20:58] - node T_259 = shr(in.bits.in1, 33) @[fpu.scala 408:54] - node T_260 = cat(T_259, fsgnj_s) @[Cat.scala 20:58] - node T_261 = bits(signNum, 64, 64) @[fpu.scala 409:49] - node T_262 = bits(in.bits.in1, 63, 0) @[fpu.scala 409:66] - node T_263 = cat(T_261, T_262) @[Cat.scala 20:58] - node fsgnj = mux(in.bits.single, T_260, T_263) @[fpu.scala 408:21] - wire mux : {data : UInt<65>, exc : UInt<5>} @[fpu.scala 411:19] - mux is invalid @[fpu.scala 411:19] - mux.exc <= UInt<1>("h00") @[fpu.scala 412:13] - mux.data <= fsgnj @[fpu.scala 413:14] - node T_272 = and(in.bits.cmd, UInt<4>("h0d")) @[fpu.scala 415:23] - node T_273 = eq(UInt<5>("h05"), T_272) @[fpu.scala 415:23] - when T_273 : @[fpu.scala 415:40] - node T_274 = bits(in.bits.in1, 31, 29) @[fpu.scala 223:7] - node T_275 = not(T_274) @[fpu.scala 223:58] - node T_277 = eq(T_275, UInt<1>("h00")) @[fpu.scala 223:58] - node T_278 = bits(in.bits.in2, 31, 29) @[fpu.scala 223:7] - node T_279 = not(T_278) @[fpu.scala 223:58] - node T_281 = eq(T_279, UInt<1>("h00")) @[fpu.scala 223:58] - node T_282 = bits(in.bits.in1, 31, 29) @[fpu.scala 223:7] - node T_283 = not(T_282) @[fpu.scala 223:58] - node T_285 = eq(T_283, UInt<1>("h00")) @[fpu.scala 223:58] - node T_286 = bits(in.bits.in1, 22, 22) @[fpu.scala 228:46] - node T_288 = eq(T_286, UInt<1>("h00")) @[fpu.scala 228:43] - node T_289 = and(T_285, T_288) @[fpu.scala 228:40] - node T_290 = bits(in.bits.in2, 31, 29) @[fpu.scala 223:7] - node T_291 = not(T_290) @[fpu.scala 223:58] - node T_293 = eq(T_291, UInt<1>("h00")) @[fpu.scala 223:58] - node T_294 = bits(in.bits.in2, 22, 22) @[fpu.scala 228:46] - node T_296 = eq(T_294, UInt<1>("h00")) @[fpu.scala 228:43] - node T_297 = and(T_293, T_296) @[fpu.scala 228:40] - node T_298 = bits(in.bits.rm, 0, 0) @[fpu.scala 421:30] - node T_299 = neq(T_298, io.lt) @[fpu.scala 421:34] - node T_301 = eq(T_277, UInt<1>("h00")) @[fpu.scala 421:47] - node T_302 = and(T_299, T_301) @[fpu.scala 421:44] - node T_303 = or(T_281, T_302) @[fpu.scala 421:17] - node T_304 = or(T_289, T_297) @[fpu.scala 421:64] - node T_305 = bits(in.bits.in1, 63, 61) @[fpu.scala 223:7] - node T_306 = not(T_305) @[fpu.scala 223:58] - node T_308 = eq(T_306, UInt<1>("h00")) @[fpu.scala 223:58] - node T_309 = bits(in.bits.in2, 63, 61) @[fpu.scala 223:7] - node T_310 = not(T_309) @[fpu.scala 223:58] - node T_312 = eq(T_310, UInt<1>("h00")) @[fpu.scala 223:58] - node T_313 = bits(in.bits.in1, 63, 61) @[fpu.scala 223:7] - node T_314 = not(T_313) @[fpu.scala 223:58] - node T_316 = eq(T_314, UInt<1>("h00")) @[fpu.scala 223:58] - node T_317 = bits(in.bits.in1, 51, 51) @[fpu.scala 228:46] - node T_319 = eq(T_317, UInt<1>("h00")) @[fpu.scala 228:43] - node T_320 = and(T_316, T_319) @[fpu.scala 228:40] - node T_321 = bits(in.bits.in2, 63, 61) @[fpu.scala 223:7] - node T_322 = not(T_321) @[fpu.scala 223:58] - node T_324 = eq(T_322, UInt<1>("h00")) @[fpu.scala 223:58] - node T_325 = bits(in.bits.in2, 51, 51) @[fpu.scala 228:46] - node T_327 = eq(T_325, UInt<1>("h00")) @[fpu.scala 228:43] - node T_328 = and(T_324, T_327) @[fpu.scala 228:40] - node T_329 = bits(in.bits.rm, 0, 0) @[fpu.scala 421:30] - node T_330 = neq(T_329, io.lt) @[fpu.scala 421:34] - node T_332 = eq(T_308, UInt<1>("h00")) @[fpu.scala 421:47] - node T_333 = and(T_330, T_332) @[fpu.scala 421:44] - node T_334 = or(T_312, T_333) @[fpu.scala 421:17] - node T_335 = or(T_320, T_328) @[fpu.scala 421:64] - node T_336 = mux(in.bits.single, T_303, T_334) @[util.scala 39:9] - node T_337 = mux(in.bits.single, T_304, T_335) @[util.scala 39:36] - node T_338 = shl(T_337, 4) @[fpu.scala 427:28] - mux.exc <= T_338 @[fpu.scala 427:15] - mux.data <= in.bits.in1 @[fpu.scala 428:16] - node T_340 = eq(T_336, UInt<1>("h00")) @[fpu.scala 429:13] - when T_340 : @[fpu.scala 429:21] - mux.data <= in.bits.in2 @[fpu.scala 429:32] - skip @[fpu.scala 429:21] - skip @[fpu.scala 415:40] - node T_343 = and(in.bits.cmd, UInt<3>("h04")) @[fpu.scala 435:27] - node T_344 = eq(UInt<5>("h00"), T_343) @[fpu.scala 435:27] - when T_344 : @[fpu.scala 435:44] - when in.bits.single : @[fpu.scala 436:33] - inst RecFNToRecFN_2 of RecFNToRecFN @[fpu.scala 437:29] + reg T_134 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : + reset => (UInt<1>("h0"), T_134) + when io.in.valid : + T_134 <- io.in.bits + wire in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + in is invalid + in.valid <= T_133 + in.bits <- T_134 + node T_252 = bits(in.bits.rm, 1, 1) + node T_253 = xor(in.bits.in1, in.bits.in2) + node T_254 = bits(in.bits.rm, 0, 0) + node T_255 = not(in.bits.in2) + node T_256 = mux(T_254, T_255, in.bits.in2) + node signNum = mux(T_252, T_253, T_256) + node T_257 = bits(signNum, 32, 32) + node T_258 = bits(in.bits.in1, 31, 0) + node fsgnj_s = cat(T_257, T_258) + node T_259 = shr(in.bits.in1, 33) + node T_260 = cat(T_259, fsgnj_s) + node T_261 = bits(signNum, 64, 64) + node T_262 = bits(in.bits.in1, 63, 0) + node T_263 = cat(T_261, T_262) + node fsgnj = mux(in.bits.single, T_260, T_263) + wire mux : { data : UInt<65>, exc : UInt<5>} + mux is invalid + mux.exc <= UInt<1>("h0") + mux.data <= fsgnj + node T_272 = and(in.bits.cmd, UInt<4>("hd")) + node T_273 = eq(UInt<5>("h5"), T_272) + when T_273 : + node T_274 = bits(in.bits.in1, 31, 29) + node T_275 = not(T_274) + node T_277 = eq(T_275, UInt<1>("h0")) + node T_278 = bits(in.bits.in2, 31, 29) + node T_279 = not(T_278) + node T_281 = eq(T_279, UInt<1>("h0")) + node T_282 = bits(in.bits.in1, 31, 29) + node T_283 = not(T_282) + node T_285 = eq(T_283, UInt<1>("h0")) + node T_286 = bits(in.bits.in1, 22, 22) + node T_288 = eq(T_286, UInt<1>("h0")) + node T_289 = and(T_285, T_288) + node T_290 = bits(in.bits.in2, 31, 29) + node T_291 = not(T_290) + node T_293 = eq(T_291, UInt<1>("h0")) + node T_294 = bits(in.bits.in2, 22, 22) + node T_296 = eq(T_294, UInt<1>("h0")) + node T_297 = and(T_293, T_296) + node T_298 = bits(in.bits.rm, 0, 0) + node T_299 = neq(T_298, io.lt) + node T_301 = eq(T_277, UInt<1>("h0")) + node T_302 = and(T_299, T_301) + node T_303 = or(T_281, T_302) + node T_304 = or(T_289, T_297) + node T_305 = bits(in.bits.in1, 63, 61) + node T_306 = not(T_305) + node T_308 = eq(T_306, UInt<1>("h0")) + node T_309 = bits(in.bits.in2, 63, 61) + node T_310 = not(T_309) + node T_312 = eq(T_310, UInt<1>("h0")) + node T_313 = bits(in.bits.in1, 63, 61) + node T_314 = not(T_313) + node T_316 = eq(T_314, UInt<1>("h0")) + node T_317 = bits(in.bits.in1, 51, 51) + node T_319 = eq(T_317, UInt<1>("h0")) + node T_320 = and(T_316, T_319) + node T_321 = bits(in.bits.in2, 63, 61) + node T_322 = not(T_321) + node T_324 = eq(T_322, UInt<1>("h0")) + node T_325 = bits(in.bits.in2, 51, 51) + node T_327 = eq(T_325, UInt<1>("h0")) + node T_328 = and(T_324, T_327) + node T_329 = bits(in.bits.rm, 0, 0) + node T_330 = neq(T_329, io.lt) + node T_332 = eq(T_308, UInt<1>("h0")) + node T_333 = and(T_330, T_332) + node T_334 = or(T_312, T_333) + node T_335 = or(T_320, T_328) + node T_336 = mux(in.bits.single, T_303, T_334) + node T_337 = mux(in.bits.single, T_304, T_335) + node T_338 = shl(T_337, 4) + mux.exc <= T_338 + mux.data <= in.bits.in1 + node T_340 = eq(T_336, UInt<1>("h0")) + when T_340 : + mux.data <= in.bits.in2 + node T_343 = and(in.bits.cmd, UInt<3>("h4")) + node T_344 = eq(UInt<5>("h0"), T_343) + when T_344 : + when in.bits.single : + inst RecFNToRecFN_2 of RecFNToRecFN RecFNToRecFN_2.io is invalid RecFNToRecFN_2.clk <= clk RecFNToRecFN_2.reset <= reset - RecFNToRecFN_2.io.in <= in.bits.in1 @[fpu.scala 438:23] - RecFNToRecFN_2.io.roundingMode <= in.bits.rm @[fpu.scala 439:33] - node T_346 = cat(UInt<32>("h0ffffffff"), RecFNToRecFN_2.io.out) @[Cat.scala 20:58] - mux.data <= T_346 @[fpu.scala 440:20] - mux.exc <= RecFNToRecFN_2.io.exceptionFlags @[fpu.scala 441:19] - skip @[fpu.scala 436:33] - node T_348 = eq(in.bits.single, UInt<1>("h00")) @[fpu.scala 436:33] - when T_348 : @[fpu.scala 442:21] - inst RecFNToRecFN_1_1 of RecFNToRecFN_1 @[fpu.scala 443:27] + RecFNToRecFN_2.io.in <= in.bits.in1 + RecFNToRecFN_2.io.roundingMode <= in.bits.rm + node T_346 = cat(UInt<32>("hffffffff"), RecFNToRecFN_2.io.out) + mux.data <= T_346 + mux.exc <= RecFNToRecFN_2.io.exceptionFlags + node T_348 = eq(in.bits.single, UInt<1>("h0")) + when T_348 : + inst RecFNToRecFN_1_1 of RecFNToRecFN_1 RecFNToRecFN_1_1.io is invalid RecFNToRecFN_1_1.clk <= clk RecFNToRecFN_1_1.reset <= reset - RecFNToRecFN_1_1.io.in <= in.bits.in1 @[fpu.scala 444:21] - RecFNToRecFN_1_1.io.roundingMode <= in.bits.rm @[fpu.scala 445:31] - mux.data <= RecFNToRecFN_1_1.io.out @[fpu.scala 446:20] - mux.exc <= RecFNToRecFN_1_1.io.exceptionFlags @[fpu.scala 447:19] - skip @[fpu.scala 442:21] - skip @[fpu.scala 435:44] - reg T_351 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + RecFNToRecFN_1_1.io.in <= in.bits.in1 + RecFNToRecFN_1_1.io.roundingMode <= in.bits.rm + mux.data <= RecFNToRecFN_1_1.io.out + mux.exc <= RecFNToRecFN_1_1.io.exceptionFlags + reg T_351 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_351 <= in.valid - reg T_352 : {data : UInt<65>, exc : UInt<5>}, clk - when in.valid : @[Reg.scala 29:19] - T_352 <- mux @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire T_363 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 39:21] - T_363 is invalid @[Valid.scala 39:21] - T_363.valid <= T_351 @[Valid.scala 40:17] - T_363.bits <- T_352 @[Valid.scala 41:16] - io.out <- T_363 @[fpu.scala 452:10] - - module MulAddRecFN_preMul_1 : + reg T_352 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_352) + when in.valid : + T_352 <- mux + wire T_363 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} + T_363 is invalid + T_363.valid <= T_351 + T_363.bits <- T_352 + io.out <- T_363 + + module MulAddRecFN_preMul_1 : input clk : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} - + output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} + io is invalid - node signA = bits(io.a, 64, 64) @[MulAddRecFN.scala 102:22] - node expA = bits(io.a, 63, 52) @[MulAddRecFN.scala 103:22] - node fractA = bits(io.a, 51, 0) @[MulAddRecFN.scala 104:22] - node T_42 = bits(expA, 11, 9) @[MulAddRecFN.scala 105:24] - node isZeroA = eq(T_42, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] - node T_45 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] - node sigA = cat(T_45, fractA) @[Cat.scala 20:58] - node signB = bits(io.b, 64, 64) @[MulAddRecFN.scala 108:22] - node expB = bits(io.b, 63, 52) @[MulAddRecFN.scala 109:22] - node fractB = bits(io.b, 51, 0) @[MulAddRecFN.scala 110:22] - node T_46 = bits(expB, 11, 9) @[MulAddRecFN.scala 111:24] - node isZeroB = eq(T_46, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] - node T_49 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] - node sigB = cat(T_49, fractB) @[Cat.scala 20:58] - node T_50 = bits(io.c, 64, 64) @[MulAddRecFN.scala 114:23] - node T_51 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] - node opSignC = xor(T_50, T_51) @[MulAddRecFN.scala 114:45] - node expC = bits(io.c, 63, 52) @[MulAddRecFN.scala 115:22] - node fractC = bits(io.c, 51, 0) @[MulAddRecFN.scala 116:22] - node T_52 = bits(expC, 11, 9) @[MulAddRecFN.scala 117:24] - node isZeroC = eq(T_52, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] - node T_55 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] - node sigC = cat(T_55, fractC) @[Cat.scala 20:58] - node T_56 = xor(signA, signB) @[MulAddRecFN.scala 122:26] - node T_57 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] - node signProd = xor(T_56, T_57) @[MulAddRecFN.scala 122:34] - node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] - node T_58 = bits(expB, 11, 11) @[MulAddRecFN.scala 125:34] - node T_60 = eq(T_58, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] - node T_61 = bits(T_60, 0, 0) @[Bitwise.scala 33:15] - node T_64 = mux(T_61, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_65 = bits(expB, 10, 0) @[MulAddRecFN.scala 125:51] - node T_66 = cat(T_64, T_65) @[Cat.scala 20:58] - node T_67 = add(expA, T_66) @[MulAddRecFN.scala 125:14] - node T_68 = tail(T_67, 1) @[MulAddRecFN.scala 125:14] - node T_70 = add(T_68, UInt<6>("h038")) @[MulAddRecFN.scala 125:70] - node sExpAlignedProd = tail(T_70, 1) @[MulAddRecFN.scala 125:70] - node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] - node T_71 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] - node sNatCAlignDist = tail(T_71, 1) @[MulAddRecFN.scala 132:42] - node T_72 = bits(sNatCAlignDist, 13, 13) @[MulAddRecFN.scala 133:56] - node CAlignDist_floor = or(isZeroProd, T_72) @[MulAddRecFN.scala 133:39] - node T_73 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 135:44] - node T_75 = eq(T_73, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] - node CAlignDist_0 = or(CAlignDist_floor, T_75) @[MulAddRecFN.scala 135:26] - node T_77 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] - node T_78 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 139:33] - node T_80 = lt(T_78, UInt<6>("h036")) @[MulAddRecFN.scala 139:51] - node T_81 = or(CAlignDist_floor, T_80) @[MulAddRecFN.scala 138:31] - node isCDominant = and(T_77, T_81) @[MulAddRecFN.scala 137:19] - node T_83 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 143:31] - node T_85 = lt(T_83, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:49] - node T_86 = bits(sNatCAlignDist, 7, 0) @[MulAddRecFN.scala 144:31] - node T_88 = mux(T_85, T_86, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:16] - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_88) @[MulAddRecFN.scala 141:12] - node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] - node T_89 = bits(CAlignDist, 7, 7) @[primitives.scala 56:25] - node T_90 = bits(CAlignDist, 6, 0) @[primitives.scala 57:26] - node T_91 = bits(T_90, 6, 6) @[primitives.scala 56:25] - node T_92 = bits(T_90, 5, 0) @[primitives.scala 57:26] - node T_95 = dshr(asSInt(UInt<65>("h010000000000000000")), T_92) @[primitives.scala 68:52] - node T_96 = bits(T_95, 63, 31) @[primitives.scala 69:26] - node T_97 = bits(T_96, 31, 0) @[Bitwise.scala 65:18] - node T_100 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 58:47] - node T_101 = xor(UInt<32>("h0ffffffff"), T_100) @[Bitwise.scala 58:21] - node T_102 = shr(T_97, 16) @[Bitwise.scala 59:21] - node T_103 = and(T_102, T_101) @[Bitwise.scala 59:31] - node T_104 = bits(T_97, 15, 0) @[Bitwise.scala 59:46] - node T_105 = shl(T_104, 16) @[Bitwise.scala 59:65] - node T_106 = not(T_101) @[Bitwise.scala 59:77] - node T_107 = and(T_105, T_106) @[Bitwise.scala 59:75] - node T_108 = or(T_103, T_107) @[Bitwise.scala 59:39] - node T_109 = bits(T_101, 23, 0) @[Bitwise.scala 58:28] - node T_110 = shl(T_109, 8) @[Bitwise.scala 58:47] - node T_111 = xor(T_101, T_110) @[Bitwise.scala 58:21] - node T_112 = shr(T_108, 8) @[Bitwise.scala 59:21] - node T_113 = and(T_112, T_111) @[Bitwise.scala 59:31] - node T_114 = bits(T_108, 23, 0) @[Bitwise.scala 59:46] - node T_115 = shl(T_114, 8) @[Bitwise.scala 59:65] - node T_116 = not(T_111) @[Bitwise.scala 59:77] - node T_117 = and(T_115, T_116) @[Bitwise.scala 59:75] - node T_118 = or(T_113, T_117) @[Bitwise.scala 59:39] - node T_119 = bits(T_111, 27, 0) @[Bitwise.scala 58:28] - node T_120 = shl(T_119, 4) @[Bitwise.scala 58:47] - node T_121 = xor(T_111, T_120) @[Bitwise.scala 58:21] - node T_122 = shr(T_118, 4) @[Bitwise.scala 59:21] - node T_123 = and(T_122, T_121) @[Bitwise.scala 59:31] - node T_124 = bits(T_118, 27, 0) @[Bitwise.scala 59:46] - node T_125 = shl(T_124, 4) @[Bitwise.scala 59:65] - node T_126 = not(T_121) @[Bitwise.scala 59:77] - node T_127 = and(T_125, T_126) @[Bitwise.scala 59:75] - node T_128 = or(T_123, T_127) @[Bitwise.scala 59:39] - node T_129 = bits(T_121, 29, 0) @[Bitwise.scala 58:28] - node T_130 = shl(T_129, 2) @[Bitwise.scala 58:47] - node T_131 = xor(T_121, T_130) @[Bitwise.scala 58:21] - node T_132 = shr(T_128, 2) @[Bitwise.scala 59:21] - node T_133 = and(T_132, T_131) @[Bitwise.scala 59:31] - node T_134 = bits(T_128, 29, 0) @[Bitwise.scala 59:46] - node T_135 = shl(T_134, 2) @[Bitwise.scala 59:65] - node T_136 = not(T_131) @[Bitwise.scala 59:77] - node T_137 = and(T_135, T_136) @[Bitwise.scala 59:75] - node T_138 = or(T_133, T_137) @[Bitwise.scala 59:39] - node T_139 = bits(T_131, 30, 0) @[Bitwise.scala 58:28] - node T_140 = shl(T_139, 1) @[Bitwise.scala 58:47] - node T_141 = xor(T_131, T_140) @[Bitwise.scala 58:21] - node T_142 = shr(T_138, 1) @[Bitwise.scala 59:21] - node T_143 = and(T_142, T_141) @[Bitwise.scala 59:31] - node T_144 = bits(T_138, 30, 0) @[Bitwise.scala 59:46] - node T_145 = shl(T_144, 1) @[Bitwise.scala 59:65] - node T_146 = not(T_141) @[Bitwise.scala 59:77] - node T_147 = and(T_145, T_146) @[Bitwise.scala 59:75] - node T_148 = or(T_143, T_147) @[Bitwise.scala 59:39] - node T_149 = bits(T_96, 32, 32) @[Bitwise.scala 65:44] - node T_150 = cat(T_148, T_149) @[Cat.scala 20:58] - node T_151 = not(T_150) @[primitives.scala 65:36] - node T_152 = mux(T_91, UInt<1>("h00"), T_151) @[primitives.scala 65:21] - node T_153 = not(T_152) @[primitives.scala 65:17] - node T_155 = cat(T_153, UInt<20>("h0fffff")) @[Cat.scala 20:58] - node T_156 = bits(T_90, 6, 6) @[primitives.scala 56:25] - node T_157 = bits(T_90, 5, 0) @[primitives.scala 57:26] - node T_159 = dshr(asSInt(UInt<65>("h010000000000000000")), T_157) @[primitives.scala 68:52] - node T_160 = bits(T_159, 19, 0) @[primitives.scala 69:26] - node T_161 = bits(T_160, 15, 0) @[Bitwise.scala 65:18] - node T_164 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_165 = xor(UInt<16>("h0ffff"), T_164) @[Bitwise.scala 58:21] - node T_166 = shr(T_161, 8) @[Bitwise.scala 59:21] - node T_167 = and(T_166, T_165) @[Bitwise.scala 59:31] - node T_168 = bits(T_161, 7, 0) @[Bitwise.scala 59:46] - node T_169 = shl(T_168, 8) @[Bitwise.scala 59:65] - node T_170 = not(T_165) @[Bitwise.scala 59:77] - node T_171 = and(T_169, T_170) @[Bitwise.scala 59:75] - node T_172 = or(T_167, T_171) @[Bitwise.scala 59:39] - node T_173 = bits(T_165, 11, 0) @[Bitwise.scala 58:28] - node T_174 = shl(T_173, 4) @[Bitwise.scala 58:47] - node T_175 = xor(T_165, T_174) @[Bitwise.scala 58:21] - node T_176 = shr(T_172, 4) @[Bitwise.scala 59:21] - node T_177 = and(T_176, T_175) @[Bitwise.scala 59:31] - node T_178 = bits(T_172, 11, 0) @[Bitwise.scala 59:46] - node T_179 = shl(T_178, 4) @[Bitwise.scala 59:65] - node T_180 = not(T_175) @[Bitwise.scala 59:77] - node T_181 = and(T_179, T_180) @[Bitwise.scala 59:75] - node T_182 = or(T_177, T_181) @[Bitwise.scala 59:39] - node T_183 = bits(T_175, 13, 0) @[Bitwise.scala 58:28] - node T_184 = shl(T_183, 2) @[Bitwise.scala 58:47] - node T_185 = xor(T_175, T_184) @[Bitwise.scala 58:21] - node T_186 = shr(T_182, 2) @[Bitwise.scala 59:21] - node T_187 = and(T_186, T_185) @[Bitwise.scala 59:31] - node T_188 = bits(T_182, 13, 0) @[Bitwise.scala 59:46] - node T_189 = shl(T_188, 2) @[Bitwise.scala 59:65] - node T_190 = not(T_185) @[Bitwise.scala 59:77] - node T_191 = and(T_189, T_190) @[Bitwise.scala 59:75] - node T_192 = or(T_187, T_191) @[Bitwise.scala 59:39] - node T_193 = bits(T_185, 14, 0) @[Bitwise.scala 58:28] - node T_194 = shl(T_193, 1) @[Bitwise.scala 58:47] - node T_195 = xor(T_185, T_194) @[Bitwise.scala 58:21] - node T_196 = shr(T_192, 1) @[Bitwise.scala 59:21] - node T_197 = and(T_196, T_195) @[Bitwise.scala 59:31] - node T_198 = bits(T_192, 14, 0) @[Bitwise.scala 59:46] - node T_199 = shl(T_198, 1) @[Bitwise.scala 59:65] - node T_200 = not(T_195) @[Bitwise.scala 59:77] - node T_201 = and(T_199, T_200) @[Bitwise.scala 59:75] - node T_202 = or(T_197, T_201) @[Bitwise.scala 59:39] - node T_203 = bits(T_160, 19, 16) @[Bitwise.scala 65:44] - node T_204 = bits(T_203, 1, 0) @[Bitwise.scala 65:18] - node T_205 = bits(T_204, 0, 0) @[Bitwise.scala 65:18] - node T_206 = bits(T_204, 1, 1) @[Bitwise.scala 65:44] - node T_207 = cat(T_205, T_206) @[Cat.scala 20:58] - node T_208 = bits(T_203, 3, 2) @[Bitwise.scala 65:44] - node T_209 = bits(T_208, 0, 0) @[Bitwise.scala 65:18] - node T_210 = bits(T_208, 1, 1) @[Bitwise.scala 65:44] - node T_211 = cat(T_209, T_210) @[Cat.scala 20:58] - node T_212 = cat(T_207, T_211) @[Cat.scala 20:58] - node T_213 = cat(T_202, T_212) @[Cat.scala 20:58] - node T_215 = mux(T_156, T_213, UInt<1>("h00")) @[primitives.scala 59:20] - node CExtraMask = mux(T_89, T_155, T_215) @[primitives.scala 61:20] - node T_216 = not(sigC) @[MulAddRecFN.scala 151:34] - node negSigC = mux(doSubMags, T_216, sigC) @[MulAddRecFN.scala 151:22] - node T_217 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_220 = mux(T_217, UInt<108>("h0fffffffffffffffffffffffffff"), UInt<108>("h00")) @[Bitwise.scala 33:12] - node T_221 = cat(doSubMags, negSigC) @[Cat.scala 20:58] - node T_222 = cat(T_221, T_220) @[Cat.scala 20:58] - node T_223 = asSInt(T_222) @[MulAddRecFN.scala 154:64] - node T_224 = dshr(T_223, CAlignDist) @[MulAddRecFN.scala 154:70] - node T_225 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] - node T_227 = neq(T_225, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] - node T_228 = xor(T_227, doSubMags) @[MulAddRecFN.scala 156:37] - node T_229 = asUInt(T_224) @[Cat.scala 20:58] - node T_230 = cat(T_229, T_228) @[Cat.scala 20:58] - node alignedNegSigC = bits(T_230, 161, 0) @[MulAddRecFN.scala 157:10] - io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] - io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] - node T_231 = bits(alignedNegSigC, 106, 1) @[MulAddRecFN.scala 161:33] - io.mulAddC <= T_231 @[MulAddRecFN.scala 161:16] - node T_232 = bits(expA, 11, 9) @[MulAddRecFN.scala 163:44] - io.toPostMul.highExpA <= T_232 @[MulAddRecFN.scala 163:37] - node T_233 = bits(fractA, 51, 51) @[MulAddRecFN.scala 164:46] - io.toPostMul.isNaN_isQuietNaNA <= T_233 @[MulAddRecFN.scala 164:37] - node T_234 = bits(expB, 11, 9) @[MulAddRecFN.scala 165:44] - io.toPostMul.highExpB <= T_234 @[MulAddRecFN.scala 165:37] - node T_235 = bits(fractB, 51, 51) @[MulAddRecFN.scala 166:46] - io.toPostMul.isNaN_isQuietNaNB <= T_235 @[MulAddRecFN.scala 166:37] - io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] - io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] - io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] - node T_236 = bits(expC, 11, 9) @[MulAddRecFN.scala 170:44] - io.toPostMul.highExpC <= T_236 @[MulAddRecFN.scala 170:37] - node T_237 = bits(fractC, 51, 51) @[MulAddRecFN.scala 171:46] - io.toPostMul.isNaN_isQuietNaNC <= T_237 @[MulAddRecFN.scala 171:37] - io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] - io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] - io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] - node T_238 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] - io.toPostMul.bit0AlignedNegSigC <= T_238 @[MulAddRecFN.scala 175:37] - node T_239 = bits(alignedNegSigC, 161, 107) @[MulAddRecFN.scala 177:23] - io.toPostMul.highAlignedNegSigC <= T_239 @[MulAddRecFN.scala 176:37] - io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] - io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] - - module MulAddRecFN_postMul_1 : + node signA = bits(io.a, 64, 64) + node expA = bits(io.a, 63, 52) + node fractA = bits(io.a, 51, 0) + node T_42 = bits(expA, 11, 9) + node isZeroA = eq(T_42, UInt<1>("h0")) + node T_45 = eq(isZeroA, UInt<1>("h0")) + node sigA = cat(T_45, fractA) + node signB = bits(io.b, 64, 64) + node expB = bits(io.b, 63, 52) + node fractB = bits(io.b, 51, 0) + node T_46 = bits(expB, 11, 9) + node isZeroB = eq(T_46, UInt<1>("h0")) + node T_49 = eq(isZeroB, UInt<1>("h0")) + node sigB = cat(T_49, fractB) + node T_50 = bits(io.c, 64, 64) + node T_51 = bits(io.op, 0, 0) + node opSignC = xor(T_50, T_51) + node expC = bits(io.c, 63, 52) + node fractC = bits(io.c, 51, 0) + node T_52 = bits(expC, 11, 9) + node isZeroC = eq(T_52, UInt<1>("h0")) + node T_55 = eq(isZeroC, UInt<1>("h0")) + node sigC = cat(T_55, fractC) + node T_56 = xor(signA, signB) + node T_57 = bits(io.op, 1, 1) + node signProd = xor(T_56, T_57) + node isZeroProd = or(isZeroA, isZeroB) + node T_58 = bits(expB, 11, 11) + node T_60 = eq(T_58, UInt<1>("h0")) + node T_61 = bits(T_60, 0, 0) + node T_64 = mux(T_61, UInt<3>("h7"), UInt<3>("h0")) + node T_65 = bits(expB, 10, 0) + node T_66 = cat(T_64, T_65) + node T_67 = add(expA, T_66) + node T_68 = tail(T_67, 1) + node T_70 = add(T_68, UInt<6>("h38")) + node sExpAlignedProd = tail(T_70, 1) + node doSubMags = xor(signProd, opSignC) + node T_71 = sub(sExpAlignedProd, expC) + node sNatCAlignDist = tail(T_71, 1) + node T_72 = bits(sNatCAlignDist, 13, 13) + node CAlignDist_floor = or(isZeroProd, T_72) + node T_73 = bits(sNatCAlignDist, 12, 0) + node T_75 = eq(T_73, UInt<1>("h0")) + node CAlignDist_0 = or(CAlignDist_floor, T_75) + node T_77 = eq(isZeroC, UInt<1>("h0")) + node T_78 = bits(sNatCAlignDist, 12, 0) + node T_80 = lt(T_78, UInt<6>("h36")) + node T_81 = or(CAlignDist_floor, T_80) + node isCDominant = and(T_77, T_81) + node T_83 = bits(sNatCAlignDist, 12, 0) + node T_85 = lt(T_83, UInt<8>("ha1")) + node T_86 = bits(sNatCAlignDist, 7, 0) + node T_88 = mux(T_85, T_86, UInt<8>("ha1")) + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h0"), T_88) + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) + node T_89 = bits(CAlignDist, 7, 7) + node T_90 = bits(CAlignDist, 6, 0) + node T_91 = bits(T_90, 6, 6) + node T_92 = bits(T_90, 5, 0) + node T_95 = dshr(asSInt(UInt<65>("h10000000000000000")), T_92) + node T_96 = bits(T_95, 63, 31) + node T_97 = bits(T_96, 31, 0) + node T_100 = shl(UInt<16>("hffff"), 16) + node T_101 = xor(UInt<32>("hffffffff"), T_100) + node T_102 = shr(T_97, 16) + node T_103 = and(T_102, T_101) + node T_104 = bits(T_97, 15, 0) + node T_105 = shl(T_104, 16) + node T_106 = not(T_101) + node T_107 = and(T_105, T_106) + node T_108 = or(T_103, T_107) + node T_109 = bits(T_101, 23, 0) + node T_110 = shl(T_109, 8) + node T_111 = xor(T_101, T_110) + node T_112 = shr(T_108, 8) + node T_113 = and(T_112, T_111) + node T_114 = bits(T_108, 23, 0) + node T_115 = shl(T_114, 8) + node T_116 = not(T_111) + node T_117 = and(T_115, T_116) + node T_118 = or(T_113, T_117) + node T_119 = bits(T_111, 27, 0) + node T_120 = shl(T_119, 4) + node T_121 = xor(T_111, T_120) + node T_122 = shr(T_118, 4) + node T_123 = and(T_122, T_121) + node T_124 = bits(T_118, 27, 0) + node T_125 = shl(T_124, 4) + node T_126 = not(T_121) + node T_127 = and(T_125, T_126) + node T_128 = or(T_123, T_127) + node T_129 = bits(T_121, 29, 0) + node T_130 = shl(T_129, 2) + node T_131 = xor(T_121, T_130) + node T_132 = shr(T_128, 2) + node T_133 = and(T_132, T_131) + node T_134 = bits(T_128, 29, 0) + node T_135 = shl(T_134, 2) + node T_136 = not(T_131) + node T_137 = and(T_135, T_136) + node T_138 = or(T_133, T_137) + node T_139 = bits(T_131, 30, 0) + node T_140 = shl(T_139, 1) + node T_141 = xor(T_131, T_140) + node T_142 = shr(T_138, 1) + node T_143 = and(T_142, T_141) + node T_144 = bits(T_138, 30, 0) + node T_145 = shl(T_144, 1) + node T_146 = not(T_141) + node T_147 = and(T_145, T_146) + node T_148 = or(T_143, T_147) + node T_149 = bits(T_96, 32, 32) + node T_150 = cat(T_148, T_149) + node T_151 = not(T_150) + node T_152 = mux(T_91, UInt<1>("h0"), T_151) + node T_153 = not(T_152) + node T_155 = cat(T_153, UInt<20>("hfffff")) + node T_156 = bits(T_90, 6, 6) + node T_157 = bits(T_90, 5, 0) + node T_159 = dshr(asSInt(UInt<65>("h10000000000000000")), T_157) + node T_160 = bits(T_159, 19, 0) + node T_161 = bits(T_160, 15, 0) + node T_164 = shl(UInt<8>("hff"), 8) + node T_165 = xor(UInt<16>("hffff"), T_164) + node T_166 = shr(T_161, 8) + node T_167 = and(T_166, T_165) + node T_168 = bits(T_161, 7, 0) + node T_169 = shl(T_168, 8) + node T_170 = not(T_165) + node T_171 = and(T_169, T_170) + node T_172 = or(T_167, T_171) + node T_173 = bits(T_165, 11, 0) + node T_174 = shl(T_173, 4) + node T_175 = xor(T_165, T_174) + node T_176 = shr(T_172, 4) + node T_177 = and(T_176, T_175) + node T_178 = bits(T_172, 11, 0) + node T_179 = shl(T_178, 4) + node T_180 = not(T_175) + node T_181 = and(T_179, T_180) + node T_182 = or(T_177, T_181) + node T_183 = bits(T_175, 13, 0) + node T_184 = shl(T_183, 2) + node T_185 = xor(T_175, T_184) + node T_186 = shr(T_182, 2) + node T_187 = and(T_186, T_185) + node T_188 = bits(T_182, 13, 0) + node T_189 = shl(T_188, 2) + node T_190 = not(T_185) + node T_191 = and(T_189, T_190) + node T_192 = or(T_187, T_191) + node T_193 = bits(T_185, 14, 0) + node T_194 = shl(T_193, 1) + node T_195 = xor(T_185, T_194) + node T_196 = shr(T_192, 1) + node T_197 = and(T_196, T_195) + node T_198 = bits(T_192, 14, 0) + node T_199 = shl(T_198, 1) + node T_200 = not(T_195) + node T_201 = and(T_199, T_200) + node T_202 = or(T_197, T_201) + node T_203 = bits(T_160, 19, 16) + node T_204 = bits(T_203, 1, 0) + node T_205 = bits(T_204, 0, 0) + node T_206 = bits(T_204, 1, 1) + node T_207 = cat(T_205, T_206) + node T_208 = bits(T_203, 3, 2) + node T_209 = bits(T_208, 0, 0) + node T_210 = bits(T_208, 1, 1) + node T_211 = cat(T_209, T_210) + node T_212 = cat(T_207, T_211) + node T_213 = cat(T_202, T_212) + node T_215 = mux(T_156, T_213, UInt<1>("h0")) + node CExtraMask = mux(T_89, T_155, T_215) + node T_216 = not(sigC) + node negSigC = mux(doSubMags, T_216, sigC) + node T_217 = bits(doSubMags, 0, 0) + node T_220 = mux(T_217, UInt<108>("hfffffffffffffffffffffffffff"), UInt<108>("h0")) + node T_221 = cat(doSubMags, negSigC) + node T_222 = cat(T_221, T_220) + node T_223 = asSInt(T_222) + node T_224 = dshr(T_223, CAlignDist) + node T_225 = and(sigC, CExtraMask) + node T_227 = neq(T_225, UInt<1>("h0")) + node T_228 = xor(T_227, doSubMags) + node T_229 = asUInt(T_224) + node T_230 = cat(T_229, T_228) + node alignedNegSigC = bits(T_230, 161, 0) + io.mulAddA <= sigA + io.mulAddB <= sigB + node T_231 = bits(alignedNegSigC, 106, 1) + io.mulAddC <= T_231 + node T_232 = bits(expA, 11, 9) + io.toPostMul.highExpA <= T_232 + node T_233 = bits(fractA, 51, 51) + io.toPostMul.isNaN_isQuietNaNA <= T_233 + node T_234 = bits(expB, 11, 9) + io.toPostMul.highExpB <= T_234 + node T_235 = bits(fractB, 51, 51) + io.toPostMul.isNaN_isQuietNaNB <= T_235 + io.toPostMul.signProd <= signProd + io.toPostMul.isZeroProd <= isZeroProd + io.toPostMul.opSignC <= opSignC + node T_236 = bits(expC, 11, 9) + io.toPostMul.highExpC <= T_236 + node T_237 = bits(fractC, 51, 51) + io.toPostMul.isNaN_isQuietNaNC <= T_237 + io.toPostMul.isCDominant <= isCDominant + io.toPostMul.CAlignDist_0 <= CAlignDist_0 + io.toPostMul.CAlignDist <= CAlignDist + node T_238 = bits(alignedNegSigC, 0, 0) + io.toPostMul.bit0AlignedNegSigC <= T_238 + node T_239 = bits(alignedNegSigC, 161, 107) + io.toPostMul.highAlignedNegSigC <= T_239 + io.toPostMul.sExpSum <= sExpSum + io.toPostMul.roundingMode <= io.roundingMode + + module MulAddRecFN_postMul_1 : input clk : Clock input reset : UInt<1> - output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} - + output io : { flip fromPreMul : { highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} + io is invalid - node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] - node T_38 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] - node isSpecialA = eq(T_38, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] - node T_40 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] - node T_42 = eq(T_40, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] - node isInfA = and(isSpecialA, T_42) @[MulAddRecFN.scala 209:29] - node T_43 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] - node isNaNA = and(isSpecialA, T_43) @[MulAddRecFN.scala 210:29] - node T_45 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] - node isSigNaNA = and(isNaNA, T_45) @[MulAddRecFN.scala 211:28] - node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] - node T_47 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] - node isSpecialB = eq(T_47, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] - node T_49 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] - node T_51 = eq(T_49, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] - node isInfB = and(isSpecialB, T_51) @[MulAddRecFN.scala 215:29] - node T_52 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] - node isNaNB = and(isSpecialB, T_52) @[MulAddRecFN.scala 216:29] - node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] - node isSigNaNB = and(isNaNB, T_54) @[MulAddRecFN.scala 217:28] - node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] - node T_56 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] - node isSpecialC = eq(T_56, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] - node T_58 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] - node T_60 = eq(T_58, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] - node isInfC = and(isSpecialC, T_60) @[MulAddRecFN.scala 221:29] - node T_61 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] - node isNaNC = and(isSpecialC, T_61) @[MulAddRecFN.scala 222:29] - node T_63 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] - node isSigNaNC = and(isNaNC, T_63) @[MulAddRecFN.scala 223:28] - node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] - node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] - node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] - node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] - node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] - node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] - node T_66 = bits(io.mulAddResult, 106, 106) @[MulAddRecFN.scala 237:32] - node T_68 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] - node T_69 = tail(T_68, 1) @[MulAddRecFN.scala 238:50] - node T_70 = mux(T_66, T_69, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] - node T_71 = bits(io.mulAddResult, 105, 0) @[MulAddRecFN.scala 241:28] - node T_72 = cat(T_70, T_71) @[Cat.scala 20:58] - node sigSum = cat(T_72, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 20:58] - node T_74 = bits(sigSum, 108, 1) @[MulAddRecFN.scala 248:38] - node T_75 = xor(UInt<108>("h00"), T_74) @[MulAddRecFN.scala 191:27] - node T_76 = or(UInt<108>("h00"), T_74) @[MulAddRecFN.scala 191:37] - node T_77 = shl(T_76, 1) @[MulAddRecFN.scala 191:41] - node T_78 = xor(T_75, T_77) @[MulAddRecFN.scala 191:32] - node T_80 = bits(T_78, 107, 0) @[primitives.scala 79:35] - node T_81 = bits(T_80, 107, 64) @[CircuitMath.scala 26:17] - node T_82 = bits(T_80, 63, 0) @[CircuitMath.scala 27:17] - node T_84 = neq(T_81, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_85 = bits(T_81, 43, 32) @[CircuitMath.scala 26:17] - node T_86 = bits(T_81, 31, 0) @[CircuitMath.scala 27:17] - node T_88 = neq(T_85, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_89 = bits(T_85, 11, 8) @[CircuitMath.scala 26:17] - node T_90 = bits(T_85, 7, 0) @[CircuitMath.scala 27:17] - node T_92 = neq(T_89, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_93 = bits(T_89, 3, 3) @[CircuitMath.scala 23:12] - node T_95 = bits(T_89, 2, 2) @[CircuitMath.scala 23:12] - node T_97 = bits(T_89, 1, 1) @[CircuitMath.scala 21:8] - node T_98 = shl(T_97, 0) @[CircuitMath.scala 23:10] - node T_99 = mux(T_95, UInt<2>("h02"), T_98) @[CircuitMath.scala 23:10] - node T_100 = mux(T_93, UInt<2>("h03"), T_99) @[CircuitMath.scala 23:10] - node T_101 = bits(T_90, 7, 4) @[CircuitMath.scala 26:17] - node T_102 = bits(T_90, 3, 0) @[CircuitMath.scala 27:17] - node T_104 = neq(T_101, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_105 = bits(T_101, 3, 3) @[CircuitMath.scala 23:12] - node T_107 = bits(T_101, 2, 2) @[CircuitMath.scala 23:12] - node T_109 = bits(T_101, 1, 1) @[CircuitMath.scala 21:8] - node T_110 = shl(T_109, 0) @[CircuitMath.scala 23:10] - node T_111 = mux(T_107, UInt<2>("h02"), T_110) @[CircuitMath.scala 23:10] - node T_112 = mux(T_105, UInt<2>("h03"), T_111) @[CircuitMath.scala 23:10] - node T_113 = bits(T_102, 3, 3) @[CircuitMath.scala 23:12] - node T_115 = bits(T_102, 2, 2) @[CircuitMath.scala 23:12] - node T_117 = bits(T_102, 1, 1) @[CircuitMath.scala 21:8] - node T_118 = shl(T_117, 0) @[CircuitMath.scala 23:10] - node T_119 = mux(T_115, UInt<2>("h02"), T_118) @[CircuitMath.scala 23:10] - node T_120 = mux(T_113, UInt<2>("h03"), T_119) @[CircuitMath.scala 23:10] - node T_121 = mux(T_104, T_112, T_120) @[CircuitMath.scala 29:21] - node T_122 = cat(T_104, T_121) @[Cat.scala 20:58] - node T_123 = mux(T_92, T_100, T_122) @[CircuitMath.scala 29:21] - node T_124 = cat(T_92, T_123) @[Cat.scala 20:58] - node T_125 = bits(T_86, 31, 16) @[CircuitMath.scala 26:17] - node T_126 = bits(T_86, 15, 0) @[CircuitMath.scala 27:17] - node T_128 = neq(T_125, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_129 = bits(T_125, 15, 8) @[CircuitMath.scala 26:17] - node T_130 = bits(T_125, 7, 0) @[CircuitMath.scala 27:17] - node T_132 = neq(T_129, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_133 = bits(T_129, 7, 4) @[CircuitMath.scala 26:17] - node T_134 = bits(T_129, 3, 0) @[CircuitMath.scala 27:17] - node T_136 = neq(T_133, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_137 = bits(T_133, 3, 3) @[CircuitMath.scala 23:12] - node T_139 = bits(T_133, 2, 2) @[CircuitMath.scala 23:12] - node T_141 = bits(T_133, 1, 1) @[CircuitMath.scala 21:8] - node T_142 = shl(T_141, 0) @[CircuitMath.scala 23:10] - node T_143 = mux(T_139, UInt<2>("h02"), T_142) @[CircuitMath.scala 23:10] - node T_144 = mux(T_137, UInt<2>("h03"), T_143) @[CircuitMath.scala 23:10] - node T_145 = bits(T_134, 3, 3) @[CircuitMath.scala 23:12] - node T_147 = bits(T_134, 2, 2) @[CircuitMath.scala 23:12] - node T_149 = bits(T_134, 1, 1) @[CircuitMath.scala 21:8] - node T_150 = shl(T_149, 0) @[CircuitMath.scala 23:10] - node T_151 = mux(T_147, UInt<2>("h02"), T_150) @[CircuitMath.scala 23:10] - node T_152 = mux(T_145, UInt<2>("h03"), T_151) @[CircuitMath.scala 23:10] - node T_153 = mux(T_136, T_144, T_152) @[CircuitMath.scala 29:21] - node T_154 = cat(T_136, T_153) @[Cat.scala 20:58] - node T_155 = bits(T_130, 7, 4) @[CircuitMath.scala 26:17] - node T_156 = bits(T_130, 3, 0) @[CircuitMath.scala 27:17] - node T_158 = neq(T_155, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_159 = bits(T_155, 3, 3) @[CircuitMath.scala 23:12] - node T_161 = bits(T_155, 2, 2) @[CircuitMath.scala 23:12] - node T_163 = bits(T_155, 1, 1) @[CircuitMath.scala 21:8] - node T_164 = shl(T_163, 0) @[CircuitMath.scala 23:10] - node T_165 = mux(T_161, UInt<2>("h02"), T_164) @[CircuitMath.scala 23:10] - node T_166 = mux(T_159, UInt<2>("h03"), T_165) @[CircuitMath.scala 23:10] - node T_167 = bits(T_156, 3, 3) @[CircuitMath.scala 23:12] - node T_169 = bits(T_156, 2, 2) @[CircuitMath.scala 23:12] - node T_171 = bits(T_156, 1, 1) @[CircuitMath.scala 21:8] - node T_172 = shl(T_171, 0) @[CircuitMath.scala 23:10] - node T_173 = mux(T_169, UInt<2>("h02"), T_172) @[CircuitMath.scala 23:10] - node T_174 = mux(T_167, UInt<2>("h03"), T_173) @[CircuitMath.scala 23:10] - node T_175 = mux(T_158, T_166, T_174) @[CircuitMath.scala 29:21] - node T_176 = cat(T_158, T_175) @[Cat.scala 20:58] - node T_177 = mux(T_132, T_154, T_176) @[CircuitMath.scala 29:21] - node T_178 = cat(T_132, T_177) @[Cat.scala 20:58] - node T_179 = bits(T_126, 15, 8) @[CircuitMath.scala 26:17] - node T_180 = bits(T_126, 7, 0) @[CircuitMath.scala 27:17] - node T_182 = neq(T_179, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_183 = bits(T_179, 7, 4) @[CircuitMath.scala 26:17] - node T_184 = bits(T_179, 3, 0) @[CircuitMath.scala 27:17] - node T_186 = neq(T_183, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_187 = bits(T_183, 3, 3) @[CircuitMath.scala 23:12] - node T_189 = bits(T_183, 2, 2) @[CircuitMath.scala 23:12] - node T_191 = bits(T_183, 1, 1) @[CircuitMath.scala 21:8] - node T_192 = shl(T_191, 0) @[CircuitMath.scala 23:10] - node T_193 = mux(T_189, UInt<2>("h02"), T_192) @[CircuitMath.scala 23:10] - node T_194 = mux(T_187, UInt<2>("h03"), T_193) @[CircuitMath.scala 23:10] - node T_195 = bits(T_184, 3, 3) @[CircuitMath.scala 23:12] - node T_197 = bits(T_184, 2, 2) @[CircuitMath.scala 23:12] - node T_199 = bits(T_184, 1, 1) @[CircuitMath.scala 21:8] - node T_200 = shl(T_199, 0) @[CircuitMath.scala 23:10] - node T_201 = mux(T_197, UInt<2>("h02"), T_200) @[CircuitMath.scala 23:10] - node T_202 = mux(T_195, UInt<2>("h03"), T_201) @[CircuitMath.scala 23:10] - node T_203 = mux(T_186, T_194, T_202) @[CircuitMath.scala 29:21] - node T_204 = cat(T_186, T_203) @[Cat.scala 20:58] - node T_205 = bits(T_180, 7, 4) @[CircuitMath.scala 26:17] - node T_206 = bits(T_180, 3, 0) @[CircuitMath.scala 27:17] - node T_208 = neq(T_205, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_209 = bits(T_205, 3, 3) @[CircuitMath.scala 23:12] - node T_211 = bits(T_205, 2, 2) @[CircuitMath.scala 23:12] - node T_213 = bits(T_205, 1, 1) @[CircuitMath.scala 21:8] - node T_214 = shl(T_213, 0) @[CircuitMath.scala 23:10] - node T_215 = mux(T_211, UInt<2>("h02"), T_214) @[CircuitMath.scala 23:10] - node T_216 = mux(T_209, UInt<2>("h03"), T_215) @[CircuitMath.scala 23:10] - node T_217 = bits(T_206, 3, 3) @[CircuitMath.scala 23:12] - node T_219 = bits(T_206, 2, 2) @[CircuitMath.scala 23:12] - node T_221 = bits(T_206, 1, 1) @[CircuitMath.scala 21:8] - node T_222 = shl(T_221, 0) @[CircuitMath.scala 23:10] - node T_223 = mux(T_219, UInt<2>("h02"), T_222) @[CircuitMath.scala 23:10] - node T_224 = mux(T_217, UInt<2>("h03"), T_223) @[CircuitMath.scala 23:10] - node T_225 = mux(T_208, T_216, T_224) @[CircuitMath.scala 29:21] - node T_226 = cat(T_208, T_225) @[Cat.scala 20:58] - node T_227 = mux(T_182, T_204, T_226) @[CircuitMath.scala 29:21] - node T_228 = cat(T_182, T_227) @[Cat.scala 20:58] - node T_229 = mux(T_128, T_178, T_228) @[CircuitMath.scala 29:21] - node T_230 = cat(T_128, T_229) @[Cat.scala 20:58] - node T_231 = mux(T_88, T_124, T_230) @[CircuitMath.scala 29:21] - node T_232 = cat(T_88, T_231) @[Cat.scala 20:58] - node T_233 = bits(T_82, 63, 32) @[CircuitMath.scala 26:17] - node T_234 = bits(T_82, 31, 0) @[CircuitMath.scala 27:17] - node T_236 = neq(T_233, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_237 = bits(T_233, 31, 16) @[CircuitMath.scala 26:17] - node T_238 = bits(T_233, 15, 0) @[CircuitMath.scala 27:17] - node T_240 = neq(T_237, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_241 = bits(T_237, 15, 8) @[CircuitMath.scala 26:17] - node T_242 = bits(T_237, 7, 0) @[CircuitMath.scala 27:17] - node T_244 = neq(T_241, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_245 = bits(T_241, 7, 4) @[CircuitMath.scala 26:17] - node T_246 = bits(T_241, 3, 0) @[CircuitMath.scala 27:17] - node T_248 = neq(T_245, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_249 = bits(T_245, 3, 3) @[CircuitMath.scala 23:12] - node T_251 = bits(T_245, 2, 2) @[CircuitMath.scala 23:12] - node T_253 = bits(T_245, 1, 1) @[CircuitMath.scala 21:8] - node T_254 = shl(T_253, 0) @[CircuitMath.scala 23:10] - node T_255 = mux(T_251, UInt<2>("h02"), T_254) @[CircuitMath.scala 23:10] - node T_256 = mux(T_249, UInt<2>("h03"), T_255) @[CircuitMath.scala 23:10] - node T_257 = bits(T_246, 3, 3) @[CircuitMath.scala 23:12] - node T_259 = bits(T_246, 2, 2) @[CircuitMath.scala 23:12] - node T_261 = bits(T_246, 1, 1) @[CircuitMath.scala 21:8] - node T_262 = shl(T_261, 0) @[CircuitMath.scala 23:10] - node T_263 = mux(T_259, UInt<2>("h02"), T_262) @[CircuitMath.scala 23:10] - node T_264 = mux(T_257, UInt<2>("h03"), T_263) @[CircuitMath.scala 23:10] - node T_265 = mux(T_248, T_256, T_264) @[CircuitMath.scala 29:21] - node T_266 = cat(T_248, T_265) @[Cat.scala 20:58] - node T_267 = bits(T_242, 7, 4) @[CircuitMath.scala 26:17] - node T_268 = bits(T_242, 3, 0) @[CircuitMath.scala 27:17] - node T_270 = neq(T_267, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_271 = bits(T_267, 3, 3) @[CircuitMath.scala 23:12] - node T_273 = bits(T_267, 2, 2) @[CircuitMath.scala 23:12] - node T_275 = bits(T_267, 1, 1) @[CircuitMath.scala 21:8] - node T_276 = shl(T_275, 0) @[CircuitMath.scala 23:10] - node T_277 = mux(T_273, UInt<2>("h02"), T_276) @[CircuitMath.scala 23:10] - node T_278 = mux(T_271, UInt<2>("h03"), T_277) @[CircuitMath.scala 23:10] - node T_279 = bits(T_268, 3, 3) @[CircuitMath.scala 23:12] - node T_281 = bits(T_268, 2, 2) @[CircuitMath.scala 23:12] - node T_283 = bits(T_268, 1, 1) @[CircuitMath.scala 21:8] - node T_284 = shl(T_283, 0) @[CircuitMath.scala 23:10] - node T_285 = mux(T_281, UInt<2>("h02"), T_284) @[CircuitMath.scala 23:10] - node T_286 = mux(T_279, UInt<2>("h03"), T_285) @[CircuitMath.scala 23:10] - node T_287 = mux(T_270, T_278, T_286) @[CircuitMath.scala 29:21] - node T_288 = cat(T_270, T_287) @[Cat.scala 20:58] - node T_289 = mux(T_244, T_266, T_288) @[CircuitMath.scala 29:21] - node T_290 = cat(T_244, T_289) @[Cat.scala 20:58] - node T_291 = bits(T_238, 15, 8) @[CircuitMath.scala 26:17] - node T_292 = bits(T_238, 7, 0) @[CircuitMath.scala 27:17] - node T_294 = neq(T_291, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_295 = bits(T_291, 7, 4) @[CircuitMath.scala 26:17] - node T_296 = bits(T_291, 3, 0) @[CircuitMath.scala 27:17] - node T_298 = neq(T_295, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_299 = bits(T_295, 3, 3) @[CircuitMath.scala 23:12] - node T_301 = bits(T_295, 2, 2) @[CircuitMath.scala 23:12] - node T_303 = bits(T_295, 1, 1) @[CircuitMath.scala 21:8] - node T_304 = shl(T_303, 0) @[CircuitMath.scala 23:10] - node T_305 = mux(T_301, UInt<2>("h02"), T_304) @[CircuitMath.scala 23:10] - node T_306 = mux(T_299, UInt<2>("h03"), T_305) @[CircuitMath.scala 23:10] - node T_307 = bits(T_296, 3, 3) @[CircuitMath.scala 23:12] - node T_309 = bits(T_296, 2, 2) @[CircuitMath.scala 23:12] - node T_311 = bits(T_296, 1, 1) @[CircuitMath.scala 21:8] - node T_312 = shl(T_311, 0) @[CircuitMath.scala 23:10] - node T_313 = mux(T_309, UInt<2>("h02"), T_312) @[CircuitMath.scala 23:10] - node T_314 = mux(T_307, UInt<2>("h03"), T_313) @[CircuitMath.scala 23:10] - node T_315 = mux(T_298, T_306, T_314) @[CircuitMath.scala 29:21] - node T_316 = cat(T_298, T_315) @[Cat.scala 20:58] - node T_317 = bits(T_292, 7, 4) @[CircuitMath.scala 26:17] - node T_318 = bits(T_292, 3, 0) @[CircuitMath.scala 27:17] - node T_320 = neq(T_317, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_321 = bits(T_317, 3, 3) @[CircuitMath.scala 23:12] - node T_323 = bits(T_317, 2, 2) @[CircuitMath.scala 23:12] - node T_325 = bits(T_317, 1, 1) @[CircuitMath.scala 21:8] - node T_326 = shl(T_325, 0) @[CircuitMath.scala 23:10] - node T_327 = mux(T_323, UInt<2>("h02"), T_326) @[CircuitMath.scala 23:10] - node T_328 = mux(T_321, UInt<2>("h03"), T_327) @[CircuitMath.scala 23:10] - node T_329 = bits(T_318, 3, 3) @[CircuitMath.scala 23:12] - node T_331 = bits(T_318, 2, 2) @[CircuitMath.scala 23:12] - node T_333 = bits(T_318, 1, 1) @[CircuitMath.scala 21:8] - node T_334 = shl(T_333, 0) @[CircuitMath.scala 23:10] - node T_335 = mux(T_331, UInt<2>("h02"), T_334) @[CircuitMath.scala 23:10] - node T_336 = mux(T_329, UInt<2>("h03"), T_335) @[CircuitMath.scala 23:10] - node T_337 = mux(T_320, T_328, T_336) @[CircuitMath.scala 29:21] - node T_338 = cat(T_320, T_337) @[Cat.scala 20:58] - node T_339 = mux(T_294, T_316, T_338) @[CircuitMath.scala 29:21] - node T_340 = cat(T_294, T_339) @[Cat.scala 20:58] - node T_341 = mux(T_240, T_290, T_340) @[CircuitMath.scala 29:21] - node T_342 = cat(T_240, T_341) @[Cat.scala 20:58] - node T_343 = bits(T_234, 31, 16) @[CircuitMath.scala 26:17] - node T_344 = bits(T_234, 15, 0) @[CircuitMath.scala 27:17] - node T_346 = neq(T_343, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_347 = bits(T_343, 15, 8) @[CircuitMath.scala 26:17] - node T_348 = bits(T_343, 7, 0) @[CircuitMath.scala 27:17] - node T_350 = neq(T_347, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_351 = bits(T_347, 7, 4) @[CircuitMath.scala 26:17] - node T_352 = bits(T_347, 3, 0) @[CircuitMath.scala 27:17] - node T_354 = neq(T_351, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_355 = bits(T_351, 3, 3) @[CircuitMath.scala 23:12] - node T_357 = bits(T_351, 2, 2) @[CircuitMath.scala 23:12] - node T_359 = bits(T_351, 1, 1) @[CircuitMath.scala 21:8] - node T_360 = shl(T_359, 0) @[CircuitMath.scala 23:10] - node T_361 = mux(T_357, UInt<2>("h02"), T_360) @[CircuitMath.scala 23:10] - node T_362 = mux(T_355, UInt<2>("h03"), T_361) @[CircuitMath.scala 23:10] - node T_363 = bits(T_352, 3, 3) @[CircuitMath.scala 23:12] - node T_365 = bits(T_352, 2, 2) @[CircuitMath.scala 23:12] - node T_367 = bits(T_352, 1, 1) @[CircuitMath.scala 21:8] - node T_368 = shl(T_367, 0) @[CircuitMath.scala 23:10] - node T_369 = mux(T_365, UInt<2>("h02"), T_368) @[CircuitMath.scala 23:10] - node T_370 = mux(T_363, UInt<2>("h03"), T_369) @[CircuitMath.scala 23:10] - node T_371 = mux(T_354, T_362, T_370) @[CircuitMath.scala 29:21] - node T_372 = cat(T_354, T_371) @[Cat.scala 20:58] - node T_373 = bits(T_348, 7, 4) @[CircuitMath.scala 26:17] - node T_374 = bits(T_348, 3, 0) @[CircuitMath.scala 27:17] - node T_376 = neq(T_373, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_377 = bits(T_373, 3, 3) @[CircuitMath.scala 23:12] - node T_379 = bits(T_373, 2, 2) @[CircuitMath.scala 23:12] - node T_381 = bits(T_373, 1, 1) @[CircuitMath.scala 21:8] - node T_382 = shl(T_381, 0) @[CircuitMath.scala 23:10] - node T_383 = mux(T_379, UInt<2>("h02"), T_382) @[CircuitMath.scala 23:10] - node T_384 = mux(T_377, UInt<2>("h03"), T_383) @[CircuitMath.scala 23:10] - node T_385 = bits(T_374, 3, 3) @[CircuitMath.scala 23:12] - node T_387 = bits(T_374, 2, 2) @[CircuitMath.scala 23:12] - node T_389 = bits(T_374, 1, 1) @[CircuitMath.scala 21:8] - node T_390 = shl(T_389, 0) @[CircuitMath.scala 23:10] - node T_391 = mux(T_387, UInt<2>("h02"), T_390) @[CircuitMath.scala 23:10] - node T_392 = mux(T_385, UInt<2>("h03"), T_391) @[CircuitMath.scala 23:10] - node T_393 = mux(T_376, T_384, T_392) @[CircuitMath.scala 29:21] - node T_394 = cat(T_376, T_393) @[Cat.scala 20:58] - node T_395 = mux(T_350, T_372, T_394) @[CircuitMath.scala 29:21] - node T_396 = cat(T_350, T_395) @[Cat.scala 20:58] - node T_397 = bits(T_344, 15, 8) @[CircuitMath.scala 26:17] - node T_398 = bits(T_344, 7, 0) @[CircuitMath.scala 27:17] - node T_400 = neq(T_397, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_401 = bits(T_397, 7, 4) @[CircuitMath.scala 26:17] - node T_402 = bits(T_397, 3, 0) @[CircuitMath.scala 27:17] - node T_404 = neq(T_401, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_405 = bits(T_401, 3, 3) @[CircuitMath.scala 23:12] - node T_407 = bits(T_401, 2, 2) @[CircuitMath.scala 23:12] - node T_409 = bits(T_401, 1, 1) @[CircuitMath.scala 21:8] - node T_410 = shl(T_409, 0) @[CircuitMath.scala 23:10] - node T_411 = mux(T_407, UInt<2>("h02"), T_410) @[CircuitMath.scala 23:10] - node T_412 = mux(T_405, UInt<2>("h03"), T_411) @[CircuitMath.scala 23:10] - node T_413 = bits(T_402, 3, 3) @[CircuitMath.scala 23:12] - node T_415 = bits(T_402, 2, 2) @[CircuitMath.scala 23:12] - node T_417 = bits(T_402, 1, 1) @[CircuitMath.scala 21:8] - node T_418 = shl(T_417, 0) @[CircuitMath.scala 23:10] - node T_419 = mux(T_415, UInt<2>("h02"), T_418) @[CircuitMath.scala 23:10] - node T_420 = mux(T_413, UInt<2>("h03"), T_419) @[CircuitMath.scala 23:10] - node T_421 = mux(T_404, T_412, T_420) @[CircuitMath.scala 29:21] - node T_422 = cat(T_404, T_421) @[Cat.scala 20:58] - node T_423 = bits(T_398, 7, 4) @[CircuitMath.scala 26:17] - node T_424 = bits(T_398, 3, 0) @[CircuitMath.scala 27:17] - node T_426 = neq(T_423, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_427 = bits(T_423, 3, 3) @[CircuitMath.scala 23:12] - node T_429 = bits(T_423, 2, 2) @[CircuitMath.scala 23:12] - node T_431 = bits(T_423, 1, 1) @[CircuitMath.scala 21:8] - node T_432 = shl(T_431, 0) @[CircuitMath.scala 23:10] - node T_433 = mux(T_429, UInt<2>("h02"), T_432) @[CircuitMath.scala 23:10] - node T_434 = mux(T_427, UInt<2>("h03"), T_433) @[CircuitMath.scala 23:10] - node T_435 = bits(T_424, 3, 3) @[CircuitMath.scala 23:12] - node T_437 = bits(T_424, 2, 2) @[CircuitMath.scala 23:12] - node T_439 = bits(T_424, 1, 1) @[CircuitMath.scala 21:8] - node T_440 = shl(T_439, 0) @[CircuitMath.scala 23:10] - node T_441 = mux(T_437, UInt<2>("h02"), T_440) @[CircuitMath.scala 23:10] - node T_442 = mux(T_435, UInt<2>("h03"), T_441) @[CircuitMath.scala 23:10] - node T_443 = mux(T_426, T_434, T_442) @[CircuitMath.scala 29:21] - node T_444 = cat(T_426, T_443) @[Cat.scala 20:58] - node T_445 = mux(T_400, T_422, T_444) @[CircuitMath.scala 29:21] - node T_446 = cat(T_400, T_445) @[Cat.scala 20:58] - node T_447 = mux(T_346, T_396, T_446) @[CircuitMath.scala 29:21] - node T_448 = cat(T_346, T_447) @[Cat.scala 20:58] - node T_449 = mux(T_236, T_342, T_448) @[CircuitMath.scala 29:21] - node T_450 = cat(T_236, T_449) @[Cat.scala 20:58] - node T_451 = mux(T_84, T_232, T_450) @[CircuitMath.scala 29:21] - node T_452 = cat(T_84, T_451) @[Cat.scala 20:58] - node T_453 = sub(UInt<8>("h0a0"), T_452) @[primitives.scala 79:25] - node estNormPos_dist = tail(T_453, 1) @[primitives.scala 79:25] - node T_454 = bits(sigSum, 75, 44) @[MulAddRecFN.scala 252:19] - node T_456 = neq(T_454, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] - node T_457 = bits(sigSum, 43, 0) @[MulAddRecFN.scala 255:19] - node T_459 = neq(T_457, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] - node firstReduceSigSum = cat(T_456, T_459) @[Cat.scala 20:58] - node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] - node T_460 = bits(complSigSum, 75, 44) @[MulAddRecFN.scala 259:24] - node T_462 = neq(T_460, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] - node T_463 = bits(complSigSum, 43, 0) @[MulAddRecFN.scala 262:24] - node T_465 = neq(T_463, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] - node firstReduceComplSigSum = cat(T_462, T_465) @[Cat.scala 20:58] - node T_466 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] - node T_468 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] - node T_469 = tail(T_468, 1) @[MulAddRecFN.scala 268:39] - node T_470 = bits(T_469, 5, 0) @[MulAddRecFN.scala 268:49] - node CDom_estNormDist = mux(T_466, io.fromPreMul.CAlignDist, T_470) @[MulAddRecFN.scala 266:12] - node T_472 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] - node T_473 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 271:46] - node T_475 = eq(T_473, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] - node T_476 = and(T_472, T_475) @[MulAddRecFN.scala 271:25] - node T_477 = bits(sigSum, 161, 76) @[MulAddRecFN.scala 272:23] - node T_479 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] - node T_480 = cat(T_477, T_479) @[Cat.scala 20:58] - node T_482 = mux(T_476, T_480, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] - node T_484 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] - node T_485 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 277:44] - node T_486 = and(T_484, T_485) @[MulAddRecFN.scala 277:25] - node T_487 = bits(sigSum, 129, 44) @[MulAddRecFN.scala 278:23] - node T_488 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] - node T_489 = cat(T_487, T_488) @[Cat.scala 20:58] - node T_491 = mux(T_486, T_489, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] - node T_492 = or(T_482, T_491) @[MulAddRecFN.scala 276:11] - node T_493 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 286:44] - node T_495 = eq(T_493, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] - node T_496 = and(doSubMags, T_495) @[MulAddRecFN.scala 286:23] - node T_497 = bits(complSigSum, 161, 76) @[MulAddRecFN.scala 287:28] - node T_499 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] - node T_500 = cat(T_497, T_499) @[Cat.scala 20:58] - node T_502 = mux(T_496, T_500, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] - node T_503 = or(T_492, T_502) @[MulAddRecFN.scala 285:11] - node T_504 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 292:42] - node T_505 = and(doSubMags, T_504) @[MulAddRecFN.scala 292:23] - node T_506 = bits(complSigSum, 129, 44) @[MulAddRecFN.scala 293:28] - node T_507 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] - node T_508 = cat(T_506, T_507) @[Cat.scala 20:58] - node T_510 = mux(T_505, T_508, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] - node CDom_firstNormAbsSigSum = or(T_503, T_510) @[MulAddRecFN.scala 291:11] - node T_511 = bits(sigSum, 108, 44) @[MulAddRecFN.scala 308:23] - node T_512 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] - node T_514 = eq(T_512, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] - node T_515 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] - node T_516 = mux(doSubMags, T_514, T_515) @[MulAddRecFN.scala 309:20] - node T_517 = cat(T_511, T_516) @[Cat.scala 20:58] - node T_518 = bits(sigSum, 97, 1) @[MulAddRecFN.scala 314:24] - node T_519 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 316:37] - node T_520 = bits(sigSum, 1, 1) @[MulAddRecFN.scala 318:32] - node T_521 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_524 = mux(T_521, UInt<86>("h03fffffffffffffffffffff"), UInt<86>("h00")) @[Bitwise.scala 33:12] - node T_525 = cat(T_520, T_524) @[Cat.scala 20:58] - node T_526 = mux(T_519, T_517, T_525) @[MulAddRecFN.scala 316:21] - node T_527 = bits(sigSum, 97, 12) @[MulAddRecFN.scala 324:28] - node T_528 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 329:39] - node T_530 = eq(T_528, UInt<1>("h00")) @[MulAddRecFN.scala 329:77] - node T_531 = bits(sigSum, 11, 1) @[MulAddRecFN.scala 331:34] - node T_533 = neq(T_531, UInt<1>("h00")) @[MulAddRecFN.scala 331:72] - node T_534 = mux(doSubMags, T_530, T_533) @[MulAddRecFN.scala 328:26] - node T_535 = cat(T_527, T_534) @[Cat.scala 20:58] - node T_536 = bits(estNormPos_dist, 6, 6) @[MulAddRecFN.scala 338:28] - node T_537 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 339:33] - node T_538 = bits(sigSum, 65, 1) @[MulAddRecFN.scala 340:28] - node T_539 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_542 = mux(T_539, UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 33:12] - node T_543 = cat(T_538, T_542) @[Cat.scala 20:58] - node T_544 = mux(T_537, T_543, T_535) @[MulAddRecFN.scala 339:17] - node T_545 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 345:33] - node T_546 = bits(sigSum, 33, 1) @[MulAddRecFN.scala 347:28] - node T_547 = bits(doSubMags, 0, 0) @[Bitwise.scala 33:15] - node T_550 = mux(T_547, UInt<54>("h03fffffffffffff"), UInt<54>("h00")) @[Bitwise.scala 33:12] - node T_551 = cat(T_546, T_550) @[Cat.scala 20:58] - node T_552 = mux(T_545, T_526, T_551) @[MulAddRecFN.scala 345:17] - node notCDom_pos_firstNormAbsSigSum = mux(T_536, T_544, T_552) @[MulAddRecFN.scala 338:12] - node T_553 = bits(complSigSum, 107, 44) @[MulAddRecFN.scala 360:28] - node T_554 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] - node T_555 = cat(T_553, T_554) @[Cat.scala 20:58] - node T_556 = bits(complSigSum, 97, 1) @[MulAddRecFN.scala 363:29] - node T_557 = bits(estNormPos_dist, 4, 4) @[MulAddRecFN.scala 365:37] - node T_558 = bits(complSigSum, 2, 1) @[MulAddRecFN.scala 367:33] - node T_559 = shl(T_558, 86) @[MulAddRecFN.scala 367:68] - node T_560 = mux(T_557, T_555, T_559) @[MulAddRecFN.scala 365:21] - node T_561 = bits(complSigSum, 98, 12) @[MulAddRecFN.scala 372:33] - node T_562 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 376:33] - node T_564 = neq(T_562, UInt<1>("h00")) @[MulAddRecFN.scala 376:71] - node T_565 = cat(T_561, T_564) @[Cat.scala 20:58] - node T_566 = bits(estNormPos_dist, 6, 6) @[MulAddRecFN.scala 379:28] - node T_567 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 380:33] - node T_568 = bits(complSigSum, 66, 1) @[MulAddRecFN.scala 381:29] - node T_569 = shl(T_568, 22) @[MulAddRecFN.scala 381:64] - node T_570 = mux(T_567, T_569, T_565) @[MulAddRecFN.scala 380:17] - node T_571 = bits(estNormPos_dist, 5, 5) @[MulAddRecFN.scala 385:33] - node T_572 = bits(complSigSum, 34, 1) @[MulAddRecFN.scala 387:29] - node T_573 = shl(T_572, 54) @[MulAddRecFN.scala 387:64] - node T_574 = mux(T_571, T_560, T_573) @[MulAddRecFN.scala 385:17] - node notCDom_neg_cFirstNormAbsSigSum = mux(T_566, T_570, T_574) @[MulAddRecFN.scala 379:12] - node notCDom_signSigSum = bits(sigSum, 109, 109) @[MulAddRecFN.scala 392:36] - node T_576 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] - node T_577 = and(doSubMags, T_576) @[MulAddRecFN.scala 395:23] - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_577, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] - node T_578 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) @[MulAddRecFN.scala 401:16] - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_578) @[MulAddRecFN.scala 399:12] - node T_579 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] - node T_580 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_579, T_580) @[MulAddRecFN.scala 407:12] - node T_582 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] - node T_584 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] - node T_585 = and(T_582, T_584) @[MulAddRecFN.scala 418:37] - node doIncrSig = and(T_585, doSubMags) @[MulAddRecFN.scala 418:61] - node estNormDist_5 = bits(estNormDist, 4, 0) @[MulAddRecFN.scala 419:36] - node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] - node T_587 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) @[primitives.scala 68:52] - node T_588 = bits(T_587, 31, 1) @[primitives.scala 69:26] - node T_589 = bits(T_588, 15, 0) @[Bitwise.scala 65:18] - node T_592 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_593 = xor(UInt<16>("h0ffff"), T_592) @[Bitwise.scala 58:21] - node T_594 = shr(T_589, 8) @[Bitwise.scala 59:21] - node T_595 = and(T_594, T_593) @[Bitwise.scala 59:31] - node T_596 = bits(T_589, 7, 0) @[Bitwise.scala 59:46] - node T_597 = shl(T_596, 8) @[Bitwise.scala 59:65] - node T_598 = not(T_593) @[Bitwise.scala 59:77] - node T_599 = and(T_597, T_598) @[Bitwise.scala 59:75] - node T_600 = or(T_595, T_599) @[Bitwise.scala 59:39] - node T_601 = bits(T_593, 11, 0) @[Bitwise.scala 58:28] - node T_602 = shl(T_601, 4) @[Bitwise.scala 58:47] - node T_603 = xor(T_593, T_602) @[Bitwise.scala 58:21] - node T_604 = shr(T_600, 4) @[Bitwise.scala 59:21] - node T_605 = and(T_604, T_603) @[Bitwise.scala 59:31] - node T_606 = bits(T_600, 11, 0) @[Bitwise.scala 59:46] - node T_607 = shl(T_606, 4) @[Bitwise.scala 59:65] - node T_608 = not(T_603) @[Bitwise.scala 59:77] - node T_609 = and(T_607, T_608) @[Bitwise.scala 59:75] - node T_610 = or(T_605, T_609) @[Bitwise.scala 59:39] - node T_611 = bits(T_603, 13, 0) @[Bitwise.scala 58:28] - node T_612 = shl(T_611, 2) @[Bitwise.scala 58:47] - node T_613 = xor(T_603, T_612) @[Bitwise.scala 58:21] - node T_614 = shr(T_610, 2) @[Bitwise.scala 59:21] - node T_615 = and(T_614, T_613) @[Bitwise.scala 59:31] - node T_616 = bits(T_610, 13, 0) @[Bitwise.scala 59:46] - node T_617 = shl(T_616, 2) @[Bitwise.scala 59:65] - node T_618 = not(T_613) @[Bitwise.scala 59:77] - node T_619 = and(T_617, T_618) @[Bitwise.scala 59:75] - node T_620 = or(T_615, T_619) @[Bitwise.scala 59:39] - node T_621 = bits(T_613, 14, 0) @[Bitwise.scala 58:28] - node T_622 = shl(T_621, 1) @[Bitwise.scala 58:47] - node T_623 = xor(T_613, T_622) @[Bitwise.scala 58:21] - node T_624 = shr(T_620, 1) @[Bitwise.scala 59:21] - node T_625 = and(T_624, T_623) @[Bitwise.scala 59:31] - node T_626 = bits(T_620, 14, 0) @[Bitwise.scala 59:46] - node T_627 = shl(T_626, 1) @[Bitwise.scala 59:65] - node T_628 = not(T_623) @[Bitwise.scala 59:77] - node T_629 = and(T_627, T_628) @[Bitwise.scala 59:75] - node T_630 = or(T_625, T_629) @[Bitwise.scala 59:39] - node T_631 = bits(T_588, 30, 16) @[Bitwise.scala 65:44] - node T_632 = bits(T_631, 7, 0) @[Bitwise.scala 65:18] - node T_635 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 58:47] - node T_636 = xor(UInt<8>("h0ff"), T_635) @[Bitwise.scala 58:21] - node T_637 = shr(T_632, 4) @[Bitwise.scala 59:21] - node T_638 = and(T_637, T_636) @[Bitwise.scala 59:31] - node T_639 = bits(T_632, 3, 0) @[Bitwise.scala 59:46] - node T_640 = shl(T_639, 4) @[Bitwise.scala 59:65] - node T_641 = not(T_636) @[Bitwise.scala 59:77] - node T_642 = and(T_640, T_641) @[Bitwise.scala 59:75] - node T_643 = or(T_638, T_642) @[Bitwise.scala 59:39] - node T_644 = bits(T_636, 5, 0) @[Bitwise.scala 58:28] - node T_645 = shl(T_644, 2) @[Bitwise.scala 58:47] - node T_646 = xor(T_636, T_645) @[Bitwise.scala 58:21] - node T_647 = shr(T_643, 2) @[Bitwise.scala 59:21] - node T_648 = and(T_647, T_646) @[Bitwise.scala 59:31] - node T_649 = bits(T_643, 5, 0) @[Bitwise.scala 59:46] - node T_650 = shl(T_649, 2) @[Bitwise.scala 59:65] - node T_651 = not(T_646) @[Bitwise.scala 59:77] - node T_652 = and(T_650, T_651) @[Bitwise.scala 59:75] - node T_653 = or(T_648, T_652) @[Bitwise.scala 59:39] - node T_654 = bits(T_646, 6, 0) @[Bitwise.scala 58:28] - node T_655 = shl(T_654, 1) @[Bitwise.scala 58:47] - node T_656 = xor(T_646, T_655) @[Bitwise.scala 58:21] - node T_657 = shr(T_653, 1) @[Bitwise.scala 59:21] - node T_658 = and(T_657, T_656) @[Bitwise.scala 59:31] - node T_659 = bits(T_653, 6, 0) @[Bitwise.scala 59:46] - node T_660 = shl(T_659, 1) @[Bitwise.scala 59:65] - node T_661 = not(T_656) @[Bitwise.scala 59:77] - node T_662 = and(T_660, T_661) @[Bitwise.scala 59:75] - node T_663 = or(T_658, T_662) @[Bitwise.scala 59:39] - node T_664 = bits(T_631, 14, 8) @[Bitwise.scala 65:44] - node T_665 = bits(T_664, 3, 0) @[Bitwise.scala 65:18] - node T_666 = bits(T_665, 1, 0) @[Bitwise.scala 65:18] - node T_667 = bits(T_666, 0, 0) @[Bitwise.scala 65:18] - node T_668 = bits(T_666, 1, 1) @[Bitwise.scala 65:44] - node T_669 = cat(T_667, T_668) @[Cat.scala 20:58] - node T_670 = bits(T_665, 3, 2) @[Bitwise.scala 65:44] - node T_671 = bits(T_670, 0, 0) @[Bitwise.scala 65:18] - node T_672 = bits(T_670, 1, 1) @[Bitwise.scala 65:44] - node T_673 = cat(T_671, T_672) @[Cat.scala 20:58] - node T_674 = cat(T_669, T_673) @[Cat.scala 20:58] - node T_675 = bits(T_664, 6, 4) @[Bitwise.scala 65:44] - node T_676 = bits(T_675, 1, 0) @[Bitwise.scala 65:18] - node T_677 = bits(T_676, 0, 0) @[Bitwise.scala 65:18] - node T_678 = bits(T_676, 1, 1) @[Bitwise.scala 65:44] - node T_679 = cat(T_677, T_678) @[Cat.scala 20:58] - node T_680 = bits(T_675, 2, 2) @[Bitwise.scala 65:44] - node T_681 = cat(T_679, T_680) @[Cat.scala 20:58] - node T_682 = cat(T_674, T_681) @[Cat.scala 20:58] - node T_683 = cat(T_663, T_682) @[Cat.scala 20:58] - node T_684 = cat(T_630, T_683) @[Cat.scala 20:58] - node absSigSumExtraMask = cat(T_684, UInt<1>("h01")) @[Cat.scala 20:58] - node T_686 = bits(cFirstNormAbsSigSum, 87, 1) @[MulAddRecFN.scala 424:32] - node T_687 = dshr(T_686, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] - node T_688 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 427:39] - node T_689 = not(T_688) @[MulAddRecFN.scala 427:19] - node T_690 = and(T_689, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] - node T_692 = eq(T_690, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] - node T_693 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 430:38] - node T_694 = and(T_693, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] - node T_696 = neq(T_694, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] - node T_697 = mux(doIncrSig, T_692, T_696) @[MulAddRecFN.scala 426:16] - node T_698 = cat(T_687, T_697) @[Cat.scala 20:58] - node sigX3 = bits(T_698, 56, 0) @[MulAddRecFN.scala 434:10] - node T_699 = bits(sigX3, 56, 55) @[MulAddRecFN.scala 436:29] - node sigX3Shift1 = eq(T_699, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] - node T_701 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] - node sExpX3 = tail(T_701, 1) @[MulAddRecFN.scala 437:40] - node T_702 = bits(sigX3, 56, 54) @[MulAddRecFN.scala 439:25] - node isZeroY = eq(T_702, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] - node T_704 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_704) @[MulAddRecFN.scala 442:12] - node sExpX3_13 = bits(sExpX3, 12, 0) @[MulAddRecFN.scala 446:27] - node T_705 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 448:34] - node T_706 = bits(T_705, 0, 0) @[Bitwise.scala 33:15] - node T_709 = mux(T_706, UInt<56>("h0ffffffffffffff"), UInt<56>("h00")) @[Bitwise.scala 33:12] - node T_710 = not(sExpX3_13) @[primitives.scala 50:21] - node T_711 = bits(T_710, 12, 12) @[primitives.scala 56:25] - node T_712 = bits(T_710, 11, 0) @[primitives.scala 57:26] - node T_713 = bits(T_712, 11, 11) @[primitives.scala 56:25] - node T_714 = bits(T_712, 10, 0) @[primitives.scala 57:26] - node T_715 = bits(T_714, 10, 10) @[primitives.scala 56:25] - node T_716 = bits(T_714, 9, 0) @[primitives.scala 57:26] - node T_717 = bits(T_716, 9, 9) @[primitives.scala 56:25] - node T_718 = bits(T_716, 8, 0) @[primitives.scala 57:26] - node T_720 = bits(T_718, 8, 8) @[primitives.scala 56:25] - node T_721 = bits(T_718, 7, 0) @[primitives.scala 57:26] - node T_723 = bits(T_721, 7, 7) @[primitives.scala 56:25] - node T_724 = bits(T_721, 6, 0) @[primitives.scala 57:26] - node T_726 = bits(T_724, 6, 6) @[primitives.scala 56:25] - node T_727 = bits(T_724, 5, 0) @[primitives.scala 57:26] - node T_730 = dshr(asSInt(UInt<65>("h010000000000000000")), T_727) @[primitives.scala 68:52] - node T_731 = bits(T_730, 63, 14) @[primitives.scala 69:26] - node T_732 = bits(T_731, 31, 0) @[Bitwise.scala 65:18] - node T_735 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 58:47] - node T_736 = xor(UInt<32>("h0ffffffff"), T_735) @[Bitwise.scala 58:21] - node T_737 = shr(T_732, 16) @[Bitwise.scala 59:21] - node T_738 = and(T_737, T_736) @[Bitwise.scala 59:31] - node T_739 = bits(T_732, 15, 0) @[Bitwise.scala 59:46] - node T_740 = shl(T_739, 16) @[Bitwise.scala 59:65] - node T_741 = not(T_736) @[Bitwise.scala 59:77] - node T_742 = and(T_740, T_741) @[Bitwise.scala 59:75] - node T_743 = or(T_738, T_742) @[Bitwise.scala 59:39] - node T_744 = bits(T_736, 23, 0) @[Bitwise.scala 58:28] - node T_745 = shl(T_744, 8) @[Bitwise.scala 58:47] - node T_746 = xor(T_736, T_745) @[Bitwise.scala 58:21] - node T_747 = shr(T_743, 8) @[Bitwise.scala 59:21] - node T_748 = and(T_747, T_746) @[Bitwise.scala 59:31] - node T_749 = bits(T_743, 23, 0) @[Bitwise.scala 59:46] - node T_750 = shl(T_749, 8) @[Bitwise.scala 59:65] - node T_751 = not(T_746) @[Bitwise.scala 59:77] - node T_752 = and(T_750, T_751) @[Bitwise.scala 59:75] - node T_753 = or(T_748, T_752) @[Bitwise.scala 59:39] - node T_754 = bits(T_746, 27, 0) @[Bitwise.scala 58:28] - node T_755 = shl(T_754, 4) @[Bitwise.scala 58:47] - node T_756 = xor(T_746, T_755) @[Bitwise.scala 58:21] - node T_757 = shr(T_753, 4) @[Bitwise.scala 59:21] - node T_758 = and(T_757, T_756) @[Bitwise.scala 59:31] - node T_759 = bits(T_753, 27, 0) @[Bitwise.scala 59:46] - node T_760 = shl(T_759, 4) @[Bitwise.scala 59:65] - node T_761 = not(T_756) @[Bitwise.scala 59:77] - node T_762 = and(T_760, T_761) @[Bitwise.scala 59:75] - node T_763 = or(T_758, T_762) @[Bitwise.scala 59:39] - node T_764 = bits(T_756, 29, 0) @[Bitwise.scala 58:28] - node T_765 = shl(T_764, 2) @[Bitwise.scala 58:47] - node T_766 = xor(T_756, T_765) @[Bitwise.scala 58:21] - node T_767 = shr(T_763, 2) @[Bitwise.scala 59:21] - node T_768 = and(T_767, T_766) @[Bitwise.scala 59:31] - node T_769 = bits(T_763, 29, 0) @[Bitwise.scala 59:46] - node T_770 = shl(T_769, 2) @[Bitwise.scala 59:65] - node T_771 = not(T_766) @[Bitwise.scala 59:77] - node T_772 = and(T_770, T_771) @[Bitwise.scala 59:75] - node T_773 = or(T_768, T_772) @[Bitwise.scala 59:39] - node T_774 = bits(T_766, 30, 0) @[Bitwise.scala 58:28] - node T_775 = shl(T_774, 1) @[Bitwise.scala 58:47] - node T_776 = xor(T_766, T_775) @[Bitwise.scala 58:21] - node T_777 = shr(T_773, 1) @[Bitwise.scala 59:21] - node T_778 = and(T_777, T_776) @[Bitwise.scala 59:31] - node T_779 = bits(T_773, 30, 0) @[Bitwise.scala 59:46] - node T_780 = shl(T_779, 1) @[Bitwise.scala 59:65] - node T_781 = not(T_776) @[Bitwise.scala 59:77] - node T_782 = and(T_780, T_781) @[Bitwise.scala 59:75] - node T_783 = or(T_778, T_782) @[Bitwise.scala 59:39] - node T_784 = bits(T_731, 49, 32) @[Bitwise.scala 65:44] - node T_785 = bits(T_784, 15, 0) @[Bitwise.scala 65:18] - node T_788 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_789 = xor(UInt<16>("h0ffff"), T_788) @[Bitwise.scala 58:21] - node T_790 = shr(T_785, 8) @[Bitwise.scala 59:21] - node T_791 = and(T_790, T_789) @[Bitwise.scala 59:31] - node T_792 = bits(T_785, 7, 0) @[Bitwise.scala 59:46] - node T_793 = shl(T_792, 8) @[Bitwise.scala 59:65] - node T_794 = not(T_789) @[Bitwise.scala 59:77] - node T_795 = and(T_793, T_794) @[Bitwise.scala 59:75] - node T_796 = or(T_791, T_795) @[Bitwise.scala 59:39] - node T_797 = bits(T_789, 11, 0) @[Bitwise.scala 58:28] - node T_798 = shl(T_797, 4) @[Bitwise.scala 58:47] - node T_799 = xor(T_789, T_798) @[Bitwise.scala 58:21] - node T_800 = shr(T_796, 4) @[Bitwise.scala 59:21] - node T_801 = and(T_800, T_799) @[Bitwise.scala 59:31] - node T_802 = bits(T_796, 11, 0) @[Bitwise.scala 59:46] - node T_803 = shl(T_802, 4) @[Bitwise.scala 59:65] - node T_804 = not(T_799) @[Bitwise.scala 59:77] - node T_805 = and(T_803, T_804) @[Bitwise.scala 59:75] - node T_806 = or(T_801, T_805) @[Bitwise.scala 59:39] - node T_807 = bits(T_799, 13, 0) @[Bitwise.scala 58:28] - node T_808 = shl(T_807, 2) @[Bitwise.scala 58:47] - node T_809 = xor(T_799, T_808) @[Bitwise.scala 58:21] - node T_810 = shr(T_806, 2) @[Bitwise.scala 59:21] - node T_811 = and(T_810, T_809) @[Bitwise.scala 59:31] - node T_812 = bits(T_806, 13, 0) @[Bitwise.scala 59:46] - node T_813 = shl(T_812, 2) @[Bitwise.scala 59:65] - node T_814 = not(T_809) @[Bitwise.scala 59:77] - node T_815 = and(T_813, T_814) @[Bitwise.scala 59:75] - node T_816 = or(T_811, T_815) @[Bitwise.scala 59:39] - node T_817 = bits(T_809, 14, 0) @[Bitwise.scala 58:28] - node T_818 = shl(T_817, 1) @[Bitwise.scala 58:47] - node T_819 = xor(T_809, T_818) @[Bitwise.scala 58:21] - node T_820 = shr(T_816, 1) @[Bitwise.scala 59:21] - node T_821 = and(T_820, T_819) @[Bitwise.scala 59:31] - node T_822 = bits(T_816, 14, 0) @[Bitwise.scala 59:46] - node T_823 = shl(T_822, 1) @[Bitwise.scala 59:65] - node T_824 = not(T_819) @[Bitwise.scala 59:77] - node T_825 = and(T_823, T_824) @[Bitwise.scala 59:75] - node T_826 = or(T_821, T_825) @[Bitwise.scala 59:39] - node T_827 = bits(T_784, 17, 16) @[Bitwise.scala 65:44] - node T_828 = bits(T_827, 0, 0) @[Bitwise.scala 65:18] - node T_829 = bits(T_827, 1, 1) @[Bitwise.scala 65:44] - node T_830 = cat(T_828, T_829) @[Cat.scala 20:58] - node T_831 = cat(T_826, T_830) @[Cat.scala 20:58] - node T_832 = cat(T_783, T_831) @[Cat.scala 20:58] - node T_833 = not(T_832) @[primitives.scala 65:36] - node T_834 = mux(T_726, UInt<1>("h00"), T_833) @[primitives.scala 65:21] - node T_835 = not(T_834) @[primitives.scala 65:17] - node T_836 = not(T_835) @[primitives.scala 65:36] - node T_837 = mux(T_723, UInt<1>("h00"), T_836) @[primitives.scala 65:21] - node T_838 = not(T_837) @[primitives.scala 65:17] - node T_839 = not(T_838) @[primitives.scala 65:36] - node T_840 = mux(T_720, UInt<1>("h00"), T_839) @[primitives.scala 65:21] - node T_841 = not(T_840) @[primitives.scala 65:17] - node T_842 = not(T_841) @[primitives.scala 65:36] - node T_843 = mux(T_717, UInt<1>("h00"), T_842) @[primitives.scala 65:21] - node T_844 = not(T_843) @[primitives.scala 65:17] - node T_846 = cat(T_844, UInt<4>("h0f")) @[Cat.scala 20:58] - node T_847 = bits(T_716, 9, 9) @[primitives.scala 56:25] - node T_848 = bits(T_716, 8, 0) @[primitives.scala 57:26] - node T_849 = bits(T_848, 8, 8) @[primitives.scala 56:25] - node T_850 = bits(T_848, 7, 0) @[primitives.scala 57:26] - node T_851 = bits(T_850, 7, 7) @[primitives.scala 56:25] - node T_852 = bits(T_850, 6, 0) @[primitives.scala 57:26] - node T_853 = bits(T_852, 6, 6) @[primitives.scala 56:25] - node T_854 = bits(T_852, 5, 0) @[primitives.scala 57:26] - node T_856 = dshr(asSInt(UInt<65>("h010000000000000000")), T_854) @[primitives.scala 68:52] - node T_857 = bits(T_856, 3, 0) @[primitives.scala 69:26] - node T_858 = bits(T_857, 1, 0) @[Bitwise.scala 65:18] - node T_859 = bits(T_858, 0, 0) @[Bitwise.scala 65:18] - node T_860 = bits(T_858, 1, 1) @[Bitwise.scala 65:44] - node T_861 = cat(T_859, T_860) @[Cat.scala 20:58] - node T_862 = bits(T_857, 3, 2) @[Bitwise.scala 65:44] - node T_863 = bits(T_862, 0, 0) @[Bitwise.scala 65:18] - node T_864 = bits(T_862, 1, 1) @[Bitwise.scala 65:44] - node T_865 = cat(T_863, T_864) @[Cat.scala 20:58] - node T_866 = cat(T_861, T_865) @[Cat.scala 20:58] - node T_868 = mux(T_853, T_866, UInt<1>("h00")) @[primitives.scala 59:20] - node T_870 = mux(T_851, T_868, UInt<1>("h00")) @[primitives.scala 59:20] - node T_872 = mux(T_849, T_870, UInt<1>("h00")) @[primitives.scala 59:20] - node T_874 = mux(T_847, T_872, UInt<1>("h00")) @[primitives.scala 59:20] - node T_875 = mux(T_715, T_846, T_874) @[primitives.scala 61:20] - node T_877 = mux(T_713, T_875, UInt<1>("h00")) @[primitives.scala 59:20] - node T_879 = mux(T_711, T_877, UInt<1>("h00")) @[primitives.scala 59:20] - node T_880 = bits(sigX3, 55, 55) @[MulAddRecFN.scala 450:26] - node T_881 = or(T_879, T_880) @[MulAddRecFN.scala 449:75] - node T_883 = cat(T_881, UInt<2>("h03")) @[Cat.scala 20:58] - node roundMask = or(T_709, T_883) @[MulAddRecFN.scala 448:50] - node T_884 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] - node T_885 = not(T_884) @[MulAddRecFN.scala 454:24] - node roundPosMask = and(T_885, roundMask) @[MulAddRecFN.scala 454:40] - node T_886 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] - node roundPosBit = neq(T_886, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] - node T_888 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] - node T_889 = and(sigX3, T_888) @[MulAddRecFN.scala 456:34] - node anyRoundExtra = neq(T_889, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] - node T_891 = not(sigX3) @[MulAddRecFN.scala 457:27] - node T_892 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] - node T_893 = and(T_891, T_892) @[MulAddRecFN.scala 457:34] - node allRoundExtra = eq(T_893, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] - node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] - node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] - node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] - node T_896 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] - node T_897 = and(T_896, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] - node T_898 = and(T_897, roundPosBit) @[MulAddRecFN.scala 462:51] - node T_899 = and(T_898, anyRoundExtra) @[MulAddRecFN.scala 463:60] - node T_901 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] - node T_902 = and(T_901, roundDirectUp) @[MulAddRecFN.scala 464:22] - node T_903 = and(T_902, anyRound) @[MulAddRecFN.scala 464:49] - node T_904 = or(T_899, T_903) @[MulAddRecFN.scala 463:78] - node T_905 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] - node T_906 = or(T_904, T_905) @[MulAddRecFN.scala 464:65] - node T_907 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] - node T_908 = and(T_907, roundPosBit) @[MulAddRecFN.scala 466:49] - node T_909 = or(T_906, T_908) @[MulAddRecFN.scala 465:65] - node T_910 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] - node T_912 = and(T_910, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] - node roundUp = or(T_909, T_912) @[MulAddRecFN.scala 466:65] - node T_914 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] - node T_915 = and(roundingMode_nearest_even, T_914) @[MulAddRecFN.scala 470:39] - node T_916 = and(T_915, allRoundExtra) @[MulAddRecFN.scala 470:56] - node T_917 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] - node T_919 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] - node T_920 = and(T_917, T_919) @[MulAddRecFN.scala 471:56] - node roundEven = mux(doIncrSig, T_916, T_920) @[MulAddRecFN.scala 469:12] - node T_922 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] - node roundInexact = mux(doIncrSig, T_922, anyRound) @[MulAddRecFN.scala 473:27] - node T_923 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] - node T_924 = shr(T_923, 2) @[MulAddRecFN.scala 475:30] - node T_926 = add(T_924, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] - node T_927 = tail(T_926, 1) @[MulAddRecFN.scala 475:35] - node roundUp_sigY3 = bits(T_927, 54, 0) @[MulAddRecFN.scala 475:45] - node T_929 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] - node T_931 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] - node T_932 = and(T_929, T_931) @[MulAddRecFN.scala 477:23] - node T_933 = not(roundMask) @[MulAddRecFN.scala 477:48] - node T_934 = and(sigX3, T_933) @[MulAddRecFN.scala 477:46] - node T_935 = shr(T_934, 2) @[MulAddRecFN.scala 477:59] - node T_937 = mux(T_932, T_935, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] - node T_939 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] - node T_940 = or(T_937, T_939) @[MulAddRecFN.scala 477:79] - node T_941 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] - node T_942 = not(T_941) @[MulAddRecFN.scala 479:53] - node T_943 = and(roundUp_sigY3, T_942) @[MulAddRecFN.scala 479:51] - node T_945 = mux(roundEven, T_943, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] - node sigY3 = or(T_940, T_945) @[MulAddRecFN.scala 478:79] - node T_946 = bits(sigY3, 54, 54) @[MulAddRecFN.scala 482:18] - node T_948 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] - node T_949 = tail(T_948, 1) @[MulAddRecFN.scala 482:41] - node T_951 = mux(T_946, T_949, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] - node T_952 = bits(sigY3, 53, 53) @[MulAddRecFN.scala 483:18] - node T_954 = mux(T_952, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] - node T_955 = or(T_951, T_954) @[MulAddRecFN.scala 482:61] - node T_956 = bits(sigY3, 54, 53) @[MulAddRecFN.scala 484:19] - node T_958 = eq(T_956, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] - node T_960 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] - node T_961 = tail(T_960, 1) @[MulAddRecFN.scala 485:20] - node T_963 = mux(T_958, T_961, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] - node sExpY = or(T_955, T_963) @[MulAddRecFN.scala 483:61] - node expY = bits(sExpY, 11, 0) @[MulAddRecFN.scala 488:21] - node T_964 = bits(sigY3, 51, 0) @[MulAddRecFN.scala 490:31] - node T_965 = bits(sigY3, 52, 1) @[MulAddRecFN.scala 490:55] - node fractY = mux(sigX3Shift1, T_964, T_965) @[MulAddRecFN.scala 490:12] - node T_966 = bits(sExpY, 12, 10) @[MulAddRecFN.scala 492:27] - node overflowY = eq(T_966, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] - node T_969 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] - node T_970 = bits(sExpY, 12, 12) @[MulAddRecFN.scala 496:19] - node T_971 = bits(sExpY, 11, 0) @[MulAddRecFN.scala 496:43] - node T_973 = lt(T_971, UInt<10>("h03ce")) @[MulAddRecFN.scala 496:57] - node T_974 = or(T_970, T_973) @[MulAddRecFN.scala 496:34] - node totalUnderflowY = and(T_969, T_974) @[MulAddRecFN.scala 495:19] - node T_975 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 499:20] - node T_978 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) @[MulAddRecFN.scala 501:26] - node T_979 = leq(sExpX3_13, T_978) @[MulAddRecFN.scala 500:29] - node T_980 = or(T_975, T_979) @[MulAddRecFN.scala 499:35] - node underflowY = and(roundInexact, T_980) @[MulAddRecFN.scala 498:22] - node T_981 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] - node T_983 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] - node T_984 = and(roundingMode_max, T_983) @[MulAddRecFN.scala 506:58] - node roundMagUp = or(T_981, T_984) @[MulAddRecFN.scala 506:37] - node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] - node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] - node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] - node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] - node T_986 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] - node T_988 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] - node commonCase = and(T_986, T_988) @[MulAddRecFN.scala 514:35] - node T_989 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] - node T_990 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] - node T_991 = or(T_989, T_990) @[MulAddRecFN.scala 517:29] - node T_993 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] - node T_995 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] - node T_996 = and(T_993, T_995) @[MulAddRecFN.scala 518:23] - node T_997 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] - node T_998 = and(T_996, T_997) @[MulAddRecFN.scala 518:35] - node T_999 = and(T_998, isInfC) @[MulAddRecFN.scala 518:57] - node T_1000 = and(T_999, doSubMags) @[MulAddRecFN.scala 518:67] - node notSigNaN_invalid = or(T_991, T_1000) @[MulAddRecFN.scala 517:52] - node T_1001 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] - node T_1002 = or(T_1001, isSigNaNC) @[MulAddRecFN.scala 519:42] - node invalid = or(T_1002, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] - node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] - node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] - node T_1003 = and(commonCase, roundInexact) @[MulAddRecFN.scala 522:43] - node inexact = or(overflow, T_1003) @[MulAddRecFN.scala 522:28] - node T_1004 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] - node notSpecial_isZeroOut = or(T_1004, totalUnderflowY) @[MulAddRecFN.scala 525:40] - node T_1005 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] - node pegMinFiniteMagOut = and(T_1005, roundMagUp) @[MulAddRecFN.scala 526:60] - node T_1007 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] - node pegMaxFiniteMagOut = and(overflow, T_1007) @[MulAddRecFN.scala 527:39] - node T_1008 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] - node T_1009 = or(T_1008, isInfC) @[MulAddRecFN.scala 529:26] - node T_1010 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] - node notNaN_isInfOut = or(T_1009, T_1010) @[MulAddRecFN.scala 529:36] - node T_1011 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] - node T_1012 = or(T_1011, isNaNC) @[MulAddRecFN.scala 530:37] - node isNaNOut = or(T_1012, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] - node T_1014 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] - node T_1015 = and(T_1014, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] - node T_1017 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] - node T_1018 = and(mulSpecial, T_1017) @[MulAddRecFN.scala 534:21] - node T_1019 = and(T_1018, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] - node T_1020 = or(T_1015, T_1019) @[MulAddRecFN.scala 533:78] - node T_1022 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] - node T_1023 = and(T_1022, isSpecialC) @[MulAddRecFN.scala 535:23] - node T_1024 = and(T_1023, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] - node T_1025 = or(T_1020, T_1024) @[MulAddRecFN.scala 534:78] - node T_1027 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] - node T_1028 = and(T_1027, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] - node T_1029 = and(T_1028, doSubMags) @[MulAddRecFN.scala 536:46] - node T_1030 = and(T_1029, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] - node uncommonCaseSignOut = or(T_1025, T_1030) @[MulAddRecFN.scala 535:78] - node T_1032 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] - node T_1033 = and(T_1032, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] - node T_1034 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] - node signOut = or(T_1033, T_1034) @[MulAddRecFN.scala 538:55] - node T_1037 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 541:18] - node T_1038 = not(T_1037) @[MulAddRecFN.scala 541:14] - node T_1039 = and(expY, T_1038) @[MulAddRecFN.scala 540:15] - node T_1041 = not(UInt<12>("h03ce")) @[MulAddRecFN.scala 546:19] - node T_1043 = mux(pegMinFiniteMagOut, T_1041, UInt<12>("h00")) @[MulAddRecFN.scala 545:18] - node T_1044 = not(T_1043) @[MulAddRecFN.scala 545:14] - node T_1045 = and(T_1039, T_1044) @[MulAddRecFN.scala 544:17] - node T_1048 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) @[MulAddRecFN.scala 549:18] - node T_1049 = not(T_1048) @[MulAddRecFN.scala 549:14] - node T_1050 = and(T_1045, T_1049) @[MulAddRecFN.scala 548:17] - node T_1053 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) @[MulAddRecFN.scala 553:18] - node T_1054 = not(T_1053) @[MulAddRecFN.scala 553:14] - node T_1055 = and(T_1050, T_1054) @[MulAddRecFN.scala 552:17] - node T_1058 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) @[MulAddRecFN.scala 557:16] - node T_1059 = or(T_1055, T_1058) @[MulAddRecFN.scala 556:18] - node T_1062 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) @[MulAddRecFN.scala 558:16] - node T_1063 = or(T_1059, T_1062) @[MulAddRecFN.scala 557:74] - node T_1066 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) @[MulAddRecFN.scala 562:16] - node T_1067 = or(T_1063, T_1066) @[MulAddRecFN.scala 561:15] - node T_1070 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 566:16] - node expOut = or(T_1067, T_1070) @[MulAddRecFN.scala 565:15] - node T_1071 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] - node T_1072 = or(T_1071, isNaNOut) @[MulAddRecFN.scala 568:45] - node T_1074 = shl(UInt<1>("h01"), 51) @[MulAddRecFN.scala 569:34] - node T_1076 = mux(isNaNOut, T_1074, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] - node T_1077 = mux(T_1072, T_1076, fractY) @[MulAddRecFN.scala 568:12] - node T_1078 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 33:15] - node T_1081 = mux(T_1078, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 33:12] - node fractOut = or(T_1077, T_1081) @[MulAddRecFN.scala 571:11] - node T_1082 = cat(signOut, expOut) @[Cat.scala 20:58] - node T_1083 = cat(T_1082, fractOut) @[Cat.scala 20:58] - io.out <= T_1083 @[MulAddRecFN.scala 574:12] - node T_1085 = cat(underflow, inexact) @[Cat.scala 20:58] - node T_1086 = cat(invalid, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1087 = cat(T_1086, overflow) @[Cat.scala 20:58] - node T_1088 = cat(T_1087, T_1085) @[Cat.scala 20:58] - io.exceptionFlags <= T_1088 @[MulAddRecFN.scala 575:23] - - module MulAddRecFN_1 : + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h0")) + node T_38 = bits(io.fromPreMul.highExpA, 2, 1) + node isSpecialA = eq(T_38, UInt<2>("h3")) + node T_40 = bits(io.fromPreMul.highExpA, 0, 0) + node T_42 = eq(T_40, UInt<1>("h0")) + node isInfA = and(isSpecialA, T_42) + node T_43 = bits(io.fromPreMul.highExpA, 0, 0) + node isNaNA = and(isSpecialA, T_43) + node T_45 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h0")) + node isSigNaNA = and(isNaNA, T_45) + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h0")) + node T_47 = bits(io.fromPreMul.highExpB, 2, 1) + node isSpecialB = eq(T_47, UInt<2>("h3")) + node T_49 = bits(io.fromPreMul.highExpB, 0, 0) + node T_51 = eq(T_49, UInt<1>("h0")) + node isInfB = and(isSpecialB, T_51) + node T_52 = bits(io.fromPreMul.highExpB, 0, 0) + node isNaNB = and(isSpecialB, T_52) + node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h0")) + node isSigNaNB = and(isNaNB, T_54) + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h0")) + node T_56 = bits(io.fromPreMul.highExpC, 2, 1) + node isSpecialC = eq(T_56, UInt<2>("h3")) + node T_58 = bits(io.fromPreMul.highExpC, 0, 0) + node T_60 = eq(T_58, UInt<1>("h0")) + node isInfC = and(isSpecialC, T_60) + node T_61 = bits(io.fromPreMul.highExpC, 0, 0) + node isNaNC = and(isSpecialC, T_61) + node T_63 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h0")) + node isSigNaNC = and(isNaNC, T_63) + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h0")) + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h1")) + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h2")) + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h3")) + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h1"), UInt<1>("h0")) + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) + node T_66 = bits(io.mulAddResult, 106, 106) + node T_68 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h1")) + node T_69 = tail(T_68, 1) + node T_70 = mux(T_66, T_69, io.fromPreMul.highAlignedNegSigC) + node T_71 = bits(io.mulAddResult, 105, 0) + node T_72 = cat(T_70, T_71) + node sigSum = cat(T_72, io.fromPreMul.bit0AlignedNegSigC) + node T_74 = bits(sigSum, 108, 1) + node T_75 = xor(UInt<108>("h0"), T_74) + node T_76 = or(UInt<108>("h0"), T_74) + node T_77 = shl(T_76, 1) + node T_78 = xor(T_75, T_77) + node T_80 = bits(T_78, 107, 0) + node T_81 = bits(T_80, 107, 64) + node T_82 = bits(T_80, 63, 0) + node T_84 = neq(T_81, UInt<1>("h0")) + node T_85 = bits(T_81, 43, 32) + node T_86 = bits(T_81, 31, 0) + node T_88 = neq(T_85, UInt<1>("h0")) + node T_89 = bits(T_85, 11, 8) + node T_90 = bits(T_85, 7, 0) + node T_92 = neq(T_89, UInt<1>("h0")) + node T_93 = bits(T_89, 3, 3) + node T_95 = bits(T_89, 2, 2) + node T_97 = bits(T_89, 1, 1) + node T_98 = shl(T_97, 0) + node T_99 = mux(T_95, UInt<2>("h2"), T_98) + node T_100 = mux(T_93, UInt<2>("h3"), T_99) + node T_101 = bits(T_90, 7, 4) + node T_102 = bits(T_90, 3, 0) + node T_104 = neq(T_101, UInt<1>("h0")) + node T_105 = bits(T_101, 3, 3) + node T_107 = bits(T_101, 2, 2) + node T_109 = bits(T_101, 1, 1) + node T_110 = shl(T_109, 0) + node T_111 = mux(T_107, UInt<2>("h2"), T_110) + node T_112 = mux(T_105, UInt<2>("h3"), T_111) + node T_113 = bits(T_102, 3, 3) + node T_115 = bits(T_102, 2, 2) + node T_117 = bits(T_102, 1, 1) + node T_118 = shl(T_117, 0) + node T_119 = mux(T_115, UInt<2>("h2"), T_118) + node T_120 = mux(T_113, UInt<2>("h3"), T_119) + node T_121 = mux(T_104, T_112, T_120) + node T_122 = cat(T_104, T_121) + node T_123 = mux(T_92, T_100, T_122) + node T_124 = cat(T_92, T_123) + node T_125 = bits(T_86, 31, 16) + node T_126 = bits(T_86, 15, 0) + node T_128 = neq(T_125, UInt<1>("h0")) + node T_129 = bits(T_125, 15, 8) + node T_130 = bits(T_125, 7, 0) + node T_132 = neq(T_129, UInt<1>("h0")) + node T_133 = bits(T_129, 7, 4) + node T_134 = bits(T_129, 3, 0) + node T_136 = neq(T_133, UInt<1>("h0")) + node T_137 = bits(T_133, 3, 3) + node T_139 = bits(T_133, 2, 2) + node T_141 = bits(T_133, 1, 1) + node T_142 = shl(T_141, 0) + node T_143 = mux(T_139, UInt<2>("h2"), T_142) + node T_144 = mux(T_137, UInt<2>("h3"), T_143) + node T_145 = bits(T_134, 3, 3) + node T_147 = bits(T_134, 2, 2) + node T_149 = bits(T_134, 1, 1) + node T_150 = shl(T_149, 0) + node T_151 = mux(T_147, UInt<2>("h2"), T_150) + node T_152 = mux(T_145, UInt<2>("h3"), T_151) + node T_153 = mux(T_136, T_144, T_152) + node T_154 = cat(T_136, T_153) + node T_155 = bits(T_130, 7, 4) + node T_156 = bits(T_130, 3, 0) + node T_158 = neq(T_155, UInt<1>("h0")) + node T_159 = bits(T_155, 3, 3) + node T_161 = bits(T_155, 2, 2) + node T_163 = bits(T_155, 1, 1) + node T_164 = shl(T_163, 0) + node T_165 = mux(T_161, UInt<2>("h2"), T_164) + node T_166 = mux(T_159, UInt<2>("h3"), T_165) + node T_167 = bits(T_156, 3, 3) + node T_169 = bits(T_156, 2, 2) + node T_171 = bits(T_156, 1, 1) + node T_172 = shl(T_171, 0) + node T_173 = mux(T_169, UInt<2>("h2"), T_172) + node T_174 = mux(T_167, UInt<2>("h3"), T_173) + node T_175 = mux(T_158, T_166, T_174) + node T_176 = cat(T_158, T_175) + node T_177 = mux(T_132, T_154, T_176) + node T_178 = cat(T_132, T_177) + node T_179 = bits(T_126, 15, 8) + node T_180 = bits(T_126, 7, 0) + node T_182 = neq(T_179, UInt<1>("h0")) + node T_183 = bits(T_179, 7, 4) + node T_184 = bits(T_179, 3, 0) + node T_186 = neq(T_183, UInt<1>("h0")) + node T_187 = bits(T_183, 3, 3) + node T_189 = bits(T_183, 2, 2) + node T_191 = bits(T_183, 1, 1) + node T_192 = shl(T_191, 0) + node T_193 = mux(T_189, UInt<2>("h2"), T_192) + node T_194 = mux(T_187, UInt<2>("h3"), T_193) + node T_195 = bits(T_184, 3, 3) + node T_197 = bits(T_184, 2, 2) + node T_199 = bits(T_184, 1, 1) + node T_200 = shl(T_199, 0) + node T_201 = mux(T_197, UInt<2>("h2"), T_200) + node T_202 = mux(T_195, UInt<2>("h3"), T_201) + node T_203 = mux(T_186, T_194, T_202) + node T_204 = cat(T_186, T_203) + node T_205 = bits(T_180, 7, 4) + node T_206 = bits(T_180, 3, 0) + node T_208 = neq(T_205, UInt<1>("h0")) + node T_209 = bits(T_205, 3, 3) + node T_211 = bits(T_205, 2, 2) + node T_213 = bits(T_205, 1, 1) + node T_214 = shl(T_213, 0) + node T_215 = mux(T_211, UInt<2>("h2"), T_214) + node T_216 = mux(T_209, UInt<2>("h3"), T_215) + node T_217 = bits(T_206, 3, 3) + node T_219 = bits(T_206, 2, 2) + node T_221 = bits(T_206, 1, 1) + node T_222 = shl(T_221, 0) + node T_223 = mux(T_219, UInt<2>("h2"), T_222) + node T_224 = mux(T_217, UInt<2>("h3"), T_223) + node T_225 = mux(T_208, T_216, T_224) + node T_226 = cat(T_208, T_225) + node T_227 = mux(T_182, T_204, T_226) + node T_228 = cat(T_182, T_227) + node T_229 = mux(T_128, T_178, T_228) + node T_230 = cat(T_128, T_229) + node T_231 = mux(T_88, T_124, T_230) + node T_232 = cat(T_88, T_231) + node T_233 = bits(T_82, 63, 32) + node T_234 = bits(T_82, 31, 0) + node T_236 = neq(T_233, UInt<1>("h0")) + node T_237 = bits(T_233, 31, 16) + node T_238 = bits(T_233, 15, 0) + node T_240 = neq(T_237, UInt<1>("h0")) + node T_241 = bits(T_237, 15, 8) + node T_242 = bits(T_237, 7, 0) + node T_244 = neq(T_241, UInt<1>("h0")) + node T_245 = bits(T_241, 7, 4) + node T_246 = bits(T_241, 3, 0) + node T_248 = neq(T_245, UInt<1>("h0")) + node T_249 = bits(T_245, 3, 3) + node T_251 = bits(T_245, 2, 2) + node T_253 = bits(T_245, 1, 1) + node T_254 = shl(T_253, 0) + node T_255 = mux(T_251, UInt<2>("h2"), T_254) + node T_256 = mux(T_249, UInt<2>("h3"), T_255) + node T_257 = bits(T_246, 3, 3) + node T_259 = bits(T_246, 2, 2) + node T_261 = bits(T_246, 1, 1) + node T_262 = shl(T_261, 0) + node T_263 = mux(T_259, UInt<2>("h2"), T_262) + node T_264 = mux(T_257, UInt<2>("h3"), T_263) + node T_265 = mux(T_248, T_256, T_264) + node T_266 = cat(T_248, T_265) + node T_267 = bits(T_242, 7, 4) + node T_268 = bits(T_242, 3, 0) + node T_270 = neq(T_267, UInt<1>("h0")) + node T_271 = bits(T_267, 3, 3) + node T_273 = bits(T_267, 2, 2) + node T_275 = bits(T_267, 1, 1) + node T_276 = shl(T_275, 0) + node T_277 = mux(T_273, UInt<2>("h2"), T_276) + node T_278 = mux(T_271, UInt<2>("h3"), T_277) + node T_279 = bits(T_268, 3, 3) + node T_281 = bits(T_268, 2, 2) + node T_283 = bits(T_268, 1, 1) + node T_284 = shl(T_283, 0) + node T_285 = mux(T_281, UInt<2>("h2"), T_284) + node T_286 = mux(T_279, UInt<2>("h3"), T_285) + node T_287 = mux(T_270, T_278, T_286) + node T_288 = cat(T_270, T_287) + node T_289 = mux(T_244, T_266, T_288) + node T_290 = cat(T_244, T_289) + node T_291 = bits(T_238, 15, 8) + node T_292 = bits(T_238, 7, 0) + node T_294 = neq(T_291, UInt<1>("h0")) + node T_295 = bits(T_291, 7, 4) + node T_296 = bits(T_291, 3, 0) + node T_298 = neq(T_295, UInt<1>("h0")) + node T_299 = bits(T_295, 3, 3) + node T_301 = bits(T_295, 2, 2) + node T_303 = bits(T_295, 1, 1) + node T_304 = shl(T_303, 0) + node T_305 = mux(T_301, UInt<2>("h2"), T_304) + node T_306 = mux(T_299, UInt<2>("h3"), T_305) + node T_307 = bits(T_296, 3, 3) + node T_309 = bits(T_296, 2, 2) + node T_311 = bits(T_296, 1, 1) + node T_312 = shl(T_311, 0) + node T_313 = mux(T_309, UInt<2>("h2"), T_312) + node T_314 = mux(T_307, UInt<2>("h3"), T_313) + node T_315 = mux(T_298, T_306, T_314) + node T_316 = cat(T_298, T_315) + node T_317 = bits(T_292, 7, 4) + node T_318 = bits(T_292, 3, 0) + node T_320 = neq(T_317, UInt<1>("h0")) + node T_321 = bits(T_317, 3, 3) + node T_323 = bits(T_317, 2, 2) + node T_325 = bits(T_317, 1, 1) + node T_326 = shl(T_325, 0) + node T_327 = mux(T_323, UInt<2>("h2"), T_326) + node T_328 = mux(T_321, UInt<2>("h3"), T_327) + node T_329 = bits(T_318, 3, 3) + node T_331 = bits(T_318, 2, 2) + node T_333 = bits(T_318, 1, 1) + node T_334 = shl(T_333, 0) + node T_335 = mux(T_331, UInt<2>("h2"), T_334) + node T_336 = mux(T_329, UInt<2>("h3"), T_335) + node T_337 = mux(T_320, T_328, T_336) + node T_338 = cat(T_320, T_337) + node T_339 = mux(T_294, T_316, T_338) + node T_340 = cat(T_294, T_339) + node T_341 = mux(T_240, T_290, T_340) + node T_342 = cat(T_240, T_341) + node T_343 = bits(T_234, 31, 16) + node T_344 = bits(T_234, 15, 0) + node T_346 = neq(T_343, UInt<1>("h0")) + node T_347 = bits(T_343, 15, 8) + node T_348 = bits(T_343, 7, 0) + node T_350 = neq(T_347, UInt<1>("h0")) + node T_351 = bits(T_347, 7, 4) + node T_352 = bits(T_347, 3, 0) + node T_354 = neq(T_351, UInt<1>("h0")) + node T_355 = bits(T_351, 3, 3) + node T_357 = bits(T_351, 2, 2) + node T_359 = bits(T_351, 1, 1) + node T_360 = shl(T_359, 0) + node T_361 = mux(T_357, UInt<2>("h2"), T_360) + node T_362 = mux(T_355, UInt<2>("h3"), T_361) + node T_363 = bits(T_352, 3, 3) + node T_365 = bits(T_352, 2, 2) + node T_367 = bits(T_352, 1, 1) + node T_368 = shl(T_367, 0) + node T_369 = mux(T_365, UInt<2>("h2"), T_368) + node T_370 = mux(T_363, UInt<2>("h3"), T_369) + node T_371 = mux(T_354, T_362, T_370) + node T_372 = cat(T_354, T_371) + node T_373 = bits(T_348, 7, 4) + node T_374 = bits(T_348, 3, 0) + node T_376 = neq(T_373, UInt<1>("h0")) + node T_377 = bits(T_373, 3, 3) + node T_379 = bits(T_373, 2, 2) + node T_381 = bits(T_373, 1, 1) + node T_382 = shl(T_381, 0) + node T_383 = mux(T_379, UInt<2>("h2"), T_382) + node T_384 = mux(T_377, UInt<2>("h3"), T_383) + node T_385 = bits(T_374, 3, 3) + node T_387 = bits(T_374, 2, 2) + node T_389 = bits(T_374, 1, 1) + node T_390 = shl(T_389, 0) + node T_391 = mux(T_387, UInt<2>("h2"), T_390) + node T_392 = mux(T_385, UInt<2>("h3"), T_391) + node T_393 = mux(T_376, T_384, T_392) + node T_394 = cat(T_376, T_393) + node T_395 = mux(T_350, T_372, T_394) + node T_396 = cat(T_350, T_395) + node T_397 = bits(T_344, 15, 8) + node T_398 = bits(T_344, 7, 0) + node T_400 = neq(T_397, UInt<1>("h0")) + node T_401 = bits(T_397, 7, 4) + node T_402 = bits(T_397, 3, 0) + node T_404 = neq(T_401, UInt<1>("h0")) + node T_405 = bits(T_401, 3, 3) + node T_407 = bits(T_401, 2, 2) + node T_409 = bits(T_401, 1, 1) + node T_410 = shl(T_409, 0) + node T_411 = mux(T_407, UInt<2>("h2"), T_410) + node T_412 = mux(T_405, UInt<2>("h3"), T_411) + node T_413 = bits(T_402, 3, 3) + node T_415 = bits(T_402, 2, 2) + node T_417 = bits(T_402, 1, 1) + node T_418 = shl(T_417, 0) + node T_419 = mux(T_415, UInt<2>("h2"), T_418) + node T_420 = mux(T_413, UInt<2>("h3"), T_419) + node T_421 = mux(T_404, T_412, T_420) + node T_422 = cat(T_404, T_421) + node T_423 = bits(T_398, 7, 4) + node T_424 = bits(T_398, 3, 0) + node T_426 = neq(T_423, UInt<1>("h0")) + node T_427 = bits(T_423, 3, 3) + node T_429 = bits(T_423, 2, 2) + node T_431 = bits(T_423, 1, 1) + node T_432 = shl(T_431, 0) + node T_433 = mux(T_429, UInt<2>("h2"), T_432) + node T_434 = mux(T_427, UInt<2>("h3"), T_433) + node T_435 = bits(T_424, 3, 3) + node T_437 = bits(T_424, 2, 2) + node T_439 = bits(T_424, 1, 1) + node T_440 = shl(T_439, 0) + node T_441 = mux(T_437, UInt<2>("h2"), T_440) + node T_442 = mux(T_435, UInt<2>("h3"), T_441) + node T_443 = mux(T_426, T_434, T_442) + node T_444 = cat(T_426, T_443) + node T_445 = mux(T_400, T_422, T_444) + node T_446 = cat(T_400, T_445) + node T_447 = mux(T_346, T_396, T_446) + node T_448 = cat(T_346, T_447) + node T_449 = mux(T_236, T_342, T_448) + node T_450 = cat(T_236, T_449) + node T_451 = mux(T_84, T_232, T_450) + node T_452 = cat(T_84, T_451) + node T_453 = sub(UInt<8>("ha0"), T_452) + node estNormPos_dist = tail(T_453, 1) + node T_454 = bits(sigSum, 75, 44) + node T_456 = neq(T_454, UInt<1>("h0")) + node T_457 = bits(sigSum, 43, 0) + node T_459 = neq(T_457, UInt<1>("h0")) + node firstReduceSigSum = cat(T_456, T_459) + node complSigSum = not(sigSum) + node T_460 = bits(complSigSum, 75, 44) + node T_462 = neq(T_460, UInt<1>("h0")) + node T_463 = bits(complSigSum, 43, 0) + node T_465 = neq(T_463, UInt<1>("h0")) + node firstReduceComplSigSum = cat(T_462, T_465) + node T_466 = or(io.fromPreMul.CAlignDist_0, doSubMags) + node T_468 = sub(io.fromPreMul.CAlignDist, UInt<1>("h1")) + node T_469 = tail(T_468, 1) + node T_470 = bits(T_469, 5, 0) + node CDom_estNormDist = mux(T_466, io.fromPreMul.CAlignDist, T_470) + node T_472 = eq(doSubMags, UInt<1>("h0")) + node T_473 = bits(CDom_estNormDist, 5, 5) + node T_475 = eq(T_473, UInt<1>("h0")) + node T_476 = and(T_472, T_475) + node T_477 = bits(sigSum, 161, 76) + node T_479 = neq(firstReduceSigSum, UInt<1>("h0")) + node T_480 = cat(T_477, T_479) + node T_482 = mux(T_476, T_480, UInt<1>("h0")) + node T_484 = eq(doSubMags, UInt<1>("h0")) + node T_485 = bits(CDom_estNormDist, 5, 5) + node T_486 = and(T_484, T_485) + node T_487 = bits(sigSum, 129, 44) + node T_488 = bits(firstReduceSigSum, 0, 0) + node T_489 = cat(T_487, T_488) + node T_491 = mux(T_486, T_489, UInt<1>("h0")) + node T_492 = or(T_482, T_491) + node T_493 = bits(CDom_estNormDist, 5, 5) + node T_495 = eq(T_493, UInt<1>("h0")) + node T_496 = and(doSubMags, T_495) + node T_497 = bits(complSigSum, 161, 76) + node T_499 = neq(firstReduceComplSigSum, UInt<1>("h0")) + node T_500 = cat(T_497, T_499) + node T_502 = mux(T_496, T_500, UInt<1>("h0")) + node T_503 = or(T_492, T_502) + node T_504 = bits(CDom_estNormDist, 5, 5) + node T_505 = and(doSubMags, T_504) + node T_506 = bits(complSigSum, 129, 44) + node T_507 = bits(firstReduceComplSigSum, 0, 0) + node T_508 = cat(T_506, T_507) + node T_510 = mux(T_505, T_508, UInt<1>("h0")) + node CDom_firstNormAbsSigSum = or(T_503, T_510) + node T_511 = bits(sigSum, 108, 44) + node T_512 = bits(firstReduceComplSigSum, 0, 0) + node T_514 = eq(T_512, UInt<1>("h0")) + node T_515 = bits(firstReduceSigSum, 0, 0) + node T_516 = mux(doSubMags, T_514, T_515) + node T_517 = cat(T_511, T_516) + node T_518 = bits(sigSum, 97, 1) + node T_519 = bits(estNormPos_dist, 4, 4) + node T_520 = bits(sigSum, 1, 1) + node T_521 = bits(doSubMags, 0, 0) + node T_524 = mux(T_521, UInt<86>("h3fffffffffffffffffffff"), UInt<86>("h0")) + node T_525 = cat(T_520, T_524) + node T_526 = mux(T_519, T_517, T_525) + node T_527 = bits(sigSum, 97, 12) + node T_528 = bits(complSigSum, 11, 1) + node T_530 = eq(T_528, UInt<1>("h0")) + node T_531 = bits(sigSum, 11, 1) + node T_533 = neq(T_531, UInt<1>("h0")) + node T_534 = mux(doSubMags, T_530, T_533) + node T_535 = cat(T_527, T_534) + node T_536 = bits(estNormPos_dist, 6, 6) + node T_537 = bits(estNormPos_dist, 5, 5) + node T_538 = bits(sigSum, 65, 1) + node T_539 = bits(doSubMags, 0, 0) + node T_542 = mux(T_539, UInt<22>("h3fffff"), UInt<22>("h0")) + node T_543 = cat(T_538, T_542) + node T_544 = mux(T_537, T_543, T_535) + node T_545 = bits(estNormPos_dist, 5, 5) + node T_546 = bits(sigSum, 33, 1) + node T_547 = bits(doSubMags, 0, 0) + node T_550 = mux(T_547, UInt<54>("h3fffffffffffff"), UInt<54>("h0")) + node T_551 = cat(T_546, T_550) + node T_552 = mux(T_545, T_526, T_551) + node notCDom_pos_firstNormAbsSigSum = mux(T_536, T_544, T_552) + node T_553 = bits(complSigSum, 107, 44) + node T_554 = bits(firstReduceComplSigSum, 0, 0) + node T_555 = cat(T_553, T_554) + node T_556 = bits(complSigSum, 97, 1) + node T_557 = bits(estNormPos_dist, 4, 4) + node T_558 = bits(complSigSum, 2, 1) + node T_559 = shl(T_558, 86) + node T_560 = mux(T_557, T_555, T_559) + node T_561 = bits(complSigSum, 98, 12) + node T_562 = bits(complSigSum, 11, 1) + node T_564 = neq(T_562, UInt<1>("h0")) + node T_565 = cat(T_561, T_564) + node T_566 = bits(estNormPos_dist, 6, 6) + node T_567 = bits(estNormPos_dist, 5, 5) + node T_568 = bits(complSigSum, 66, 1) + node T_569 = shl(T_568, 22) + node T_570 = mux(T_567, T_569, T_565) + node T_571 = bits(estNormPos_dist, 5, 5) + node T_572 = bits(complSigSum, 34, 1) + node T_573 = shl(T_572, 54) + node T_574 = mux(T_571, T_560, T_573) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_566, T_570, T_574) + node notCDom_signSigSum = bits(sigSum, 109, 109) + node T_576 = eq(isZeroC, UInt<1>("h0")) + node T_577 = and(doSubMags, T_576) + node doNegSignSum = mux(io.fromPreMul.isCDominant, T_577, notCDom_signSigSum) + node T_578 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_578) + node T_579 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_580 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_579, T_580) + node T_582 = eq(io.fromPreMul.isCDominant, UInt<1>("h0")) + node T_584 = eq(notCDom_signSigSum, UInt<1>("h0")) + node T_585 = and(T_582, T_584) + node doIncrSig = and(T_585, doSubMags) + node estNormDist_5 = bits(estNormDist, 4, 0) + node normTo2ShiftDist = not(estNormDist_5) + node T_587 = dshr(asSInt(UInt<33>("h100000000")), normTo2ShiftDist) + node T_588 = bits(T_587, 31, 1) + node T_589 = bits(T_588, 15, 0) + node T_592 = shl(UInt<8>("hff"), 8) + node T_593 = xor(UInt<16>("hffff"), T_592) + node T_594 = shr(T_589, 8) + node T_595 = and(T_594, T_593) + node T_596 = bits(T_589, 7, 0) + node T_597 = shl(T_596, 8) + node T_598 = not(T_593) + node T_599 = and(T_597, T_598) + node T_600 = or(T_595, T_599) + node T_601 = bits(T_593, 11, 0) + node T_602 = shl(T_601, 4) + node T_603 = xor(T_593, T_602) + node T_604 = shr(T_600, 4) + node T_605 = and(T_604, T_603) + node T_606 = bits(T_600, 11, 0) + node T_607 = shl(T_606, 4) + node T_608 = not(T_603) + node T_609 = and(T_607, T_608) + node T_610 = or(T_605, T_609) + node T_611 = bits(T_603, 13, 0) + node T_612 = shl(T_611, 2) + node T_613 = xor(T_603, T_612) + node T_614 = shr(T_610, 2) + node T_615 = and(T_614, T_613) + node T_616 = bits(T_610, 13, 0) + node T_617 = shl(T_616, 2) + node T_618 = not(T_613) + node T_619 = and(T_617, T_618) + node T_620 = or(T_615, T_619) + node T_621 = bits(T_613, 14, 0) + node T_622 = shl(T_621, 1) + node T_623 = xor(T_613, T_622) + node T_624 = shr(T_620, 1) + node T_625 = and(T_624, T_623) + node T_626 = bits(T_620, 14, 0) + node T_627 = shl(T_626, 1) + node T_628 = not(T_623) + node T_629 = and(T_627, T_628) + node T_630 = or(T_625, T_629) + node T_631 = bits(T_588, 30, 16) + node T_632 = bits(T_631, 7, 0) + node T_635 = shl(UInt<4>("hf"), 4) + node T_636 = xor(UInt<8>("hff"), T_635) + node T_637 = shr(T_632, 4) + node T_638 = and(T_637, T_636) + node T_639 = bits(T_632, 3, 0) + node T_640 = shl(T_639, 4) + node T_641 = not(T_636) + node T_642 = and(T_640, T_641) + node T_643 = or(T_638, T_642) + node T_644 = bits(T_636, 5, 0) + node T_645 = shl(T_644, 2) + node T_646 = xor(T_636, T_645) + node T_647 = shr(T_643, 2) + node T_648 = and(T_647, T_646) + node T_649 = bits(T_643, 5, 0) + node T_650 = shl(T_649, 2) + node T_651 = not(T_646) + node T_652 = and(T_650, T_651) + node T_653 = or(T_648, T_652) + node T_654 = bits(T_646, 6, 0) + node T_655 = shl(T_654, 1) + node T_656 = xor(T_646, T_655) + node T_657 = shr(T_653, 1) + node T_658 = and(T_657, T_656) + node T_659 = bits(T_653, 6, 0) + node T_660 = shl(T_659, 1) + node T_661 = not(T_656) + node T_662 = and(T_660, T_661) + node T_663 = or(T_658, T_662) + node T_664 = bits(T_631, 14, 8) + node T_665 = bits(T_664, 3, 0) + node T_666 = bits(T_665, 1, 0) + node T_667 = bits(T_666, 0, 0) + node T_668 = bits(T_666, 1, 1) + node T_669 = cat(T_667, T_668) + node T_670 = bits(T_665, 3, 2) + node T_671 = bits(T_670, 0, 0) + node T_672 = bits(T_670, 1, 1) + node T_673 = cat(T_671, T_672) + node T_674 = cat(T_669, T_673) + node T_675 = bits(T_664, 6, 4) + node T_676 = bits(T_675, 1, 0) + node T_677 = bits(T_676, 0, 0) + node T_678 = bits(T_676, 1, 1) + node T_679 = cat(T_677, T_678) + node T_680 = bits(T_675, 2, 2) + node T_681 = cat(T_679, T_680) + node T_682 = cat(T_674, T_681) + node T_683 = cat(T_663, T_682) + node T_684 = cat(T_630, T_683) + node absSigSumExtraMask = cat(T_684, UInt<1>("h1")) + node T_686 = bits(cFirstNormAbsSigSum, 87, 1) + node T_687 = dshr(T_686, normTo2ShiftDist) + node T_688 = bits(cFirstNormAbsSigSum, 31, 0) + node T_689 = not(T_688) + node T_690 = and(T_689, absSigSumExtraMask) + node T_692 = eq(T_690, UInt<1>("h0")) + node T_693 = bits(cFirstNormAbsSigSum, 31, 0) + node T_694 = and(T_693, absSigSumExtraMask) + node T_696 = neq(T_694, UInt<1>("h0")) + node T_697 = mux(doIncrSig, T_692, T_696) + node T_698 = cat(T_687, T_697) + node sigX3 = bits(T_698, 56, 0) + node T_699 = bits(sigX3, 56, 55) + node sigX3Shift1 = eq(T_699, UInt<1>("h0")) + node T_701 = sub(io.fromPreMul.sExpSum, estNormDist) + node sExpX3 = tail(T_701, 1) + node T_702 = bits(sigX3, 56, 54) + node isZeroY = eq(T_702, UInt<1>("h0")) + node T_704 = xor(io.fromPreMul.signProd, doNegSignSum) + node signY = mux(isZeroY, signZeroNotEqOpSigns, T_704) + node sExpX3_13 = bits(sExpX3, 12, 0) + node T_705 = bits(sExpX3, 13, 13) + node T_706 = bits(T_705, 0, 0) + node T_709 = mux(T_706, UInt<56>("hffffffffffffff"), UInt<56>("h0")) + node T_710 = not(sExpX3_13) + node T_711 = bits(T_710, 12, 12) + node T_712 = bits(T_710, 11, 0) + node T_713 = bits(T_712, 11, 11) + node T_714 = bits(T_712, 10, 0) + node T_715 = bits(T_714, 10, 10) + node T_716 = bits(T_714, 9, 0) + node T_717 = bits(T_716, 9, 9) + node T_718 = bits(T_716, 8, 0) + node T_720 = bits(T_718, 8, 8) + node T_721 = bits(T_718, 7, 0) + node T_723 = bits(T_721, 7, 7) + node T_724 = bits(T_721, 6, 0) + node T_726 = bits(T_724, 6, 6) + node T_727 = bits(T_724, 5, 0) + node T_730 = dshr(asSInt(UInt<65>("h10000000000000000")), T_727) + node T_731 = bits(T_730, 63, 14) + node T_732 = bits(T_731, 31, 0) + node T_735 = shl(UInt<16>("hffff"), 16) + node T_736 = xor(UInt<32>("hffffffff"), T_735) + node T_737 = shr(T_732, 16) + node T_738 = and(T_737, T_736) + node T_739 = bits(T_732, 15, 0) + node T_740 = shl(T_739, 16) + node T_741 = not(T_736) + node T_742 = and(T_740, T_741) + node T_743 = or(T_738, T_742) + node T_744 = bits(T_736, 23, 0) + node T_745 = shl(T_744, 8) + node T_746 = xor(T_736, T_745) + node T_747 = shr(T_743, 8) + node T_748 = and(T_747, T_746) + node T_749 = bits(T_743, 23, 0) + node T_750 = shl(T_749, 8) + node T_751 = not(T_746) + node T_752 = and(T_750, T_751) + node T_753 = or(T_748, T_752) + node T_754 = bits(T_746, 27, 0) + node T_755 = shl(T_754, 4) + node T_756 = xor(T_746, T_755) + node T_757 = shr(T_753, 4) + node T_758 = and(T_757, T_756) + node T_759 = bits(T_753, 27, 0) + node T_760 = shl(T_759, 4) + node T_761 = not(T_756) + node T_762 = and(T_760, T_761) + node T_763 = or(T_758, T_762) + node T_764 = bits(T_756, 29, 0) + node T_765 = shl(T_764, 2) + node T_766 = xor(T_756, T_765) + node T_767 = shr(T_763, 2) + node T_768 = and(T_767, T_766) + node T_769 = bits(T_763, 29, 0) + node T_770 = shl(T_769, 2) + node T_771 = not(T_766) + node T_772 = and(T_770, T_771) + node T_773 = or(T_768, T_772) + node T_774 = bits(T_766, 30, 0) + node T_775 = shl(T_774, 1) + node T_776 = xor(T_766, T_775) + node T_777 = shr(T_773, 1) + node T_778 = and(T_777, T_776) + node T_779 = bits(T_773, 30, 0) + node T_780 = shl(T_779, 1) + node T_781 = not(T_776) + node T_782 = and(T_780, T_781) + node T_783 = or(T_778, T_782) + node T_784 = bits(T_731, 49, 32) + node T_785 = bits(T_784, 15, 0) + node T_788 = shl(UInt<8>("hff"), 8) + node T_789 = xor(UInt<16>("hffff"), T_788) + node T_790 = shr(T_785, 8) + node T_791 = and(T_790, T_789) + node T_792 = bits(T_785, 7, 0) + node T_793 = shl(T_792, 8) + node T_794 = not(T_789) + node T_795 = and(T_793, T_794) + node T_796 = or(T_791, T_795) + node T_797 = bits(T_789, 11, 0) + node T_798 = shl(T_797, 4) + node T_799 = xor(T_789, T_798) + node T_800 = shr(T_796, 4) + node T_801 = and(T_800, T_799) + node T_802 = bits(T_796, 11, 0) + node T_803 = shl(T_802, 4) + node T_804 = not(T_799) + node T_805 = and(T_803, T_804) + node T_806 = or(T_801, T_805) + node T_807 = bits(T_799, 13, 0) + node T_808 = shl(T_807, 2) + node T_809 = xor(T_799, T_808) + node T_810 = shr(T_806, 2) + node T_811 = and(T_810, T_809) + node T_812 = bits(T_806, 13, 0) + node T_813 = shl(T_812, 2) + node T_814 = not(T_809) + node T_815 = and(T_813, T_814) + node T_816 = or(T_811, T_815) + node T_817 = bits(T_809, 14, 0) + node T_818 = shl(T_817, 1) + node T_819 = xor(T_809, T_818) + node T_820 = shr(T_816, 1) + node T_821 = and(T_820, T_819) + node T_822 = bits(T_816, 14, 0) + node T_823 = shl(T_822, 1) + node T_824 = not(T_819) + node T_825 = and(T_823, T_824) + node T_826 = or(T_821, T_825) + node T_827 = bits(T_784, 17, 16) + node T_828 = bits(T_827, 0, 0) + node T_829 = bits(T_827, 1, 1) + node T_830 = cat(T_828, T_829) + node T_831 = cat(T_826, T_830) + node T_832 = cat(T_783, T_831) + node T_833 = not(T_832) + node T_834 = mux(T_726, UInt<1>("h0"), T_833) + node T_835 = not(T_834) + node T_836 = not(T_835) + node T_837 = mux(T_723, UInt<1>("h0"), T_836) + node T_838 = not(T_837) + node T_839 = not(T_838) + node T_840 = mux(T_720, UInt<1>("h0"), T_839) + node T_841 = not(T_840) + node T_842 = not(T_841) + node T_843 = mux(T_717, UInt<1>("h0"), T_842) + node T_844 = not(T_843) + node T_846 = cat(T_844, UInt<4>("hf")) + node T_847 = bits(T_716, 9, 9) + node T_848 = bits(T_716, 8, 0) + node T_849 = bits(T_848, 8, 8) + node T_850 = bits(T_848, 7, 0) + node T_851 = bits(T_850, 7, 7) + node T_852 = bits(T_850, 6, 0) + node T_853 = bits(T_852, 6, 6) + node T_854 = bits(T_852, 5, 0) + node T_856 = dshr(asSInt(UInt<65>("h10000000000000000")), T_854) + node T_857 = bits(T_856, 3, 0) + node T_858 = bits(T_857, 1, 0) + node T_859 = bits(T_858, 0, 0) + node T_860 = bits(T_858, 1, 1) + node T_861 = cat(T_859, T_860) + node T_862 = bits(T_857, 3, 2) + node T_863 = bits(T_862, 0, 0) + node T_864 = bits(T_862, 1, 1) + node T_865 = cat(T_863, T_864) + node T_866 = cat(T_861, T_865) + node T_868 = mux(T_853, T_866, UInt<1>("h0")) + node T_870 = mux(T_851, T_868, UInt<1>("h0")) + node T_872 = mux(T_849, T_870, UInt<1>("h0")) + node T_874 = mux(T_847, T_872, UInt<1>("h0")) + node T_875 = mux(T_715, T_846, T_874) + node T_877 = mux(T_713, T_875, UInt<1>("h0")) + node T_879 = mux(T_711, T_877, UInt<1>("h0")) + node T_880 = bits(sigX3, 55, 55) + node T_881 = or(T_879, T_880) + node T_883 = cat(T_881, UInt<2>("h3")) + node roundMask = or(T_709, T_883) + node T_884 = shr(roundMask, 1) + node T_885 = not(T_884) + node roundPosMask = and(T_885, roundMask) + node T_886 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_886, UInt<1>("h0")) + node T_888 = shr(roundMask, 1) + node T_889 = and(sigX3, T_888) + node anyRoundExtra = neq(T_889, UInt<1>("h0")) + node T_891 = not(sigX3) + node T_892 = shr(roundMask, 1) + node T_893 = and(T_891, T_892) + node allRoundExtra = eq(T_893, UInt<1>("h0")) + node anyRound = or(roundPosBit, anyRoundExtra) + node allRound = and(roundPosBit, allRoundExtra) + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) + node T_896 = eq(doIncrSig, UInt<1>("h0")) + node T_897 = and(T_896, roundingMode_nearest_even) + node T_898 = and(T_897, roundPosBit) + node T_899 = and(T_898, anyRoundExtra) + node T_901 = eq(doIncrSig, UInt<1>("h0")) + node T_902 = and(T_901, roundDirectUp) + node T_903 = and(T_902, anyRound) + node T_904 = or(T_899, T_903) + node T_905 = and(doIncrSig, allRound) + node T_906 = or(T_904, T_905) + node T_907 = and(doIncrSig, roundingMode_nearest_even) + node T_908 = and(T_907, roundPosBit) + node T_909 = or(T_906, T_908) + node T_910 = and(doIncrSig, roundDirectUp) + node T_912 = and(T_910, UInt<1>("h1")) + node roundUp = or(T_909, T_912) + node T_914 = eq(roundPosBit, UInt<1>("h0")) + node T_915 = and(roundingMode_nearest_even, T_914) + node T_916 = and(T_915, allRoundExtra) + node T_917 = and(roundingMode_nearest_even, roundPosBit) + node T_919 = eq(anyRoundExtra, UInt<1>("h0")) + node T_920 = and(T_917, T_919) + node roundEven = mux(doIncrSig, T_916, T_920) + node T_922 = eq(allRound, UInt<1>("h0")) + node roundInexact = mux(doIncrSig, T_922, anyRound) + node T_923 = or(sigX3, roundMask) + node T_924 = shr(T_923, 2) + node T_926 = add(T_924, UInt<1>("h1")) + node T_927 = tail(T_926, 1) + node roundUp_sigY3 = bits(T_927, 54, 0) + node T_929 = eq(roundUp, UInt<1>("h0")) + node T_931 = eq(roundEven, UInt<1>("h0")) + node T_932 = and(T_929, T_931) + node T_933 = not(roundMask) + node T_934 = and(sigX3, T_933) + node T_935 = shr(T_934, 2) + node T_937 = mux(T_932, T_935, UInt<1>("h0")) + node T_939 = mux(roundUp, roundUp_sigY3, UInt<1>("h0")) + node T_940 = or(T_937, T_939) + node T_941 = shr(roundMask, 1) + node T_942 = not(T_941) + node T_943 = and(roundUp_sigY3, T_942) + node T_945 = mux(roundEven, T_943, UInt<1>("h0")) + node sigY3 = or(T_940, T_945) + node T_946 = bits(sigY3, 54, 54) + node T_948 = add(sExpX3, UInt<1>("h1")) + node T_949 = tail(T_948, 1) + node T_951 = mux(T_946, T_949, UInt<1>("h0")) + node T_952 = bits(sigY3, 53, 53) + node T_954 = mux(T_952, sExpX3, UInt<1>("h0")) + node T_955 = or(T_951, T_954) + node T_956 = bits(sigY3, 54, 53) + node T_958 = eq(T_956, UInt<1>("h0")) + node T_960 = sub(sExpX3, UInt<1>("h1")) + node T_961 = tail(T_960, 1) + node T_963 = mux(T_958, T_961, UInt<1>("h0")) + node sExpY = or(T_955, T_963) + node expY = bits(sExpY, 11, 0) + node T_964 = bits(sigY3, 51, 0) + node T_965 = bits(sigY3, 52, 1) + node fractY = mux(sigX3Shift1, T_964, T_965) + node T_966 = bits(sExpY, 12, 10) + node overflowY = eq(T_966, UInt<2>("h3")) + node T_969 = eq(isZeroY, UInt<1>("h0")) + node T_970 = bits(sExpY, 12, 12) + node T_971 = bits(sExpY, 11, 0) + node T_973 = lt(T_971, UInt<10>("h3ce")) + node T_974 = or(T_970, T_973) + node totalUnderflowY = and(T_969, T_974) + node T_975 = bits(sExpX3, 13, 13) + node T_978 = mux(sigX3Shift1, UInt<11>("h402"), UInt<11>("h401")) + node T_979 = leq(sExpX3_13, T_978) + node T_980 = or(T_975, T_979) + node underflowY = and(roundInexact, T_980) + node T_981 = and(roundingMode_min, signY) + node T_983 = eq(signY, UInt<1>("h0")) + node T_984 = and(roundingMode_max, T_983) + node roundMagUp = or(T_981, T_984) + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) + node mulSpecial = or(isSpecialA, isSpecialB) + node addSpecial = or(mulSpecial, isSpecialC) + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) + node T_986 = eq(addSpecial, UInt<1>("h0")) + node T_988 = eq(notSpecial_addZeros, UInt<1>("h0")) + node commonCase = and(T_986, T_988) + node T_989 = and(isInfA, isZeroB) + node T_990 = and(isZeroA, isInfB) + node T_991 = or(T_989, T_990) + node T_993 = eq(isNaNA, UInt<1>("h0")) + node T_995 = eq(isNaNB, UInt<1>("h0")) + node T_996 = and(T_993, T_995) + node T_997 = or(isInfA, isInfB) + node T_998 = and(T_996, T_997) + node T_999 = and(T_998, isInfC) + node T_1000 = and(T_999, doSubMags) + node notSigNaN_invalid = or(T_991, T_1000) + node T_1001 = or(isSigNaNA, isSigNaNB) + node T_1002 = or(T_1001, isSigNaNC) + node invalid = or(T_1002, notSigNaN_invalid) + node overflow = and(commonCase, overflowY) + node underflow = and(commonCase, underflowY) + node T_1003 = and(commonCase, roundInexact) + node inexact = or(overflow, T_1003) + node T_1004 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_1004, totalUnderflowY) + node T_1005 = and(commonCase, totalUnderflowY) + node pegMinFiniteMagOut = and(T_1005, roundMagUp) + node T_1007 = eq(overflowY_roundMagUp, UInt<1>("h0")) + node pegMaxFiniteMagOut = and(overflow, T_1007) + node T_1008 = or(isInfA, isInfB) + node T_1009 = or(T_1008, isInfC) + node T_1010 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_1009, T_1010) + node T_1011 = or(isNaNA, isNaNB) + node T_1012 = or(T_1011, isNaNC) + node isNaNOut = or(T_1012, notSigNaN_invalid) + node T_1014 = eq(doSubMags, UInt<1>("h0")) + node T_1015 = and(T_1014, io.fromPreMul.opSignC) + node T_1017 = eq(isSpecialC, UInt<1>("h0")) + node T_1018 = and(mulSpecial, T_1017) + node T_1019 = and(T_1018, io.fromPreMul.signProd) + node T_1020 = or(T_1015, T_1019) + node T_1022 = eq(mulSpecial, UInt<1>("h0")) + node T_1023 = and(T_1022, isSpecialC) + node T_1024 = and(T_1023, io.fromPreMul.opSignC) + node T_1025 = or(T_1020, T_1024) + node T_1027 = eq(mulSpecial, UInt<1>("h0")) + node T_1028 = and(T_1027, notSpecial_addZeros) + node T_1029 = and(T_1028, doSubMags) + node T_1030 = and(T_1029, signZeroNotEqOpSigns) + node uncommonCaseSignOut = or(T_1025, T_1030) + node T_1032 = eq(isNaNOut, UInt<1>("h0")) + node T_1033 = and(T_1032, uncommonCaseSignOut) + node T_1034 = and(commonCase, signY) + node signOut = or(T_1033, T_1034) + node T_1037 = mux(notSpecial_isZeroOut, UInt<12>("he00"), UInt<12>("h0")) + node T_1038 = not(T_1037) + node T_1039 = and(expY, T_1038) + node T_1041 = not(UInt<12>("h3ce")) + node T_1043 = mux(pegMinFiniteMagOut, T_1041, UInt<12>("h0")) + node T_1044 = not(T_1043) + node T_1045 = and(T_1039, T_1044) + node T_1048 = mux(pegMaxFiniteMagOut, UInt<12>("h400"), UInt<12>("h0")) + node T_1049 = not(T_1048) + node T_1050 = and(T_1045, T_1049) + node T_1053 = mux(notNaN_isInfOut, UInt<10>("h200"), UInt<12>("h0")) + node T_1054 = not(T_1053) + node T_1055 = and(T_1050, T_1054) + node T_1058 = mux(pegMinFiniteMagOut, UInt<10>("h3ce"), UInt<12>("h0")) + node T_1059 = or(T_1055, T_1058) + node T_1062 = mux(pegMaxFiniteMagOut, UInt<12>("hbff"), UInt<12>("h0")) + node T_1063 = or(T_1059, T_1062) + node T_1066 = mux(notNaN_isInfOut, UInt<12>("hc00"), UInt<12>("h0")) + node T_1067 = or(T_1063, T_1066) + node T_1070 = mux(isNaNOut, UInt<12>("he00"), UInt<12>("h0")) + node expOut = or(T_1067, T_1070) + node T_1071 = and(totalUnderflowY, roundMagUp) + node T_1072 = or(T_1071, isNaNOut) + node T_1074 = shl(UInt<1>("h1"), 51) + node T_1076 = mux(isNaNOut, T_1074, UInt<1>("h0")) + node T_1077 = mux(T_1072, T_1076, fractY) + node T_1078 = bits(pegMaxFiniteMagOut, 0, 0) + node T_1081 = mux(T_1078, UInt<52>("hfffffffffffff"), UInt<52>("h0")) + node fractOut = or(T_1077, T_1081) + node T_1082 = cat(signOut, expOut) + node T_1083 = cat(T_1082, fractOut) + io.out <= T_1083 + node T_1085 = cat(underflow, inexact) + node T_1086 = cat(invalid, UInt<1>("h0")) + node T_1087 = cat(T_1086, overflow) + node T_1088 = cat(T_1087, T_1085) + io.exceptionFlags <= T_1088 + + module MulAddRecFN_1 : input clk : Clock input reset : UInt<1> - output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - + output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + io is invalid - inst mulAddRecFN_preMul of MulAddRecFN_preMul_1 @[MulAddRecFN.scala 598:15] + inst mulAddRecFN_preMul of MulAddRecFN_preMul_1 mulAddRecFN_preMul.io is invalid mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset - inst mulAddRecFN_postMul of MulAddRecFN_postMul_1 @[MulAddRecFN.scala 600:15] + inst mulAddRecFN_postMul of MulAddRecFN_postMul_1 mulAddRecFN_postMul.io is invalid mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset - mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] - mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] - mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] - mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] - mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] - mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] - node T_7 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] - node T_9 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 20:58] - node T_10 = add(T_7, T_9) @[MulAddRecFN.scala 610:71] - node T_11 = tail(T_10, 1) @[MulAddRecFN.scala 610:71] - mulAddRecFN_postMul.io.mulAddResult <= T_11 @[MulAddRecFN.scala 609:41] - io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] - io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] - - module FPUFMAPipe_1 : + mulAddRecFN_preMul.io.op <= io.op + mulAddRecFN_preMul.io.a <= io.a + mulAddRecFN_preMul.io.b <= io.b + mulAddRecFN_preMul.io.c <= io.c + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul + node T_7 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) + node T_9 = cat(UInt<1>("h0"), mulAddRecFN_preMul.io.mulAddC) + node T_10 = add(T_7, T_9) + node T_11 = tail(T_10, 1) + mulAddRecFN_postMul.io.mulAddResult <= T_11 + io.out <= mulAddRecFN_postMul.io.out + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags + + module FPUFMAPipe_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - + output io : { flip in : { valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} + io is invalid - node one = shl(UInt<1>("h01"), 63) @[fpu.scala 462:21] - node T_131 = bits(io.in.bits.in1, 64, 64) @[fpu.scala 463:29] - node T_132 = bits(io.in.bits.in2, 64, 64) @[fpu.scala 463:53] - node T_133 = xor(T_131, T_132) @[fpu.scala 463:37] - node zero = shl(T_133, 64) @[fpu.scala 463:62] - reg valid : UInt<1>, clk + node one = shl(UInt<1>("h1"), 63) + node T_131 = bits(io.in.bits.in1, 64, 64) + node T_132 = bits(io.in.bits.in2, 64, 64) + node T_133 = xor(T_131, T_132) + node zero = shl(T_133, 64) + reg valid : UInt<1>, clk with : + reset => (UInt<1>("h0"), valid) valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk - when io.in.valid : @[fpu.scala 467:22] - in <- io.in.bits @[fpu.scala 468:8] - node T_179 = bits(io.in.bits.cmd, 1, 1) @[fpu.scala 471:33] - node T_180 = or(io.in.bits.ren3, io.in.bits.swap23) @[fpu.scala 471:48] - node T_181 = and(T_179, T_180) @[fpu.scala 471:37] - node T_182 = bits(io.in.bits.cmd, 0, 0) @[fpu.scala 471:78] - node T_183 = cat(T_181, T_182) @[Cat.scala 20:58] - in.cmd <= T_183 @[fpu.scala 471:12] - when io.in.bits.swap23 : @[fpu.scala 472:23] - in.in2 <= one @[fpu.scala 472:32] - skip @[fpu.scala 472:23] - node T_184 = or(io.in.bits.ren3, io.in.bits.swap23) @[fpu.scala 473:21] - node T_186 = eq(T_184, UInt<1>("h00")) @[Conditional.scala 18:11] - when T_186 : @[Conditional.scala 18:15] - in.in3 <= zero @[fpu.scala 473:45] - skip @[Conditional.scala 18:15] - skip @[fpu.scala 467:22] - inst fma of MulAddRecFN_1 @[fpu.scala 476:19] + reg in : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk with : + reset => (UInt<1>("h0"), in) + when io.in.valid : + in <- io.in.bits + node T_179 = bits(io.in.bits.cmd, 1, 1) + node T_180 = or(io.in.bits.ren3, io.in.bits.swap23) + node T_181 = and(T_179, T_180) + node T_182 = bits(io.in.bits.cmd, 0, 0) + node T_183 = cat(T_181, T_182) + in.cmd <= T_183 + when io.in.bits.swap23 : + in.in2 <= one + node T_184 = or(io.in.bits.ren3, io.in.bits.swap23) + node T_186 = eq(T_184, UInt<1>("h0")) + when T_186 : + in.in3 <= zero + inst fma of MulAddRecFN_1 fma.io is invalid fma.clk <= clk fma.reset <= reset - fma.io.op <= in.cmd @[fpu.scala 477:13] - fma.io.roundingMode <= in.rm @[fpu.scala 478:23] - fma.io.a <= in.in1 @[fpu.scala 479:12] - fma.io.b <= in.in2 @[fpu.scala 480:12] - fma.io.c <= in.in3 @[fpu.scala 481:12] - wire res : {data : UInt<65>, exc : UInt<5>} @[fpu.scala 483:17] - res is invalid @[fpu.scala 483:17] - node T_193 = cat(UInt<1>("h00"), fma.io.out) @[Cat.scala 20:58] - res.data <= T_193 @[fpu.scala 484:12] - res.exc <= fma.io.exceptionFlags @[fpu.scala 485:11] - reg T_196 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + fma.io.op <= in.cmd + fma.io.roundingMode <= in.rm + fma.io.a <= in.in1 + fma.io.b <= in.in2 + fma.io.c <= in.in3 + wire res : { data : UInt<65>, exc : UInt<5>} + res is invalid + node T_193 = cat(UInt<1>("h0"), fma.io.out) + res.data <= T_193 + res.exc <= fma.io.exceptionFlags + reg T_196 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_196 <= valid - reg T_197 : {data : UInt<65>, exc : UInt<5>}, clk - when valid : @[Reg.scala 29:19] - T_197 <- res @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg T_202 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_197 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_197) + when valid : + T_197 <- res + reg T_202 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_202 <= T_196 - reg T_203 : {data : UInt<65>, exc : UInt<5>}, clk - when T_196 : @[Reg.scala 29:19] - T_203 <- T_197 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg T_208 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_203 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_203) + when T_196 : + T_203 <- T_197 + reg T_208 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) T_208 <= T_202 - reg T_209 : {data : UInt<65>, exc : UInt<5>}, clk - when T_202 : @[Reg.scala 29:19] - T_209 <- T_203 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - wire T_220 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 39:21] - T_220 is invalid @[Valid.scala 39:21] - T_220.valid <= T_208 @[Valid.scala 40:17] - T_220.bits <- T_209 @[Valid.scala 41:16] - io.out <- T_220 @[fpu.scala 486:10] - - module DivSqrtRecF64_mulAddZ31 : + reg T_209 : { data : UInt<65>, exc : UInt<5>}, clk with : + reset => (UInt<1>("h0"), T_209) + when T_202 : + T_209 <- T_203 + wire T_220 : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} + T_220 is invalid + T_220.valid <= T_208 + T_220.bits <- T_209 + io.out <- T_220 + + module DivSqrtRecF64_mulAddZ31 : input clk : Clock input reset : UInt<1> - output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} - + output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} + io is invalid - reg valid_PA : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PA : UInt<1>, clk - reg sign_PA : UInt<1>, clk - reg specialCodeB_PA : UInt<3>, clk - reg fractB_51_PA : UInt<1>, clk - reg roundingMode_PA : UInt<2>, clk - reg specialCodeA_PA : UInt<3>, clk - reg fractA_51_PA : UInt<1>, clk - reg exp_PA : UInt<14>, clk - reg fractB_other_PA : UInt<51>, clk - reg fractA_other_PA : UInt<51>, clk - reg valid_PB : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PB : UInt<1>, clk - reg sign_PB : UInt<1>, clk - reg specialCodeA_PB : UInt<3>, clk - reg fractA_51_PB : UInt<1>, clk - reg specialCodeB_PB : UInt<3>, clk - reg fractB_51_PB : UInt<1>, clk - reg roundingMode_PB : UInt<2>, clk - reg exp_PB : UInt<14>, clk - reg fractA_0_PB : UInt<1>, clk - reg fractB_other_PB : UInt<51>, clk - reg valid_PC : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg sqrtOp_PC : UInt<1>, clk - reg sign_PC : UInt<1>, clk - reg specialCodeA_PC : UInt<3>, clk - reg fractA_51_PC : UInt<1>, clk - reg specialCodeB_PC : UInt<3>, clk - reg fractB_51_PC : UInt<1>, clk - reg roundingMode_PC : UInt<2>, clk - reg exp_PC : UInt<14>, clk - reg fractA_0_PC : UInt<1>, clk - reg fractB_other_PC : UInt<51>, clk - reg cycleNum_A : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg cycleNum_B : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg cycleNum_C : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg cycleNum_E : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg fractR0_A : UInt<9>, clk - reg hiSqrR0_A_sqrt : UInt<10>, clk - reg partNegSigma0_A : UInt<21>, clk - reg nextMulAdd9A_A : UInt<9>, clk - reg nextMulAdd9B_A : UInt<9>, clk - reg ER1_B_sqrt : UInt<17>, clk - reg ESqrR1_B_sqrt : UInt<32>, clk - reg sigX1_B : UInt<58>, clk - reg sqrSigma1_C : UInt<33>, clk - reg sigXN_C : UInt<58>, clk - reg u_C_sqrt : UInt<31>, clk - reg E_E_div : UInt<1>, clk - reg sigT_E : UInt<53>, clk - reg extraT_E : UInt<1>, clk - reg isNegRemT_E : UInt<1>, clk - reg trueEqX_E1 : UInt<1>, clk - wire ready_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 143:24] - ready_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 143:24] - wire ready_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 144:24] - ready_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 144:24] - wire ready_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 145:24] - ready_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 145:24] - wire leaving_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 146:26] - leaving_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 146:26] - wire leaving_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 147:26] - leaving_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 147:26] - wire leaving_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 148:26] - leaving_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 148:26] - wire cyc_B10_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 150:28] - cyc_B10_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 150:28] - wire cyc_B9_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 151:28] - cyc_B9_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 151:28] - wire cyc_B8_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 152:28] - cyc_B8_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 152:28] - wire cyc_B7_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 153:28] - cyc_B7_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 153:28] - wire cyc_B6 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 155:22] - cyc_B6 is invalid @[DivSqrtRecF64_mulAddZ31.scala 155:22] - wire cyc_B5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 156:22] - cyc_B5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 156:22] - wire cyc_B4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 157:22] - cyc_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 157:22] - wire cyc_B3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 158:22] - cyc_B3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 158:22] - wire cyc_B2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 159:22] - cyc_B2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 159:22] - wire cyc_B1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 160:22] - cyc_B1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 160:22] - wire cyc_B6_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 162:26] - cyc_B6_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 162:26] - wire cyc_B5_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 163:26] - cyc_B5_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 163:26] - wire cyc_B4_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 164:26] - cyc_B4_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 164:26] - wire cyc_B3_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 165:26] - cyc_B3_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 165:26] - wire cyc_B2_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 166:26] - cyc_B2_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 166:26] - wire cyc_B1_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 167:26] - cyc_B1_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 167:26] - wire cyc_B6_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 169:27] - cyc_B6_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 169:27] - wire cyc_B5_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 170:27] - cyc_B5_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 170:27] - wire cyc_B4_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 171:27] - cyc_B4_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 171:27] - wire cyc_B3_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 172:27] - cyc_B3_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 172:27] - wire cyc_B2_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 173:27] - cyc_B2_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 173:27] - wire cyc_B1_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 174:27] - cyc_B1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 174:27] - wire cyc_C5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 176:22] - cyc_C5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 176:22] - wire cyc_C4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 177:22] - cyc_C4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 177:22] - wire valid_normalCase_leaving_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 178:22] - valid_normalCase_leaving_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 178:22] - wire cyc_C2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 179:22] - cyc_C2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 179:22] - wire cyc_C1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 180:22] - cyc_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 180:22] - wire cyc_E4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 182:22] - cyc_E4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 182:22] - wire cyc_E3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 183:22] - cyc_E3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 183:22] - wire cyc_E2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 184:22] - cyc_E2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 184:22] - wire cyc_E1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 185:22] - cyc_E1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 185:22] - wire zSigma1_B4 : UInt @[DivSqrtRecF64_mulAddZ31.scala 187:34] - zSigma1_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 187:34] - wire sigXNU_B3_CX : UInt @[DivSqrtRecF64_mulAddZ31.scala 188:34] - sigXNU_B3_CX is invalid @[DivSqrtRecF64_mulAddZ31.scala 188:34] - wire zComplSigT_C1_sqrt : UInt @[DivSqrtRecF64_mulAddZ31.scala 189:34] - zComplSigT_C1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 189:34] - wire zComplSigT_C1 : UInt @[DivSqrtRecF64_mulAddZ31.scala 190:34] - zComplSigT_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 190:34] - node T_113 = eq(cyc_B7_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:21] - node T_114 = and(ready_PA, T_113) @[DivSqrtRecF64_mulAddZ31.scala 197:18] - node T_116 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:38] - node T_117 = and(T_114, T_116) @[DivSqrtRecF64_mulAddZ31.scala 197:35] - node T_119 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:55] - node T_120 = and(T_117, T_119) @[DivSqrtRecF64_mulAddZ31.scala 197:52] - node T_122 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:13] - node T_123 = and(T_120, T_122) @[DivSqrtRecF64_mulAddZ31.scala 197:69] - node T_125 = eq(cyc_B3, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:30] - node T_126 = and(T_123, T_125) @[DivSqrtRecF64_mulAddZ31.scala 198:27] - node T_128 = eq(cyc_B2, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:42] - node T_129 = and(T_126, T_128) @[DivSqrtRecF64_mulAddZ31.scala 198:39] - node T_131 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:54] - node T_132 = and(T_129, T_131) @[DivSqrtRecF64_mulAddZ31.scala 198:51] - node T_134 = eq(cyc_C5, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:13] - node T_135 = and(T_132, T_134) @[DivSqrtRecF64_mulAddZ31.scala 198:68] - node T_137 = eq(cyc_C4, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:25] - node T_138 = and(T_135, T_137) @[DivSqrtRecF64_mulAddZ31.scala 199:22] - io.inReady_div <= T_138 @[DivSqrtRecF64_mulAddZ31.scala 195:20] - node T_140 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:21] - node T_141 = and(ready_PA, T_140) @[DivSqrtRecF64_mulAddZ31.scala 201:18] - node T_143 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:38] - node T_144 = and(T_141, T_143) @[DivSqrtRecF64_mulAddZ31.scala 201:35] - node T_146 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:55] - node T_147 = and(T_144, T_146) @[DivSqrtRecF64_mulAddZ31.scala 201:52] - node T_149 = eq(cyc_B2_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:13] - node T_150 = and(T_147, T_149) @[DivSqrtRecF64_mulAddZ31.scala 201:69] - node T_152 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:29] - node T_153 = and(T_150, T_152) @[DivSqrtRecF64_mulAddZ31.scala 202:26] - io.inReady_sqrt <= T_153 @[DivSqrtRecF64_mulAddZ31.scala 200:21] - node T_154 = and(io.inReady_div, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 203:38] - node T_156 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 203:55] - node cyc_S_div = and(T_154, T_156) @[DivSqrtRecF64_mulAddZ31.scala 203:52] - node T_157 = and(io.inReady_sqrt, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 204:38] - node cyc_S_sqrt = and(T_157, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 204:52] - node cyc_S = or(cyc_S_div, cyc_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 205:27] - node signA_S = bits(io.a, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 207:24] - node expA_S = bits(io.a, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 208:24] - node fractA_S = bits(io.a, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 209:24] - node specialCodeA_S = bits(expA_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 210:32] - node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 211:40] - node T_159 = bits(specialCodeA_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 212:39] - node isSpecialA_S = eq(T_159, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 212:46] - node signB_S = bits(io.b, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 214:24] - node expB_S = bits(io.b, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 215:24] - node fractB_S = bits(io.b, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 216:24] - node specialCodeB_S = bits(expB_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 217:32] - node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 218:40] - node T_162 = bits(specialCodeB_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 219:39] - node isSpecialB_S = eq(T_162, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 219:46] - node T_164 = xor(signA_S, signB_S) @[DivSqrtRecF64_mulAddZ31.scala 221:50] - node sign_S = mux(io.sqrtOp, signB_S, T_164) @[DivSqrtRecF64_mulAddZ31.scala 221:21] - node T_166 = eq(isSpecialA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:9] - node T_168 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:27] - node T_169 = and(T_166, T_168) @[DivSqrtRecF64_mulAddZ31.scala 224:24] - node T_171 = eq(isZeroA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:45] - node T_172 = and(T_169, T_171) @[DivSqrtRecF64_mulAddZ31.scala 224:42] - node T_174 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:60] - node normalCase_S_div = and(T_172, T_174) @[DivSqrtRecF64_mulAddZ31.scala 224:57] - node T_176 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:29] - node T_178 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:47] - node T_179 = and(T_176, T_178) @[DivSqrtRecF64_mulAddZ31.scala 225:44] - node T_181 = eq(signB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:62] - node normalCase_S_sqrt = and(T_179, T_181) @[DivSqrtRecF64_mulAddZ31.scala 225:59] - node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 226:27] - node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 228:50] - node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 229:50] - node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 231:36] - node T_183 = eq(ready_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 233:58] - node T_184 = or(valid_PA, T_183) @[DivSqrtRecF64_mulAddZ31.scala 233:55] - node T_185 = and(cyc_S, T_184) @[DivSqrtRecF64_mulAddZ31.scala 233:42] - node entering_PA = or(entering_PA_normalCase, T_185) @[DivSqrtRecF64_mulAddZ31.scala 233:32] - node T_187 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:18] - node T_188 = and(cyc_S, T_187) @[DivSqrtRecF64_mulAddZ31.scala 235:15] - node T_190 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:36] - node T_191 = and(T_188, T_190) @[DivSqrtRecF64_mulAddZ31.scala 235:33] - node T_193 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:29] - node T_195 = eq(ready_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:43] - node T_196 = and(T_193, T_195) @[DivSqrtRecF64_mulAddZ31.scala 236:40] - node T_197 = or(leaving_PB, T_196) @[DivSqrtRecF64_mulAddZ31.scala 236:25] - node entering_PB_S = and(T_191, T_197) @[DivSqrtRecF64_mulAddZ31.scala 235:47] - node T_199 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:18] - node T_200 = and(cyc_S, T_199) @[DivSqrtRecF64_mulAddZ31.scala 238:15] - node T_202 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:36] - node T_203 = and(T_200, T_202) @[DivSqrtRecF64_mulAddZ31.scala 238:33] - node T_205 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:50] - node T_206 = and(T_203, T_205) @[DivSqrtRecF64_mulAddZ31.scala 238:47] - node entering_PC_S = and(T_206, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 238:61] - node T_207 = or(entering_PA, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 240:23] - when T_207 : @[DivSqrtRecF64_mulAddZ31.scala 240:38] - valid_PA <= entering_PA @[DivSqrtRecF64_mulAddZ31.scala 241:18] - skip @[DivSqrtRecF64_mulAddZ31.scala 240:38] - when entering_PA : @[DivSqrtRecF64_mulAddZ31.scala 243:24] - sqrtOp_PA <= io.sqrtOp @[DivSqrtRecF64_mulAddZ31.scala 244:25] - sign_PA <= sign_S @[DivSqrtRecF64_mulAddZ31.scala 245:25] - specialCodeB_PA <= specialCodeB_S @[DivSqrtRecF64_mulAddZ31.scala 246:25] - node T_208 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 247:36] - fractB_51_PA <= T_208 @[DivSqrtRecF64_mulAddZ31.scala 247:25] - roundingMode_PA <= io.roundingMode @[DivSqrtRecF64_mulAddZ31.scala 248:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 243:24] - node T_210 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 250:26] - node T_211 = and(entering_PA, T_210) @[DivSqrtRecF64_mulAddZ31.scala 250:23] - when T_211 : @[DivSqrtRecF64_mulAddZ31.scala 250:39] - specialCodeA_PA <= specialCodeA_S @[DivSqrtRecF64_mulAddZ31.scala 251:25] - node T_212 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 252:36] - fractA_51_PA <= T_212 @[DivSqrtRecF64_mulAddZ31.scala 252:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 250:39] - when entering_PA_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 254:35] - node T_213 = bits(expB_S, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 258:44] - node T_214 = bits(T_213, 0, 0) @[Bitwise.scala 33:15] - node T_217 = mux(T_214, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_218 = bits(expB_S, 10, 0) @[DivSqrtRecF64_mulAddZ31.scala 258:58] - node T_219 = not(T_218) @[DivSqrtRecF64_mulAddZ31.scala 258:51] - node T_220 = cat(T_217, T_219) @[Cat.scala 20:58] - node T_221 = add(expA_S, T_220) @[DivSqrtRecF64_mulAddZ31.scala 258:24] - node T_222 = tail(T_221, 1) @[DivSqrtRecF64_mulAddZ31.scala 258:24] - node T_223 = mux(io.sqrtOp, expB_S, T_222) @[DivSqrtRecF64_mulAddZ31.scala 256:16] - exp_PA <= T_223 @[DivSqrtRecF64_mulAddZ31.scala 255:16] - node T_224 = bits(fractB_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 260:36] - fractB_other_PA <= T_224 @[DivSqrtRecF64_mulAddZ31.scala 260:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 254:35] - when entering_PA_normalCase_div : @[DivSqrtRecF64_mulAddZ31.scala 262:39] - node T_225 = bits(fractA_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 263:36] - fractA_other_PA <= T_225 @[DivSqrtRecF64_mulAddZ31.scala 263:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 262:39] - node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 266:42] - node T_227 = bits(specialCodeA_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 267:41] - node isSpecialA_PA = eq(T_227, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 267:48] - node T_230 = cat(UInt<1>("h01"), fractA_51_PA) @[Cat.scala 20:58] - node sigA_PA = cat(T_230, fractA_other_PA) @[Cat.scala 20:58] - node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 270:42] - node T_232 = bits(specialCodeB_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 271:41] - node isSpecialB_PA = eq(T_232, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 271:48] - node T_235 = cat(UInt<1>("h01"), fractB_51_PA) @[Cat.scala 20:58] - node sigB_PA = cat(T_235, fractB_other_PA) @[Cat.scala 20:58] - node T_237 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:13] - node T_239 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:32] - node T_240 = and(T_237, T_239) @[DivSqrtRecF64_mulAddZ31.scala 276:29] - node T_242 = eq(sign_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:48] - node T_243 = and(T_240, T_242) @[DivSqrtRecF64_mulAddZ31.scala 276:45] - node T_245 = eq(isSpecialA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:13] - node T_247 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:32] - node T_248 = and(T_245, T_247) @[DivSqrtRecF64_mulAddZ31.scala 277:29] - node T_250 = eq(isZeroA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:51] - node T_251 = and(T_248, T_250) @[DivSqrtRecF64_mulAddZ31.scala 277:48] - node T_253 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:67] - node T_254 = and(T_251, T_253) @[DivSqrtRecF64_mulAddZ31.scala 277:64] - node normalCase_PA = mux(sqrtOp_PA, T_243, T_254) @[DivSqrtRecF64_mulAddZ31.scala 275:12] - node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 280:50] - node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) @[DivSqrtRecF64_mulAddZ31.scala 282:12] - node T_255 = and(valid_PA, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 283:28] - leaving_PA <= T_255 @[DivSqrtRecF64_mulAddZ31.scala 283:16] - node T_257 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 284:17] - node T_258 = or(T_257, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 284:28] - ready_PA <= T_258 @[DivSqrtRecF64_mulAddZ31.scala 284:14] - node T_259 = and(valid_PA, normalCase_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:18] - node entering_PB_normalCase = and(T_259, valid_normalCase_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:35] - node entering_PB = or(entering_PB_S, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 288:37] - node T_260 = or(entering_PB, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 290:23] - when T_260 : @[DivSqrtRecF64_mulAddZ31.scala 290:38] - valid_PB <= entering_PB @[DivSqrtRecF64_mulAddZ31.scala 291:18] - skip @[DivSqrtRecF64_mulAddZ31.scala 290:38] - when entering_PB : @[DivSqrtRecF64_mulAddZ31.scala 293:24] - node T_261 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 294:31] - sqrtOp_PB <= T_261 @[DivSqrtRecF64_mulAddZ31.scala 294:25] - node T_262 = mux(valid_PA, sign_PA, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 295:31] - sign_PB <= T_262 @[DivSqrtRecF64_mulAddZ31.scala 295:25] - node T_263 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 296:31] - specialCodeA_PB <= T_263 @[DivSqrtRecF64_mulAddZ31.scala 296:25] - node T_264 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 297:67] - node T_265 = mux(valid_PA, fractA_51_PA, T_264) @[DivSqrtRecF64_mulAddZ31.scala 297:31] - fractA_51_PB <= T_265 @[DivSqrtRecF64_mulAddZ31.scala 297:25] - node T_266 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 298:31] - specialCodeB_PB <= T_266 @[DivSqrtRecF64_mulAddZ31.scala 298:25] - node T_267 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 299:67] - node T_268 = mux(valid_PA, fractB_51_PA, T_267) @[DivSqrtRecF64_mulAddZ31.scala 299:31] - fractB_51_PB <= T_268 @[DivSqrtRecF64_mulAddZ31.scala 299:25] - node T_269 = mux(valid_PA, roundingMode_PA, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 300:31] - roundingMode_PB <= T_269 @[DivSqrtRecF64_mulAddZ31.scala 300:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 293:24] - when entering_PB_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 302:35] - exp_PB <= exp_PA @[DivSqrtRecF64_mulAddZ31.scala 303:25] - node T_270 = bits(fractA_other_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 304:43] - fractA_0_PB <= T_270 @[DivSqrtRecF64_mulAddZ31.scala 304:25] - fractB_other_PB <= fractB_other_PA @[DivSqrtRecF64_mulAddZ31.scala 305:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 302:35] - node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 308:42] - node T_272 = bits(specialCodeA_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 309:41] - node isSpecialA_PB = eq(T_272, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 309:48] - node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 310:42] - node T_275 = bits(specialCodeB_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 311:41] - node isSpecialB_PB = eq(T_275, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 311:48] - node T_278 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:13] - node T_280 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:32] - node T_281 = and(T_278, T_280) @[DivSqrtRecF64_mulAddZ31.scala 314:29] - node T_283 = eq(sign_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:48] - node T_284 = and(T_281, T_283) @[DivSqrtRecF64_mulAddZ31.scala 314:45] - node T_286 = eq(isSpecialA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:13] - node T_288 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:32] - node T_289 = and(T_286, T_288) @[DivSqrtRecF64_mulAddZ31.scala 315:29] - node T_291 = eq(isZeroA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:51] - node T_292 = and(T_289, T_291) @[DivSqrtRecF64_mulAddZ31.scala 315:48] - node T_294 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:67] - node T_295 = and(T_292, T_294) @[DivSqrtRecF64_mulAddZ31.scala 315:64] - node normalCase_PB = mux(sqrtOp_PB, T_284, T_295) @[DivSqrtRecF64_mulAddZ31.scala 313:12] - node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 320:12] - node T_296 = and(valid_PB, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 321:28] - leaving_PB <= T_296 @[DivSqrtRecF64_mulAddZ31.scala 321:16] - node T_298 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 322:17] - node T_299 = or(T_298, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 322:28] - ready_PB <= T_299 @[DivSqrtRecF64_mulAddZ31.scala 322:14] - node T_300 = and(valid_PB, normalCase_PB) @[DivSqrtRecF64_mulAddZ31.scala 325:18] - node entering_PC_normalCase = and(T_300, valid_normalCase_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 325:35] - node entering_PC = or(entering_PC_S, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 326:37] - node T_301 = or(entering_PC, leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 328:23] - when T_301 : @[DivSqrtRecF64_mulAddZ31.scala 328:38] - valid_PC <= entering_PC @[DivSqrtRecF64_mulAddZ31.scala 329:18] - skip @[DivSqrtRecF64_mulAddZ31.scala 328:38] - when entering_PC : @[DivSqrtRecF64_mulAddZ31.scala 331:24] - node T_302 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 332:31] - sqrtOp_PC <= T_302 @[DivSqrtRecF64_mulAddZ31.scala 332:25] - node T_303 = mux(valid_PB, sign_PB, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 333:31] - sign_PC <= T_303 @[DivSqrtRecF64_mulAddZ31.scala 333:25] - node T_304 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 334:31] - specialCodeA_PC <= T_304 @[DivSqrtRecF64_mulAddZ31.scala 334:25] - node T_305 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 335:67] - node T_306 = mux(valid_PB, fractA_51_PB, T_305) @[DivSqrtRecF64_mulAddZ31.scala 335:31] - fractA_51_PC <= T_306 @[DivSqrtRecF64_mulAddZ31.scala 335:25] - node T_307 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 336:31] - specialCodeB_PC <= T_307 @[DivSqrtRecF64_mulAddZ31.scala 336:25] - node T_308 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 337:67] - node T_309 = mux(valid_PB, fractB_51_PB, T_308) @[DivSqrtRecF64_mulAddZ31.scala 337:31] - fractB_51_PC <= T_309 @[DivSqrtRecF64_mulAddZ31.scala 337:25] - node T_310 = mux(valid_PB, roundingMode_PB, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 338:31] - roundingMode_PC <= T_310 @[DivSqrtRecF64_mulAddZ31.scala 338:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 331:24] - when entering_PC_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 340:35] - exp_PC <= exp_PB @[DivSqrtRecF64_mulAddZ31.scala 341:25] - fractA_0_PC <= fractA_0_PB @[DivSqrtRecF64_mulAddZ31.scala 342:25] - fractB_other_PC <= fractB_other_PB @[DivSqrtRecF64_mulAddZ31.scala 343:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 340:35] - node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 346:42] - node T_312 = bits(specialCodeA_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 347:41] - node isSpecialA_PC = eq(T_312, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 347:48] - node T_314 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 348:59] - node T_316 = eq(T_314, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 348:42] - node isInfA_PC = and(isSpecialA_PC, T_316) @[DivSqrtRecF64_mulAddZ31.scala 348:39] - node T_317 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 349:59] - node isNaNA_PC = and(isSpecialA_PC, T_317) @[DivSqrtRecF64_mulAddZ31.scala 349:39] - node T_319 = eq(fractA_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 350:38] - node isSigNaNA_PC = and(isNaNA_PC, T_319) @[DivSqrtRecF64_mulAddZ31.scala 350:35] - node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 352:42] - node T_321 = bits(specialCodeB_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 353:41] - node isSpecialB_PC = eq(T_321, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 353:48] - node T_323 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 354:59] - node T_325 = eq(T_323, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 354:42] - node isInfB_PC = and(isSpecialB_PC, T_325) @[DivSqrtRecF64_mulAddZ31.scala 354:39] - node T_326 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 355:59] - node isNaNB_PC = and(isSpecialB_PC, T_326) @[DivSqrtRecF64_mulAddZ31.scala 355:39] - node T_328 = eq(fractB_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 356:38] - node isSigNaNB_PC = and(isNaNB_PC, T_328) @[DivSqrtRecF64_mulAddZ31.scala 356:35] - node T_330 = cat(UInt<1>("h01"), fractB_51_PC) @[Cat.scala 20:58] - node sigB_PC = cat(T_330, fractB_other_PC) @[Cat.scala 20:58] - node T_332 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:24] - node T_334 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:43] - node T_335 = and(T_332, T_334) @[DivSqrtRecF64_mulAddZ31.scala 360:40] - node T_337 = eq(sign_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:59] - node T_338 = and(T_335, T_337) @[DivSqrtRecF64_mulAddZ31.scala 360:56] - node T_340 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:13] - node T_342 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:32] - node T_343 = and(T_340, T_342) @[DivSqrtRecF64_mulAddZ31.scala 361:29] - node T_345 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:51] - node T_346 = and(T_343, T_345) @[DivSqrtRecF64_mulAddZ31.scala 361:48] - node T_348 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:67] - node T_349 = and(T_346, T_348) @[DivSqrtRecF64_mulAddZ31.scala 361:64] - node normalCase_PC = mux(sqrtOp_PC, T_338, T_349) @[DivSqrtRecF64_mulAddZ31.scala 360:12] - node T_351 = add(exp_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 363:27] - node expP2_PC = tail(T_351, 1) @[DivSqrtRecF64_mulAddZ31.scala 363:27] - node T_352 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 365:19] - node T_353 = bits(expP2_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 366:25] - node T_355 = cat(T_353, UInt<1>("h00")) @[Cat.scala 20:58] - node T_356 = bits(exp_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 367:23] - node T_358 = cat(T_356, UInt<1>("h01")) @[Cat.scala 20:58] - node expP1_PC = mux(T_352, T_355, T_358) @[DivSqrtRecF64_mulAddZ31.scala 365:12] - node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 370:54] - node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 371:54] - node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 372:54] - node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 373:54] - node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) @[DivSqrtRecF64_mulAddZ31.scala 376:12] - node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 377:61] - node T_360 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:27] - node T_362 = eq(roundingMode_near_even_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:46] - node roundMagDown_PC = and(T_360, T_362) @[DivSqrtRecF64_mulAddZ31.scala 378:43] - node T_364 = eq(normalCase_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 380:28] - node valid_leaving_PC = or(T_364, cyc_E1) @[DivSqrtRecF64_mulAddZ31.scala 380:44] - node T_365 = and(valid_PC, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 381:28] - leaving_PC <= T_365 @[DivSqrtRecF64_mulAddZ31.scala 381:16] - node T_367 = eq(valid_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 382:17] - node T_368 = or(T_367, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 382:28] - ready_PC <= T_368 @[DivSqrtRecF64_mulAddZ31.scala 382:14] - node T_370 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 383:39] - node T_371 = and(leaving_PC, T_370) @[DivSqrtRecF64_mulAddZ31.scala 383:36] - io.outValid_div <= T_371 @[DivSqrtRecF64_mulAddZ31.scala 383:22] - node T_372 = and(leaving_PC, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 384:36] - io.outValid_sqrt <= T_372 @[DivSqrtRecF64_mulAddZ31.scala 384:22] - node T_374 = neq(cycleNum_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 388:49] - node T_375 = or(entering_PA_normalCase, T_374) @[DivSqrtRecF64_mulAddZ31.scala 388:34] - when T_375 : @[DivSqrtRecF64_mulAddZ31.scala 388:63] - node T_378 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 390:16] - node T_381 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 391:16] - node T_382 = or(T_378, T_381) @[DivSqrtRecF64_mulAddZ31.scala 390:74] - node T_384 = eq(entering_PA_normalCase, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:17] - node T_386 = sub(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 392:54] - node T_387 = tail(T_386, 1) @[DivSqrtRecF64_mulAddZ31.scala 392:54] - node T_389 = mux(T_384, T_387, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:16] - node T_390 = or(T_382, T_389) @[DivSqrtRecF64_mulAddZ31.scala 391:74] - cycleNum_A <= T_390 @[DivSqrtRecF64_mulAddZ31.scala 389:20] - skip @[DivSqrtRecF64_mulAddZ31.scala 388:63] - node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 396:35] - node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 397:35] - node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 398:35] - node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) @[DivSqrtRecF64_mulAddZ31.scala 402:30] - node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 403:30] - node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 404:30] - node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 405:30] - node T_398 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 407:32] - node cyc_A3_div = and(cyc_A3, T_398) @[DivSqrtRecF64_mulAddZ31.scala 407:29] - node T_400 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 408:32] - node cyc_A2_div = and(cyc_A2, T_400) @[DivSqrtRecF64_mulAddZ31.scala 408:29] - node T_402 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 409:32] - node cyc_A1_div = and(cyc_A1, T_402) @[DivSqrtRecF64_mulAddZ31.scala 409:29] - node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 411:30] - node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 412:30] - node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 413:30] - node T_404 = neq(cycleNum_B, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 415:33] - node T_405 = or(cyc_A1, T_404) @[DivSqrtRecF64_mulAddZ31.scala 415:18] - when T_405 : @[DivSqrtRecF64_mulAddZ31.scala 415:47] - node T_408 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 418:20] - node T_410 = sub(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 419:28] - node T_411 = tail(T_410, 1) @[DivSqrtRecF64_mulAddZ31.scala 419:28] - node T_412 = mux(cyc_A1, T_408, T_411) @[DivSqrtRecF64_mulAddZ31.scala 417:16] - cycleNum_B <= T_412 @[DivSqrtRecF64_mulAddZ31.scala 416:20] - skip @[DivSqrtRecF64_mulAddZ31.scala 415:47] - node T_414 = eq(cycleNum_B, UInt<4>("h0a")) @[DivSqrtRecF64_mulAddZ31.scala 423:33] - cyc_B10_sqrt <= T_414 @[DivSqrtRecF64_mulAddZ31.scala 423:18] - node T_416 = eq(cycleNum_B, UInt<4>("h09")) @[DivSqrtRecF64_mulAddZ31.scala 424:33] - cyc_B9_sqrt <= T_416 @[DivSqrtRecF64_mulAddZ31.scala 424:18] - node T_418 = eq(cycleNum_B, UInt<4>("h08")) @[DivSqrtRecF64_mulAddZ31.scala 425:33] - cyc_B8_sqrt <= T_418 @[DivSqrtRecF64_mulAddZ31.scala 425:18] - node T_420 = eq(cycleNum_B, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 426:33] - cyc_B7_sqrt <= T_420 @[DivSqrtRecF64_mulAddZ31.scala 426:18] - node T_422 = eq(cycleNum_B, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 428:27] - cyc_B6 <= T_422 @[DivSqrtRecF64_mulAddZ31.scala 428:12] - node T_424 = eq(cycleNum_B, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 429:27] - cyc_B5 <= T_424 @[DivSqrtRecF64_mulAddZ31.scala 429:12] - node T_426 = eq(cycleNum_B, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 430:27] - cyc_B4 <= T_426 @[DivSqrtRecF64_mulAddZ31.scala 430:12] - node T_428 = eq(cycleNum_B, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 431:27] - cyc_B3 <= T_428 @[DivSqrtRecF64_mulAddZ31.scala 431:12] - node T_430 = eq(cycleNum_B, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 432:27] - cyc_B2 <= T_430 @[DivSqrtRecF64_mulAddZ31.scala 432:12] - node T_432 = eq(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 433:27] - cyc_B1 <= T_432 @[DivSqrtRecF64_mulAddZ31.scala 433:12] - node T_433 = and(cyc_B6, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 435:26] - node T_435 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 435:41] - node T_436 = and(T_433, T_435) @[DivSqrtRecF64_mulAddZ31.scala 435:38] - cyc_B6_div <= T_436 @[DivSqrtRecF64_mulAddZ31.scala 435:16] - node T_437 = and(cyc_B5, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 436:26] - node T_439 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 436:41] - node T_440 = and(T_437, T_439) @[DivSqrtRecF64_mulAddZ31.scala 436:38] - cyc_B5_div <= T_440 @[DivSqrtRecF64_mulAddZ31.scala 436:16] - node T_441 = and(cyc_B4, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 437:26] - node T_443 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 437:41] - node T_444 = and(T_441, T_443) @[DivSqrtRecF64_mulAddZ31.scala 437:38] - cyc_B4_div <= T_444 @[DivSqrtRecF64_mulAddZ31.scala 437:16] - node T_446 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 438:29] - node T_447 = and(cyc_B3, T_446) @[DivSqrtRecF64_mulAddZ31.scala 438:26] - cyc_B3_div <= T_447 @[DivSqrtRecF64_mulAddZ31.scala 438:16] - node T_449 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 439:29] - node T_450 = and(cyc_B2, T_449) @[DivSqrtRecF64_mulAddZ31.scala 439:26] - cyc_B2_div <= T_450 @[DivSqrtRecF64_mulAddZ31.scala 439:16] - node T_452 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 440:29] - node T_453 = and(cyc_B1, T_452) @[DivSqrtRecF64_mulAddZ31.scala 440:26] - cyc_B1_div <= T_453 @[DivSqrtRecF64_mulAddZ31.scala 440:16] - node T_454 = and(cyc_B6, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:27] - node T_455 = and(T_454, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:39] - cyc_B6_sqrt <= T_455 @[DivSqrtRecF64_mulAddZ31.scala 442:17] - node T_456 = and(cyc_B5, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:27] - node T_457 = and(T_456, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:39] - cyc_B5_sqrt <= T_457 @[DivSqrtRecF64_mulAddZ31.scala 443:17] - node T_458 = and(cyc_B4, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:27] - node T_459 = and(T_458, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:39] - cyc_B4_sqrt <= T_459 @[DivSqrtRecF64_mulAddZ31.scala 444:17] - node T_460 = and(cyc_B3, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 445:27] - cyc_B3_sqrt <= T_460 @[DivSqrtRecF64_mulAddZ31.scala 445:17] - node T_461 = and(cyc_B2, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 446:27] - cyc_B2_sqrt <= T_461 @[DivSqrtRecF64_mulAddZ31.scala 446:17] - node T_462 = and(cyc_B1, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 447:27] - cyc_B1_sqrt <= T_462 @[DivSqrtRecF64_mulAddZ31.scala 447:17] - node T_464 = neq(cycleNum_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 449:33] - node T_465 = or(cyc_B1, T_464) @[DivSqrtRecF64_mulAddZ31.scala 449:18] - when T_465 : @[DivSqrtRecF64_mulAddZ31.scala 449:47] - node T_468 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 451:28] - node T_470 = sub(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 451:70] - node T_471 = tail(T_470, 1) @[DivSqrtRecF64_mulAddZ31.scala 451:70] - node T_472 = mux(cyc_B1, T_468, T_471) @[DivSqrtRecF64_mulAddZ31.scala 451:16] - cycleNum_C <= T_472 @[DivSqrtRecF64_mulAddZ31.scala 450:20] - skip @[DivSqrtRecF64_mulAddZ31.scala 449:47] - node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 454:35] - node T_475 = eq(cycleNum_C, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 456:27] - cyc_C5 <= T_475 @[DivSqrtRecF64_mulAddZ31.scala 456:12] - node T_477 = eq(cycleNum_C, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 457:27] - cyc_C4 <= T_477 @[DivSqrtRecF64_mulAddZ31.scala 457:12] - node T_479 = eq(cycleNum_C, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 458:27] - valid_normalCase_leaving_PB <= T_479 @[DivSqrtRecF64_mulAddZ31.scala 458:12] - node T_481 = eq(cycleNum_C, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 459:27] - cyc_C2 <= T_481 @[DivSqrtRecF64_mulAddZ31.scala 459:12] - node T_483 = eq(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 460:27] - cyc_C1 <= T_483 @[DivSqrtRecF64_mulAddZ31.scala 460:12] - node T_485 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 462:32] - node cyc_C5_div = and(cyc_C5, T_485) @[DivSqrtRecF64_mulAddZ31.scala 462:29] - node T_487 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 463:32] - node cyc_C4_div = and(cyc_C4, T_487) @[DivSqrtRecF64_mulAddZ31.scala 463:29] - node T_489 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 464:32] - node cyc_C3_div = and(valid_normalCase_leaving_PB, T_489) @[DivSqrtRecF64_mulAddZ31.scala 464:29] - node T_491 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 465:32] - node cyc_C2_div = and(cyc_C2, T_491) @[DivSqrtRecF64_mulAddZ31.scala 465:29] - node T_493 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 466:32] - node cyc_C1_div = and(cyc_C1, T_493) @[DivSqrtRecF64_mulAddZ31.scala 466:29] - node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 468:30] - node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 469:30] - node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 470:30] - node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 471:30] - node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 472:30] - node T_495 = neq(cycleNum_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 474:33] - node T_496 = or(cyc_C1, T_495) @[DivSqrtRecF64_mulAddZ31.scala 474:18] - when T_496 : @[DivSqrtRecF64_mulAddZ31.scala 474:47] - node T_499 = sub(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 475:55] - node T_500 = tail(T_499, 1) @[DivSqrtRecF64_mulAddZ31.scala 475:55] - node T_501 = mux(cyc_C1, UInt<3>("h04"), T_500) @[DivSqrtRecF64_mulAddZ31.scala 475:26] - cycleNum_E <= T_501 @[DivSqrtRecF64_mulAddZ31.scala 475:20] - skip @[DivSqrtRecF64_mulAddZ31.scala 474:47] - node T_503 = eq(cycleNum_E, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 478:27] - cyc_E4 <= T_503 @[DivSqrtRecF64_mulAddZ31.scala 478:12] - node T_505 = eq(cycleNum_E, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 479:27] - cyc_E3 <= T_505 @[DivSqrtRecF64_mulAddZ31.scala 479:12] - node T_507 = eq(cycleNum_E, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 480:27] - cyc_E2 <= T_507 @[DivSqrtRecF64_mulAddZ31.scala 480:12] - node T_509 = eq(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 481:27] - cyc_E1 <= T_509 @[DivSqrtRecF64_mulAddZ31.scala 481:12] - node T_511 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 483:32] - node cyc_E4_div = and(cyc_E4, T_511) @[DivSqrtRecF64_mulAddZ31.scala 483:29] - node T_513 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 484:32] - node cyc_E3_div = and(cyc_E3, T_513) @[DivSqrtRecF64_mulAddZ31.scala 484:29] - node T_515 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 485:32] - node cyc_E2_div = and(cyc_E2, T_515) @[DivSqrtRecF64_mulAddZ31.scala 485:29] - node T_517 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 486:32] - node cyc_E1_div = and(cyc_E1, T_517) @[DivSqrtRecF64_mulAddZ31.scala 486:29] - node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 488:30] - node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 489:30] - node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 490:30] - node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 491:30] - node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 496:29] - node T_519 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 498:53] - node T_521 = eq(T_519, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 498:62] - node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_521) @[DivSqrtRecF64_mulAddZ31.scala 498:41] - node T_522 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 499:53] - node T_524 = eq(T_522, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 499:62] - node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_524) @[DivSqrtRecF64_mulAddZ31.scala 499:41] - node T_525 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 500:53] - node T_527 = eq(T_525, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 500:62] - node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_527) @[DivSqrtRecF64_mulAddZ31.scala 500:41] - node T_528 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 501:53] - node T_530 = eq(T_528, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 501:62] - node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_530) @[DivSqrtRecF64_mulAddZ31.scala 501:41] - node T_531 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 502:53] - node T_533 = eq(T_531, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 502:62] - node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_533) @[DivSqrtRecF64_mulAddZ31.scala 502:41] - node T_534 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 503:53] - node T_536 = eq(T_534, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 503:62] - node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_536) @[DivSqrtRecF64_mulAddZ31.scala 503:41] - node T_537 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 504:53] - node T_539 = eq(T_537, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 504:62] - node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_539) @[DivSqrtRecF64_mulAddZ31.scala 504:41] - node T_540 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 505:53] - node T_542 = eq(T_540, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 505:62] - node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_542) @[DivSqrtRecF64_mulAddZ31.scala 505:41] - node T_545 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 507:12] - node T_548 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 508:12] - node T_549 = or(T_545, T_548) @[DivSqrtRecF64_mulAddZ31.scala 507:59] - node T_552 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 509:12] - node T_553 = or(T_549, T_552) @[DivSqrtRecF64_mulAddZ31.scala 508:59] - node T_556 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 510:12] - node T_557 = or(T_553, T_556) @[DivSqrtRecF64_mulAddZ31.scala 509:59] - node T_560 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 511:12] - node T_561 = or(T_557, T_560) @[DivSqrtRecF64_mulAddZ31.scala 510:59] - node T_564 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 512:12] - node T_565 = or(T_561, T_564) @[DivSqrtRecF64_mulAddZ31.scala 511:59] - node T_568 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 513:12] - node T_569 = or(T_565, T_568) @[DivSqrtRecF64_mulAddZ31.scala 512:59] - node T_572 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 514:12] - node zK1_A4_div = or(T_569, T_572) @[DivSqrtRecF64_mulAddZ31.scala 513:59] - node T_574 = not(UInt<12>("h0fe3")) @[DivSqrtRecF64_mulAddZ31.scala 516:33] - node T_576 = mux(zLinPiece_0_A4_div, T_574, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 516:12] - node T_578 = not(UInt<12>("h0c5d")) @[DivSqrtRecF64_mulAddZ31.scala 517:33] - node T_580 = mux(zLinPiece_1_A4_div, T_578, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 517:12] - node T_581 = or(T_576, T_580) @[DivSqrtRecF64_mulAddZ31.scala 516:61] - node T_583 = not(UInt<12>("h098a")) @[DivSqrtRecF64_mulAddZ31.scala 518:33] - node T_585 = mux(zLinPiece_2_A4_div, T_583, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 518:12] - node T_586 = or(T_581, T_585) @[DivSqrtRecF64_mulAddZ31.scala 517:61] - node T_588 = not(UInt<12>("h0739")) @[DivSqrtRecF64_mulAddZ31.scala 519:33] - node T_590 = mux(zLinPiece_3_A4_div, T_588, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 519:12] - node T_591 = or(T_586, T_590) @[DivSqrtRecF64_mulAddZ31.scala 518:61] - node T_593 = not(UInt<12>("h054b")) @[DivSqrtRecF64_mulAddZ31.scala 520:33] - node T_595 = mux(zLinPiece_4_A4_div, T_593, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 520:12] - node T_596 = or(T_591, T_595) @[DivSqrtRecF64_mulAddZ31.scala 519:61] - node T_598 = not(UInt<12>("h03a9")) @[DivSqrtRecF64_mulAddZ31.scala 521:33] - node T_600 = mux(zLinPiece_5_A4_div, T_598, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 521:12] - node T_601 = or(T_596, T_600) @[DivSqrtRecF64_mulAddZ31.scala 520:61] - node T_603 = not(UInt<12>("h0242")) @[DivSqrtRecF64_mulAddZ31.scala 522:33] - node T_605 = mux(zLinPiece_6_A4_div, T_603, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 522:12] - node T_606 = or(T_601, T_605) @[DivSqrtRecF64_mulAddZ31.scala 521:61] - node T_608 = not(UInt<12>("h010b")) @[DivSqrtRecF64_mulAddZ31.scala 523:33] - node T_610 = mux(zLinPiece_7_A4_div, T_608, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 523:12] - node zComplFractK0_A4_div = or(T_606, T_610) @[DivSqrtRecF64_mulAddZ31.scala 522:61] - node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 525:30] - node T_612 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 527:55] - node T_614 = eq(T_612, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:47] - node T_615 = and(entering_PA_normalCase_sqrt, T_614) @[DivSqrtRecF64_mulAddZ31.scala 527:44] - node T_616 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 527:72] - node T_618 = eq(T_616, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:62] - node zQuadPiece_0_A7_sqrt = and(T_615, T_618) @[DivSqrtRecF64_mulAddZ31.scala 527:59] - node T_619 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 528:55] - node T_621 = eq(T_619, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 528:47] - node T_622 = and(entering_PA_normalCase_sqrt, T_621) @[DivSqrtRecF64_mulAddZ31.scala 528:44] - node T_623 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 528:72] - node zQuadPiece_1_A7_sqrt = and(T_622, T_623) @[DivSqrtRecF64_mulAddZ31.scala 528:59] - node T_624 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 529:55] - node T_625 = and(entering_PA_normalCase_sqrt, T_624) @[DivSqrtRecF64_mulAddZ31.scala 529:44] - node T_626 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 529:72] - node T_628 = eq(T_626, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 529:62] - node zQuadPiece_2_A7_sqrt = and(T_625, T_628) @[DivSqrtRecF64_mulAddZ31.scala 529:59] - node T_629 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 530:55] - node T_630 = and(entering_PA_normalCase_sqrt, T_629) @[DivSqrtRecF64_mulAddZ31.scala 530:44] - node T_631 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 530:72] - node zQuadPiece_3_A7_sqrt = and(T_630, T_631) @[DivSqrtRecF64_mulAddZ31.scala 530:59] - node T_634 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 532:12] - node T_637 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 533:12] - node T_638 = or(T_634, T_637) @[DivSqrtRecF64_mulAddZ31.scala 532:61] - node T_641 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 534:12] - node T_642 = or(T_638, T_641) @[DivSqrtRecF64_mulAddZ31.scala 533:61] - node T_645 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 535:12] - node zK2_A7_sqrt = or(T_642, T_645) @[DivSqrtRecF64_mulAddZ31.scala 534:61] - node T_647 = not(UInt<10>("h03d0")) @[DivSqrtRecF64_mulAddZ31.scala 537:35] - node T_649 = mux(zQuadPiece_0_A7_sqrt, T_647, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 537:12] - node T_651 = not(UInt<10>("h0220")) @[DivSqrtRecF64_mulAddZ31.scala 538:35] - node T_653 = mux(zQuadPiece_1_A7_sqrt, T_651, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 538:12] - node T_654 = or(T_649, T_653) @[DivSqrtRecF64_mulAddZ31.scala 537:63] - node T_656 = not(UInt<10>("h02b2")) @[DivSqrtRecF64_mulAddZ31.scala 539:35] - node T_658 = mux(zQuadPiece_2_A7_sqrt, T_656, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 539:12] - node T_659 = or(T_654, T_658) @[DivSqrtRecF64_mulAddZ31.scala 538:63] - node T_661 = not(UInt<10>("h0181")) @[DivSqrtRecF64_mulAddZ31.scala 540:35] - node T_663 = mux(zQuadPiece_3_A7_sqrt, T_661, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 540:12] - node zComplK1_A7_sqrt = or(T_659, T_663) @[DivSqrtRecF64_mulAddZ31.scala 539:63] - node T_664 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 542:55] - node T_666 = eq(T_664, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:47] - node T_667 = and(cyc_A6_sqrt, T_666) @[DivSqrtRecF64_mulAddZ31.scala 542:44] - node T_668 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 542:71] - node T_670 = eq(T_668, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:62] - node zQuadPiece_0_A6_sqrt = and(T_667, T_670) @[DivSqrtRecF64_mulAddZ31.scala 542:59] - node T_671 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 543:55] - node T_673 = eq(T_671, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 543:47] - node T_674 = and(cyc_A6_sqrt, T_673) @[DivSqrtRecF64_mulAddZ31.scala 543:44] - node T_675 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 543:71] - node zQuadPiece_1_A6_sqrt = and(T_674, T_675) @[DivSqrtRecF64_mulAddZ31.scala 543:59] - node T_676 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 544:55] - node T_677 = and(cyc_A6_sqrt, T_676) @[DivSqrtRecF64_mulAddZ31.scala 544:44] - node T_678 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 544:71] - node T_680 = eq(T_678, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 544:62] - node zQuadPiece_2_A6_sqrt = and(T_677, T_680) @[DivSqrtRecF64_mulAddZ31.scala 544:59] - node T_681 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 545:55] - node T_682 = and(cyc_A6_sqrt, T_681) @[DivSqrtRecF64_mulAddZ31.scala 545:44] - node T_683 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 545:71] - node zQuadPiece_3_A6_sqrt = and(T_682, T_683) @[DivSqrtRecF64_mulAddZ31.scala 545:59] - node T_685 = not(UInt<13>("h01fe5")) @[DivSqrtRecF64_mulAddZ31.scala 547:35] - node T_687 = mux(zQuadPiece_0_A6_sqrt, T_685, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 547:12] - node T_689 = not(UInt<13>("h01435")) @[DivSqrtRecF64_mulAddZ31.scala 548:35] - node T_691 = mux(zQuadPiece_1_A6_sqrt, T_689, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 548:12] - node T_692 = or(T_687, T_691) @[DivSqrtRecF64_mulAddZ31.scala 547:64] - node T_694 = not(UInt<13>("h0d2c")) @[DivSqrtRecF64_mulAddZ31.scala 549:35] - node T_696 = mux(zQuadPiece_2_A6_sqrt, T_694, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 549:12] - node T_697 = or(T_692, T_696) @[DivSqrtRecF64_mulAddZ31.scala 548:64] - node T_699 = not(UInt<13>("h04e8")) @[DivSqrtRecF64_mulAddZ31.scala 550:35] - node T_701 = mux(zQuadPiece_3_A6_sqrt, T_699, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 550:12] - node zComplFractK0_A6_sqrt = or(T_697, T_701) @[DivSqrtRecF64_mulAddZ31.scala 549:64] - node T_702 = bits(zFractB_A4_div, 48, 40) @[DivSqrtRecF64_mulAddZ31.scala 553:23] - node T_703 = or(T_702, zK2_A7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 553:32] - node T_705 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:17] - node T_707 = mux(T_705, nextMulAdd9A_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:16] - node mulAdd9A_A = or(T_703, T_707) @[DivSqrtRecF64_mulAddZ31.scala 553:46] - node T_708 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 556:37] - node T_709 = or(zK1_A4_div, T_708) @[DivSqrtRecF64_mulAddZ31.scala 556:20] - node T_711 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:17] - node T_713 = mux(T_711, nextMulAdd9B_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:16] - node mulAdd9B_A = or(T_709, T_713) @[DivSqrtRecF64_mulAddZ31.scala 556:46] - node T_714 = bits(entering_PA_normalCase_sqrt, 0, 0) @[Bitwise.scala 33:15] - node T_717 = mux(T_714, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 33:12] - node T_718 = cat(zComplK1_A7_sqrt, T_717) @[Cat.scala 20:58] - node T_719 = bits(cyc_A6_sqrt, 0, 0) @[Bitwise.scala 33:15] - node T_722 = mux(T_719, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 33:12] - node T_723 = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) @[Cat.scala 20:58] - node T_724 = cat(T_723, T_722) @[Cat.scala 20:58] - node T_725 = or(T_718, T_724) @[DivSqrtRecF64_mulAddZ31.scala 559:71] - node T_726 = bits(entering_PA_normalCase_div, 0, 0) @[Bitwise.scala 33:15] - node T_729 = mux(T_726, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_730 = cat(entering_PA_normalCase_div, zComplFractK0_A4_div) @[Cat.scala 20:58] - node T_731 = cat(T_730, T_729) @[Cat.scala 20:58] - node T_732 = or(T_725, T_731) @[DivSqrtRecF64_mulAddZ31.scala 560:71] - node T_734 = shl(fractR0_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 563:54] - node T_735 = add(UInt<20>("h040000"), T_734) @[DivSqrtRecF64_mulAddZ31.scala 563:42] - node T_736 = tail(T_735, 1) @[DivSqrtRecF64_mulAddZ31.scala 563:42] - node T_738 = mux(cyc_A5_sqrt, T_736, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 563:12] - node T_739 = or(T_732, T_738) @[DivSqrtRecF64_mulAddZ31.scala 561:71] - node T_740 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 564:44] - node T_742 = eq(T_740, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:28] - node T_743 = and(cyc_A4_sqrt, T_742) @[DivSqrtRecF64_mulAddZ31.scala 564:25] - node T_746 = mux(T_743, UInt<11>("h0400"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:12] - node T_747 = or(T_739, T_746) @[DivSqrtRecF64_mulAddZ31.scala 563:70] - node T_748 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 565:43] - node T_749 = and(cyc_A4_sqrt, T_748) @[DivSqrtRecF64_mulAddZ31.scala 565:26] - node T_750 = or(T_749, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 565:48] - node T_751 = bits(sigB_PA, 46, 26) @[DivSqrtRecF64_mulAddZ31.scala 566:20] - node T_753 = add(T_751, UInt<11>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 566:29] - node T_754 = tail(T_753, 1) @[DivSqrtRecF64_mulAddZ31.scala 566:29] - node T_756 = mux(T_750, T_754, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 565:12] - node T_757 = or(T_747, T_756) @[DivSqrtRecF64_mulAddZ31.scala 564:71] - node T_758 = or(cyc_A3_sqrt, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 569:25] - node T_760 = mux(T_758, partNegSigma0_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 569:12] - node T_761 = or(T_757, T_760) @[DivSqrtRecF64_mulAddZ31.scala 568:11] - node T_762 = shl(fractR0_A, 16) @[DivSqrtRecF64_mulAddZ31.scala 570:45] - node T_764 = mux(cyc_A1_sqrt, T_762, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 570:12] - node T_765 = or(T_761, T_764) @[DivSqrtRecF64_mulAddZ31.scala 569:62] - node T_766 = shl(fractR0_A, 15) @[DivSqrtRecF64_mulAddZ31.scala 571:45] - node T_768 = mux(cyc_A1_div, T_766, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 571:12] - node mulAdd9C_A = or(T_765, T_768) @[DivSqrtRecF64_mulAddZ31.scala 570:62] - node T_769 = mul(mulAdd9A_A, mulAdd9B_A) @[DivSqrtRecF64_mulAddZ31.scala 573:20] - node T_771 = bits(mulAdd9C_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 573:61] - node T_772 = cat(UInt<1>("h00"), T_771) @[Cat.scala 20:58] - node T_773 = add(T_769, T_772) @[DivSqrtRecF64_mulAddZ31.scala 573:33] - node loMulAdd9Out_A = tail(T_773, 1) @[DivSqrtRecF64_mulAddZ31.scala 573:33] - node T_774 = bits(loMulAdd9Out_A, 18, 18) @[DivSqrtRecF64_mulAddZ31.scala 575:31] - node T_775 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 576:27] - node T_777 = add(T_775, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 576:36] - node T_778 = tail(T_777, 1) @[DivSqrtRecF64_mulAddZ31.scala 576:36] - node T_779 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 577:27] - node T_780 = mux(T_774, T_778, T_779) @[DivSqrtRecF64_mulAddZ31.scala 575:16] - node T_781 = bits(loMulAdd9Out_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 579:27] - node mulAdd9Out_A = cat(T_780, T_781) @[Cat.scala 20:58] - node T_782 = bits(mulAdd9Out_A, 19, 19) @[DivSqrtRecF64_mulAddZ31.scala 583:40] - node T_783 = and(cyc_A6_sqrt, T_782) @[DivSqrtRecF64_mulAddZ31.scala 583:25] - node T_784 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 584:13] - node T_785 = shr(T_784, 10) @[DivSqrtRecF64_mulAddZ31.scala 584:26] - node T_787 = mux(T_783, T_785, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 583:12] - node zFractR0_A6_sqrt = bits(T_787, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 586:10] - node T_788 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 590:35] - node T_789 = shl(mulAdd9Out_A, 1) @[DivSqrtRecF64_mulAddZ31.scala 590:52] - node sqrR0_A5_sqrt = mux(T_788, T_789, mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 590:28] - node T_790 = bits(mulAdd9Out_A, 20, 20) @[DivSqrtRecF64_mulAddZ31.scala 592:39] - node T_791 = and(entering_PA_normalCase_div, T_790) @[DivSqrtRecF64_mulAddZ31.scala 592:24] - node T_792 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 593:13] - node T_793 = shr(T_792, 11) @[DivSqrtRecF64_mulAddZ31.scala 593:26] - node T_795 = mux(T_791, T_793, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 592:12] - node zFractR0_A4_div = bits(T_795, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 595:10] - node T_796 = bits(mulAdd9Out_A, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 598:35] - node T_797 = and(cyc_A2, T_796) @[DivSqrtRecF64_mulAddZ31.scala 598:20] - node T_798 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 598:41] - node T_799 = shr(T_798, 2) @[DivSqrtRecF64_mulAddZ31.scala 598:54] - node T_801 = mux(T_797, T_799, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 598:12] - node zSigma0_A2 = bits(T_801, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 598:67] - node T_802 = shr(mulAdd9Out_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 601:36] - node T_803 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 601:54] - node T_804 = mux(sqrtOp_PA, T_802, T_803) @[DivSqrtRecF64_mulAddZ31.scala 601:12] - node fractR1_A1 = bits(T_804, 14, 0) @[DivSqrtRecF64_mulAddZ31.scala 601:58] - node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) @[Cat.scala 20:58] - node T_806 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 603:33] - node T_807 = shl(r1_A1, 1) @[DivSqrtRecF64_mulAddZ31.scala 603:43] - node ER1_A1_sqrt = mux(T_806, T_807, r1_A1) @[DivSqrtRecF64_mulAddZ31.scala 603:26] - node T_808 = or(cyc_A6_sqrt, entering_PA_normalCase_div) @[DivSqrtRecF64_mulAddZ31.scala 605:23] - when T_808 : @[DivSqrtRecF64_mulAddZ31.scala 605:38] - node T_809 = or(zFractR0_A6_sqrt, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 606:39] - fractR0_A <= T_809 @[DivSqrtRecF64_mulAddZ31.scala 606:19] - skip @[DivSqrtRecF64_mulAddZ31.scala 605:38] - when cyc_A5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 609:24] - node T_810 = shr(sqrR0_A5_sqrt, 10) @[DivSqrtRecF64_mulAddZ31.scala 610:40] - hiSqrR0_A_sqrt <= T_810 @[DivSqrtRecF64_mulAddZ31.scala 610:24] - skip @[DivSqrtRecF64_mulAddZ31.scala 609:24] - node T_811 = or(cyc_A4_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 613:23] - when T_811 : @[DivSqrtRecF64_mulAddZ31.scala 613:34] - node T_812 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 616:56] - node T_813 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_812) @[DivSqrtRecF64_mulAddZ31.scala 616:16] - node T_814 = bits(T_813, 20, 0) @[DivSqrtRecF64_mulAddZ31.scala 616:60] - partNegSigma0_A <= T_814 @[DivSqrtRecF64_mulAddZ31.scala 615:25] - skip @[DivSqrtRecF64_mulAddZ31.scala 613:34] - node T_815 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:21] - node T_816 = or(T_815, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:36] - node T_817 = or(T_816, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 620:51] - node T_818 = or(T_817, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 620:61] - node T_819 = or(T_818, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 620:71] - when T_819 : @[DivSqrtRecF64_mulAddZ31.scala 621:7] - node T_820 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 623:40] - node T_821 = shr(T_820, 11) @[DivSqrtRecF64_mulAddZ31.scala 623:53] - node T_823 = mux(entering_PA_normalCase_sqrt, T_821, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 623:16] - node T_824 = or(T_823, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 623:68] - node T_825 = bits(sigB_PA, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 625:47] - node T_827 = mux(cyc_A4_sqrt, T_825, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 625:16] - node T_828 = or(T_824, T_827) @[DivSqrtRecF64_mulAddZ31.scala 624:68] - node T_829 = bits(zFractB_A4_div, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 626:27] - node T_830 = or(T_828, T_829) @[DivSqrtRecF64_mulAddZ31.scala 625:68] - node T_831 = or(cyc_A5_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 627:29] - node T_832 = bits(sigB_PA, 52, 44) @[DivSqrtRecF64_mulAddZ31.scala 627:47] - node T_834 = mux(T_831, T_832, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 627:16] - node T_835 = or(T_830, T_834) @[DivSqrtRecF64_mulAddZ31.scala 626:68] - node T_836 = or(T_835, zSigma0_A2) @[DivSqrtRecF64_mulAddZ31.scala 627:68] - nextMulAdd9A_A <= T_836 @[DivSqrtRecF64_mulAddZ31.scala 622:24] - skip @[DivSqrtRecF64_mulAddZ31.scala 621:7] - node T_837 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:23] - node T_838 = or(T_837, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:38] - node T_839 = or(T_838, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 630:53] - node T_840 = or(T_839, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 630:63] - when T_840 : @[DivSqrtRecF64_mulAddZ31.scala 630:74] - node T_841 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 632:28] - node T_842 = or(T_841, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 632:73] - node T_843 = bits(sqrR0_A5_sqrt, 9, 1) @[DivSqrtRecF64_mulAddZ31.scala 634:43] - node T_845 = mux(cyc_A5_sqrt, T_843, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 634:16] - node T_846 = or(T_842, T_845) @[DivSqrtRecF64_mulAddZ31.scala 633:73] - node T_847 = or(T_846, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 634:73] - node T_848 = bits(hiSqrR0_A_sqrt, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 636:44] - node T_850 = mux(cyc_A4_sqrt, T_848, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 636:16] - node T_851 = or(T_847, T_850) @[DivSqrtRecF64_mulAddZ31.scala 635:73] - node T_853 = bits(fractR0_A, 8, 1) @[DivSqrtRecF64_mulAddZ31.scala 637:55] - node T_854 = cat(UInt<1>("h01"), T_853) @[Cat.scala 20:58] - node T_856 = mux(cyc_A2, T_854, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 637:16] - node T_857 = or(T_851, T_856) @[DivSqrtRecF64_mulAddZ31.scala 636:73] - nextMulAdd9B_A <= T_857 @[DivSqrtRecF64_mulAddZ31.scala 631:24] - skip @[DivSqrtRecF64_mulAddZ31.scala 630:74] - when cyc_A1_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 640:24] - ER1_B_sqrt <= ER1_A1_sqrt @[DivSqrtRecF64_mulAddZ31.scala 641:20] - skip @[DivSqrtRecF64_mulAddZ31.scala 640:24] - node T_858 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:16] - node T_859 = or(T_858, cyc_B6_div) @[DivSqrtRecF64_mulAddZ31.scala 647:31] - node T_860 = or(T_859, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 647:45] - node T_861 = or(T_860, cyc_B3) @[DivSqrtRecF64_mulAddZ31.scala 647:55] - node T_862 = or(T_861, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:65] - node T_863 = or(T_862, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 648:25] - node T_864 = or(T_863, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 648:35] - io.latchMulAddA_0 <= T_864 @[DivSqrtRecF64_mulAddZ31.scala 646:23] - node T_865 = shl(ER1_A1_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 650:51] - node T_867 = mux(cyc_A1_sqrt, T_865, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 650:12] - node T_868 = or(cyc_B7_sqrt, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 651:25] - node T_870 = mux(T_868, sigB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 651:12] - node T_871 = or(T_867, T_870) @[DivSqrtRecF64_mulAddZ31.scala 650:67] - node T_873 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 652:12] - node T_874 = or(T_871, T_873) @[DivSqrtRecF64_mulAddZ31.scala 651:67] - node T_875 = bits(zSigma1_B4, 45, 12) @[DivSqrtRecF64_mulAddZ31.scala 653:19] - node T_876 = or(T_874, T_875) @[DivSqrtRecF64_mulAddZ31.scala 652:67] - node T_877 = or(cyc_B3, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 655:20] - node T_878 = bits(sigXNU_B3_CX, 57, 12) @[DivSqrtRecF64_mulAddZ31.scala 655:48] - node T_880 = mux(T_877, T_878, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 655:12] - node T_881 = or(T_876, T_880) @[DivSqrtRecF64_mulAddZ31.scala 653:67] - node T_882 = bits(sigXN_C, 57, 25) @[DivSqrtRecF64_mulAddZ31.scala 656:43] - node T_883 = shl(T_882, 13) @[DivSqrtRecF64_mulAddZ31.scala 656:51] - node T_885 = mux(cyc_C4_div, T_883, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 656:12] - node T_886 = or(T_881, T_885) @[DivSqrtRecF64_mulAddZ31.scala 655:67] - node T_887 = shl(u_C_sqrt, 15) @[DivSqrtRecF64_mulAddZ31.scala 657:44] - node T_889 = mux(cyc_C4_sqrt, T_887, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 657:12] - node T_890 = or(T_886, T_889) @[DivSqrtRecF64_mulAddZ31.scala 656:67] - node T_892 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 658:12] - node T_893 = or(T_890, T_892) @[DivSqrtRecF64_mulAddZ31.scala 657:67] - node T_894 = or(T_893, zComplSigT_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 658:67] - io.mulAddA_0 <= T_894 @[DivSqrtRecF64_mulAddZ31.scala 649:18] - node T_895 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:16] - node T_896 = or(T_895, cyc_B6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:31] - node T_897 = or(T_896, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 661:46] - node T_898 = or(T_897, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:56] - node T_899 = or(T_898, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 662:25] - node T_900 = or(T_899, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 662:35] - io.latchMulAddB_0 <= T_900 @[DivSqrtRecF64_mulAddZ31.scala 660:23] - node T_901 = shl(r1_A1, 36) @[DivSqrtRecF64_mulAddZ31.scala 664:31] - node T_903 = mux(cyc_A1, T_901, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 664:12] - node T_904 = shl(ESqrR1_B_sqrt, 19) @[DivSqrtRecF64_mulAddZ31.scala 665:39] - node T_906 = mux(cyc_B7_sqrt, T_904, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 665:12] - node T_907 = or(T_903, T_906) @[DivSqrtRecF64_mulAddZ31.scala 664:55] - node T_908 = shl(ER1_B_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 666:36] - node T_910 = mux(cyc_B6_sqrt, T_908, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 666:12] - node T_911 = or(T_907, T_910) @[DivSqrtRecF64_mulAddZ31.scala 665:55] - node T_912 = or(T_911, zSigma1_B4) @[DivSqrtRecF64_mulAddZ31.scala 666:55] - node T_913 = bits(sqrSigma1_C, 30, 1) @[DivSqrtRecF64_mulAddZ31.scala 668:37] - node T_915 = mux(cyc_C6_sqrt, T_913, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 668:12] - node T_916 = or(T_912, T_915) @[DivSqrtRecF64_mulAddZ31.scala 667:55] - node T_918 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 669:12] - node T_919 = or(T_916, T_918) @[DivSqrtRecF64_mulAddZ31.scala 668:55] - node T_920 = or(T_919, zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 669:55] - io.mulAddB_0 <= T_920 @[DivSqrtRecF64_mulAddZ31.scala 663:18] - node T_921 = or(cyc_A4, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 672:20] - node T_922 = or(T_921, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 672:34] - node T_923 = or(T_922, cyc_B10_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 672:48] - node T_924 = or(T_923, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:30] - node T_925 = or(T_924, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:45] - node T_926 = or(T_925, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 673:60] - node T_927 = or(T_926, cyc_B5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:70] - node T_928 = or(T_927, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:29] - node T_929 = or(T_928, cyc_B2_div) @[DivSqrtRecF64_mulAddZ31.scala 674:44] - node T_930 = or(T_929, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:58] - node T_931 = or(T_930, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 674:73] - node T_932 = or(cyc_A3, cyc_A2_div) @[DivSqrtRecF64_mulAddZ31.scala 676:20] - node T_933 = or(T_932, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 676:34] - node T_934 = or(T_933, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:29] - node T_935 = or(T_934, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 677:44] - node T_936 = or(T_935, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 677:54] - node T_937 = or(T_936, cyc_B4_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:64] - node T_938 = or(T_937, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:29] - node T_939 = or(T_938, cyc_B1_div) @[DivSqrtRecF64_mulAddZ31.scala 678:44] - node T_940 = or(T_939, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:58] - node T_941 = or(T_940, valid_normalCase_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 678:73] - node T_942 = or(cyc_A2, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 680:20] - node T_943 = or(T_942, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 680:34] - node T_944 = or(T_943, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:29] - node T_945 = or(T_944, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 681:44] - node T_946 = or(T_945, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 681:54] - node T_947 = or(T_946, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:64] - node T_948 = or(T_947, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 682:29] - node T_949 = or(T_948, cyc_C5) @[DivSqrtRecF64_mulAddZ31.scala 682:44] - node T_950 = or(T_949, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 682:54] - node T_951 = or(io.latchMulAddA_0, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 684:31] - node T_952 = or(T_951, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 684:41] - node T_953 = cat(T_950, T_952) @[Cat.scala 20:58] - node T_954 = cat(T_931, T_941) @[Cat.scala 20:58] - node T_955 = cat(T_954, T_953) @[Cat.scala 20:58] - io.usingMulAdd <= T_955 @[DivSqrtRecF64_mulAddZ31.scala 671:20] - node T_956 = shl(sigX1_B, 47) @[DivSqrtRecF64_mulAddZ31.scala 688:45] - node T_958 = mux(cyc_B1, T_956, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 688:12] - node T_959 = shl(sigX1_B, 46) @[DivSqrtRecF64_mulAddZ31.scala 689:45] - node T_961 = mux(cyc_C6_sqrt, T_959, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 689:12] - node T_962 = or(T_958, T_961) @[DivSqrtRecF64_mulAddZ31.scala 688:64] - node T_963 = or(cyc_C4_sqrt, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 690:25] - node T_964 = shl(sigXN_C, 47) @[DivSqrtRecF64_mulAddZ31.scala 690:45] - node T_966 = mux(T_963, T_964, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 690:12] - node T_967 = or(T_962, T_966) @[DivSqrtRecF64_mulAddZ31.scala 689:64] - node T_969 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:27] - node T_970 = and(cyc_E3_div, T_969) @[DivSqrtRecF64_mulAddZ31.scala 691:24] - node T_971 = shl(fractA_0_PC, 53) @[DivSqrtRecF64_mulAddZ31.scala 691:49] - node T_973 = mux(T_970, T_971, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:12] - node T_974 = or(T_967, T_973) @[DivSqrtRecF64_mulAddZ31.scala 690:64] - node T_975 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 693:24] - node T_976 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 694:29] - node T_978 = cat(T_976, UInt<1>("h00")) @[Cat.scala 20:58] - node T_979 = bits(sigB_PC, 1, 1) @[DivSqrtRecF64_mulAddZ31.scala 695:29] - node T_980 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:42] - node T_981 = xor(T_979, T_980) @[DivSqrtRecF64_mulAddZ31.scala 695:33] - node T_982 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:54] - node T_983 = cat(T_981, T_982) @[Cat.scala 20:58] - node T_984 = mux(T_975, T_978, T_983) @[DivSqrtRecF64_mulAddZ31.scala 693:17] - node T_986 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 696:22] - node T_988 = cat(T_986, UInt<1>("h00")) @[Cat.scala 20:58] - node T_989 = xor(T_984, T_988) @[DivSqrtRecF64_mulAddZ31.scala 696:16] - node T_990 = shl(T_989, 54) @[DivSqrtRecF64_mulAddZ31.scala 697:14] - node T_992 = mux(cyc_E3_sqrt, T_990, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 692:12] - node T_993 = or(T_974, T_992) @[DivSqrtRecF64_mulAddZ31.scala 691:64] - io.mulAddC_2 <= T_993 @[DivSqrtRecF64_mulAddZ31.scala 687:18] - node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) @[DivSqrtRecF64_mulAddZ31.scala 701:43] - node T_994 = bits(io.mulAddResult_3, 90, 45) @[DivSqrtRecF64_mulAddZ31.scala 702:49] - node T_995 = not(T_994) @[DivSqrtRecF64_mulAddZ31.scala 702:31] - node T_997 = mux(cyc_B4, T_995, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 702:22] - zSigma1_B4 <= T_997 @[DivSqrtRecF64_mulAddZ31.scala 702:16] - node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) @[DivSqrtRecF64_mulAddZ31.scala 703:41] - node T_998 = bits(io.mulAddResult_3, 104, 47) @[DivSqrtRecF64_mulAddZ31.scala 704:38] - sigXNU_B3_CX <= T_998 @[DivSqrtRecF64_mulAddZ31.scala 704:18] - node T_999 = bits(io.mulAddResult_3, 104, 104) @[DivSqrtRecF64_mulAddZ31.scala 705:39] - node E_C1_div = eq(T_999, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 705:20] - node T_1002 = eq(E_C1_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:28] - node T_1003 = and(cyc_C1_div, T_1002) @[DivSqrtRecF64_mulAddZ31.scala 707:25] - node T_1004 = or(T_1003, cyc_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 707:40] - node T_1005 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 708:31] - node T_1006 = not(T_1005) @[DivSqrtRecF64_mulAddZ31.scala 708:13] - node T_1008 = mux(T_1004, T_1006, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:12] - node T_1009 = and(cyc_C1_div, E_C1_div) @[DivSqrtRecF64_mulAddZ31.scala 711:24] - node T_1011 = bits(io.mulAddResult_3, 102, 50) @[DivSqrtRecF64_mulAddZ31.scala 712:47] - node T_1012 = not(T_1011) @[DivSqrtRecF64_mulAddZ31.scala 712:29] - node T_1013 = cat(UInt<1>("h00"), T_1012) @[Cat.scala 20:58] - node T_1015 = mux(T_1009, T_1013, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 711:12] - node T_1016 = or(T_1008, T_1015) @[DivSqrtRecF64_mulAddZ31.scala 710:11] - zComplSigT_C1 <= T_1016 @[DivSqrtRecF64_mulAddZ31.scala 706:19] - node T_1017 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 716:44] - node T_1018 = not(T_1017) @[DivSqrtRecF64_mulAddZ31.scala 716:26] - node T_1020 = mux(cyc_C1_sqrt, T_1018, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 716:12] - zComplSigT_C1_sqrt <= T_1020 @[DivSqrtRecF64_mulAddZ31.scala 715:24] - node sigT_C1 = not(zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 720:19] - node remT_E2 = bits(io.mulAddResult_3, 55, 0) @[DivSqrtRecF64_mulAddZ31.scala 721:36] - when cyc_B8_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 723:24] - ESqrR1_B_sqrt <= ESqrR1_B8_sqrt @[DivSqrtRecF64_mulAddZ31.scala 724:23] - skip @[DivSqrtRecF64_mulAddZ31.scala 723:24] - when cyc_B3 : @[DivSqrtRecF64_mulAddZ31.scala 726:19] - sigX1_B <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 727:17] - skip @[DivSqrtRecF64_mulAddZ31.scala 726:19] - when cyc_B1 : @[DivSqrtRecF64_mulAddZ31.scala 729:19] - sqrSigma1_C <= sqrSigma1_B1 @[DivSqrtRecF64_mulAddZ31.scala 730:21] - skip @[DivSqrtRecF64_mulAddZ31.scala 729:19] - node T_1021 = or(cyc_C6_sqrt, cyc_C5_div) @[DivSqrtRecF64_mulAddZ31.scala 733:23] - node T_1022 = or(T_1021, cyc_C3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 733:37] - when T_1022 : @[DivSqrtRecF64_mulAddZ31.scala 733:53] - sigXN_C <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 734:17] - skip @[DivSqrtRecF64_mulAddZ31.scala 733:53] - when cyc_C5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 736:24] - node T_1023 = bits(sigXNU_B3_CX, 56, 26) @[DivSqrtRecF64_mulAddZ31.scala 737:33] - u_C_sqrt <= T_1023 @[DivSqrtRecF64_mulAddZ31.scala 737:18] - skip @[DivSqrtRecF64_mulAddZ31.scala 736:24] - when cyc_C1 : @[DivSqrtRecF64_mulAddZ31.scala 739:19] - E_E_div <= E_C1_div @[DivSqrtRecF64_mulAddZ31.scala 740:18] - node T_1024 = bits(sigT_C1, 53, 1) @[DivSqrtRecF64_mulAddZ31.scala 741:28] - sigT_E <= T_1024 @[DivSqrtRecF64_mulAddZ31.scala 741:18] - node T_1025 = bits(sigT_C1, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 742:28] - extraT_E <= T_1025 @[DivSqrtRecF64_mulAddZ31.scala 742:18] - skip @[DivSqrtRecF64_mulAddZ31.scala 739:19] - when cyc_E2 : @[DivSqrtRecF64_mulAddZ31.scala 745:19] - node T_1026 = bits(remT_E2, 55, 55) @[DivSqrtRecF64_mulAddZ31.scala 746:47] - node T_1027 = bits(remT_E2, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 746:61] - node T_1028 = mux(sqrtOp_PC, T_1026, T_1027) @[DivSqrtRecF64_mulAddZ31.scala 746:27] - isNegRemT_E <= T_1028 @[DivSqrtRecF64_mulAddZ31.scala 746:21] - node T_1029 = bits(remT_E2, 53, 0) @[DivSqrtRecF64_mulAddZ31.scala 748:21] - node T_1031 = eq(T_1029, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 748:29] - node T_1033 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:18] - node T_1034 = bits(remT_E2, 55, 54) @[DivSqrtRecF64_mulAddZ31.scala 749:41] - node T_1036 = eq(T_1034, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:50] - node T_1037 = or(T_1033, T_1036) @[DivSqrtRecF64_mulAddZ31.scala 749:30] - node T_1038 = and(T_1031, T_1037) @[DivSqrtRecF64_mulAddZ31.scala 748:42] - trueEqX_E1 <= T_1038 @[DivSqrtRecF64_mulAddZ31.scala 747:22] - skip @[DivSqrtRecF64_mulAddZ31.scala 745:19] - node T_1040 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:13] - node T_1041 = and(T_1040, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 755:25] - node T_1043 = mux(T_1041, exp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:12] - node T_1045 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:13] - node T_1047 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:28] - node T_1048 = and(T_1045, T_1047) @[DivSqrtRecF64_mulAddZ31.scala 756:25] - node T_1050 = mux(T_1048, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:12] - node T_1051 = or(T_1043, T_1050) @[DivSqrtRecF64_mulAddZ31.scala 755:76] - node T_1052 = shr(exp_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:42] - node T_1054 = add(T_1052, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 757:47] - node T_1055 = tail(T_1054, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:47] - node T_1057 = mux(sqrtOp_PC, T_1055, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 757:12] - node sExpX_E = or(T_1051, T_1057) @[DivSqrtRecF64_mulAddZ31.scala 756:76] - node posExpX_E = bits(sExpX_E, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 759:28] - node T_1058 = not(posExpX_E) @[primitives.scala 50:21] - node T_1059 = bits(T_1058, 12, 12) @[primitives.scala 56:25] - node T_1060 = bits(T_1058, 11, 0) @[primitives.scala 57:26] - node T_1061 = bits(T_1060, 11, 11) @[primitives.scala 56:25] - node T_1062 = bits(T_1060, 10, 0) @[primitives.scala 57:26] - node T_1063 = bits(T_1062, 10, 10) @[primitives.scala 56:25] - node T_1064 = bits(T_1062, 9, 0) @[primitives.scala 57:26] - node T_1065 = bits(T_1064, 9, 9) @[primitives.scala 56:25] - node T_1066 = bits(T_1064, 8, 0) @[primitives.scala 57:26] - node T_1068 = bits(T_1066, 8, 8) @[primitives.scala 56:25] - node T_1069 = bits(T_1066, 7, 0) @[primitives.scala 57:26] - node T_1071 = bits(T_1069, 7, 7) @[primitives.scala 56:25] - node T_1072 = bits(T_1069, 6, 0) @[primitives.scala 57:26] - node T_1074 = bits(T_1072, 6, 6) @[primitives.scala 56:25] - node T_1075 = bits(T_1072, 5, 0) @[primitives.scala 57:26] - node T_1078 = dshr(asSInt(UInt<65>("h010000000000000000")), T_1075) @[primitives.scala 68:52] - node T_1079 = bits(T_1078, 63, 14) @[primitives.scala 69:26] - node T_1080 = bits(T_1079, 31, 0) @[Bitwise.scala 65:18] - node T_1083 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 58:47] - node T_1084 = xor(UInt<32>("h0ffffffff"), T_1083) @[Bitwise.scala 58:21] - node T_1085 = shr(T_1080, 16) @[Bitwise.scala 59:21] - node T_1086 = and(T_1085, T_1084) @[Bitwise.scala 59:31] - node T_1087 = bits(T_1080, 15, 0) @[Bitwise.scala 59:46] - node T_1088 = shl(T_1087, 16) @[Bitwise.scala 59:65] - node T_1089 = not(T_1084) @[Bitwise.scala 59:77] - node T_1090 = and(T_1088, T_1089) @[Bitwise.scala 59:75] - node T_1091 = or(T_1086, T_1090) @[Bitwise.scala 59:39] - node T_1092 = bits(T_1084, 23, 0) @[Bitwise.scala 58:28] - node T_1093 = shl(T_1092, 8) @[Bitwise.scala 58:47] - node T_1094 = xor(T_1084, T_1093) @[Bitwise.scala 58:21] - node T_1095 = shr(T_1091, 8) @[Bitwise.scala 59:21] - node T_1096 = and(T_1095, T_1094) @[Bitwise.scala 59:31] - node T_1097 = bits(T_1091, 23, 0) @[Bitwise.scala 59:46] - node T_1098 = shl(T_1097, 8) @[Bitwise.scala 59:65] - node T_1099 = not(T_1094) @[Bitwise.scala 59:77] - node T_1100 = and(T_1098, T_1099) @[Bitwise.scala 59:75] - node T_1101 = or(T_1096, T_1100) @[Bitwise.scala 59:39] - node T_1102 = bits(T_1094, 27, 0) @[Bitwise.scala 58:28] - node T_1103 = shl(T_1102, 4) @[Bitwise.scala 58:47] - node T_1104 = xor(T_1094, T_1103) @[Bitwise.scala 58:21] - node T_1105 = shr(T_1101, 4) @[Bitwise.scala 59:21] - node T_1106 = and(T_1105, T_1104) @[Bitwise.scala 59:31] - node T_1107 = bits(T_1101, 27, 0) @[Bitwise.scala 59:46] - node T_1108 = shl(T_1107, 4) @[Bitwise.scala 59:65] - node T_1109 = not(T_1104) @[Bitwise.scala 59:77] - node T_1110 = and(T_1108, T_1109) @[Bitwise.scala 59:75] - node T_1111 = or(T_1106, T_1110) @[Bitwise.scala 59:39] - node T_1112 = bits(T_1104, 29, 0) @[Bitwise.scala 58:28] - node T_1113 = shl(T_1112, 2) @[Bitwise.scala 58:47] - node T_1114 = xor(T_1104, T_1113) @[Bitwise.scala 58:21] - node T_1115 = shr(T_1111, 2) @[Bitwise.scala 59:21] - node T_1116 = and(T_1115, T_1114) @[Bitwise.scala 59:31] - node T_1117 = bits(T_1111, 29, 0) @[Bitwise.scala 59:46] - node T_1118 = shl(T_1117, 2) @[Bitwise.scala 59:65] - node T_1119 = not(T_1114) @[Bitwise.scala 59:77] - node T_1120 = and(T_1118, T_1119) @[Bitwise.scala 59:75] - node T_1121 = or(T_1116, T_1120) @[Bitwise.scala 59:39] - node T_1122 = bits(T_1114, 30, 0) @[Bitwise.scala 58:28] - node T_1123 = shl(T_1122, 1) @[Bitwise.scala 58:47] - node T_1124 = xor(T_1114, T_1123) @[Bitwise.scala 58:21] - node T_1125 = shr(T_1121, 1) @[Bitwise.scala 59:21] - node T_1126 = and(T_1125, T_1124) @[Bitwise.scala 59:31] - node T_1127 = bits(T_1121, 30, 0) @[Bitwise.scala 59:46] - node T_1128 = shl(T_1127, 1) @[Bitwise.scala 59:65] - node T_1129 = not(T_1124) @[Bitwise.scala 59:77] - node T_1130 = and(T_1128, T_1129) @[Bitwise.scala 59:75] - node T_1131 = or(T_1126, T_1130) @[Bitwise.scala 59:39] - node T_1132 = bits(T_1079, 49, 32) @[Bitwise.scala 65:44] - node T_1133 = bits(T_1132, 15, 0) @[Bitwise.scala 65:18] - node T_1136 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 58:47] - node T_1137 = xor(UInt<16>("h0ffff"), T_1136) @[Bitwise.scala 58:21] - node T_1138 = shr(T_1133, 8) @[Bitwise.scala 59:21] - node T_1139 = and(T_1138, T_1137) @[Bitwise.scala 59:31] - node T_1140 = bits(T_1133, 7, 0) @[Bitwise.scala 59:46] - node T_1141 = shl(T_1140, 8) @[Bitwise.scala 59:65] - node T_1142 = not(T_1137) @[Bitwise.scala 59:77] - node T_1143 = and(T_1141, T_1142) @[Bitwise.scala 59:75] - node T_1144 = or(T_1139, T_1143) @[Bitwise.scala 59:39] - node T_1145 = bits(T_1137, 11, 0) @[Bitwise.scala 58:28] - node T_1146 = shl(T_1145, 4) @[Bitwise.scala 58:47] - node T_1147 = xor(T_1137, T_1146) @[Bitwise.scala 58:21] - node T_1148 = shr(T_1144, 4) @[Bitwise.scala 59:21] - node T_1149 = and(T_1148, T_1147) @[Bitwise.scala 59:31] - node T_1150 = bits(T_1144, 11, 0) @[Bitwise.scala 59:46] - node T_1151 = shl(T_1150, 4) @[Bitwise.scala 59:65] - node T_1152 = not(T_1147) @[Bitwise.scala 59:77] - node T_1153 = and(T_1151, T_1152) @[Bitwise.scala 59:75] - node T_1154 = or(T_1149, T_1153) @[Bitwise.scala 59:39] - node T_1155 = bits(T_1147, 13, 0) @[Bitwise.scala 58:28] - node T_1156 = shl(T_1155, 2) @[Bitwise.scala 58:47] - node T_1157 = xor(T_1147, T_1156) @[Bitwise.scala 58:21] - node T_1158 = shr(T_1154, 2) @[Bitwise.scala 59:21] - node T_1159 = and(T_1158, T_1157) @[Bitwise.scala 59:31] - node T_1160 = bits(T_1154, 13, 0) @[Bitwise.scala 59:46] - node T_1161 = shl(T_1160, 2) @[Bitwise.scala 59:65] - node T_1162 = not(T_1157) @[Bitwise.scala 59:77] - node T_1163 = and(T_1161, T_1162) @[Bitwise.scala 59:75] - node T_1164 = or(T_1159, T_1163) @[Bitwise.scala 59:39] - node T_1165 = bits(T_1157, 14, 0) @[Bitwise.scala 58:28] - node T_1166 = shl(T_1165, 1) @[Bitwise.scala 58:47] - node T_1167 = xor(T_1157, T_1166) @[Bitwise.scala 58:21] - node T_1168 = shr(T_1164, 1) @[Bitwise.scala 59:21] - node T_1169 = and(T_1168, T_1167) @[Bitwise.scala 59:31] - node T_1170 = bits(T_1164, 14, 0) @[Bitwise.scala 59:46] - node T_1171 = shl(T_1170, 1) @[Bitwise.scala 59:65] - node T_1172 = not(T_1167) @[Bitwise.scala 59:77] - node T_1173 = and(T_1171, T_1172) @[Bitwise.scala 59:75] - node T_1174 = or(T_1169, T_1173) @[Bitwise.scala 59:39] - node T_1175 = bits(T_1132, 17, 16) @[Bitwise.scala 65:44] - node T_1176 = bits(T_1175, 0, 0) @[Bitwise.scala 65:18] - node T_1177 = bits(T_1175, 1, 1) @[Bitwise.scala 65:44] - node T_1178 = cat(T_1176, T_1177) @[Cat.scala 20:58] - node T_1179 = cat(T_1174, T_1178) @[Cat.scala 20:58] - node T_1180 = cat(T_1131, T_1179) @[Cat.scala 20:58] - node T_1181 = not(T_1180) @[primitives.scala 65:36] - node T_1182 = mux(T_1074, UInt<1>("h00"), T_1181) @[primitives.scala 65:21] - node T_1183 = not(T_1182) @[primitives.scala 65:17] - node T_1184 = not(T_1183) @[primitives.scala 65:36] - node T_1185 = mux(T_1071, UInt<1>("h00"), T_1184) @[primitives.scala 65:21] - node T_1186 = not(T_1185) @[primitives.scala 65:17] - node T_1187 = not(T_1186) @[primitives.scala 65:36] - node T_1188 = mux(T_1068, UInt<1>("h00"), T_1187) @[primitives.scala 65:21] - node T_1189 = not(T_1188) @[primitives.scala 65:17] - node T_1190 = not(T_1189) @[primitives.scala 65:36] - node T_1191 = mux(T_1065, UInt<1>("h00"), T_1190) @[primitives.scala 65:21] - node T_1192 = not(T_1191) @[primitives.scala 65:17] - node T_1194 = cat(T_1192, UInt<3>("h07")) @[Cat.scala 20:58] - node T_1195 = bits(T_1064, 9, 9) @[primitives.scala 56:25] - node T_1196 = bits(T_1064, 8, 0) @[primitives.scala 57:26] - node T_1197 = bits(T_1196, 8, 8) @[primitives.scala 56:25] - node T_1198 = bits(T_1196, 7, 0) @[primitives.scala 57:26] - node T_1199 = bits(T_1198, 7, 7) @[primitives.scala 56:25] - node T_1200 = bits(T_1198, 6, 0) @[primitives.scala 57:26] - node T_1201 = bits(T_1200, 6, 6) @[primitives.scala 56:25] - node T_1202 = bits(T_1200, 5, 0) @[primitives.scala 57:26] - node T_1204 = dshr(asSInt(UInt<65>("h010000000000000000")), T_1202) @[primitives.scala 68:52] - node T_1205 = bits(T_1204, 2, 0) @[primitives.scala 69:26] - node T_1206 = bits(T_1205, 1, 0) @[Bitwise.scala 65:18] - node T_1207 = bits(T_1206, 0, 0) @[Bitwise.scala 65:18] - node T_1208 = bits(T_1206, 1, 1) @[Bitwise.scala 65:44] - node T_1209 = cat(T_1207, T_1208) @[Cat.scala 20:58] - node T_1210 = bits(T_1205, 2, 2) @[Bitwise.scala 65:44] - node T_1211 = cat(T_1209, T_1210) @[Cat.scala 20:58] - node T_1213 = mux(T_1201, T_1211, UInt<1>("h00")) @[primitives.scala 59:20] - node T_1215 = mux(T_1199, T_1213, UInt<1>("h00")) @[primitives.scala 59:20] - node T_1217 = mux(T_1197, T_1215, UInt<1>("h00")) @[primitives.scala 59:20] - node T_1219 = mux(T_1195, T_1217, UInt<1>("h00")) @[primitives.scala 59:20] - node T_1220 = mux(T_1063, T_1194, T_1219) @[primitives.scala 61:20] - node T_1222 = mux(T_1061, T_1220, UInt<1>("h00")) @[primitives.scala 59:20] - node roundMask_E = mux(T_1059, T_1222, UInt<1>("h00")) @[primitives.scala 59:20] - node T_1225 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 20:58] - node T_1226 = not(T_1225) @[DivSqrtRecF64_mulAddZ31.scala 763:9] - node T_1228 = cat(roundMask_E, UInt<1>("h01")) @[Cat.scala 20:58] - node incrPosMask_E = and(T_1226, T_1228) @[DivSqrtRecF64_mulAddZ31.scala 763:39] - node T_1229 = shr(incrPosMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 765:51] - node T_1230 = and(sigT_E, T_1229) @[DivSqrtRecF64_mulAddZ31.scala 765:36] - node hiRoundPosBitT_E = neq(T_1230, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 765:56] - node T_1232 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 766:55] - node T_1233 = and(sigT_E, T_1232) @[DivSqrtRecF64_mulAddZ31.scala 766:42] - node all0sHiRoundExtraT_E = eq(T_1233, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 766:60] - node T_1235 = not(sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 767:34] - node T_1236 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 767:55] - node T_1237 = and(T_1235, T_1236) @[DivSqrtRecF64_mulAddZ31.scala 767:42] - node all1sHiRoundExtraT_E = eq(T_1237, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 767:60] - node T_1239 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 769:23] - node T_1241 = eq(T_1239, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 769:10] - node T_1242 = or(T_1241, hiRoundPosBitT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:27] - node all1sHiRoundT_E = and(T_1242, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:48] - node T_1244 = add(UInt<54>("h00"), sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 773:33] - node T_1245 = tail(T_1244, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:33] - node T_1246 = add(T_1245, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 773:42] - node sigAdjT_E = tail(T_1246, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:42] - node T_1248 = not(roundMask_E) @[DivSqrtRecF64_mulAddZ31.scala 774:47] - node T_1249 = cat(UInt<1>("h01"), T_1248) @[Cat.scala 20:58] - node sigY0_E = and(sigAdjT_E, T_1249) @[DivSqrtRecF64_mulAddZ31.scala 774:29] - node T_1251 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 20:58] - node T_1252 = or(sigAdjT_E, T_1251) @[DivSqrtRecF64_mulAddZ31.scala 775:30] - node T_1254 = add(T_1252, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 775:62] - node sigY1_E = tail(T_1254, 1) @[DivSqrtRecF64_mulAddZ31.scala 775:62] - node T_1256 = eq(isNegRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:24] - node T_1258 = eq(trueEqX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:41] - node T_1259 = and(T_1256, T_1258) @[DivSqrtRecF64_mulAddZ31.scala 783:38] - node trueLtX_E1 = mux(sqrtOp_PC, T_1259, isNegRemT_E) @[DivSqrtRecF64_mulAddZ31.scala 783:12] - node T_1260 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 793:25] - node T_1262 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 793:32] - node T_1263 = and(T_1260, T_1262) @[DivSqrtRecF64_mulAddZ31.scala 793:29] - node T_1264 = and(T_1263, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:45] - node T_1265 = and(T_1264, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:69] - node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1265) @[DivSqrtRecF64_mulAddZ31.scala 792:26] - node T_1267 = eq(trueEqX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:28] - node T_1269 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:44] - node T_1270 = or(T_1267, T_1269) @[DivSqrtRecF64_mulAddZ31.scala 795:41] - node T_1272 = eq(all1sHiRoundExtraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:58] - node anyRoundExtra_E1 = or(T_1270, T_1272) @[DivSqrtRecF64_mulAddZ31.scala 795:55] - node T_1273 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) @[DivSqrtRecF64_mulAddZ31.scala 797:39] - node T_1275 = eq(anyRoundExtra_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 798:17] - node T_1276 = and(T_1273, T_1275) @[DivSqrtRecF64_mulAddZ31.scala 797:59] - node roundEvenMask_E1 = mux(T_1276, incrPosMask_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 797:12] - node T_1278 = and(roundMagDown_PC, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:30] - node T_1280 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 804:45] - node T_1281 = and(T_1278, T_1280) @[DivSqrtRecF64_mulAddZ31.scala 804:42] - node T_1282 = and(T_1281, all1sHiRoundT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:58] - node T_1284 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:32] - node T_1285 = and(extraT_E, T_1284) @[DivSqrtRecF64_mulAddZ31.scala 806:29] - node T_1287 = eq(trueEqX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:48] - node T_1288 = and(T_1285, T_1287) @[DivSqrtRecF64_mulAddZ31.scala 806:45] - node T_1290 = eq(all1sHiRoundT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 807:23] - node T_1291 = or(T_1288, T_1290) @[DivSqrtRecF64_mulAddZ31.scala 806:62] - node T_1292 = and(roundMagUp_PC, T_1291) @[DivSqrtRecF64_mulAddZ31.scala 805:28] - node T_1293 = or(T_1282, T_1292) @[DivSqrtRecF64_mulAddZ31.scala 804:78] - node T_1295 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:37] - node T_1296 = or(extraT_E, T_1295) @[DivSqrtRecF64_mulAddZ31.scala 810:34] - node T_1297 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 810:67] - node T_1299 = eq(T_1297, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:54] - node T_1300 = and(T_1296, T_1299) @[DivSqrtRecF64_mulAddZ31.scala 810:51] - node T_1301 = or(hiRoundPosBitT_E, T_1300) @[DivSqrtRecF64_mulAddZ31.scala 809:36] - node T_1303 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 811:36] - node T_1304 = and(extraT_E, T_1303) @[DivSqrtRecF64_mulAddZ31.scala 811:33] - node T_1305 = and(T_1304, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 811:49] - node T_1306 = or(T_1301, T_1305) @[DivSqrtRecF64_mulAddZ31.scala 810:72] - node T_1307 = and(roundingMode_near_even_PC, T_1306) @[DivSqrtRecF64_mulAddZ31.scala 808:40] - node T_1308 = or(T_1293, T_1307) @[DivSqrtRecF64_mulAddZ31.scala 807:43] - node T_1309 = mux(T_1308, sigY1_E, sigY0_E) @[DivSqrtRecF64_mulAddZ31.scala 804:12] - node T_1310 = not(roundEvenMask_E1) @[DivSqrtRecF64_mulAddZ31.scala 814:13] - node sigY_E1 = and(T_1309, T_1310) @[DivSqrtRecF64_mulAddZ31.scala 814:11] - node fractY_E1 = bits(sigY_E1, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 815:28] - node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) @[DivSqrtRecF64_mulAddZ31.scala 816:40] - node T_1311 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 818:22] - node T_1313 = eq(T_1311, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:13] - node T_1315 = mux(T_1313, sExpX_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:12] - node T_1316 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 819:20] - node T_1318 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:28] - node T_1319 = and(T_1316, T_1318) @[DivSqrtRecF64_mulAddZ31.scala 819:25] - node T_1320 = and(T_1319, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 819:40] - node T_1322 = mux(T_1320, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:12] - node T_1323 = or(T_1315, T_1322) @[DivSqrtRecF64_mulAddZ31.scala 818:73] - node T_1324 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 820:20] - node T_1326 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:28] - node T_1327 = and(T_1324, T_1326) @[DivSqrtRecF64_mulAddZ31.scala 820:25] - node T_1329 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:43] - node T_1330 = and(T_1327, T_1329) @[DivSqrtRecF64_mulAddZ31.scala 820:40] - node T_1332 = mux(T_1330, expP2_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:12] - node T_1333 = or(T_1323, T_1332) @[DivSqrtRecF64_mulAddZ31.scala 819:73] - node T_1334 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 821:20] - node T_1335 = and(T_1334, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 821:25] - node T_1336 = shr(expP2_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:22] - node T_1338 = add(T_1336, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 822:27] - node T_1339 = tail(T_1338, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:27] - node T_1341 = mux(T_1335, T_1339, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 821:12] - node sExpY_E1 = or(T_1333, T_1341) @[DivSqrtRecF64_mulAddZ31.scala 820:73] - node expY_E1 = bits(sExpY_E1, 11, 0) @[DivSqrtRecF64_mulAddZ31.scala 825:27] - node T_1342 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 827:34] - node T_1344 = eq(T_1342, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 827:24] - node T_1346 = bits(sExpY_E1, 12, 10) @[DivSqrtRecF64_mulAddZ31.scala 827:70] - node T_1347 = leq(UInt<3>("h03"), T_1346) @[DivSqrtRecF64_mulAddZ31.scala 827:59] - node overflowY_E1 = and(T_1344, T_1347) @[DivSqrtRecF64_mulAddZ31.scala 827:39] - node T_1348 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 830:17] - node T_1349 = bits(sExpY_E1, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 830:34] - node T_1351 = lt(T_1349, UInt<13>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 830:42] - node totalUnderflowY_E1 = or(T_1348, T_1351) @[DivSqrtRecF64_mulAddZ31.scala 830:22] - node T_1353 = leq(posExpX_E, UInt<13>("h0401")) @[DivSqrtRecF64_mulAddZ31.scala 833:25] - node T_1354 = and(T_1353, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 833:56] - node underflowY_E1 = or(totalUnderflowY_E1, T_1354) @[DivSqrtRecF64_mulAddZ31.scala 832:28] - node T_1356 = eq(isNaNB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:13] - node T_1358 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:28] - node T_1359 = and(T_1356, T_1358) @[DivSqrtRecF64_mulAddZ31.scala 839:25] - node T_1360 = and(T_1359, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 839:41] - node T_1361 = and(isZeroA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:25] - node T_1362 = and(isInfA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:54] - node T_1363 = or(T_1361, T_1362) @[DivSqrtRecF64_mulAddZ31.scala 840:40] - node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1360, T_1363) @[DivSqrtRecF64_mulAddZ31.scala 838:12] - node T_1365 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 843:10] - node T_1366 = and(T_1365, isSigNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:22] - node T_1367 = or(T_1366, isSigNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:39] - node invalid_PC = or(T_1367, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:55] - node T_1369 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:9] - node T_1371 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:24] - node T_1372 = and(T_1369, T_1371) @[DivSqrtRecF64_mulAddZ31.scala 845:21] - node T_1374 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:43] - node T_1375 = and(T_1372, T_1374) @[DivSqrtRecF64_mulAddZ31.scala 845:40] - node infinity_PC = and(T_1375, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 845:56] - node overflow_E1 = and(normalCase_PC, overflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 847:37] - node underflow_E1 = and(normalCase_PC, underflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 848:38] - node T_1376 = or(overflow_E1, underflow_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:21] - node T_1377 = and(normalCase_PC, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:55] - node inexact_E1 = or(T_1376, T_1377) @[DivSqrtRecF64_mulAddZ31.scala 852:37] - node T_1378 = or(isZeroA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 857:24] - node T_1380 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 857:63] - node T_1381 = and(totalUnderflowY_E1, T_1380) @[DivSqrtRecF64_mulAddZ31.scala 857:60] - node T_1382 = or(T_1378, T_1381) @[DivSqrtRecF64_mulAddZ31.scala 857:37] - node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1382) @[DivSqrtRecF64_mulAddZ31.scala 855:12] - node T_1383 = and(normalCase_PC, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 860:23] - node pegMinFiniteMagOut_E1 = and(T_1383, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 860:45] - node T_1385 = eq(overflowY_roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 861:48] - node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1385) @[DivSqrtRecF64_mulAddZ31.scala 861:45] - node T_1386 = or(isInfA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:23] - node T_1387 = and(overflow_E1, overflowY_roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:53] - node T_1388 = or(T_1386, T_1387) @[DivSqrtRecF64_mulAddZ31.scala 865:37] - node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1388) @[DivSqrtRecF64_mulAddZ31.scala 863:12] - node T_1390 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 868:10] - node T_1391 = and(T_1390, isNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:22] - node T_1392 = or(T_1391, isNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:36] - node isNaNOut_PC = or(T_1392, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:49] - node T_1394 = eq(isNaNOut_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 871:9] - node T_1395 = and(isZeroB_PC, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:52] - node T_1396 = mux(sqrtOp_PC, T_1395, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:29] - node signOut_PC = and(T_1394, T_1396) @[DivSqrtRecF64_mulAddZ31.scala 871:23] - node T_1398 = not(UInt<12>("h01ff")) @[DivSqrtRecF64_mulAddZ31.scala 875:19] - node T_1400 = mux(notSpecial_isZeroOut_E1, T_1398, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 874:18] - node T_1401 = not(T_1400) @[DivSqrtRecF64_mulAddZ31.scala 874:14] - node T_1402 = and(expY_E1, T_1401) @[DivSqrtRecF64_mulAddZ31.scala 873:18] - node T_1404 = not(UInt<12>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 879:19] - node T_1406 = mux(pegMinFiniteMagOut_E1, T_1404, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 878:18] - node T_1407 = not(T_1406) @[DivSqrtRecF64_mulAddZ31.scala 878:14] - node T_1408 = and(T_1402, T_1407) @[DivSqrtRecF64_mulAddZ31.scala 877:16] - node T_1410 = not(UInt<12>("h0bff")) @[DivSqrtRecF64_mulAddZ31.scala 883:19] - node T_1412 = mux(pegMaxFiniteMagOut_E1, T_1410, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 882:18] - node T_1413 = not(T_1412) @[DivSqrtRecF64_mulAddZ31.scala 882:14] - node T_1414 = and(T_1408, T_1413) @[DivSqrtRecF64_mulAddZ31.scala 881:16] - node T_1416 = not(UInt<12>("h0dff")) @[DivSqrtRecF64_mulAddZ31.scala 887:19] - node T_1418 = mux(notNaN_isInfOut_E1, T_1416, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 886:18] - node T_1419 = not(T_1418) @[DivSqrtRecF64_mulAddZ31.scala 886:14] - node T_1420 = and(T_1414, T_1419) @[DivSqrtRecF64_mulAddZ31.scala 885:16] - node T_1423 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 890:16] - node T_1424 = or(T_1420, T_1423) @[DivSqrtRecF64_mulAddZ31.scala 889:17] - node T_1427 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 891:16] - node T_1428 = or(T_1424, T_1427) @[DivSqrtRecF64_mulAddZ31.scala 890:76] - node T_1431 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 892:16] - node T_1432 = or(T_1428, T_1431) @[DivSqrtRecF64_mulAddZ31.scala 891:76] - node T_1435 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 893:16] - node expOut_E1 = or(T_1432, T_1435) @[DivSqrtRecF64_mulAddZ31.scala 892:76] - node T_1436 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:37] - node T_1437 = or(T_1436, isNaNOut_PC) @[DivSqrtRecF64_mulAddZ31.scala 895:59] - node T_1439 = shl(UInt<1>("h01"), 51) @[DivSqrtRecF64_mulAddZ31.scala 896:37] - node T_1441 = mux(isNaNOut_PC, T_1439, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 896:16] - node T_1442 = mux(T_1437, T_1441, fractY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:12] - node T_1443 = bits(pegMaxFiniteMagOut_E1, 0, 0) @[Bitwise.scala 33:15] - node T_1446 = mux(T_1443, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 33:12] - node fractOut_E1 = or(T_1442, T_1446) @[DivSqrtRecF64_mulAddZ31.scala 898:11] - node T_1447 = cat(signOut_PC, expOut_E1) @[Cat.scala 20:58] - node T_1448 = cat(T_1447, fractOut_E1) @[Cat.scala 20:58] - io.out <= T_1448 @[DivSqrtRecF64_mulAddZ31.scala 900:12] - node T_1449 = cat(underflow_E1, inexact_E1) @[Cat.scala 20:58] - node T_1450 = cat(invalid_PC, infinity_PC) @[Cat.scala 20:58] - node T_1451 = cat(T_1450, overflow_E1) @[Cat.scala 20:58] - node T_1452 = cat(T_1451, T_1449) @[Cat.scala 20:58] - io.exceptionFlags <= T_1452 @[DivSqrtRecF64_mulAddZ31.scala 902:23] - - module Mul54 : + reg valid_PA : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg sqrtOp_PA : UInt<1>, clk with : + reset => (UInt<1>("h0"), sqrtOp_PA) + reg sign_PA : UInt<1>, clk with : + reset => (UInt<1>("h0"), sign_PA) + reg specialCodeB_PA : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeB_PA) + reg fractB_51_PA : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractB_51_PA) + reg roundingMode_PA : UInt<2>, clk with : + reset => (UInt<1>("h0"), roundingMode_PA) + reg specialCodeA_PA : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeA_PA) + reg fractA_51_PA : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractA_51_PA) + reg exp_PA : UInt<14>, clk with : + reset => (UInt<1>("h0"), exp_PA) + reg fractB_other_PA : UInt<51>, clk with : + reset => (UInt<1>("h0"), fractB_other_PA) + reg fractA_other_PA : UInt<51>, clk with : + reset => (UInt<1>("h0"), fractA_other_PA) + reg valid_PB : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg sqrtOp_PB : UInt<1>, clk with : + reset => (UInt<1>("h0"), sqrtOp_PB) + reg sign_PB : UInt<1>, clk with : + reset => (UInt<1>("h0"), sign_PB) + reg specialCodeA_PB : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeA_PB) + reg fractA_51_PB : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractA_51_PB) + reg specialCodeB_PB : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeB_PB) + reg fractB_51_PB : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractB_51_PB) + reg roundingMode_PB : UInt<2>, clk with : + reset => (UInt<1>("h0"), roundingMode_PB) + reg exp_PB : UInt<14>, clk with : + reset => (UInt<1>("h0"), exp_PB) + reg fractA_0_PB : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractA_0_PB) + reg fractB_other_PB : UInt<51>, clk with : + reset => (UInt<1>("h0"), fractB_other_PB) + reg valid_PC : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg sqrtOp_PC : UInt<1>, clk with : + reset => (UInt<1>("h0"), sqrtOp_PC) + reg sign_PC : UInt<1>, clk with : + reset => (UInt<1>("h0"), sign_PC) + reg specialCodeA_PC : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeA_PC) + reg fractA_51_PC : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractA_51_PC) + reg specialCodeB_PC : UInt<3>, clk with : + reset => (UInt<1>("h0"), specialCodeB_PC) + reg fractB_51_PC : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractB_51_PC) + reg roundingMode_PC : UInt<2>, clk with : + reset => (UInt<1>("h0"), roundingMode_PC) + reg exp_PC : UInt<14>, clk with : + reset => (UInt<1>("h0"), exp_PC) + reg fractA_0_PC : UInt<1>, clk with : + reset => (UInt<1>("h0"), fractA_0_PC) + reg fractB_other_PC : UInt<51>, clk with : + reset => (UInt<1>("h0"), fractB_other_PC) + reg cycleNum_A : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg cycleNum_B : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg cycleNum_C : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg cycleNum_E : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg fractR0_A : UInt<9>, clk with : + reset => (UInt<1>("h0"), fractR0_A) + reg hiSqrR0_A_sqrt : UInt<10>, clk with : + reset => (UInt<1>("h0"), hiSqrR0_A_sqrt) + reg partNegSigma0_A : UInt<21>, clk with : + reset => (UInt<1>("h0"), partNegSigma0_A) + reg nextMulAdd9A_A : UInt<9>, clk with : + reset => (UInt<1>("h0"), nextMulAdd9A_A) + reg nextMulAdd9B_A : UInt<9>, clk with : + reset => (UInt<1>("h0"), nextMulAdd9B_A) + reg ER1_B_sqrt : UInt<17>, clk with : + reset => (UInt<1>("h0"), ER1_B_sqrt) + reg ESqrR1_B_sqrt : UInt<32>, clk with : + reset => (UInt<1>("h0"), ESqrR1_B_sqrt) + reg sigX1_B : UInt<58>, clk with : + reset => (UInt<1>("h0"), sigX1_B) + reg sqrSigma1_C : UInt<33>, clk with : + reset => (UInt<1>("h0"), sqrSigma1_C) + reg sigXN_C : UInt<58>, clk with : + reset => (UInt<1>("h0"), sigXN_C) + reg u_C_sqrt : UInt<31>, clk with : + reset => (UInt<1>("h0"), u_C_sqrt) + reg E_E_div : UInt<1>, clk with : + reset => (UInt<1>("h0"), E_E_div) + reg sigT_E : UInt<53>, clk with : + reset => (UInt<1>("h0"), sigT_E) + reg extraT_E : UInt<1>, clk with : + reset => (UInt<1>("h0"), extraT_E) + reg isNegRemT_E : UInt<1>, clk with : + reset => (UInt<1>("h0"), isNegRemT_E) + reg trueEqX_E1 : UInt<1>, clk with : + reset => (UInt<1>("h0"), trueEqX_E1) + wire ready_PA : UInt<1> + ready_PA is invalid + wire ready_PB : UInt<1> + ready_PB is invalid + wire ready_PC : UInt<1> + ready_PC is invalid + wire leaving_PA : UInt<1> + leaving_PA is invalid + wire leaving_PB : UInt<1> + leaving_PB is invalid + wire leaving_PC : UInt<1> + leaving_PC is invalid + wire cyc_B10_sqrt : UInt<1> + cyc_B10_sqrt is invalid + wire cyc_B9_sqrt : UInt<1> + cyc_B9_sqrt is invalid + wire cyc_B8_sqrt : UInt<1> + cyc_B8_sqrt is invalid + wire cyc_B7_sqrt : UInt<1> + cyc_B7_sqrt is invalid + wire cyc_B6 : UInt<1> + cyc_B6 is invalid + wire cyc_B5 : UInt<1> + cyc_B5 is invalid + wire cyc_B4 : UInt<1> + cyc_B4 is invalid + wire cyc_B3 : UInt<1> + cyc_B3 is invalid + wire cyc_B2 : UInt<1> + cyc_B2 is invalid + wire cyc_B1 : UInt<1> + cyc_B1 is invalid + wire cyc_B6_div : UInt<1> + cyc_B6_div is invalid + wire cyc_B5_div : UInt<1> + cyc_B5_div is invalid + wire cyc_B4_div : UInt<1> + cyc_B4_div is invalid + wire cyc_B3_div : UInt<1> + cyc_B3_div is invalid + wire cyc_B2_div : UInt<1> + cyc_B2_div is invalid + wire cyc_B1_div : UInt<1> + cyc_B1_div is invalid + wire cyc_B6_sqrt : UInt<1> + cyc_B6_sqrt is invalid + wire cyc_B5_sqrt : UInt<1> + cyc_B5_sqrt is invalid + wire cyc_B4_sqrt : UInt<1> + cyc_B4_sqrt is invalid + wire cyc_B3_sqrt : UInt<1> + cyc_B3_sqrt is invalid + wire cyc_B2_sqrt : UInt<1> + cyc_B2_sqrt is invalid + wire cyc_B1_sqrt : UInt<1> + cyc_B1_sqrt is invalid + wire cyc_C5 : UInt<1> + cyc_C5 is invalid + wire cyc_C4 : UInt<1> + cyc_C4 is invalid + wire valid_normalCase_leaving_PB : UInt<1> + valid_normalCase_leaving_PB is invalid + wire cyc_C2 : UInt<1> + cyc_C2 is invalid + wire cyc_C1 : UInt<1> + cyc_C1 is invalid + wire cyc_E4 : UInt<1> + cyc_E4 is invalid + wire cyc_E3 : UInt<1> + cyc_E3 is invalid + wire cyc_E2 : UInt<1> + cyc_E2 is invalid + wire cyc_E1 : UInt<1> + cyc_E1 is invalid + wire zSigma1_B4 : UInt + zSigma1_B4 is invalid + wire sigXNU_B3_CX : UInt + sigXNU_B3_CX is invalid + wire zComplSigT_C1_sqrt : UInt + zComplSigT_C1_sqrt is invalid + wire zComplSigT_C1 : UInt + zComplSigT_C1 is invalid + node T_113 = eq(cyc_B7_sqrt, UInt<1>("h0")) + node T_114 = and(ready_PA, T_113) + node T_116 = eq(cyc_B6_sqrt, UInt<1>("h0")) + node T_117 = and(T_114, T_116) + node T_119 = eq(cyc_B5_sqrt, UInt<1>("h0")) + node T_120 = and(T_117, T_119) + node T_122 = eq(cyc_B4_sqrt, UInt<1>("h0")) + node T_123 = and(T_120, T_122) + node T_125 = eq(cyc_B3, UInt<1>("h0")) + node T_126 = and(T_123, T_125) + node T_128 = eq(cyc_B2, UInt<1>("h0")) + node T_129 = and(T_126, T_128) + node T_131 = eq(cyc_B1_sqrt, UInt<1>("h0")) + node T_132 = and(T_129, T_131) + node T_134 = eq(cyc_C5, UInt<1>("h0")) + node T_135 = and(T_132, T_134) + node T_137 = eq(cyc_C4, UInt<1>("h0")) + node T_138 = and(T_135, T_137) + io.inReady_div <= T_138 + node T_140 = eq(cyc_B6_sqrt, UInt<1>("h0")) + node T_141 = and(ready_PA, T_140) + node T_143 = eq(cyc_B5_sqrt, UInt<1>("h0")) + node T_144 = and(T_141, T_143) + node T_146 = eq(cyc_B4_sqrt, UInt<1>("h0")) + node T_147 = and(T_144, T_146) + node T_149 = eq(cyc_B2_div, UInt<1>("h0")) + node T_150 = and(T_147, T_149) + node T_152 = eq(cyc_B1_sqrt, UInt<1>("h0")) + node T_153 = and(T_150, T_152) + io.inReady_sqrt <= T_153 + node T_154 = and(io.inReady_div, io.inValid) + node T_156 = eq(io.sqrtOp, UInt<1>("h0")) + node cyc_S_div = and(T_154, T_156) + node T_157 = and(io.inReady_sqrt, io.inValid) + node cyc_S_sqrt = and(T_157, io.sqrtOp) + node cyc_S = or(cyc_S_div, cyc_S_sqrt) + node signA_S = bits(io.a, 64, 64) + node expA_S = bits(io.a, 63, 52) + node fractA_S = bits(io.a, 51, 0) + node specialCodeA_S = bits(expA_S, 11, 9) + node isZeroA_S = eq(specialCodeA_S, UInt<3>("h0")) + node T_159 = bits(specialCodeA_S, 2, 1) + node isSpecialA_S = eq(T_159, UInt<2>("h3")) + node signB_S = bits(io.b, 64, 64) + node expB_S = bits(io.b, 63, 52) + node fractB_S = bits(io.b, 51, 0) + node specialCodeB_S = bits(expB_S, 11, 9) + node isZeroB_S = eq(specialCodeB_S, UInt<3>("h0")) + node T_162 = bits(specialCodeB_S, 2, 1) + node isSpecialB_S = eq(T_162, UInt<2>("h3")) + node T_164 = xor(signA_S, signB_S) + node sign_S = mux(io.sqrtOp, signB_S, T_164) + node T_166 = eq(isSpecialA_S, UInt<1>("h0")) + node T_168 = eq(isSpecialB_S, UInt<1>("h0")) + node T_169 = and(T_166, T_168) + node T_171 = eq(isZeroA_S, UInt<1>("h0")) + node T_172 = and(T_169, T_171) + node T_174 = eq(isZeroB_S, UInt<1>("h0")) + node normalCase_S_div = and(T_172, T_174) + node T_176 = eq(isSpecialB_S, UInt<1>("h0")) + node T_178 = eq(isZeroB_S, UInt<1>("h0")) + node T_179 = and(T_176, T_178) + node T_181 = eq(signB_S, UInt<1>("h0")) + node normalCase_S_sqrt = and(T_179, T_181) + node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) + node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) + node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) + node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) + node T_183 = eq(ready_PB, UInt<1>("h0")) + node T_184 = or(valid_PA, T_183) + node T_185 = and(cyc_S, T_184) + node entering_PA = or(entering_PA_normalCase, T_185) + node T_187 = eq(normalCase_S, UInt<1>("h0")) + node T_188 = and(cyc_S, T_187) + node T_190 = eq(valid_PA, UInt<1>("h0")) + node T_191 = and(T_188, T_190) + node T_193 = eq(valid_PB, UInt<1>("h0")) + node T_195 = eq(ready_PC, UInt<1>("h0")) + node T_196 = and(T_193, T_195) + node T_197 = or(leaving_PB, T_196) + node entering_PB_S = and(T_191, T_197) + node T_199 = eq(normalCase_S, UInt<1>("h0")) + node T_200 = and(cyc_S, T_199) + node T_202 = eq(valid_PA, UInt<1>("h0")) + node T_203 = and(T_200, T_202) + node T_205 = eq(valid_PB, UInt<1>("h0")) + node T_206 = and(T_203, T_205) + node entering_PC_S = and(T_206, ready_PC) + node T_207 = or(entering_PA, leaving_PA) + when T_207 : + valid_PA <= entering_PA + when entering_PA : + sqrtOp_PA <= io.sqrtOp + sign_PA <= sign_S + specialCodeB_PA <= specialCodeB_S + node T_208 = bits(fractB_S, 51, 51) + fractB_51_PA <= T_208 + roundingMode_PA <= io.roundingMode + node T_210 = eq(io.sqrtOp, UInt<1>("h0")) + node T_211 = and(entering_PA, T_210) + when T_211 : + specialCodeA_PA <= specialCodeA_S + node T_212 = bits(fractA_S, 51, 51) + fractA_51_PA <= T_212 + when entering_PA_normalCase : + node T_213 = bits(expB_S, 11, 11) + node T_214 = bits(T_213, 0, 0) + node T_217 = mux(T_214, UInt<3>("h7"), UInt<3>("h0")) + node T_218 = bits(expB_S, 10, 0) + node T_219 = not(T_218) + node T_220 = cat(T_217, T_219) + node T_221 = add(expA_S, T_220) + node T_222 = tail(T_221, 1) + node T_223 = mux(io.sqrtOp, expB_S, T_222) + exp_PA <= T_223 + node T_224 = bits(fractB_S, 50, 0) + fractB_other_PA <= T_224 + when entering_PA_normalCase_div : + node T_225 = bits(fractA_S, 50, 0) + fractA_other_PA <= T_225 + node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h0")) + node T_227 = bits(specialCodeA_PA, 2, 1) + node isSpecialA_PA = eq(T_227, UInt<2>("h3")) + node T_230 = cat(UInt<1>("h1"), fractA_51_PA) + node sigA_PA = cat(T_230, fractA_other_PA) + node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h0")) + node T_232 = bits(specialCodeB_PA, 2, 1) + node isSpecialB_PA = eq(T_232, UInt<2>("h3")) + node T_235 = cat(UInt<1>("h1"), fractB_51_PA) + node sigB_PA = cat(T_235, fractB_other_PA) + node T_237 = eq(isSpecialB_PA, UInt<1>("h0")) + node T_239 = eq(isZeroB_PA, UInt<1>("h0")) + node T_240 = and(T_237, T_239) + node T_242 = eq(sign_PA, UInt<1>("h0")) + node T_243 = and(T_240, T_242) + node T_245 = eq(isSpecialA_PA, UInt<1>("h0")) + node T_247 = eq(isSpecialB_PA, UInt<1>("h0")) + node T_248 = and(T_245, T_247) + node T_250 = eq(isZeroA_PA, UInt<1>("h0")) + node T_251 = and(T_248, T_250) + node T_253 = eq(isZeroB_PA, UInt<1>("h0")) + node T_254 = and(T_251, T_253) + node normalCase_PA = mux(sqrtOp_PA, T_243, T_254) + node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) + node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) + node T_255 = and(valid_PA, valid_leaving_PA) + leaving_PA <= T_255 + node T_257 = eq(valid_PA, UInt<1>("h0")) + node T_258 = or(T_257, valid_leaving_PA) + ready_PA <= T_258 + node T_259 = and(valid_PA, normalCase_PA) + node entering_PB_normalCase = and(T_259, valid_normalCase_leaving_PA) + node entering_PB = or(entering_PB_S, leaving_PA) + node T_260 = or(entering_PB, leaving_PB) + when T_260 : + valid_PB <= entering_PB + when entering_PB : + node T_261 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) + sqrtOp_PB <= T_261 + node T_262 = mux(valid_PA, sign_PA, sign_S) + sign_PB <= T_262 + node T_263 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) + specialCodeA_PB <= T_263 + node T_264 = bits(fractA_S, 51, 51) + node T_265 = mux(valid_PA, fractA_51_PA, T_264) + fractA_51_PB <= T_265 + node T_266 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) + specialCodeB_PB <= T_266 + node T_267 = bits(fractB_S, 51, 51) + node T_268 = mux(valid_PA, fractB_51_PA, T_267) + fractB_51_PB <= T_268 + node T_269 = mux(valid_PA, roundingMode_PA, io.roundingMode) + roundingMode_PB <= T_269 + when entering_PB_normalCase : + exp_PB <= exp_PA + node T_270 = bits(fractA_other_PA, 0, 0) + fractA_0_PB <= T_270 + fractB_other_PB <= fractB_other_PA + node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h0")) + node T_272 = bits(specialCodeA_PB, 2, 1) + node isSpecialA_PB = eq(T_272, UInt<2>("h3")) + node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h0")) + node T_275 = bits(specialCodeB_PB, 2, 1) + node isSpecialB_PB = eq(T_275, UInt<2>("h3")) + node T_278 = eq(isSpecialB_PB, UInt<1>("h0")) + node T_280 = eq(isZeroB_PB, UInt<1>("h0")) + node T_281 = and(T_278, T_280) + node T_283 = eq(sign_PB, UInt<1>("h0")) + node T_284 = and(T_281, T_283) + node T_286 = eq(isSpecialA_PB, UInt<1>("h0")) + node T_288 = eq(isSpecialB_PB, UInt<1>("h0")) + node T_289 = and(T_286, T_288) + node T_291 = eq(isZeroA_PB, UInt<1>("h0")) + node T_292 = and(T_289, T_291) + node T_294 = eq(isZeroB_PB, UInt<1>("h0")) + node T_295 = and(T_292, T_294) + node normalCase_PB = mux(sqrtOp_PB, T_284, T_295) + node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) + node T_296 = and(valid_PB, valid_leaving_PB) + leaving_PB <= T_296 + node T_298 = eq(valid_PB, UInt<1>("h0")) + node T_299 = or(T_298, valid_leaving_PB) + ready_PB <= T_299 + node T_300 = and(valid_PB, normalCase_PB) + node entering_PC_normalCase = and(T_300, valid_normalCase_leaving_PB) + node entering_PC = or(entering_PC_S, leaving_PB) + node T_301 = or(entering_PC, leaving_PC) + when T_301 : + valid_PC <= entering_PC + when entering_PC : + node T_302 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) + sqrtOp_PC <= T_302 + node T_303 = mux(valid_PB, sign_PB, sign_S) + sign_PC <= T_303 + node T_304 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) + specialCodeA_PC <= T_304 + node T_305 = bits(fractA_S, 51, 51) + node T_306 = mux(valid_PB, fractA_51_PB, T_305) + fractA_51_PC <= T_306 + node T_307 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) + specialCodeB_PC <= T_307 + node T_308 = bits(fractB_S, 51, 51) + node T_309 = mux(valid_PB, fractB_51_PB, T_308) + fractB_51_PC <= T_309 + node T_310 = mux(valid_PB, roundingMode_PB, io.roundingMode) + roundingMode_PC <= T_310 + when entering_PC_normalCase : + exp_PC <= exp_PB + fractA_0_PC <= fractA_0_PB + fractB_other_PC <= fractB_other_PB + node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h0")) + node T_312 = bits(specialCodeA_PC, 2, 1) + node isSpecialA_PC = eq(T_312, UInt<2>("h3")) + node T_314 = bits(specialCodeA_PC, 0, 0) + node T_316 = eq(T_314, UInt<1>("h0")) + node isInfA_PC = and(isSpecialA_PC, T_316) + node T_317 = bits(specialCodeA_PC, 0, 0) + node isNaNA_PC = and(isSpecialA_PC, T_317) + node T_319 = eq(fractA_51_PC, UInt<1>("h0")) + node isSigNaNA_PC = and(isNaNA_PC, T_319) + node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h0")) + node T_321 = bits(specialCodeB_PC, 2, 1) + node isSpecialB_PC = eq(T_321, UInt<2>("h3")) + node T_323 = bits(specialCodeB_PC, 0, 0) + node T_325 = eq(T_323, UInt<1>("h0")) + node isInfB_PC = and(isSpecialB_PC, T_325) + node T_326 = bits(specialCodeB_PC, 0, 0) + node isNaNB_PC = and(isSpecialB_PC, T_326) + node T_328 = eq(fractB_51_PC, UInt<1>("h0")) + node isSigNaNB_PC = and(isNaNB_PC, T_328) + node T_330 = cat(UInt<1>("h1"), fractB_51_PC) + node sigB_PC = cat(T_330, fractB_other_PC) + node T_332 = eq(isSpecialB_PC, UInt<1>("h0")) + node T_334 = eq(isZeroB_PC, UInt<1>("h0")) + node T_335 = and(T_332, T_334) + node T_337 = eq(sign_PC, UInt<1>("h0")) + node T_338 = and(T_335, T_337) + node T_340 = eq(isSpecialA_PC, UInt<1>("h0")) + node T_342 = eq(isSpecialB_PC, UInt<1>("h0")) + node T_343 = and(T_340, T_342) + node T_345 = eq(isZeroA_PC, UInt<1>("h0")) + node T_346 = and(T_343, T_345) + node T_348 = eq(isZeroB_PC, UInt<1>("h0")) + node T_349 = and(T_346, T_348) + node normalCase_PC = mux(sqrtOp_PC, T_338, T_349) + node T_351 = add(exp_PC, UInt<2>("h2")) + node expP2_PC = tail(T_351, 1) + node T_352 = bits(exp_PC, 0, 0) + node T_353 = bits(expP2_PC, 13, 1) + node T_355 = cat(T_353, UInt<1>("h0")) + node T_356 = bits(exp_PC, 13, 1) + node T_358 = cat(T_356, UInt<1>("h1")) + node expP1_PC = mux(T_352, T_355, T_358) + node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h0")) + node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h1")) + node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h2")) + node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h3")) + node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) + node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) + node T_360 = eq(roundMagUp_PC, UInt<1>("h0")) + node T_362 = eq(roundingMode_near_even_PC, UInt<1>("h0")) + node roundMagDown_PC = and(T_360, T_362) + node T_364 = eq(normalCase_PC, UInt<1>("h0")) + node valid_leaving_PC = or(T_364, cyc_E1) + node T_365 = and(valid_PC, valid_leaving_PC) + leaving_PC <= T_365 + node T_367 = eq(valid_PC, UInt<1>("h0")) + node T_368 = or(T_367, valid_leaving_PC) + ready_PC <= T_368 + node T_370 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_371 = and(leaving_PC, T_370) + io.outValid_div <= T_371 + node T_372 = and(leaving_PC, sqrtOp_PC) + io.outValid_sqrt <= T_372 + node T_374 = neq(cycleNum_A, UInt<1>("h0")) + node T_375 = or(entering_PA_normalCase, T_374) + when T_375 : + node T_378 = mux(entering_PA_normalCase_div, UInt<2>("h3"), UInt<1>("h0")) + node T_381 = mux(entering_PA_normalCase_sqrt, UInt<3>("h6"), UInt<1>("h0")) + node T_382 = or(T_378, T_381) + node T_384 = eq(entering_PA_normalCase, UInt<1>("h0")) + node T_386 = sub(cycleNum_A, UInt<1>("h1")) + node T_387 = tail(T_386, 1) + node T_389 = mux(T_384, T_387, UInt<1>("h0")) + node T_390 = or(T_382, T_389) + cycleNum_A <= T_390 + node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h6")) + node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h5")) + node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h4")) + node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) + node cyc_A3 = eq(cycleNum_A, UInt<2>("h3")) + node cyc_A2 = eq(cycleNum_A, UInt<2>("h2")) + node cyc_A1 = eq(cycleNum_A, UInt<1>("h1")) + node T_398 = eq(sqrtOp_PA, UInt<1>("h0")) + node cyc_A3_div = and(cyc_A3, T_398) + node T_400 = eq(sqrtOp_PA, UInt<1>("h0")) + node cyc_A2_div = and(cyc_A2, T_400) + node T_402 = eq(sqrtOp_PA, UInt<1>("h0")) + node cyc_A1_div = and(cyc_A1, T_402) + node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) + node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) + node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) + node T_404 = neq(cycleNum_B, UInt<1>("h0")) + node T_405 = or(cyc_A1, T_404) + when T_405 : + node T_408 = mux(sqrtOp_PA, UInt<4>("ha"), UInt<3>("h6")) + node T_410 = sub(cycleNum_B, UInt<1>("h1")) + node T_411 = tail(T_410, 1) + node T_412 = mux(cyc_A1, T_408, T_411) + cycleNum_B <= T_412 + node T_414 = eq(cycleNum_B, UInt<4>("ha")) + cyc_B10_sqrt <= T_414 + node T_416 = eq(cycleNum_B, UInt<4>("h9")) + cyc_B9_sqrt <= T_416 + node T_418 = eq(cycleNum_B, UInt<4>("h8")) + cyc_B8_sqrt <= T_418 + node T_420 = eq(cycleNum_B, UInt<3>("h7")) + cyc_B7_sqrt <= T_420 + node T_422 = eq(cycleNum_B, UInt<3>("h6")) + cyc_B6 <= T_422 + node T_424 = eq(cycleNum_B, UInt<3>("h5")) + cyc_B5 <= T_424 + node T_426 = eq(cycleNum_B, UInt<3>("h4")) + cyc_B4 <= T_426 + node T_428 = eq(cycleNum_B, UInt<2>("h3")) + cyc_B3 <= T_428 + node T_430 = eq(cycleNum_B, UInt<2>("h2")) + cyc_B2 <= T_430 + node T_432 = eq(cycleNum_B, UInt<1>("h1")) + cyc_B1 <= T_432 + node T_433 = and(cyc_B6, valid_PA) + node T_435 = eq(sqrtOp_PA, UInt<1>("h0")) + node T_436 = and(T_433, T_435) + cyc_B6_div <= T_436 + node T_437 = and(cyc_B5, valid_PA) + node T_439 = eq(sqrtOp_PA, UInt<1>("h0")) + node T_440 = and(T_437, T_439) + cyc_B5_div <= T_440 + node T_441 = and(cyc_B4, valid_PA) + node T_443 = eq(sqrtOp_PA, UInt<1>("h0")) + node T_444 = and(T_441, T_443) + cyc_B4_div <= T_444 + node T_446 = eq(sqrtOp_PB, UInt<1>("h0")) + node T_447 = and(cyc_B3, T_446) + cyc_B3_div <= T_447 + node T_449 = eq(sqrtOp_PB, UInt<1>("h0")) + node T_450 = and(cyc_B2, T_449) + cyc_B2_div <= T_450 + node T_452 = eq(sqrtOp_PB, UInt<1>("h0")) + node T_453 = and(cyc_B1, T_452) + cyc_B1_div <= T_453 + node T_454 = and(cyc_B6, valid_PB) + node T_455 = and(T_454, sqrtOp_PB) + cyc_B6_sqrt <= T_455 + node T_456 = and(cyc_B5, valid_PB) + node T_457 = and(T_456, sqrtOp_PB) + cyc_B5_sqrt <= T_457 + node T_458 = and(cyc_B4, valid_PB) + node T_459 = and(T_458, sqrtOp_PB) + cyc_B4_sqrt <= T_459 + node T_460 = and(cyc_B3, sqrtOp_PB) + cyc_B3_sqrt <= T_460 + node T_461 = and(cyc_B2, sqrtOp_PB) + cyc_B2_sqrt <= T_461 + node T_462 = and(cyc_B1, sqrtOp_PB) + cyc_B1_sqrt <= T_462 + node T_464 = neq(cycleNum_C, UInt<1>("h0")) + node T_465 = or(cyc_B1, T_464) + when T_465 : + node T_468 = mux(sqrtOp_PB, UInt<3>("h6"), UInt<3>("h5")) + node T_470 = sub(cycleNum_C, UInt<1>("h1")) + node T_471 = tail(T_470, 1) + node T_472 = mux(cyc_B1, T_468, T_471) + cycleNum_C <= T_472 + node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h6")) + node T_475 = eq(cycleNum_C, UInt<3>("h5")) + cyc_C5 <= T_475 + node T_477 = eq(cycleNum_C, UInt<3>("h4")) + cyc_C4 <= T_477 + node T_479 = eq(cycleNum_C, UInt<2>("h3")) + valid_normalCase_leaving_PB <= T_479 + node T_481 = eq(cycleNum_C, UInt<2>("h2")) + cyc_C2 <= T_481 + node T_483 = eq(cycleNum_C, UInt<1>("h1")) + cyc_C1 <= T_483 + node T_485 = eq(sqrtOp_PB, UInt<1>("h0")) + node cyc_C5_div = and(cyc_C5, T_485) + node T_487 = eq(sqrtOp_PB, UInt<1>("h0")) + node cyc_C4_div = and(cyc_C4, T_487) + node T_489 = eq(sqrtOp_PB, UInt<1>("h0")) + node cyc_C3_div = and(valid_normalCase_leaving_PB, T_489) + node T_491 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_C2_div = and(cyc_C2, T_491) + node T_493 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_C1_div = and(cyc_C1, T_493) + node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) + node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) + node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) + node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) + node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) + node T_495 = neq(cycleNum_E, UInt<1>("h0")) + node T_496 = or(cyc_C1, T_495) + when T_496 : + node T_499 = sub(cycleNum_E, UInt<1>("h1")) + node T_500 = tail(T_499, 1) + node T_501 = mux(cyc_C1, UInt<3>("h4"), T_500) + cycleNum_E <= T_501 + node T_503 = eq(cycleNum_E, UInt<3>("h4")) + cyc_E4 <= T_503 + node T_505 = eq(cycleNum_E, UInt<2>("h3")) + cyc_E3 <= T_505 + node T_507 = eq(cycleNum_E, UInt<2>("h2")) + cyc_E2 <= T_507 + node T_509 = eq(cycleNum_E, UInt<1>("h1")) + cyc_E1 <= T_509 + node T_511 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_E4_div = and(cyc_E4, T_511) + node T_513 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_E3_div = and(cyc_E3, T_513) + node T_515 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_E2_div = and(cyc_E2, T_515) + node T_517 = eq(sqrtOp_PC, UInt<1>("h0")) + node cyc_E1_div = and(cyc_E1, T_517) + node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) + node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) + node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) + node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) + node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h0")) + node T_519 = bits(fractB_S, 51, 49) + node T_521 = eq(T_519, UInt<1>("h0")) + node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_521) + node T_522 = bits(fractB_S, 51, 49) + node T_524 = eq(T_522, UInt<1>("h1")) + node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_524) + node T_525 = bits(fractB_S, 51, 49) + node T_527 = eq(T_525, UInt<2>("h2")) + node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_527) + node T_528 = bits(fractB_S, 51, 49) + node T_530 = eq(T_528, UInt<2>("h3")) + node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_530) + node T_531 = bits(fractB_S, 51, 49) + node T_533 = eq(T_531, UInt<3>("h4")) + node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_533) + node T_534 = bits(fractB_S, 51, 49) + node T_536 = eq(T_534, UInt<3>("h5")) + node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_536) + node T_537 = bits(fractB_S, 51, 49) + node T_539 = eq(T_537, UInt<3>("h6")) + node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_539) + node T_540 = bits(fractB_S, 51, 49) + node T_542 = eq(T_540, UInt<3>("h7")) + node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_542) + node T_545 = mux(zLinPiece_0_A4_div, UInt<9>("h1c7"), UInt<1>("h0")) + node T_548 = mux(zLinPiece_1_A4_div, UInt<9>("h16c"), UInt<1>("h0")) + node T_549 = or(T_545, T_548) + node T_552 = mux(zLinPiece_2_A4_div, UInt<9>("h12a"), UInt<1>("h0")) + node T_553 = or(T_549, T_552) + node T_556 = mux(zLinPiece_3_A4_div, UInt<9>("hf8"), UInt<1>("h0")) + node T_557 = or(T_553, T_556) + node T_560 = mux(zLinPiece_4_A4_div, UInt<9>("hd2"), UInt<1>("h0")) + node T_561 = or(T_557, T_560) + node T_564 = mux(zLinPiece_5_A4_div, UInt<9>("hb4"), UInt<1>("h0")) + node T_565 = or(T_561, T_564) + node T_568 = mux(zLinPiece_6_A4_div, UInt<9>("h9c"), UInt<1>("h0")) + node T_569 = or(T_565, T_568) + node T_572 = mux(zLinPiece_7_A4_div, UInt<9>("h89"), UInt<1>("h0")) + node zK1_A4_div = or(T_569, T_572) + node T_574 = not(UInt<12>("hfe3")) + node T_576 = mux(zLinPiece_0_A4_div, T_574, UInt<1>("h0")) + node T_578 = not(UInt<12>("hc5d")) + node T_580 = mux(zLinPiece_1_A4_div, T_578, UInt<1>("h0")) + node T_581 = or(T_576, T_580) + node T_583 = not(UInt<12>("h98a")) + node T_585 = mux(zLinPiece_2_A4_div, T_583, UInt<1>("h0")) + node T_586 = or(T_581, T_585) + node T_588 = not(UInt<12>("h739")) + node T_590 = mux(zLinPiece_3_A4_div, T_588, UInt<1>("h0")) + node T_591 = or(T_586, T_590) + node T_593 = not(UInt<12>("h54b")) + node T_595 = mux(zLinPiece_4_A4_div, T_593, UInt<1>("h0")) + node T_596 = or(T_591, T_595) + node T_598 = not(UInt<12>("h3a9")) + node T_600 = mux(zLinPiece_5_A4_div, T_598, UInt<1>("h0")) + node T_601 = or(T_596, T_600) + node T_603 = not(UInt<12>("h242")) + node T_605 = mux(zLinPiece_6_A4_div, T_603, UInt<1>("h0")) + node T_606 = or(T_601, T_605) + node T_608 = not(UInt<12>("h10b")) + node T_610 = mux(zLinPiece_7_A4_div, T_608, UInt<1>("h0")) + node zComplFractK0_A4_div = or(T_606, T_610) + node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h0")) + node T_612 = bits(expB_S, 0, 0) + node T_614 = eq(T_612, UInt<1>("h0")) + node T_615 = and(entering_PA_normalCase_sqrt, T_614) + node T_616 = bits(fractB_S, 51, 51) + node T_618 = eq(T_616, UInt<1>("h0")) + node zQuadPiece_0_A7_sqrt = and(T_615, T_618) + node T_619 = bits(expB_S, 0, 0) + node T_621 = eq(T_619, UInt<1>("h0")) + node T_622 = and(entering_PA_normalCase_sqrt, T_621) + node T_623 = bits(fractB_S, 51, 51) + node zQuadPiece_1_A7_sqrt = and(T_622, T_623) + node T_624 = bits(expB_S, 0, 0) + node T_625 = and(entering_PA_normalCase_sqrt, T_624) + node T_626 = bits(fractB_S, 51, 51) + node T_628 = eq(T_626, UInt<1>("h0")) + node zQuadPiece_2_A7_sqrt = and(T_625, T_628) + node T_629 = bits(expB_S, 0, 0) + node T_630 = and(entering_PA_normalCase_sqrt, T_629) + node T_631 = bits(fractB_S, 51, 51) + node zQuadPiece_3_A7_sqrt = and(T_630, T_631) + node T_634 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h1c8"), UInt<1>("h0")) + node T_637 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("hc1"), UInt<1>("h0")) + node T_638 = or(T_634, T_637) + node T_641 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h143"), UInt<1>("h0")) + node T_642 = or(T_638, T_641) + node T_645 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h89"), UInt<1>("h0")) + node zK2_A7_sqrt = or(T_642, T_645) + node T_647 = not(UInt<10>("h3d0")) + node T_649 = mux(zQuadPiece_0_A7_sqrt, T_647, UInt<1>("h0")) + node T_651 = not(UInt<10>("h220")) + node T_653 = mux(zQuadPiece_1_A7_sqrt, T_651, UInt<1>("h0")) + node T_654 = or(T_649, T_653) + node T_656 = not(UInt<10>("h2b2")) + node T_658 = mux(zQuadPiece_2_A7_sqrt, T_656, UInt<1>("h0")) + node T_659 = or(T_654, T_658) + node T_661 = not(UInt<10>("h181")) + node T_663 = mux(zQuadPiece_3_A7_sqrt, T_661, UInt<1>("h0")) + node zComplK1_A7_sqrt = or(T_659, T_663) + node T_664 = bits(exp_PA, 0, 0) + node T_666 = eq(T_664, UInt<1>("h0")) + node T_667 = and(cyc_A6_sqrt, T_666) + node T_668 = bits(sigB_PA, 51, 51) + node T_670 = eq(T_668, UInt<1>("h0")) + node zQuadPiece_0_A6_sqrt = and(T_667, T_670) + node T_671 = bits(exp_PA, 0, 0) + node T_673 = eq(T_671, UInt<1>("h0")) + node T_674 = and(cyc_A6_sqrt, T_673) + node T_675 = bits(sigB_PA, 51, 51) + node zQuadPiece_1_A6_sqrt = and(T_674, T_675) + node T_676 = bits(exp_PA, 0, 0) + node T_677 = and(cyc_A6_sqrt, T_676) + node T_678 = bits(sigB_PA, 51, 51) + node T_680 = eq(T_678, UInt<1>("h0")) + node zQuadPiece_2_A6_sqrt = and(T_677, T_680) + node T_681 = bits(exp_PA, 0, 0) + node T_682 = and(cyc_A6_sqrt, T_681) + node T_683 = bits(sigB_PA, 51, 51) + node zQuadPiece_3_A6_sqrt = and(T_682, T_683) + node T_685 = not(UInt<13>("h1fe5")) + node T_687 = mux(zQuadPiece_0_A6_sqrt, T_685, UInt<1>("h0")) + node T_689 = not(UInt<13>("h1435")) + node T_691 = mux(zQuadPiece_1_A6_sqrt, T_689, UInt<1>("h0")) + node T_692 = or(T_687, T_691) + node T_694 = not(UInt<13>("hd2c")) + node T_696 = mux(zQuadPiece_2_A6_sqrt, T_694, UInt<1>("h0")) + node T_697 = or(T_692, T_696) + node T_699 = not(UInt<13>("h4e8")) + node T_701 = mux(zQuadPiece_3_A6_sqrt, T_699, UInt<1>("h0")) + node zComplFractK0_A6_sqrt = or(T_697, T_701) + node T_702 = bits(zFractB_A4_div, 48, 40) + node T_703 = or(T_702, zK2_A7_sqrt) + node T_705 = eq(cyc_S, UInt<1>("h0")) + node T_707 = mux(T_705, nextMulAdd9A_A, UInt<1>("h0")) + node mulAdd9A_A = or(T_703, T_707) + node T_708 = bits(zFractB_A7_sqrt, 50, 42) + node T_709 = or(zK1_A4_div, T_708) + node T_711 = eq(cyc_S, UInt<1>("h0")) + node T_713 = mux(T_711, nextMulAdd9B_A, UInt<1>("h0")) + node mulAdd9B_A = or(T_709, T_713) + node T_714 = bits(entering_PA_normalCase_sqrt, 0, 0) + node T_717 = mux(T_714, UInt<10>("h3ff"), UInt<10>("h0")) + node T_718 = cat(zComplK1_A7_sqrt, T_717) + node T_719 = bits(cyc_A6_sqrt, 0, 0) + node T_722 = mux(T_719, UInt<6>("h3f"), UInt<6>("h0")) + node T_723 = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) + node T_724 = cat(T_723, T_722) + node T_725 = or(T_718, T_724) + node T_726 = bits(entering_PA_normalCase_div, 0, 0) + node T_729 = mux(T_726, UInt<8>("hff"), UInt<8>("h0")) + node T_730 = cat(entering_PA_normalCase_div, zComplFractK0_A4_div) + node T_731 = cat(T_730, T_729) + node T_732 = or(T_725, T_731) + node T_734 = shl(fractR0_A, 10) + node T_735 = add(UInt<20>("h40000"), T_734) + node T_736 = tail(T_735, 1) + node T_738 = mux(cyc_A5_sqrt, T_736, UInt<1>("h0")) + node T_739 = or(T_732, T_738) + node T_740 = bits(hiSqrR0_A_sqrt, 9, 9) + node T_742 = eq(T_740, UInt<1>("h0")) + node T_743 = and(cyc_A4_sqrt, T_742) + node T_746 = mux(T_743, UInt<11>("h400"), UInt<1>("h0")) + node T_747 = or(T_739, T_746) + node T_748 = bits(hiSqrR0_A_sqrt, 9, 9) + node T_749 = and(cyc_A4_sqrt, T_748) + node T_750 = or(T_749, cyc_A3_div) + node T_751 = bits(sigB_PA, 46, 26) + node T_753 = add(T_751, UInt<11>("h400")) + node T_754 = tail(T_753, 1) + node T_756 = mux(T_750, T_754, UInt<1>("h0")) + node T_757 = or(T_747, T_756) + node T_758 = or(cyc_A3_sqrt, cyc_A2) + node T_760 = mux(T_758, partNegSigma0_A, UInt<1>("h0")) + node T_761 = or(T_757, T_760) + node T_762 = shl(fractR0_A, 16) + node T_764 = mux(cyc_A1_sqrt, T_762, UInt<1>("h0")) + node T_765 = or(T_761, T_764) + node T_766 = shl(fractR0_A, 15) + node T_768 = mux(cyc_A1_div, T_766, UInt<1>("h0")) + node mulAdd9C_A = or(T_765, T_768) + node T_769 = mul(mulAdd9A_A, mulAdd9B_A) + node T_771 = bits(mulAdd9C_A, 17, 0) + node T_772 = cat(UInt<1>("h0"), T_771) + node T_773 = add(T_769, T_772) + node loMulAdd9Out_A = tail(T_773, 1) + node T_774 = bits(loMulAdd9Out_A, 18, 18) + node T_775 = bits(mulAdd9C_A, 24, 18) + node T_777 = add(T_775, UInt<1>("h1")) + node T_778 = tail(T_777, 1) + node T_779 = bits(mulAdd9C_A, 24, 18) + node T_780 = mux(T_774, T_778, T_779) + node T_781 = bits(loMulAdd9Out_A, 17, 0) + node mulAdd9Out_A = cat(T_780, T_781) + node T_782 = bits(mulAdd9Out_A, 19, 19) + node T_783 = and(cyc_A6_sqrt, T_782) + node T_784 = not(mulAdd9Out_A) + node T_785 = shr(T_784, 10) + node T_787 = mux(T_783, T_785, UInt<1>("h0")) + node zFractR0_A6_sqrt = bits(T_787, 8, 0) + node T_788 = bits(exp_PA, 0, 0) + node T_789 = shl(mulAdd9Out_A, 1) + node sqrR0_A5_sqrt = mux(T_788, T_789, mulAdd9Out_A) + node T_790 = bits(mulAdd9Out_A, 20, 20) + node T_791 = and(entering_PA_normalCase_div, T_790) + node T_792 = not(mulAdd9Out_A) + node T_793 = shr(T_792, 11) + node T_795 = mux(T_791, T_793, UInt<1>("h0")) + node zFractR0_A4_div = bits(T_795, 8, 0) + node T_796 = bits(mulAdd9Out_A, 11, 11) + node T_797 = and(cyc_A2, T_796) + node T_798 = not(mulAdd9Out_A) + node T_799 = shr(T_798, 2) + node T_801 = mux(T_797, T_799, UInt<1>("h0")) + node zSigma0_A2 = bits(T_801, 8, 0) + node T_802 = shr(mulAdd9Out_A, 10) + node T_803 = shr(mulAdd9Out_A, 9) + node T_804 = mux(sqrtOp_PA, T_802, T_803) + node fractR1_A1 = bits(T_804, 14, 0) + node r1_A1 = cat(UInt<1>("h1"), fractR1_A1) + node T_806 = bits(exp_PA, 0, 0) + node T_807 = shl(r1_A1, 1) + node ER1_A1_sqrt = mux(T_806, T_807, r1_A1) + node T_808 = or(cyc_A6_sqrt, entering_PA_normalCase_div) + when T_808 : + node T_809 = or(zFractR0_A6_sqrt, zFractR0_A4_div) + fractR0_A <= T_809 + when cyc_A5_sqrt : + node T_810 = shr(sqrR0_A5_sqrt, 10) + hiSqrR0_A_sqrt <= T_810 + node T_811 = or(cyc_A4_sqrt, cyc_A3) + when T_811 : + node T_812 = shr(mulAdd9Out_A, 9) + node T_813 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_812) + node T_814 = bits(T_813, 20, 0) + partNegSigma0_A <= T_814 + node T_815 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_816 = or(T_815, cyc_A5_sqrt) + node T_817 = or(T_816, cyc_A4) + node T_818 = or(T_817, cyc_A3) + node T_819 = or(T_818, cyc_A2) + when T_819 : + node T_820 = not(mulAdd9Out_A) + node T_821 = shr(T_820, 11) + node T_823 = mux(entering_PA_normalCase_sqrt, T_821, UInt<1>("h0")) + node T_824 = or(T_823, zFractR0_A6_sqrt) + node T_825 = bits(sigB_PA, 43, 35) + node T_827 = mux(cyc_A4_sqrt, T_825, UInt<1>("h0")) + node T_828 = or(T_824, T_827) + node T_829 = bits(zFractB_A4_div, 43, 35) + node T_830 = or(T_828, T_829) + node T_831 = or(cyc_A5_sqrt, cyc_A3) + node T_832 = bits(sigB_PA, 52, 44) + node T_834 = mux(T_831, T_832, UInt<1>("h0")) + node T_835 = or(T_830, T_834) + node T_836 = or(T_835, zSigma0_A2) + nextMulAdd9A_A <= T_836 + node T_837 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_838 = or(T_837, cyc_A5_sqrt) + node T_839 = or(T_838, cyc_A4) + node T_840 = or(T_839, cyc_A2) + when T_840 : + node T_841 = bits(zFractB_A7_sqrt, 50, 42) + node T_842 = or(T_841, zFractR0_A6_sqrt) + node T_843 = bits(sqrR0_A5_sqrt, 9, 1) + node T_845 = mux(cyc_A5_sqrt, T_843, UInt<1>("h0")) + node T_846 = or(T_842, T_845) + node T_847 = or(T_846, zFractR0_A4_div) + node T_848 = bits(hiSqrR0_A_sqrt, 8, 0) + node T_850 = mux(cyc_A4_sqrt, T_848, UInt<1>("h0")) + node T_851 = or(T_847, T_850) + node T_853 = bits(fractR0_A, 8, 1) + node T_854 = cat(UInt<1>("h1"), T_853) + node T_856 = mux(cyc_A2, T_854, UInt<1>("h0")) + node T_857 = or(T_851, T_856) + nextMulAdd9B_A <= T_857 + when cyc_A1_sqrt : + ER1_B_sqrt <= ER1_A1_sqrt + node T_858 = or(cyc_A1, cyc_B7_sqrt) + node T_859 = or(T_858, cyc_B6_div) + node T_860 = or(T_859, cyc_B4) + node T_861 = or(T_860, cyc_B3) + node T_862 = or(T_861, cyc_C6_sqrt) + node T_863 = or(T_862, cyc_C4) + node T_864 = or(T_863, cyc_C1) + io.latchMulAddA_0 <= T_864 + node T_865 = shl(ER1_A1_sqrt, 36) + node T_867 = mux(cyc_A1_sqrt, T_865, UInt<1>("h0")) + node T_868 = or(cyc_B7_sqrt, cyc_A1_div) + node T_870 = mux(T_868, sigB_PA, UInt<1>("h0")) + node T_871 = or(T_867, T_870) + node T_873 = mux(cyc_B6_div, sigA_PA, UInt<1>("h0")) + node T_874 = or(T_871, T_873) + node T_875 = bits(zSigma1_B4, 45, 12) + node T_876 = or(T_874, T_875) + node T_877 = or(cyc_B3, cyc_C6_sqrt) + node T_878 = bits(sigXNU_B3_CX, 57, 12) + node T_880 = mux(T_877, T_878, UInt<1>("h0")) + node T_881 = or(T_876, T_880) + node T_882 = bits(sigXN_C, 57, 25) + node T_883 = shl(T_882, 13) + node T_885 = mux(cyc_C4_div, T_883, UInt<1>("h0")) + node T_886 = or(T_881, T_885) + node T_887 = shl(u_C_sqrt, 15) + node T_889 = mux(cyc_C4_sqrt, T_887, UInt<1>("h0")) + node T_890 = or(T_886, T_889) + node T_892 = mux(cyc_C1_div, sigB_PC, UInt<1>("h0")) + node T_893 = or(T_890, T_892) + node T_894 = or(T_893, zComplSigT_C1_sqrt) + io.mulAddA_0 <= T_894 + node T_895 = or(cyc_A1, cyc_B7_sqrt) + node T_896 = or(T_895, cyc_B6_sqrt) + node T_897 = or(T_896, cyc_B4) + node T_898 = or(T_897, cyc_C6_sqrt) + node T_899 = or(T_898, cyc_C4) + node T_900 = or(T_899, cyc_C1) + io.latchMulAddB_0 <= T_900 + node T_901 = shl(r1_A1, 36) + node T_903 = mux(cyc_A1, T_901, UInt<1>("h0")) + node T_904 = shl(ESqrR1_B_sqrt, 19) + node T_906 = mux(cyc_B7_sqrt, T_904, UInt<1>("h0")) + node T_907 = or(T_903, T_906) + node T_908 = shl(ER1_B_sqrt, 36) + node T_910 = mux(cyc_B6_sqrt, T_908, UInt<1>("h0")) + node T_911 = or(T_907, T_910) + node T_912 = or(T_911, zSigma1_B4) + node T_913 = bits(sqrSigma1_C, 30, 1) + node T_915 = mux(cyc_C6_sqrt, T_913, UInt<1>("h0")) + node T_916 = or(T_912, T_915) + node T_918 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h0")) + node T_919 = or(T_916, T_918) + node T_920 = or(T_919, zComplSigT_C1) + io.mulAddB_0 <= T_920 + node T_921 = or(cyc_A4, cyc_A3_div) + node T_922 = or(T_921, cyc_A1_div) + node T_923 = or(T_922, cyc_B10_sqrt) + node T_924 = or(T_923, cyc_B9_sqrt) + node T_925 = or(T_924, cyc_B7_sqrt) + node T_926 = or(T_925, cyc_B6) + node T_927 = or(T_926, cyc_B5_sqrt) + node T_928 = or(T_927, cyc_B3_sqrt) + node T_929 = or(T_928, cyc_B2_div) + node T_930 = or(T_929, cyc_B1_sqrt) + node T_931 = or(T_930, cyc_C4) + node T_932 = or(cyc_A3, cyc_A2_div) + node T_933 = or(T_932, cyc_B9_sqrt) + node T_934 = or(T_933, cyc_B8_sqrt) + node T_935 = or(T_934, cyc_B6) + node T_936 = or(T_935, cyc_B5) + node T_937 = or(T_936, cyc_B4_sqrt) + node T_938 = or(T_937, cyc_B2_sqrt) + node T_939 = or(T_938, cyc_B1_div) + node T_940 = or(T_939, cyc_C6_sqrt) + node T_941 = or(T_940, valid_normalCase_leaving_PB) + node T_942 = or(cyc_A2, cyc_A1_div) + node T_943 = or(T_942, cyc_B8_sqrt) + node T_944 = or(T_943, cyc_B7_sqrt) + node T_945 = or(T_944, cyc_B5) + node T_946 = or(T_945, cyc_B4) + node T_947 = or(T_946, cyc_B3_sqrt) + node T_948 = or(T_947, cyc_B1_sqrt) + node T_949 = or(T_948, cyc_C5) + node T_950 = or(T_949, cyc_C2) + node T_951 = or(io.latchMulAddA_0, cyc_B6) + node T_952 = or(T_951, cyc_B2_sqrt) + node T_953 = cat(T_950, T_952) + node T_954 = cat(T_931, T_941) + node T_955 = cat(T_954, T_953) + io.usingMulAdd <= T_955 + node T_956 = shl(sigX1_B, 47) + node T_958 = mux(cyc_B1, T_956, UInt<1>("h0")) + node T_959 = shl(sigX1_B, 46) + node T_961 = mux(cyc_C6_sqrt, T_959, UInt<1>("h0")) + node T_962 = or(T_958, T_961) + node T_963 = or(cyc_C4_sqrt, cyc_C2) + node T_964 = shl(sigXN_C, 47) + node T_966 = mux(T_963, T_964, UInt<1>("h0")) + node T_967 = or(T_962, T_966) + node T_969 = eq(E_E_div, UInt<1>("h0")) + node T_970 = and(cyc_E3_div, T_969) + node T_971 = shl(fractA_0_PC, 53) + node T_973 = mux(T_970, T_971, UInt<1>("h0")) + node T_974 = or(T_967, T_973) + node T_975 = bits(exp_PC, 0, 0) + node T_976 = bits(sigB_PC, 0, 0) + node T_978 = cat(T_976, UInt<1>("h0")) + node T_979 = bits(sigB_PC, 1, 1) + node T_980 = bits(sigB_PC, 0, 0) + node T_981 = xor(T_979, T_980) + node T_982 = bits(sigB_PC, 0, 0) + node T_983 = cat(T_981, T_982) + node T_984 = mux(T_975, T_978, T_983) + node T_986 = eq(extraT_E, UInt<1>("h0")) + node T_988 = cat(T_986, UInt<1>("h0")) + node T_989 = xor(T_984, T_988) + node T_990 = shl(T_989, 54) + node T_992 = mux(cyc_E3_sqrt, T_990, UInt<1>("h0")) + node T_993 = or(T_974, T_992) + io.mulAddC_2 <= T_993 + node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) + node T_994 = bits(io.mulAddResult_3, 90, 45) + node T_995 = not(T_994) + node T_997 = mux(cyc_B4, T_995, UInt<1>("h0")) + zSigma1_B4 <= T_997 + node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) + node T_998 = bits(io.mulAddResult_3, 104, 47) + sigXNU_B3_CX <= T_998 + node T_999 = bits(io.mulAddResult_3, 104, 104) + node E_C1_div = eq(T_999, UInt<1>("h0")) + node T_1002 = eq(E_C1_div, UInt<1>("h0")) + node T_1003 = and(cyc_C1_div, T_1002) + node T_1004 = or(T_1003, cyc_C1_sqrt) + node T_1005 = bits(io.mulAddResult_3, 104, 51) + node T_1006 = not(T_1005) + node T_1008 = mux(T_1004, T_1006, UInt<1>("h0")) + node T_1009 = and(cyc_C1_div, E_C1_div) + node T_1011 = bits(io.mulAddResult_3, 102, 50) + node T_1012 = not(T_1011) + node T_1013 = cat(UInt<1>("h0"), T_1012) + node T_1015 = mux(T_1009, T_1013, UInt<1>("h0")) + node T_1016 = or(T_1008, T_1015) + zComplSigT_C1 <= T_1016 + node T_1017 = bits(io.mulAddResult_3, 104, 51) + node T_1018 = not(T_1017) + node T_1020 = mux(cyc_C1_sqrt, T_1018, UInt<1>("h0")) + zComplSigT_C1_sqrt <= T_1020 + node sigT_C1 = not(zComplSigT_C1) + node remT_E2 = bits(io.mulAddResult_3, 55, 0) + when cyc_B8_sqrt : + ESqrR1_B_sqrt <= ESqrR1_B8_sqrt + when cyc_B3 : + sigX1_B <= sigXNU_B3_CX + when cyc_B1 : + sqrSigma1_C <= sqrSigma1_B1 + node T_1021 = or(cyc_C6_sqrt, cyc_C5_div) + node T_1022 = or(T_1021, cyc_C3_sqrt) + when T_1022 : + sigXN_C <= sigXNU_B3_CX + when cyc_C5_sqrt : + node T_1023 = bits(sigXNU_B3_CX, 56, 26) + u_C_sqrt <= T_1023 + when cyc_C1 : + E_E_div <= E_C1_div + node T_1024 = bits(sigT_C1, 53, 1) + sigT_E <= T_1024 + node T_1025 = bits(sigT_C1, 0, 0) + extraT_E <= T_1025 + when cyc_E2 : + node T_1026 = bits(remT_E2, 55, 55) + node T_1027 = bits(remT_E2, 53, 53) + node T_1028 = mux(sqrtOp_PC, T_1026, T_1027) + isNegRemT_E <= T_1028 + node T_1029 = bits(remT_E2, 53, 0) + node T_1031 = eq(T_1029, UInt<1>("h0")) + node T_1033 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1034 = bits(remT_E2, 55, 54) + node T_1036 = eq(T_1034, UInt<1>("h0")) + node T_1037 = or(T_1033, T_1036) + node T_1038 = and(T_1031, T_1037) + trueEqX_E1 <= T_1038 + node T_1040 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1041 = and(T_1040, E_E_div) + node T_1043 = mux(T_1041, exp_PC, UInt<1>("h0")) + node T_1045 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1047 = eq(E_E_div, UInt<1>("h0")) + node T_1048 = and(T_1045, T_1047) + node T_1050 = mux(T_1048, expP1_PC, UInt<1>("h0")) + node T_1051 = or(T_1043, T_1050) + node T_1052 = shr(exp_PC, 1) + node T_1054 = add(T_1052, UInt<12>("h400")) + node T_1055 = tail(T_1054, 1) + node T_1057 = mux(sqrtOp_PC, T_1055, UInt<1>("h0")) + node sExpX_E = or(T_1051, T_1057) + node posExpX_E = bits(sExpX_E, 12, 0) + node T_1058 = not(posExpX_E) + node T_1059 = bits(T_1058, 12, 12) + node T_1060 = bits(T_1058, 11, 0) + node T_1061 = bits(T_1060, 11, 11) + node T_1062 = bits(T_1060, 10, 0) + node T_1063 = bits(T_1062, 10, 10) + node T_1064 = bits(T_1062, 9, 0) + node T_1065 = bits(T_1064, 9, 9) + node T_1066 = bits(T_1064, 8, 0) + node T_1068 = bits(T_1066, 8, 8) + node T_1069 = bits(T_1066, 7, 0) + node T_1071 = bits(T_1069, 7, 7) + node T_1072 = bits(T_1069, 6, 0) + node T_1074 = bits(T_1072, 6, 6) + node T_1075 = bits(T_1072, 5, 0) + node T_1078 = dshr(asSInt(UInt<65>("h10000000000000000")), T_1075) + node T_1079 = bits(T_1078, 63, 14) + node T_1080 = bits(T_1079, 31, 0) + node T_1083 = shl(UInt<16>("hffff"), 16) + node T_1084 = xor(UInt<32>("hffffffff"), T_1083) + node T_1085 = shr(T_1080, 16) + node T_1086 = and(T_1085, T_1084) + node T_1087 = bits(T_1080, 15, 0) + node T_1088 = shl(T_1087, 16) + node T_1089 = not(T_1084) + node T_1090 = and(T_1088, T_1089) + node T_1091 = or(T_1086, T_1090) + node T_1092 = bits(T_1084, 23, 0) + node T_1093 = shl(T_1092, 8) + node T_1094 = xor(T_1084, T_1093) + node T_1095 = shr(T_1091, 8) + node T_1096 = and(T_1095, T_1094) + node T_1097 = bits(T_1091, 23, 0) + node T_1098 = shl(T_1097, 8) + node T_1099 = not(T_1094) + node T_1100 = and(T_1098, T_1099) + node T_1101 = or(T_1096, T_1100) + node T_1102 = bits(T_1094, 27, 0) + node T_1103 = shl(T_1102, 4) + node T_1104 = xor(T_1094, T_1103) + node T_1105 = shr(T_1101, 4) + node T_1106 = and(T_1105, T_1104) + node T_1107 = bits(T_1101, 27, 0) + node T_1108 = shl(T_1107, 4) + node T_1109 = not(T_1104) + node T_1110 = and(T_1108, T_1109) + node T_1111 = or(T_1106, T_1110) + node T_1112 = bits(T_1104, 29, 0) + node T_1113 = shl(T_1112, 2) + node T_1114 = xor(T_1104, T_1113) + node T_1115 = shr(T_1111, 2) + node T_1116 = and(T_1115, T_1114) + node T_1117 = bits(T_1111, 29, 0) + node T_1118 = shl(T_1117, 2) + node T_1119 = not(T_1114) + node T_1120 = and(T_1118, T_1119) + node T_1121 = or(T_1116, T_1120) + node T_1122 = bits(T_1114, 30, 0) + node T_1123 = shl(T_1122, 1) + node T_1124 = xor(T_1114, T_1123) + node T_1125 = shr(T_1121, 1) + node T_1126 = and(T_1125, T_1124) + node T_1127 = bits(T_1121, 30, 0) + node T_1128 = shl(T_1127, 1) + node T_1129 = not(T_1124) + node T_1130 = and(T_1128, T_1129) + node T_1131 = or(T_1126, T_1130) + node T_1132 = bits(T_1079, 49, 32) + node T_1133 = bits(T_1132, 15, 0) + node T_1136 = shl(UInt<8>("hff"), 8) + node T_1137 = xor(UInt<16>("hffff"), T_1136) + node T_1138 = shr(T_1133, 8) + node T_1139 = and(T_1138, T_1137) + node T_1140 = bits(T_1133, 7, 0) + node T_1141 = shl(T_1140, 8) + node T_1142 = not(T_1137) + node T_1143 = and(T_1141, T_1142) + node T_1144 = or(T_1139, T_1143) + node T_1145 = bits(T_1137, 11, 0) + node T_1146 = shl(T_1145, 4) + node T_1147 = xor(T_1137, T_1146) + node T_1148 = shr(T_1144, 4) + node T_1149 = and(T_1148, T_1147) + node T_1150 = bits(T_1144, 11, 0) + node T_1151 = shl(T_1150, 4) + node T_1152 = not(T_1147) + node T_1153 = and(T_1151, T_1152) + node T_1154 = or(T_1149, T_1153) + node T_1155 = bits(T_1147, 13, 0) + node T_1156 = shl(T_1155, 2) + node T_1157 = xor(T_1147, T_1156) + node T_1158 = shr(T_1154, 2) + node T_1159 = and(T_1158, T_1157) + node T_1160 = bits(T_1154, 13, 0) + node T_1161 = shl(T_1160, 2) + node T_1162 = not(T_1157) + node T_1163 = and(T_1161, T_1162) + node T_1164 = or(T_1159, T_1163) + node T_1165 = bits(T_1157, 14, 0) + node T_1166 = shl(T_1165, 1) + node T_1167 = xor(T_1157, T_1166) + node T_1168 = shr(T_1164, 1) + node T_1169 = and(T_1168, T_1167) + node T_1170 = bits(T_1164, 14, 0) + node T_1171 = shl(T_1170, 1) + node T_1172 = not(T_1167) + node T_1173 = and(T_1171, T_1172) + node T_1174 = or(T_1169, T_1173) + node T_1175 = bits(T_1132, 17, 16) + node T_1176 = bits(T_1175, 0, 0) + node T_1177 = bits(T_1175, 1, 1) + node T_1178 = cat(T_1176, T_1177) + node T_1179 = cat(T_1174, T_1178) + node T_1180 = cat(T_1131, T_1179) + node T_1181 = not(T_1180) + node T_1182 = mux(T_1074, UInt<1>("h0"), T_1181) + node T_1183 = not(T_1182) + node T_1184 = not(T_1183) + node T_1185 = mux(T_1071, UInt<1>("h0"), T_1184) + node T_1186 = not(T_1185) + node T_1187 = not(T_1186) + node T_1188 = mux(T_1068, UInt<1>("h0"), T_1187) + node T_1189 = not(T_1188) + node T_1190 = not(T_1189) + node T_1191 = mux(T_1065, UInt<1>("h0"), T_1190) + node T_1192 = not(T_1191) + node T_1194 = cat(T_1192, UInt<3>("h7")) + node T_1195 = bits(T_1064, 9, 9) + node T_1196 = bits(T_1064, 8, 0) + node T_1197 = bits(T_1196, 8, 8) + node T_1198 = bits(T_1196, 7, 0) + node T_1199 = bits(T_1198, 7, 7) + node T_1200 = bits(T_1198, 6, 0) + node T_1201 = bits(T_1200, 6, 6) + node T_1202 = bits(T_1200, 5, 0) + node T_1204 = dshr(asSInt(UInt<65>("h10000000000000000")), T_1202) + node T_1205 = bits(T_1204, 2, 0) + node T_1206 = bits(T_1205, 1, 0) + node T_1207 = bits(T_1206, 0, 0) + node T_1208 = bits(T_1206, 1, 1) + node T_1209 = cat(T_1207, T_1208) + node T_1210 = bits(T_1205, 2, 2) + node T_1211 = cat(T_1209, T_1210) + node T_1213 = mux(T_1201, T_1211, UInt<1>("h0")) + node T_1215 = mux(T_1199, T_1213, UInt<1>("h0")) + node T_1217 = mux(T_1197, T_1215, UInt<1>("h0")) + node T_1219 = mux(T_1195, T_1217, UInt<1>("h0")) + node T_1220 = mux(T_1063, T_1194, T_1219) + node T_1222 = mux(T_1061, T_1220, UInt<1>("h0")) + node roundMask_E = mux(T_1059, T_1222, UInt<1>("h0")) + node T_1225 = cat(UInt<1>("h0"), roundMask_E) + node T_1226 = not(T_1225) + node T_1228 = cat(roundMask_E, UInt<1>("h1")) + node incrPosMask_E = and(T_1226, T_1228) + node T_1229 = shr(incrPosMask_E, 1) + node T_1230 = and(sigT_E, T_1229) + node hiRoundPosBitT_E = neq(T_1230, UInt<1>("h0")) + node T_1232 = shr(roundMask_E, 1) + node T_1233 = and(sigT_E, T_1232) + node all0sHiRoundExtraT_E = eq(T_1233, UInt<1>("h0")) + node T_1235 = not(sigT_E) + node T_1236 = shr(roundMask_E, 1) + node T_1237 = and(T_1235, T_1236) + node all1sHiRoundExtraT_E = eq(T_1237, UInt<1>("h0")) + node T_1239 = bits(roundMask_E, 0, 0) + node T_1241 = eq(T_1239, UInt<1>("h0")) + node T_1242 = or(T_1241, hiRoundPosBitT_E) + node all1sHiRoundT_E = and(T_1242, all1sHiRoundExtraT_E) + node T_1244 = add(UInt<54>("h0"), sigT_E) + node T_1245 = tail(T_1244, 1) + node T_1246 = add(T_1245, roundMagUp_PC) + node sigAdjT_E = tail(T_1246, 1) + node T_1248 = not(roundMask_E) + node T_1249 = cat(UInt<1>("h1"), T_1248) + node sigY0_E = and(sigAdjT_E, T_1249) + node T_1251 = cat(UInt<1>("h0"), roundMask_E) + node T_1252 = or(sigAdjT_E, T_1251) + node T_1254 = add(T_1252, UInt<1>("h1")) + node sigY1_E = tail(T_1254, 1) + node T_1256 = eq(isNegRemT_E, UInt<1>("h0")) + node T_1258 = eq(trueEqX_E1, UInt<1>("h0")) + node T_1259 = and(T_1256, T_1258) + node trueLtX_E1 = mux(sqrtOp_PC, T_1259, isNegRemT_E) + node T_1260 = bits(roundMask_E, 0, 0) + node T_1262 = eq(trueLtX_E1, UInt<1>("h0")) + node T_1263 = and(T_1260, T_1262) + node T_1264 = and(T_1263, all1sHiRoundExtraT_E) + node T_1265 = and(T_1264, extraT_E) + node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1265) + node T_1267 = eq(trueEqX_E1, UInt<1>("h0")) + node T_1269 = eq(extraT_E, UInt<1>("h0")) + node T_1270 = or(T_1267, T_1269) + node T_1272 = eq(all1sHiRoundExtraT_E, UInt<1>("h0")) + node anyRoundExtra_E1 = or(T_1270, T_1272) + node T_1273 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) + node T_1275 = eq(anyRoundExtra_E1, UInt<1>("h0")) + node T_1276 = and(T_1273, T_1275) + node roundEvenMask_E1 = mux(T_1276, incrPosMask_E, UInt<1>("h0")) + node T_1278 = and(roundMagDown_PC, extraT_E) + node T_1280 = eq(trueLtX_E1, UInt<1>("h0")) + node T_1281 = and(T_1278, T_1280) + node T_1282 = and(T_1281, all1sHiRoundT_E) + node T_1284 = eq(trueLtX_E1, UInt<1>("h0")) + node T_1285 = and(extraT_E, T_1284) + node T_1287 = eq(trueEqX_E1, UInt<1>("h0")) + node T_1288 = and(T_1285, T_1287) + node T_1290 = eq(all1sHiRoundT_E, UInt<1>("h0")) + node T_1291 = or(T_1288, T_1290) + node T_1292 = and(roundMagUp_PC, T_1291) + node T_1293 = or(T_1282, T_1292) + node T_1295 = eq(trueLtX_E1, UInt<1>("h0")) + node T_1296 = or(extraT_E, T_1295) + node T_1297 = bits(roundMask_E, 0, 0) + node T_1299 = eq(T_1297, UInt<1>("h0")) + node T_1300 = and(T_1296, T_1299) + node T_1301 = or(hiRoundPosBitT_E, T_1300) + node T_1303 = eq(trueLtX_E1, UInt<1>("h0")) + node T_1304 = and(extraT_E, T_1303) + node T_1305 = and(T_1304, all1sHiRoundExtraT_E) + node T_1306 = or(T_1301, T_1305) + node T_1307 = and(roundingMode_near_even_PC, T_1306) + node T_1308 = or(T_1293, T_1307) + node T_1309 = mux(T_1308, sigY1_E, sigY0_E) + node T_1310 = not(roundEvenMask_E1) + node sigY_E1 = and(T_1309, T_1310) + node fractY_E1 = bits(sigY_E1, 51, 0) + node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) + node T_1311 = bits(sigY_E1, 53, 53) + node T_1313 = eq(T_1311, UInt<1>("h0")) + node T_1315 = mux(T_1313, sExpX_E, UInt<1>("h0")) + node T_1316 = bits(sigY_E1, 53, 53) + node T_1318 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1319 = and(T_1316, T_1318) + node T_1320 = and(T_1319, E_E_div) + node T_1322 = mux(T_1320, expP1_PC, UInt<1>("h0")) + node T_1323 = or(T_1315, T_1322) + node T_1324 = bits(sigY_E1, 53, 53) + node T_1326 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1327 = and(T_1324, T_1326) + node T_1329 = eq(E_E_div, UInt<1>("h0")) + node T_1330 = and(T_1327, T_1329) + node T_1332 = mux(T_1330, expP2_PC, UInt<1>("h0")) + node T_1333 = or(T_1323, T_1332) + node T_1334 = bits(sigY_E1, 53, 53) + node T_1335 = and(T_1334, sqrtOp_PC) + node T_1336 = shr(expP2_PC, 1) + node T_1338 = add(T_1336, UInt<12>("h400")) + node T_1339 = tail(T_1338, 1) + node T_1341 = mux(T_1335, T_1339, UInt<1>("h0")) + node sExpY_E1 = or(T_1333, T_1341) + node expY_E1 = bits(sExpY_E1, 11, 0) + node T_1342 = bits(sExpY_E1, 13, 13) + node T_1344 = eq(T_1342, UInt<1>("h0")) + node T_1346 = bits(sExpY_E1, 12, 10) + node T_1347 = leq(UInt<3>("h3"), T_1346) + node overflowY_E1 = and(T_1344, T_1347) + node T_1348 = bits(sExpY_E1, 13, 13) + node T_1349 = bits(sExpY_E1, 12, 0) + node T_1351 = lt(T_1349, UInt<13>("h3ce")) + node totalUnderflowY_E1 = or(T_1348, T_1351) + node T_1353 = leq(posExpX_E, UInt<13>("h401")) + node T_1354 = and(T_1353, inexactY_E1) + node underflowY_E1 = or(totalUnderflowY_E1, T_1354) + node T_1356 = eq(isNaNB_PC, UInt<1>("h0")) + node T_1358 = eq(isZeroB_PC, UInt<1>("h0")) + node T_1359 = and(T_1356, T_1358) + node T_1360 = and(T_1359, sign_PC) + node T_1361 = and(isZeroA_PC, isZeroB_PC) + node T_1362 = and(isInfA_PC, isInfB_PC) + node T_1363 = or(T_1361, T_1362) + node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1360, T_1363) + node T_1365 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1366 = and(T_1365, isSigNaNA_PC) + node T_1367 = or(T_1366, isSigNaNB_PC) + node invalid_PC = or(T_1367, notSigNaN_invalid_PC) + node T_1369 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1371 = eq(isSpecialA_PC, UInt<1>("h0")) + node T_1372 = and(T_1369, T_1371) + node T_1374 = eq(isZeroA_PC, UInt<1>("h0")) + node T_1375 = and(T_1372, T_1374) + node infinity_PC = and(T_1375, isZeroB_PC) + node overflow_E1 = and(normalCase_PC, overflowY_E1) + node underflow_E1 = and(normalCase_PC, underflowY_E1) + node T_1376 = or(overflow_E1, underflow_E1) + node T_1377 = and(normalCase_PC, inexactY_E1) + node inexact_E1 = or(T_1376, T_1377) + node T_1378 = or(isZeroA_PC, isInfB_PC) + node T_1380 = eq(roundMagUp_PC, UInt<1>("h0")) + node T_1381 = and(totalUnderflowY_E1, T_1380) + node T_1382 = or(T_1378, T_1381) + node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1382) + node T_1383 = and(normalCase_PC, totalUnderflowY_E1) + node pegMinFiniteMagOut_E1 = and(T_1383, roundMagUp_PC) + node T_1385 = eq(overflowY_roundMagUp_PC, UInt<1>("h0")) + node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1385) + node T_1386 = or(isInfA_PC, isZeroB_PC) + node T_1387 = and(overflow_E1, overflowY_roundMagUp_PC) + node T_1388 = or(T_1386, T_1387) + node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1388) + node T_1390 = eq(sqrtOp_PC, UInt<1>("h0")) + node T_1391 = and(T_1390, isNaNA_PC) + node T_1392 = or(T_1391, isNaNB_PC) + node isNaNOut_PC = or(T_1392, notSigNaN_invalid_PC) + node T_1394 = eq(isNaNOut_PC, UInt<1>("h0")) + node T_1395 = and(isZeroB_PC, sign_PC) + node T_1396 = mux(sqrtOp_PC, T_1395, sign_PC) + node signOut_PC = and(T_1394, T_1396) + node T_1398 = not(UInt<12>("h1ff")) + node T_1400 = mux(notSpecial_isZeroOut_E1, T_1398, UInt<1>("h0")) + node T_1401 = not(T_1400) + node T_1402 = and(expY_E1, T_1401) + node T_1404 = not(UInt<12>("h3ce")) + node T_1406 = mux(pegMinFiniteMagOut_E1, T_1404, UInt<1>("h0")) + node T_1407 = not(T_1406) + node T_1408 = and(T_1402, T_1407) + node T_1410 = not(UInt<12>("hbff")) + node T_1412 = mux(pegMaxFiniteMagOut_E1, T_1410, UInt<1>("h0")) + node T_1413 = not(T_1412) + node T_1414 = and(T_1408, T_1413) + node T_1416 = not(UInt<12>("hdff")) + node T_1418 = mux(notNaN_isInfOut_E1, T_1416, UInt<1>("h0")) + node T_1419 = not(T_1418) + node T_1420 = and(T_1414, T_1419) + node T_1423 = mux(pegMinFiniteMagOut_E1, UInt<12>("h3ce"), UInt<1>("h0")) + node T_1424 = or(T_1420, T_1423) + node T_1427 = mux(pegMaxFiniteMagOut_E1, UInt<12>("hbff"), UInt<1>("h0")) + node T_1428 = or(T_1424, T_1427) + node T_1431 = mux(notNaN_isInfOut_E1, UInt<12>("hc00"), UInt<1>("h0")) + node T_1432 = or(T_1428, T_1431) + node T_1435 = mux(isNaNOut_PC, UInt<12>("he00"), UInt<1>("h0")) + node expOut_E1 = or(T_1432, T_1435) + node T_1436 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) + node T_1437 = or(T_1436, isNaNOut_PC) + node T_1439 = shl(UInt<1>("h1"), 51) + node T_1441 = mux(isNaNOut_PC, T_1439, UInt<1>("h0")) + node T_1442 = mux(T_1437, T_1441, fractY_E1) + node T_1443 = bits(pegMaxFiniteMagOut_E1, 0, 0) + node T_1446 = mux(T_1443, UInt<52>("hfffffffffffff"), UInt<52>("h0")) + node fractOut_E1 = or(T_1442, T_1446) + node T_1447 = cat(signOut_PC, expOut_E1) + node T_1448 = cat(T_1447, fractOut_E1) + io.out <= T_1448 + node T_1449 = cat(underflow_E1, inexact_E1) + node T_1450 = cat(invalid_PC, infinity_PC) + node T_1451 = cat(T_1450, overflow_E1) + node T_1452 = cat(T_1451, T_1449) + io.exceptionFlags <= T_1452 + + module Mul54 : input clk : Clock input reset : UInt<1> - output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} - + output io : { flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} + io is invalid - reg val_s1 : UInt<1>, clk - reg val_s2 : UInt<1>, clk - reg reg_a_s1 : UInt<54>, clk - reg reg_b_s1 : UInt<54>, clk - reg reg_a_s2 : UInt<54>, clk - reg reg_b_s2 : UInt<54>, clk - reg reg_result_s3 : UInt<105>, clk - val_s1 <= io.val_s0 @[DivSqrtRecF64.scala 104:12] - val_s2 <= val_s1 @[DivSqrtRecF64.scala 105:12] - when io.val_s0 : @[DivSqrtRecF64.scala 107:22] - when io.latch_a_s0 : @[DivSqrtRecF64.scala 108:30] - reg_a_s1 <= io.a_s0 @[DivSqrtRecF64.scala 109:22] - skip @[DivSqrtRecF64.scala 108:30] - when io.latch_b_s0 : @[DivSqrtRecF64.scala 111:30] - reg_b_s1 <= io.b_s0 @[DivSqrtRecF64.scala 112:22] - skip @[DivSqrtRecF64.scala 111:30] - skip @[DivSqrtRecF64.scala 107:22] - when val_s1 : @[DivSqrtRecF64.scala 116:19] - reg_a_s2 <= reg_a_s1 @[DivSqrtRecF64.scala 117:18] - reg_b_s2 <= reg_b_s1 @[DivSqrtRecF64.scala 118:18] - skip @[DivSqrtRecF64.scala 116:19] - when val_s2 : @[DivSqrtRecF64.scala 121:19] - node T_14 = mul(reg_a_s2, reg_b_s2) @[DivSqrtRecF64.scala 122:36] - node T_15 = bits(T_14, 104, 0) @[DivSqrtRecF64.scala 122:47] - node T_16 = add(T_15, io.c_s2) @[DivSqrtRecF64.scala 122:55] - node T_17 = tail(T_16, 1) @[DivSqrtRecF64.scala 122:55] - reg_result_s3 <= T_17 @[DivSqrtRecF64.scala 122:23] - skip @[DivSqrtRecF64.scala 121:19] - io.result_s3 <= reg_result_s3 @[DivSqrtRecF64.scala 125:18] - - module DivSqrtRecF64 : + reg val_s1 : UInt<1>, clk with : + reset => (UInt<1>("h0"), val_s1) + reg val_s2 : UInt<1>, clk with : + reset => (UInt<1>("h0"), val_s2) + reg reg_a_s1 : UInt<54>, clk with : + reset => (UInt<1>("h0"), reg_a_s1) + reg reg_b_s1 : UInt<54>, clk with : + reset => (UInt<1>("h0"), reg_b_s1) + reg reg_a_s2 : UInt<54>, clk with : + reset => (UInt<1>("h0"), reg_a_s2) + reg reg_b_s2 : UInt<54>, clk with : + reset => (UInt<1>("h0"), reg_b_s2) + reg reg_result_s3 : UInt<105>, clk with : + reset => (UInt<1>("h0"), reg_result_s3) + val_s1 <= io.val_s0 + val_s2 <= val_s1 + when io.val_s0 : + when io.latch_a_s0 : + reg_a_s1 <= io.a_s0 + when io.latch_b_s0 : + reg_b_s1 <= io.b_s0 + when val_s1 : + reg_a_s2 <= reg_a_s1 + reg_b_s2 <= reg_b_s1 + when val_s2 : + node T_14 = mul(reg_a_s2, reg_b_s2) + node T_15 = bits(T_14, 104, 0) + node T_16 = add(T_15, io.c_s2) + node T_17 = tail(T_16, 1) + reg_result_s3 <= T_17 + io.result_s3 <= reg_result_s3 + + module DivSqrtRecF64 : input clk : Clock input reset : UInt<1> - output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} - + output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} + io is invalid - inst ds of DivSqrtRecF64_mulAddZ31 @[DivSqrtRecF64.scala 59:20] + inst ds of DivSqrtRecF64_mulAddZ31 ds.io is invalid ds.clk <= clk ds.reset <= reset - io.inReady_div <= ds.io.inReady_div @[DivSqrtRecF64.scala 61:20] - io.inReady_sqrt <= ds.io.inReady_sqrt @[DivSqrtRecF64.scala 62:21] - ds.io.inValid <= io.inValid @[DivSqrtRecF64.scala 63:19] - ds.io.sqrtOp <= io.sqrtOp @[DivSqrtRecF64.scala 64:18] - ds.io.a <= io.a @[DivSqrtRecF64.scala 65:13] - ds.io.b <= io.b @[DivSqrtRecF64.scala 66:13] - ds.io.roundingMode <= io.roundingMode @[DivSqrtRecF64.scala 67:24] - io.outValid_div <= ds.io.outValid_div @[DivSqrtRecF64.scala 68:21] - io.outValid_sqrt <= ds.io.outValid_sqrt @[DivSqrtRecF64.scala 69:22] - io.out <= ds.io.out @[DivSqrtRecF64.scala 70:12] - io.exceptionFlags <= ds.io.exceptionFlags @[DivSqrtRecF64.scala 71:23] - inst mul of Mul54 @[DivSqrtRecF64.scala 73:21] + io.inReady_div <= ds.io.inReady_div + io.inReady_sqrt <= ds.io.inReady_sqrt + ds.io.inValid <= io.inValid + ds.io.sqrtOp <= io.sqrtOp + ds.io.a <= io.a + ds.io.b <= io.b + ds.io.roundingMode <= io.roundingMode + io.outValid_div <= ds.io.outValid_div + io.outValid_sqrt <= ds.io.outValid_sqrt + io.out <= ds.io.out + io.exceptionFlags <= ds.io.exceptionFlags + inst mul of Mul54 mul.io is invalid mul.clk <= clk mul.reset <= reset - node T_11 = bits(ds.io.usingMulAdd, 0, 0) @[DivSqrtRecF64.scala 75:39] - mul.io.val_s0 <= T_11 @[DivSqrtRecF64.scala 75:19] - mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 @[DivSqrtRecF64.scala 76:23] - mul.io.a_s0 <= ds.io.mulAddA_0 @[DivSqrtRecF64.scala 77:17] - mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 @[DivSqrtRecF64.scala 78:23] - mul.io.b_s0 <= ds.io.mulAddB_0 @[DivSqrtRecF64.scala 79:17] - mul.io.c_s2 <= ds.io.mulAddC_2 @[DivSqrtRecF64.scala 80:17] - ds.io.mulAddResult_3 <= mul.io.result_s3 @[DivSqrtRecF64.scala 81:26] - - module RecFNToRecFN_2 : + node T_11 = bits(ds.io.usingMulAdd, 0, 0) + mul.io.val_s0 <= T_11 + mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 + mul.io.a_s0 <= ds.io.mulAddA_0 + mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 + mul.io.b_s0 <= ds.io.mulAddB_0 + mul.io.c_s2 <= ds.io.mulAddC_2 + ds.io.mulAddResult_3 <= mul.io.result_s3 + + module RecFNToRecFN_2 : input clk : Clock input reset : UInt<1> - output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - + output io : { flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + io is invalid - node T_4 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] - node T_5 = bits(T_4, 11, 9) @[rawFNFromRecFN.scala 51:29] - node T_7 = eq(T_5, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] - node T_8 = bits(T_4, 11, 10) @[rawFNFromRecFN.scala 52:29] - node T_10 = eq(T_8, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] - wire T_18 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] - T_18 is invalid @[rawFNFromRecFN.scala 54:23] - node T_25 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] - T_18.sign <= T_25 @[rawFNFromRecFN.scala 55:18] - node T_26 = bits(T_4, 9, 9) @[rawFNFromRecFN.scala 56:40] - node T_27 = and(T_10, T_26) @[rawFNFromRecFN.scala 56:32] - T_18.isNaN <= T_27 @[rawFNFromRecFN.scala 56:19] - node T_28 = bits(T_4, 9, 9) @[rawFNFromRecFN.scala 57:40] - node T_30 = eq(T_28, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] - node T_31 = and(T_10, T_30) @[rawFNFromRecFN.scala 57:32] - T_18.isInf <= T_31 @[rawFNFromRecFN.scala 57:19] - T_18.isZero <= T_7 @[rawFNFromRecFN.scala 58:20] - node T_32 = cvt(T_4) @[rawFNFromRecFN.scala 59:25] - T_18.sExp <= T_32 @[rawFNFromRecFN.scala 59:18] - node T_35 = eq(T_7, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] - node T_36 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] - node T_38 = cat(T_36, UInt<2>("h00")) @[Cat.scala 20:58] - node T_39 = cat(UInt<1>("h00"), T_35) @[Cat.scala 20:58] - node T_40 = cat(T_39, T_38) @[Cat.scala 20:58] - T_18.sig <= T_40 @[rawFNFromRecFN.scala 60:17] - node T_42 = add(T_18.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] - wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] - outRawFloat is invalid @[resizeRawFN.scala 51:23] - outRawFloat.sign <= T_18.sign @[resizeRawFN.scala 52:20] - outRawFloat.isNaN <= T_18.isNaN @[resizeRawFN.scala 53:20] - outRawFloat.isInf <= T_18.isInf @[resizeRawFN.scala 54:20] - outRawFloat.isZero <= T_18.isZero @[resizeRawFN.scala 55:20] - node T_57 = lt(T_42, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] - node T_58 = bits(T_42, 12, 9) @[resizeRawFN.scala 61:33] - node T_60 = neq(T_58, UInt<1>("h00")) @[resizeRawFN.scala 61:65] - node T_65 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_67 = cat(T_65, UInt<2>("h00")) @[Cat.scala 20:58] - node T_68 = bits(T_42, 8, 0) @[resizeRawFN.scala 63:33] - node T_69 = mux(T_60, T_67, T_68) @[resizeRawFN.scala 61:25] - node T_70 = cat(T_57, T_69) @[Cat.scala 20:58] - node T_71 = asSInt(T_70) @[resizeRawFN.scala 65:20] - outRawFloat.sExp <= T_71 @[resizeRawFN.scala 56:18] - node T_72 = bits(T_18.sig, 55, 30) @[resizeRawFN.scala 71:28] - node T_73 = bits(T_18.sig, 29, 0) @[resizeRawFN.scala 72:28] - node T_75 = neq(T_73, UInt<1>("h00")) @[resizeRawFN.scala 72:56] - node T_76 = cat(T_72, T_75) @[Cat.scala 20:58] - outRawFloat.sig <= T_76 @[resizeRawFN.scala 67:17] - node T_77 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] - node T_79 = eq(T_77, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] - node invalidExc = and(outRawFloat.isNaN, T_79) @[RoundRawFNToRecFN.scala 61:46] - inst RoundRawFNToRecFN_1_1 of RoundRawFNToRecFN @[RecFNToRecFN.scala 102:19] + node T_4 = bits(io.in, 63, 52) + node T_5 = bits(T_4, 11, 9) + node T_7 = eq(T_5, UInt<1>("h0")) + node T_8 = bits(T_4, 11, 10) + node T_10 = eq(T_8, UInt<2>("h3")) + wire T_18 : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} + T_18 is invalid + node T_25 = bits(io.in, 64, 64) + T_18.sign <= T_25 + node T_26 = bits(T_4, 9, 9) + node T_27 = and(T_10, T_26) + T_18.isNaN <= T_27 + node T_28 = bits(T_4, 9, 9) + node T_30 = eq(T_28, UInt<1>("h0")) + node T_31 = and(T_10, T_30) + T_18.isInf <= T_31 + T_18.isZero <= T_7 + node T_32 = cvt(T_4) + T_18.sExp <= T_32 + node T_35 = eq(T_7, UInt<1>("h0")) + node T_36 = bits(io.in, 51, 0) + node T_38 = cat(T_36, UInt<2>("h0")) + node T_39 = cat(UInt<1>("h0"), T_35) + node T_40 = cat(T_39, T_38) + T_18.sig <= T_40 + node T_42 = add(T_18.sExp, asSInt(UInt<12>("h900"))) + wire outRawFloat : { sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} + outRawFloat is invalid + outRawFloat.sign <= T_18.sign + outRawFloat.isNaN <= T_18.isNaN + outRawFloat.isInf <= T_18.isInf + outRawFloat.isZero <= T_18.isZero + node T_57 = lt(T_42, asSInt(UInt<1>("h0"))) + node T_58 = bits(T_42, 12, 9) + node T_60 = neq(T_58, UInt<1>("h0")) + node T_65 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_67 = cat(T_65, UInt<2>("h0")) + node T_68 = bits(T_42, 8, 0) + node T_69 = mux(T_60, T_67, T_68) + node T_70 = cat(T_57, T_69) + node T_71 = asSInt(T_70) + outRawFloat.sExp <= T_71 + node T_72 = bits(T_18.sig, 55, 30) + node T_73 = bits(T_18.sig, 29, 0) + node T_75 = neq(T_73, UInt<1>("h0")) + node T_76 = cat(T_72, T_75) + outRawFloat.sig <= T_76 + node T_77 = bits(outRawFloat.sig, 24, 24) + node T_79 = eq(T_77, UInt<1>("h0")) + node invalidExc = and(outRawFloat.isNaN, T_79) + inst RoundRawFNToRecFN_1_1 of RoundRawFNToRecFN RoundRawFNToRecFN_1_1.io is invalid RoundRawFNToRecFN_1_1.clk <= clk RoundRawFNToRecFN_1_1.reset <= reset - RoundRawFNToRecFN_1_1.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] - RoundRawFNToRecFN_1_1.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] - RoundRawFNToRecFN_1_1.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] - RoundRawFNToRecFN_1_1.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] - io.out <= RoundRawFNToRecFN_1_1.io.out @[RecFNToRecFN.scala 107:16] - io.exceptionFlags <= RoundRawFNToRecFN_1_1.io.exceptionFlags @[RecFNToRecFN.scala 108:27] - - module FPU : + RoundRawFNToRecFN_1_1.io.invalidExc <= invalidExc + RoundRawFNToRecFN_1_1.io.infiniteExc <= UInt<1>("h0") + RoundRawFNToRecFN_1_1.io.in <- outRawFloat + RoundRawFNToRecFN_1_1.io.roundingMode <= io.roundingMode + io.out <= RoundRawFNToRecFN_1_1.io.out + io.exceptionFlags <= RoundRawFNToRecFN_1_1.io.exceptionFlags + + module FPU : input clk : Clock input reset : UInt<1> - output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - + output io : { flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} + io is invalid - reg ex_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg ex_reg_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) ex_reg_valid <= io.valid - node req_valid = or(ex_reg_valid, io.cp_req.valid) @[fpu.scala 493:32] - reg ex_reg_inst : UInt<32>, clk - when io.valid : @[Reg.scala 29:19] - ex_reg_inst <= io.inst @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) @[Decoupled.scala 21:42] - node T_194 = eq(io.killx, UInt<1>("h00")) @[fpu.scala 496:48] - node T_195 = and(ex_reg_valid, T_194) @[fpu.scala 496:45] - node T_196 = or(T_195, ex_cp_valid) @[fpu.scala 496:58] - reg mem_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node req_valid = or(ex_reg_valid, io.cp_req.valid) + reg ex_reg_inst : UInt<32>, clk with : + reset => (UInt<1>("h0"), ex_reg_inst) + when io.valid : + ex_reg_inst <= io.inst + node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) + node T_194 = eq(io.killx, UInt<1>("h0")) + node T_195 = and(ex_reg_valid, T_194) + node T_196 = or(T_195, ex_cp_valid) + reg mem_reg_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) mem_reg_valid <= T_196 - reg mem_reg_inst : UInt<32>, clk - when ex_reg_valid : @[Reg.scala 29:19] - mem_reg_inst <= ex_reg_inst @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg mem_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg mem_reg_inst : UInt<32>, clk with : + reset => (UInt<1>("h0"), mem_reg_inst) + when ex_reg_valid : + mem_reg_inst <= ex_reg_inst + reg mem_cp_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) mem_cp_valid <= ex_cp_valid - node T_199 = or(io.killm, io.nack_mem) @[fpu.scala 499:25] - node T_201 = eq(mem_cp_valid, UInt<1>("h00")) @[fpu.scala 499:44] - node killm = and(T_199, T_201) @[fpu.scala 499:41] - node T_203 = eq(killm, UInt<1>("h00")) @[fpu.scala 500:49] - node T_204 = or(T_203, mem_cp_valid) @[fpu.scala 500:56] - node T_205 = and(mem_reg_valid, T_204) @[fpu.scala 500:45] - reg wb_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_199 = or(io.killm, io.nack_mem) + node T_201 = eq(mem_cp_valid, UInt<1>("h0")) + node killm = and(T_199, T_201) + node T_203 = eq(killm, UInt<1>("h0")) + node T_204 = or(T_203, mem_cp_valid) + node T_205 = and(mem_reg_valid, T_204) + reg wb_reg_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) wb_reg_valid <= T_205 - reg wb_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg wb_cp_valid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) wb_cp_valid <= mem_cp_valid - inst fp_decoder of FPUDecoder @[fpu.scala 503:26] + inst fp_decoder of FPUDecoder fp_decoder.io is invalid fp_decoder.clk <= clk fp_decoder.reset <= reset - fp_decoder.io.inst <= io.inst @[fpu.scala 504:22] - wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} @[fpu.scala 506:21] - cp_ctrl is invalid @[fpu.scala 506:21] - cp_ctrl <- io.cp_req.bits @[fpu.scala 507:11] - io.cp_resp.valid <= UInt<1>("h00") @[fpu.scala 508:20] - io.cp_resp.bits.data <= UInt<1>("h00") @[fpu.scala 509:24] - reg T_245 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when io.valid : @[Reg.scala 29:19] - T_245 <- fp_decoder.io.sigs @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node ex_ctrl = mux(ex_cp_valid, cp_ctrl, T_245) @[fpu.scala 512:20] - reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when req_valid : @[Reg.scala 29:19] - mem_ctrl <- ex_ctrl @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk - when mem_reg_valid : @[Reg.scala 29:19] - wb_ctrl <- mem_ctrl @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg load_wb : UInt<1>, clk + fp_decoder.io.inst <= io.inst + wire cp_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} + cp_ctrl is invalid + cp_ctrl <- io.cp_req.bits + io.cp_resp.valid <= UInt<1>("h0") + io.cp_resp.bits.data <= UInt<1>("h0") + reg T_245 : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : + reset => (UInt<1>("h0"), T_245) + when io.valid : + T_245 <- fp_decoder.io.sigs + node ex_ctrl = mux(ex_cp_valid, cp_ctrl, T_245) + reg mem_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : + reset => (UInt<1>("h0"), mem_ctrl) + when req_valid : + mem_ctrl <- ex_ctrl + reg wb_ctrl : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk with : + reset => (UInt<1>("h0"), wb_ctrl) + when mem_reg_valid : + wb_ctrl <- mem_ctrl + reg load_wb : UInt<1>, clk with : + reset => (UInt<1>("h0"), load_wb) load_wb <= io.dmem_resp_val - node T_314 = bits(io.dmem_resp_type, 0, 0) @[fpu.scala 518:52] - node T_316 = eq(T_314, UInt<1>("h00")) @[fpu.scala 518:34] - reg load_wb_single : UInt<1>, clk - when io.dmem_resp_val : @[Reg.scala 29:19] - load_wb_single <= T_316 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg load_wb_data : UInt<64>, clk - when io.dmem_resp_val : @[Reg.scala 29:19] - load_wb_data <= io.dmem_resp_data @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg load_wb_tag : UInt<5>, clk - when io.dmem_resp_val : @[Reg.scala 29:19] - load_wb_tag <= io.dmem_resp_tag @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_317 = bits(load_wb_data, 31, 31) @[recFNFromFN.scala 47:22] - node T_318 = bits(load_wb_data, 30, 23) @[recFNFromFN.scala 48:23] - node T_319 = bits(load_wb_data, 22, 0) @[recFNFromFN.scala 49:25] - node T_321 = eq(T_318, UInt<1>("h00")) @[recFNFromFN.scala 51:34] - node T_323 = eq(T_319, UInt<1>("h00")) @[recFNFromFN.scala 52:38] - node T_324 = and(T_321, T_323) @[recFNFromFN.scala 53:34] - node T_325 = shl(T_319, 9) @[recFNFromFN.scala 56:26] - node T_326 = bits(T_325, 31, 16) @[CircuitMath.scala 26:17] - node T_327 = bits(T_325, 15, 0) @[CircuitMath.scala 27:17] - node T_329 = neq(T_326, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_330 = bits(T_326, 15, 8) @[CircuitMath.scala 26:17] - node T_331 = bits(T_326, 7, 0) @[CircuitMath.scala 27:17] - node T_333 = neq(T_330, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_334 = bits(T_330, 7, 4) @[CircuitMath.scala 26:17] - node T_335 = bits(T_330, 3, 0) @[CircuitMath.scala 27:17] - node T_337 = neq(T_334, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_338 = bits(T_334, 3, 3) @[CircuitMath.scala 23:12] - node T_340 = bits(T_334, 2, 2) @[CircuitMath.scala 23:12] - node T_342 = bits(T_334, 1, 1) @[CircuitMath.scala 21:8] - node T_343 = shl(T_342, 0) @[CircuitMath.scala 23:10] - node T_344 = mux(T_340, UInt<2>("h02"), T_343) @[CircuitMath.scala 23:10] - node T_345 = mux(T_338, UInt<2>("h03"), T_344) @[CircuitMath.scala 23:10] - node T_346 = bits(T_335, 3, 3) @[CircuitMath.scala 23:12] - node T_348 = bits(T_335, 2, 2) @[CircuitMath.scala 23:12] - node T_350 = bits(T_335, 1, 1) @[CircuitMath.scala 21:8] - node T_351 = shl(T_350, 0) @[CircuitMath.scala 23:10] - node T_352 = mux(T_348, UInt<2>("h02"), T_351) @[CircuitMath.scala 23:10] - node T_353 = mux(T_346, UInt<2>("h03"), T_352) @[CircuitMath.scala 23:10] - node T_354 = mux(T_337, T_345, T_353) @[CircuitMath.scala 29:21] - node T_355 = cat(T_337, T_354) @[Cat.scala 20:58] - node T_356 = bits(T_331, 7, 4) @[CircuitMath.scala 26:17] - node T_357 = bits(T_331, 3, 0) @[CircuitMath.scala 27:17] - node T_359 = neq(T_356, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_360 = bits(T_356, 3, 3) @[CircuitMath.scala 23:12] - node T_362 = bits(T_356, 2, 2) @[CircuitMath.scala 23:12] - node T_364 = bits(T_356, 1, 1) @[CircuitMath.scala 21:8] - node T_365 = shl(T_364, 0) @[CircuitMath.scala 23:10] - node T_366 = mux(T_362, UInt<2>("h02"), T_365) @[CircuitMath.scala 23:10] - node T_367 = mux(T_360, UInt<2>("h03"), T_366) @[CircuitMath.scala 23:10] - node T_368 = bits(T_357, 3, 3) @[CircuitMath.scala 23:12] - node T_370 = bits(T_357, 2, 2) @[CircuitMath.scala 23:12] - node T_372 = bits(T_357, 1, 1) @[CircuitMath.scala 21:8] - node T_373 = shl(T_372, 0) @[CircuitMath.scala 23:10] - node T_374 = mux(T_370, UInt<2>("h02"), T_373) @[CircuitMath.scala 23:10] - node T_375 = mux(T_368, UInt<2>("h03"), T_374) @[CircuitMath.scala 23:10] - node T_376 = mux(T_359, T_367, T_375) @[CircuitMath.scala 29:21] - node T_377 = cat(T_359, T_376) @[Cat.scala 20:58] - node T_378 = mux(T_333, T_355, T_377) @[CircuitMath.scala 29:21] - node T_379 = cat(T_333, T_378) @[Cat.scala 20:58] - node T_380 = bits(T_327, 15, 8) @[CircuitMath.scala 26:17] - node T_381 = bits(T_327, 7, 0) @[CircuitMath.scala 27:17] - node T_383 = neq(T_380, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_384 = bits(T_380, 7, 4) @[CircuitMath.scala 26:17] - node T_385 = bits(T_380, 3, 0) @[CircuitMath.scala 27:17] - node T_387 = neq(T_384, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_388 = bits(T_384, 3, 3) @[CircuitMath.scala 23:12] - node T_390 = bits(T_384, 2, 2) @[CircuitMath.scala 23:12] - node T_392 = bits(T_384, 1, 1) @[CircuitMath.scala 21:8] - node T_393 = shl(T_392, 0) @[CircuitMath.scala 23:10] - node T_394 = mux(T_390, UInt<2>("h02"), T_393) @[CircuitMath.scala 23:10] - node T_395 = mux(T_388, UInt<2>("h03"), T_394) @[CircuitMath.scala 23:10] - node T_396 = bits(T_385, 3, 3) @[CircuitMath.scala 23:12] - node T_398 = bits(T_385, 2, 2) @[CircuitMath.scala 23:12] - node T_400 = bits(T_385, 1, 1) @[CircuitMath.scala 21:8] - node T_401 = shl(T_400, 0) @[CircuitMath.scala 23:10] - node T_402 = mux(T_398, UInt<2>("h02"), T_401) @[CircuitMath.scala 23:10] - node T_403 = mux(T_396, UInt<2>("h03"), T_402) @[CircuitMath.scala 23:10] - node T_404 = mux(T_387, T_395, T_403) @[CircuitMath.scala 29:21] - node T_405 = cat(T_387, T_404) @[Cat.scala 20:58] - node T_406 = bits(T_381, 7, 4) @[CircuitMath.scala 26:17] - node T_407 = bits(T_381, 3, 0) @[CircuitMath.scala 27:17] - node T_409 = neq(T_406, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_410 = bits(T_406, 3, 3) @[CircuitMath.scala 23:12] - node T_412 = bits(T_406, 2, 2) @[CircuitMath.scala 23:12] - node T_414 = bits(T_406, 1, 1) @[CircuitMath.scala 21:8] - node T_415 = shl(T_414, 0) @[CircuitMath.scala 23:10] - node T_416 = mux(T_412, UInt<2>("h02"), T_415) @[CircuitMath.scala 23:10] - node T_417 = mux(T_410, UInt<2>("h03"), T_416) @[CircuitMath.scala 23:10] - node T_418 = bits(T_407, 3, 3) @[CircuitMath.scala 23:12] - node T_420 = bits(T_407, 2, 2) @[CircuitMath.scala 23:12] - node T_422 = bits(T_407, 1, 1) @[CircuitMath.scala 21:8] - node T_423 = shl(T_422, 0) @[CircuitMath.scala 23:10] - node T_424 = mux(T_420, UInt<2>("h02"), T_423) @[CircuitMath.scala 23:10] - node T_425 = mux(T_418, UInt<2>("h03"), T_424) @[CircuitMath.scala 23:10] - node T_426 = mux(T_409, T_417, T_425) @[CircuitMath.scala 29:21] - node T_427 = cat(T_409, T_426) @[Cat.scala 20:58] - node T_428 = mux(T_383, T_405, T_427) @[CircuitMath.scala 29:21] - node T_429 = cat(T_383, T_428) @[Cat.scala 20:58] - node T_430 = mux(T_329, T_379, T_429) @[CircuitMath.scala 29:21] - node T_431 = cat(T_329, T_430) @[Cat.scala 20:58] - node T_432 = not(T_431) @[recFNFromFN.scala 56:13] - node T_433 = dshl(T_319, T_432) @[recFNFromFN.scala 58:25] - node T_434 = bits(T_433, 21, 0) @[recFNFromFN.scala 58:37] - node T_436 = cat(T_434, UInt<1>("h00")) @[Cat.scala 20:58] - node T_441 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 33:12] - node T_442 = xor(T_432, T_441) @[recFNFromFN.scala 62:27] - node T_443 = mux(T_321, T_442, T_318) @[recFNFromFN.scala 61:16] - node T_447 = mux(T_321, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] - node T_448 = or(UInt<8>("h080"), T_447) @[recFNFromFN.scala 64:42] - node T_449 = add(T_443, T_448) @[recFNFromFN.scala 64:15] - node T_450 = tail(T_449, 1) @[recFNFromFN.scala 64:15] - node T_451 = bits(T_450, 8, 7) @[recFNFromFN.scala 67:25] - node T_453 = eq(T_451, UInt<2>("h03")) @[recFNFromFN.scala 67:50] - node T_455 = eq(T_323, UInt<1>("h00")) @[recFNFromFN.scala 68:17] - node T_456 = and(T_453, T_455) @[recFNFromFN.scala 67:63] - node T_457 = bits(T_324, 0, 0) @[Bitwise.scala 33:15] - node T_460 = mux(T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_461 = shl(T_460, 6) @[recFNFromFN.scala 71:45] - node T_462 = not(T_461) @[recFNFromFN.scala 71:28] - node T_463 = and(T_450, T_462) @[recFNFromFN.scala 71:26] - node T_464 = shl(T_456, 6) @[recFNFromFN.scala 72:22] - node T_465 = or(T_463, T_464) @[recFNFromFN.scala 71:64] - node T_466 = mux(T_321, T_436, T_319) @[recFNFromFN.scala 73:27] - node T_467 = cat(T_317, T_465) @[Cat.scala 20:58] - node rec_s = cat(T_467, T_466) @[Cat.scala 20:58] - node T_468 = bits(load_wb_data, 63, 63) @[recFNFromFN.scala 47:22] - node T_469 = bits(load_wb_data, 62, 52) @[recFNFromFN.scala 48:23] - node T_470 = bits(load_wb_data, 51, 0) @[recFNFromFN.scala 49:25] - node T_472 = eq(T_469, UInt<1>("h00")) @[recFNFromFN.scala 51:34] - node T_474 = eq(T_470, UInt<1>("h00")) @[recFNFromFN.scala 52:38] - node T_475 = and(T_472, T_474) @[recFNFromFN.scala 53:34] - node T_476 = shl(T_470, 12) @[recFNFromFN.scala 56:26] - node T_477 = bits(T_476, 63, 32) @[CircuitMath.scala 26:17] - node T_478 = bits(T_476, 31, 0) @[CircuitMath.scala 27:17] - node T_480 = neq(T_477, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_481 = bits(T_477, 31, 16) @[CircuitMath.scala 26:17] - node T_482 = bits(T_477, 15, 0) @[CircuitMath.scala 27:17] - node T_484 = neq(T_481, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_485 = bits(T_481, 15, 8) @[CircuitMath.scala 26:17] - node T_486 = bits(T_481, 7, 0) @[CircuitMath.scala 27:17] - node T_488 = neq(T_485, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_489 = bits(T_485, 7, 4) @[CircuitMath.scala 26:17] - node T_490 = bits(T_485, 3, 0) @[CircuitMath.scala 27:17] - node T_492 = neq(T_489, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_493 = bits(T_489, 3, 3) @[CircuitMath.scala 23:12] - node T_495 = bits(T_489, 2, 2) @[CircuitMath.scala 23:12] - node T_497 = bits(T_489, 1, 1) @[CircuitMath.scala 21:8] - node T_498 = shl(T_497, 0) @[CircuitMath.scala 23:10] - node T_499 = mux(T_495, UInt<2>("h02"), T_498) @[CircuitMath.scala 23:10] - node T_500 = mux(T_493, UInt<2>("h03"), T_499) @[CircuitMath.scala 23:10] - node T_501 = bits(T_490, 3, 3) @[CircuitMath.scala 23:12] - node T_503 = bits(T_490, 2, 2) @[CircuitMath.scala 23:12] - node T_505 = bits(T_490, 1, 1) @[CircuitMath.scala 21:8] - node T_506 = shl(T_505, 0) @[CircuitMath.scala 23:10] - node T_507 = mux(T_503, UInt<2>("h02"), T_506) @[CircuitMath.scala 23:10] - node T_508 = mux(T_501, UInt<2>("h03"), T_507) @[CircuitMath.scala 23:10] - node T_509 = mux(T_492, T_500, T_508) @[CircuitMath.scala 29:21] - node T_510 = cat(T_492, T_509) @[Cat.scala 20:58] - node T_511 = bits(T_486, 7, 4) @[CircuitMath.scala 26:17] - node T_512 = bits(T_486, 3, 0) @[CircuitMath.scala 27:17] - node T_514 = neq(T_511, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_515 = bits(T_511, 3, 3) @[CircuitMath.scala 23:12] - node T_517 = bits(T_511, 2, 2) @[CircuitMath.scala 23:12] - node T_519 = bits(T_511, 1, 1) @[CircuitMath.scala 21:8] - node T_520 = shl(T_519, 0) @[CircuitMath.scala 23:10] - node T_521 = mux(T_517, UInt<2>("h02"), T_520) @[CircuitMath.scala 23:10] - node T_522 = mux(T_515, UInt<2>("h03"), T_521) @[CircuitMath.scala 23:10] - node T_523 = bits(T_512, 3, 3) @[CircuitMath.scala 23:12] - node T_525 = bits(T_512, 2, 2) @[CircuitMath.scala 23:12] - node T_527 = bits(T_512, 1, 1) @[CircuitMath.scala 21:8] - node T_528 = shl(T_527, 0) @[CircuitMath.scala 23:10] - node T_529 = mux(T_525, UInt<2>("h02"), T_528) @[CircuitMath.scala 23:10] - node T_530 = mux(T_523, UInt<2>("h03"), T_529) @[CircuitMath.scala 23:10] - node T_531 = mux(T_514, T_522, T_530) @[CircuitMath.scala 29:21] - node T_532 = cat(T_514, T_531) @[Cat.scala 20:58] - node T_533 = mux(T_488, T_510, T_532) @[CircuitMath.scala 29:21] - node T_534 = cat(T_488, T_533) @[Cat.scala 20:58] - node T_535 = bits(T_482, 15, 8) @[CircuitMath.scala 26:17] - node T_536 = bits(T_482, 7, 0) @[CircuitMath.scala 27:17] - node T_538 = neq(T_535, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_539 = bits(T_535, 7, 4) @[CircuitMath.scala 26:17] - node T_540 = bits(T_535, 3, 0) @[CircuitMath.scala 27:17] - node T_542 = neq(T_539, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_543 = bits(T_539, 3, 3) @[CircuitMath.scala 23:12] - node T_545 = bits(T_539, 2, 2) @[CircuitMath.scala 23:12] - node T_547 = bits(T_539, 1, 1) @[CircuitMath.scala 21:8] - node T_548 = shl(T_547, 0) @[CircuitMath.scala 23:10] - node T_549 = mux(T_545, UInt<2>("h02"), T_548) @[CircuitMath.scala 23:10] - node T_550 = mux(T_543, UInt<2>("h03"), T_549) @[CircuitMath.scala 23:10] - node T_551 = bits(T_540, 3, 3) @[CircuitMath.scala 23:12] - node T_553 = bits(T_540, 2, 2) @[CircuitMath.scala 23:12] - node T_555 = bits(T_540, 1, 1) @[CircuitMath.scala 21:8] - node T_556 = shl(T_555, 0) @[CircuitMath.scala 23:10] - node T_557 = mux(T_553, UInt<2>("h02"), T_556) @[CircuitMath.scala 23:10] - node T_558 = mux(T_551, UInt<2>("h03"), T_557) @[CircuitMath.scala 23:10] - node T_559 = mux(T_542, T_550, T_558) @[CircuitMath.scala 29:21] - node T_560 = cat(T_542, T_559) @[Cat.scala 20:58] - node T_561 = bits(T_536, 7, 4) @[CircuitMath.scala 26:17] - node T_562 = bits(T_536, 3, 0) @[CircuitMath.scala 27:17] - node T_564 = neq(T_561, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_565 = bits(T_561, 3, 3) @[CircuitMath.scala 23:12] - node T_567 = bits(T_561, 2, 2) @[CircuitMath.scala 23:12] - node T_569 = bits(T_561, 1, 1) @[CircuitMath.scala 21:8] - node T_570 = shl(T_569, 0) @[CircuitMath.scala 23:10] - node T_571 = mux(T_567, UInt<2>("h02"), T_570) @[CircuitMath.scala 23:10] - node T_572 = mux(T_565, UInt<2>("h03"), T_571) @[CircuitMath.scala 23:10] - node T_573 = bits(T_562, 3, 3) @[CircuitMath.scala 23:12] - node T_575 = bits(T_562, 2, 2) @[CircuitMath.scala 23:12] - node T_577 = bits(T_562, 1, 1) @[CircuitMath.scala 21:8] - node T_578 = shl(T_577, 0) @[CircuitMath.scala 23:10] - node T_579 = mux(T_575, UInt<2>("h02"), T_578) @[CircuitMath.scala 23:10] - node T_580 = mux(T_573, UInt<2>("h03"), T_579) @[CircuitMath.scala 23:10] - node T_581 = mux(T_564, T_572, T_580) @[CircuitMath.scala 29:21] - node T_582 = cat(T_564, T_581) @[Cat.scala 20:58] - node T_583 = mux(T_538, T_560, T_582) @[CircuitMath.scala 29:21] - node T_584 = cat(T_538, T_583) @[Cat.scala 20:58] - node T_585 = mux(T_484, T_534, T_584) @[CircuitMath.scala 29:21] - node T_586 = cat(T_484, T_585) @[Cat.scala 20:58] - node T_587 = bits(T_478, 31, 16) @[CircuitMath.scala 26:17] - node T_588 = bits(T_478, 15, 0) @[CircuitMath.scala 27:17] - node T_590 = neq(T_587, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_591 = bits(T_587, 15, 8) @[CircuitMath.scala 26:17] - node T_592 = bits(T_587, 7, 0) @[CircuitMath.scala 27:17] - node T_594 = neq(T_591, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_595 = bits(T_591, 7, 4) @[CircuitMath.scala 26:17] - node T_596 = bits(T_591, 3, 0) @[CircuitMath.scala 27:17] - node T_598 = neq(T_595, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_599 = bits(T_595, 3, 3) @[CircuitMath.scala 23:12] - node T_601 = bits(T_595, 2, 2) @[CircuitMath.scala 23:12] - node T_603 = bits(T_595, 1, 1) @[CircuitMath.scala 21:8] - node T_604 = shl(T_603, 0) @[CircuitMath.scala 23:10] - node T_605 = mux(T_601, UInt<2>("h02"), T_604) @[CircuitMath.scala 23:10] - node T_606 = mux(T_599, UInt<2>("h03"), T_605) @[CircuitMath.scala 23:10] - node T_607 = bits(T_596, 3, 3) @[CircuitMath.scala 23:12] - node T_609 = bits(T_596, 2, 2) @[CircuitMath.scala 23:12] - node T_611 = bits(T_596, 1, 1) @[CircuitMath.scala 21:8] - node T_612 = shl(T_611, 0) @[CircuitMath.scala 23:10] - node T_613 = mux(T_609, UInt<2>("h02"), T_612) @[CircuitMath.scala 23:10] - node T_614 = mux(T_607, UInt<2>("h03"), T_613) @[CircuitMath.scala 23:10] - node T_615 = mux(T_598, T_606, T_614) @[CircuitMath.scala 29:21] - node T_616 = cat(T_598, T_615) @[Cat.scala 20:58] - node T_617 = bits(T_592, 7, 4) @[CircuitMath.scala 26:17] - node T_618 = bits(T_592, 3, 0) @[CircuitMath.scala 27:17] - node T_620 = neq(T_617, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_621 = bits(T_617, 3, 3) @[CircuitMath.scala 23:12] - node T_623 = bits(T_617, 2, 2) @[CircuitMath.scala 23:12] - node T_625 = bits(T_617, 1, 1) @[CircuitMath.scala 21:8] - node T_626 = shl(T_625, 0) @[CircuitMath.scala 23:10] - node T_627 = mux(T_623, UInt<2>("h02"), T_626) @[CircuitMath.scala 23:10] - node T_628 = mux(T_621, UInt<2>("h03"), T_627) @[CircuitMath.scala 23:10] - node T_629 = bits(T_618, 3, 3) @[CircuitMath.scala 23:12] - node T_631 = bits(T_618, 2, 2) @[CircuitMath.scala 23:12] - node T_633 = bits(T_618, 1, 1) @[CircuitMath.scala 21:8] - node T_634 = shl(T_633, 0) @[CircuitMath.scala 23:10] - node T_635 = mux(T_631, UInt<2>("h02"), T_634) @[CircuitMath.scala 23:10] - node T_636 = mux(T_629, UInt<2>("h03"), T_635) @[CircuitMath.scala 23:10] - node T_637 = mux(T_620, T_628, T_636) @[CircuitMath.scala 29:21] - node T_638 = cat(T_620, T_637) @[Cat.scala 20:58] - node T_639 = mux(T_594, T_616, T_638) @[CircuitMath.scala 29:21] - node T_640 = cat(T_594, T_639) @[Cat.scala 20:58] - node T_641 = bits(T_588, 15, 8) @[CircuitMath.scala 26:17] - node T_642 = bits(T_588, 7, 0) @[CircuitMath.scala 27:17] - node T_644 = neq(T_641, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_645 = bits(T_641, 7, 4) @[CircuitMath.scala 26:17] - node T_646 = bits(T_641, 3, 0) @[CircuitMath.scala 27:17] - node T_648 = neq(T_645, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_649 = bits(T_645, 3, 3) @[CircuitMath.scala 23:12] - node T_651 = bits(T_645, 2, 2) @[CircuitMath.scala 23:12] - node T_653 = bits(T_645, 1, 1) @[CircuitMath.scala 21:8] - node T_654 = shl(T_653, 0) @[CircuitMath.scala 23:10] - node T_655 = mux(T_651, UInt<2>("h02"), T_654) @[CircuitMath.scala 23:10] - node T_656 = mux(T_649, UInt<2>("h03"), T_655) @[CircuitMath.scala 23:10] - node T_657 = bits(T_646, 3, 3) @[CircuitMath.scala 23:12] - node T_659 = bits(T_646, 2, 2) @[CircuitMath.scala 23:12] - node T_661 = bits(T_646, 1, 1) @[CircuitMath.scala 21:8] - node T_662 = shl(T_661, 0) @[CircuitMath.scala 23:10] - node T_663 = mux(T_659, UInt<2>("h02"), T_662) @[CircuitMath.scala 23:10] - node T_664 = mux(T_657, UInt<2>("h03"), T_663) @[CircuitMath.scala 23:10] - node T_665 = mux(T_648, T_656, T_664) @[CircuitMath.scala 29:21] - node T_666 = cat(T_648, T_665) @[Cat.scala 20:58] - node T_667 = bits(T_642, 7, 4) @[CircuitMath.scala 26:17] - node T_668 = bits(T_642, 3, 0) @[CircuitMath.scala 27:17] - node T_670 = neq(T_667, UInt<1>("h00")) @[CircuitMath.scala 28:22] - node T_671 = bits(T_667, 3, 3) @[CircuitMath.scala 23:12] - node T_673 = bits(T_667, 2, 2) @[CircuitMath.scala 23:12] - node T_675 = bits(T_667, 1, 1) @[CircuitMath.scala 21:8] - node T_676 = shl(T_675, 0) @[CircuitMath.scala 23:10] - node T_677 = mux(T_673, UInt<2>("h02"), T_676) @[CircuitMath.scala 23:10] - node T_678 = mux(T_671, UInt<2>("h03"), T_677) @[CircuitMath.scala 23:10] - node T_679 = bits(T_668, 3, 3) @[CircuitMath.scala 23:12] - node T_681 = bits(T_668, 2, 2) @[CircuitMath.scala 23:12] - node T_683 = bits(T_668, 1, 1) @[CircuitMath.scala 21:8] - node T_684 = shl(T_683, 0) @[CircuitMath.scala 23:10] - node T_685 = mux(T_681, UInt<2>("h02"), T_684) @[CircuitMath.scala 23:10] - node T_686 = mux(T_679, UInt<2>("h03"), T_685) @[CircuitMath.scala 23:10] - node T_687 = mux(T_670, T_678, T_686) @[CircuitMath.scala 29:21] - node T_688 = cat(T_670, T_687) @[Cat.scala 20:58] - node T_689 = mux(T_644, T_666, T_688) @[CircuitMath.scala 29:21] - node T_690 = cat(T_644, T_689) @[Cat.scala 20:58] - node T_691 = mux(T_590, T_640, T_690) @[CircuitMath.scala 29:21] - node T_692 = cat(T_590, T_691) @[Cat.scala 20:58] - node T_693 = mux(T_480, T_586, T_692) @[CircuitMath.scala 29:21] - node T_694 = cat(T_480, T_693) @[Cat.scala 20:58] - node T_695 = not(T_694) @[recFNFromFN.scala 56:13] - node T_696 = dshl(T_470, T_695) @[recFNFromFN.scala 58:25] - node T_697 = bits(T_696, 50, 0) @[recFNFromFN.scala 58:37] - node T_699 = cat(T_697, UInt<1>("h00")) @[Cat.scala 20:58] - node T_704 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 33:12] - node T_705 = xor(T_695, T_704) @[recFNFromFN.scala 62:27] - node T_706 = mux(T_472, T_705, T_469) @[recFNFromFN.scala 61:16] - node T_710 = mux(T_472, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] - node T_711 = or(UInt<11>("h0400"), T_710) @[recFNFromFN.scala 64:42] - node T_712 = add(T_706, T_711) @[recFNFromFN.scala 64:15] - node T_713 = tail(T_712, 1) @[recFNFromFN.scala 64:15] - node T_714 = bits(T_713, 11, 10) @[recFNFromFN.scala 67:25] - node T_716 = eq(T_714, UInt<2>("h03")) @[recFNFromFN.scala 67:50] - node T_718 = eq(T_474, UInt<1>("h00")) @[recFNFromFN.scala 68:17] - node T_719 = and(T_716, T_718) @[recFNFromFN.scala 67:63] - node T_720 = bits(T_475, 0, 0) @[Bitwise.scala 33:15] - node T_723 = mux(T_720, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 33:12] - node T_724 = shl(T_723, 9) @[recFNFromFN.scala 71:45] - node T_725 = not(T_724) @[recFNFromFN.scala 71:28] - node T_726 = and(T_713, T_725) @[recFNFromFN.scala 71:26] - node T_727 = shl(T_719, 9) @[recFNFromFN.scala 72:22] - node T_728 = or(T_726, T_727) @[recFNFromFN.scala 71:64] - node T_729 = mux(T_472, T_699, T_470) @[recFNFromFN.scala 73:27] - node T_730 = cat(T_468, T_728) @[Cat.scala 20:58] - node T_731 = cat(T_730, T_729) @[Cat.scala 20:58] - node T_733 = cat(UInt<32>("h0ffffffff"), rec_s) @[Cat.scala 20:58] - node load_wb_data_recoded = mux(load_wb_single, T_733, T_731) @[fpu.scala 526:10] - cmem regfile : UInt<65>[32] @[fpu.scala 530:20] - when load_wb : @[fpu.scala 531:18] + node T_314 = bits(io.dmem_resp_type, 0, 0) + node T_316 = eq(T_314, UInt<1>("h0")) + reg load_wb_single : UInt<1>, clk with : + reset => (UInt<1>("h0"), load_wb_single) + when io.dmem_resp_val : + load_wb_single <= T_316 + reg load_wb_data : UInt<64>, clk with : + reset => (UInt<1>("h0"), load_wb_data) + when io.dmem_resp_val : + load_wb_data <= io.dmem_resp_data + reg load_wb_tag : UInt<5>, clk with : + reset => (UInt<1>("h0"), load_wb_tag) + when io.dmem_resp_val : + load_wb_tag <= io.dmem_resp_tag + node T_317 = bits(load_wb_data, 31, 31) + node T_318 = bits(load_wb_data, 30, 23) + node T_319 = bits(load_wb_data, 22, 0) + node T_321 = eq(T_318, UInt<1>("h0")) + node T_323 = eq(T_319, UInt<1>("h0")) + node T_324 = and(T_321, T_323) + node T_325 = shl(T_319, 9) + node T_326 = bits(T_325, 31, 16) + node T_327 = bits(T_325, 15, 0) + node T_329 = neq(T_326, UInt<1>("h0")) + node T_330 = bits(T_326, 15, 8) + node T_331 = bits(T_326, 7, 0) + node T_333 = neq(T_330, UInt<1>("h0")) + node T_334 = bits(T_330, 7, 4) + node T_335 = bits(T_330, 3, 0) + node T_337 = neq(T_334, UInt<1>("h0")) + node T_338 = bits(T_334, 3, 3) + node T_340 = bits(T_334, 2, 2) + node T_342 = bits(T_334, 1, 1) + node T_343 = shl(T_342, 0) + node T_344 = mux(T_340, UInt<2>("h2"), T_343) + node T_345 = mux(T_338, UInt<2>("h3"), T_344) + node T_346 = bits(T_335, 3, 3) + node T_348 = bits(T_335, 2, 2) + node T_350 = bits(T_335, 1, 1) + node T_351 = shl(T_350, 0) + node T_352 = mux(T_348, UInt<2>("h2"), T_351) + node T_353 = mux(T_346, UInt<2>("h3"), T_352) + node T_354 = mux(T_337, T_345, T_353) + node T_355 = cat(T_337, T_354) + node T_356 = bits(T_331, 7, 4) + node T_357 = bits(T_331, 3, 0) + node T_359 = neq(T_356, UInt<1>("h0")) + node T_360 = bits(T_356, 3, 3) + node T_362 = bits(T_356, 2, 2) + node T_364 = bits(T_356, 1, 1) + node T_365 = shl(T_364, 0) + node T_366 = mux(T_362, UInt<2>("h2"), T_365) + node T_367 = mux(T_360, UInt<2>("h3"), T_366) + node T_368 = bits(T_357, 3, 3) + node T_370 = bits(T_357, 2, 2) + node T_372 = bits(T_357, 1, 1) + node T_373 = shl(T_372, 0) + node T_374 = mux(T_370, UInt<2>("h2"), T_373) + node T_375 = mux(T_368, UInt<2>("h3"), T_374) + node T_376 = mux(T_359, T_367, T_375) + node T_377 = cat(T_359, T_376) + node T_378 = mux(T_333, T_355, T_377) + node T_379 = cat(T_333, T_378) + node T_380 = bits(T_327, 15, 8) + node T_381 = bits(T_327, 7, 0) + node T_383 = neq(T_380, UInt<1>("h0")) + node T_384 = bits(T_380, 7, 4) + node T_385 = bits(T_380, 3, 0) + node T_387 = neq(T_384, UInt<1>("h0")) + node T_388 = bits(T_384, 3, 3) + node T_390 = bits(T_384, 2, 2) + node T_392 = bits(T_384, 1, 1) + node T_393 = shl(T_392, 0) + node T_394 = mux(T_390, UInt<2>("h2"), T_393) + node T_395 = mux(T_388, UInt<2>("h3"), T_394) + node T_396 = bits(T_385, 3, 3) + node T_398 = bits(T_385, 2, 2) + node T_400 = bits(T_385, 1, 1) + node T_401 = shl(T_400, 0) + node T_402 = mux(T_398, UInt<2>("h2"), T_401) + node T_403 = mux(T_396, UInt<2>("h3"), T_402) + node T_404 = mux(T_387, T_395, T_403) + node T_405 = cat(T_387, T_404) + node T_406 = bits(T_381, 7, 4) + node T_407 = bits(T_381, 3, 0) + node T_409 = neq(T_406, UInt<1>("h0")) + node T_410 = bits(T_406, 3, 3) + node T_412 = bits(T_406, 2, 2) + node T_414 = bits(T_406, 1, 1) + node T_415 = shl(T_414, 0) + node T_416 = mux(T_412, UInt<2>("h2"), T_415) + node T_417 = mux(T_410, UInt<2>("h3"), T_416) + node T_418 = bits(T_407, 3, 3) + node T_420 = bits(T_407, 2, 2) + node T_422 = bits(T_407, 1, 1) + node T_423 = shl(T_422, 0) + node T_424 = mux(T_420, UInt<2>("h2"), T_423) + node T_425 = mux(T_418, UInt<2>("h3"), T_424) + node T_426 = mux(T_409, T_417, T_425) + node T_427 = cat(T_409, T_426) + node T_428 = mux(T_383, T_405, T_427) + node T_429 = cat(T_383, T_428) + node T_430 = mux(T_329, T_379, T_429) + node T_431 = cat(T_329, T_430) + node T_432 = not(T_431) + node T_433 = dshl(T_319, T_432) + node T_434 = bits(T_433, 21, 0) + node T_436 = cat(T_434, UInt<1>("h0")) + node T_441 = mux(UInt<1>("h1"), UInt<9>("h1ff"), UInt<9>("h0")) + node T_442 = xor(T_432, T_441) + node T_443 = mux(T_321, T_442, T_318) + node T_447 = mux(T_321, UInt<2>("h2"), UInt<1>("h1")) + node T_448 = or(UInt<8>("h80"), T_447) + node T_449 = add(T_443, T_448) + node T_450 = tail(T_449, 1) + node T_451 = bits(T_450, 8, 7) + node T_453 = eq(T_451, UInt<2>("h3")) + node T_455 = eq(T_323, UInt<1>("h0")) + node T_456 = and(T_453, T_455) + node T_457 = bits(T_324, 0, 0) + node T_460 = mux(T_457, UInt<3>("h7"), UInt<3>("h0")) + node T_461 = shl(T_460, 6) + node T_462 = not(T_461) + node T_463 = and(T_450, T_462) + node T_464 = shl(T_456, 6) + node T_465 = or(T_463, T_464) + node T_466 = mux(T_321, T_436, T_319) + node T_467 = cat(T_317, T_465) + node rec_s = cat(T_467, T_466) + node T_468 = bits(load_wb_data, 63, 63) + node T_469 = bits(load_wb_data, 62, 52) + node T_470 = bits(load_wb_data, 51, 0) + node T_472 = eq(T_469, UInt<1>("h0")) + node T_474 = eq(T_470, UInt<1>("h0")) + node T_475 = and(T_472, T_474) + node T_476 = shl(T_470, 12) + node T_477 = bits(T_476, 63, 32) + node T_478 = bits(T_476, 31, 0) + node T_480 = neq(T_477, UInt<1>("h0")) + node T_481 = bits(T_477, 31, 16) + node T_482 = bits(T_477, 15, 0) + node T_484 = neq(T_481, UInt<1>("h0")) + node T_485 = bits(T_481, 15, 8) + node T_486 = bits(T_481, 7, 0) + node T_488 = neq(T_485, UInt<1>("h0")) + node T_489 = bits(T_485, 7, 4) + node T_490 = bits(T_485, 3, 0) + node T_492 = neq(T_489, UInt<1>("h0")) + node T_493 = bits(T_489, 3, 3) + node T_495 = bits(T_489, 2, 2) + node T_497 = bits(T_489, 1, 1) + node T_498 = shl(T_497, 0) + node T_499 = mux(T_495, UInt<2>("h2"), T_498) + node T_500 = mux(T_493, UInt<2>("h3"), T_499) + node T_501 = bits(T_490, 3, 3) + node T_503 = bits(T_490, 2, 2) + node T_505 = bits(T_490, 1, 1) + node T_506 = shl(T_505, 0) + node T_507 = mux(T_503, UInt<2>("h2"), T_506) + node T_508 = mux(T_501, UInt<2>("h3"), T_507) + node T_509 = mux(T_492, T_500, T_508) + node T_510 = cat(T_492, T_509) + node T_511 = bits(T_486, 7, 4) + node T_512 = bits(T_486, 3, 0) + node T_514 = neq(T_511, UInt<1>("h0")) + node T_515 = bits(T_511, 3, 3) + node T_517 = bits(T_511, 2, 2) + node T_519 = bits(T_511, 1, 1) + node T_520 = shl(T_519, 0) + node T_521 = mux(T_517, UInt<2>("h2"), T_520) + node T_522 = mux(T_515, UInt<2>("h3"), T_521) + node T_523 = bits(T_512, 3, 3) + node T_525 = bits(T_512, 2, 2) + node T_527 = bits(T_512, 1, 1) + node T_528 = shl(T_527, 0) + node T_529 = mux(T_525, UInt<2>("h2"), T_528) + node T_530 = mux(T_523, UInt<2>("h3"), T_529) + node T_531 = mux(T_514, T_522, T_530) + node T_532 = cat(T_514, T_531) + node T_533 = mux(T_488, T_510, T_532) + node T_534 = cat(T_488, T_533) + node T_535 = bits(T_482, 15, 8) + node T_536 = bits(T_482, 7, 0) + node T_538 = neq(T_535, UInt<1>("h0")) + node T_539 = bits(T_535, 7, 4) + node T_540 = bits(T_535, 3, 0) + node T_542 = neq(T_539, UInt<1>("h0")) + node T_543 = bits(T_539, 3, 3) + node T_545 = bits(T_539, 2, 2) + node T_547 = bits(T_539, 1, 1) + node T_548 = shl(T_547, 0) + node T_549 = mux(T_545, UInt<2>("h2"), T_548) + node T_550 = mux(T_543, UInt<2>("h3"), T_549) + node T_551 = bits(T_540, 3, 3) + node T_553 = bits(T_540, 2, 2) + node T_555 = bits(T_540, 1, 1) + node T_556 = shl(T_555, 0) + node T_557 = mux(T_553, UInt<2>("h2"), T_556) + node T_558 = mux(T_551, UInt<2>("h3"), T_557) + node T_559 = mux(T_542, T_550, T_558) + node T_560 = cat(T_542, T_559) + node T_561 = bits(T_536, 7, 4) + node T_562 = bits(T_536, 3, 0) + node T_564 = neq(T_561, UInt<1>("h0")) + node T_565 = bits(T_561, 3, 3) + node T_567 = bits(T_561, 2, 2) + node T_569 = bits(T_561, 1, 1) + node T_570 = shl(T_569, 0) + node T_571 = mux(T_567, UInt<2>("h2"), T_570) + node T_572 = mux(T_565, UInt<2>("h3"), T_571) + node T_573 = bits(T_562, 3, 3) + node T_575 = bits(T_562, 2, 2) + node T_577 = bits(T_562, 1, 1) + node T_578 = shl(T_577, 0) + node T_579 = mux(T_575, UInt<2>("h2"), T_578) + node T_580 = mux(T_573, UInt<2>("h3"), T_579) + node T_581 = mux(T_564, T_572, T_580) + node T_582 = cat(T_564, T_581) + node T_583 = mux(T_538, T_560, T_582) + node T_584 = cat(T_538, T_583) + node T_585 = mux(T_484, T_534, T_584) + node T_586 = cat(T_484, T_585) + node T_587 = bits(T_478, 31, 16) + node T_588 = bits(T_478, 15, 0) + node T_590 = neq(T_587, UInt<1>("h0")) + node T_591 = bits(T_587, 15, 8) + node T_592 = bits(T_587, 7, 0) + node T_594 = neq(T_591, UInt<1>("h0")) + node T_595 = bits(T_591, 7, 4) + node T_596 = bits(T_591, 3, 0) + node T_598 = neq(T_595, UInt<1>("h0")) + node T_599 = bits(T_595, 3, 3) + node T_601 = bits(T_595, 2, 2) + node T_603 = bits(T_595, 1, 1) + node T_604 = shl(T_603, 0) + node T_605 = mux(T_601, UInt<2>("h2"), T_604) + node T_606 = mux(T_599, UInt<2>("h3"), T_605) + node T_607 = bits(T_596, 3, 3) + node T_609 = bits(T_596, 2, 2) + node T_611 = bits(T_596, 1, 1) + node T_612 = shl(T_611, 0) + node T_613 = mux(T_609, UInt<2>("h2"), T_612) + node T_614 = mux(T_607, UInt<2>("h3"), T_613) + node T_615 = mux(T_598, T_606, T_614) + node T_616 = cat(T_598, T_615) + node T_617 = bits(T_592, 7, 4) + node T_618 = bits(T_592, 3, 0) + node T_620 = neq(T_617, UInt<1>("h0")) + node T_621 = bits(T_617, 3, 3) + node T_623 = bits(T_617, 2, 2) + node T_625 = bits(T_617, 1, 1) + node T_626 = shl(T_625, 0) + node T_627 = mux(T_623, UInt<2>("h2"), T_626) + node T_628 = mux(T_621, UInt<2>("h3"), T_627) + node T_629 = bits(T_618, 3, 3) + node T_631 = bits(T_618, 2, 2) + node T_633 = bits(T_618, 1, 1) + node T_634 = shl(T_633, 0) + node T_635 = mux(T_631, UInt<2>("h2"), T_634) + node T_636 = mux(T_629, UInt<2>("h3"), T_635) + node T_637 = mux(T_620, T_628, T_636) + node T_638 = cat(T_620, T_637) + node T_639 = mux(T_594, T_616, T_638) + node T_640 = cat(T_594, T_639) + node T_641 = bits(T_588, 15, 8) + node T_642 = bits(T_588, 7, 0) + node T_644 = neq(T_641, UInt<1>("h0")) + node T_645 = bits(T_641, 7, 4) + node T_646 = bits(T_641, 3, 0) + node T_648 = neq(T_645, UInt<1>("h0")) + node T_649 = bits(T_645, 3, 3) + node T_651 = bits(T_645, 2, 2) + node T_653 = bits(T_645, 1, 1) + node T_654 = shl(T_653, 0) + node T_655 = mux(T_651, UInt<2>("h2"), T_654) + node T_656 = mux(T_649, UInt<2>("h3"), T_655) + node T_657 = bits(T_646, 3, 3) + node T_659 = bits(T_646, 2, 2) + node T_661 = bits(T_646, 1, 1) + node T_662 = shl(T_661, 0) + node T_663 = mux(T_659, UInt<2>("h2"), T_662) + node T_664 = mux(T_657, UInt<2>("h3"), T_663) + node T_665 = mux(T_648, T_656, T_664) + node T_666 = cat(T_648, T_665) + node T_667 = bits(T_642, 7, 4) + node T_668 = bits(T_642, 3, 0) + node T_670 = neq(T_667, UInt<1>("h0")) + node T_671 = bits(T_667, 3, 3) + node T_673 = bits(T_667, 2, 2) + node T_675 = bits(T_667, 1, 1) + node T_676 = shl(T_675, 0) + node T_677 = mux(T_673, UInt<2>("h2"), T_676) + node T_678 = mux(T_671, UInt<2>("h3"), T_677) + node T_679 = bits(T_668, 3, 3) + node T_681 = bits(T_668, 2, 2) + node T_683 = bits(T_668, 1, 1) + node T_684 = shl(T_683, 0) + node T_685 = mux(T_681, UInt<2>("h2"), T_684) + node T_686 = mux(T_679, UInt<2>("h3"), T_685) + node T_687 = mux(T_670, T_678, T_686) + node T_688 = cat(T_670, T_687) + node T_689 = mux(T_644, T_666, T_688) + node T_690 = cat(T_644, T_689) + node T_691 = mux(T_590, T_640, T_690) + node T_692 = cat(T_590, T_691) + node T_693 = mux(T_480, T_586, T_692) + node T_694 = cat(T_480, T_693) + node T_695 = not(T_694) + node T_696 = dshl(T_470, T_695) + node T_697 = bits(T_696, 50, 0) + node T_699 = cat(T_697, UInt<1>("h0")) + node T_704 = mux(UInt<1>("h1"), UInt<12>("hfff"), UInt<12>("h0")) + node T_705 = xor(T_695, T_704) + node T_706 = mux(T_472, T_705, T_469) + node T_710 = mux(T_472, UInt<2>("h2"), UInt<1>("h1")) + node T_711 = or(UInt<11>("h400"), T_710) + node T_712 = add(T_706, T_711) + node T_713 = tail(T_712, 1) + node T_714 = bits(T_713, 11, 10) + node T_716 = eq(T_714, UInt<2>("h3")) + node T_718 = eq(T_474, UInt<1>("h0")) + node T_719 = and(T_716, T_718) + node T_720 = bits(T_475, 0, 0) + node T_723 = mux(T_720, UInt<3>("h7"), UInt<3>("h0")) + node T_724 = shl(T_723, 9) + node T_725 = not(T_724) + node T_726 = and(T_713, T_725) + node T_727 = shl(T_719, 9) + node T_728 = or(T_726, T_727) + node T_729 = mux(T_472, T_699, T_470) + node T_730 = cat(T_468, T_728) + node T_731 = cat(T_730, T_729) + node T_733 = cat(UInt<32>("hffffffff"), rec_s) + node load_wb_data_recoded = mux(load_wb_single, T_733, T_731) + cmem regfile : UInt<65> [32] + when load_wb : infer mport T_736 = regfile[load_wb_tag], clk - T_736 <= load_wb_data_recoded @[fpu.scala 532:26] - skip @[fpu.scala 531:18] - reg ex_ra1 : UInt, clk - reg ex_ra2 : UInt, clk - reg ex_ra3 : UInt, clk - when io.valid : @[fpu.scala 538:19] - when fp_decoder.io.sigs.ren1 : @[fpu.scala 539:25] - node T_741 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[fpu.scala 540:13] - when T_741 : @[fpu.scala 540:30] - node T_742 = bits(io.inst, 19, 15) @[fpu.scala 540:49] - ex_ra1 <= T_742 @[fpu.scala 540:39] - skip @[fpu.scala 540:30] - when fp_decoder.io.sigs.swap12 : @[fpu.scala 541:29] - node T_743 = bits(io.inst, 19, 15) @[fpu.scala 541:48] - ex_ra2 <= T_743 @[fpu.scala 541:38] - skip @[fpu.scala 541:29] - skip @[fpu.scala 539:25] - when fp_decoder.io.sigs.ren2 : @[fpu.scala 543:25] - when fp_decoder.io.sigs.swap12 : @[fpu.scala 544:29] - node T_744 = bits(io.inst, 24, 20) @[fpu.scala 544:48] - ex_ra1 <= T_744 @[fpu.scala 544:38] - skip @[fpu.scala 544:29] - when fp_decoder.io.sigs.swap23 : @[fpu.scala 545:29] - node T_745 = bits(io.inst, 24, 20) @[fpu.scala 545:48] - ex_ra3 <= T_745 @[fpu.scala 545:38] - skip @[fpu.scala 545:29] - node T_747 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[fpu.scala 546:13] - node T_749 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) @[fpu.scala 546:32] - node T_750 = and(T_747, T_749) @[fpu.scala 546:29] - when T_750 : @[fpu.scala 546:49] - node T_751 = bits(io.inst, 24, 20) @[fpu.scala 546:68] - ex_ra2 <= T_751 @[fpu.scala 546:58] - skip @[fpu.scala 546:49] - skip @[fpu.scala 543:25] - when fp_decoder.io.sigs.ren3 : @[fpu.scala 548:25] - node T_752 = bits(io.inst, 31, 27) @[fpu.scala 548:44] - ex_ra3 <= T_752 @[fpu.scala 548:34] - skip @[fpu.scala 548:25] - skip @[fpu.scala 538:19] - node T_753 = bits(ex_reg_inst, 14, 12) @[fpu.scala 550:30] - node T_755 = eq(T_753, UInt<3>("h07")) @[fpu.scala 550:38] - node T_756 = bits(ex_reg_inst, 14, 12) @[fpu.scala 550:74] - node ex_rm = mux(T_755, io.fcsr_rm, T_756) @[fpu.scala 550:18] - wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[fpu.scala 552:17] - req is invalid @[fpu.scala 552:17] - req <- ex_ctrl @[fpu.scala 553:7] - req.rm <= ex_rm @[fpu.scala 554:10] + T_736 <= load_wb_data_recoded + reg ex_ra1 : UInt, clk with : + reset => (UInt<1>("h0"), ex_ra1) + reg ex_ra2 : UInt, clk with : + reset => (UInt<1>("h0"), ex_ra2) + reg ex_ra3 : UInt, clk with : + reset => (UInt<1>("h0"), ex_ra3) + when io.valid : + when fp_decoder.io.sigs.ren1 : + node T_741 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h0")) + when T_741 : + node T_742 = bits(io.inst, 19, 15) + ex_ra1 <= T_742 + when fp_decoder.io.sigs.swap12 : + node T_743 = bits(io.inst, 19, 15) + ex_ra2 <= T_743 + when fp_decoder.io.sigs.ren2 : + when fp_decoder.io.sigs.swap12 : + node T_744 = bits(io.inst, 24, 20) + ex_ra1 <= T_744 + when fp_decoder.io.sigs.swap23 : + node T_745 = bits(io.inst, 24, 20) + ex_ra3 <= T_745 + node T_747 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h0")) + node T_749 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h0")) + node T_750 = and(T_747, T_749) + when T_750 : + node T_751 = bits(io.inst, 24, 20) + ex_ra2 <= T_751 + when fp_decoder.io.sigs.ren3 : + node T_752 = bits(io.inst, 31, 27) + ex_ra3 <= T_752 + node T_753 = bits(ex_reg_inst, 14, 12) + node T_755 = eq(T_753, UInt<3>("h7")) + node T_756 = bits(ex_reg_inst, 14, 12) + node ex_rm = mux(T_755, io.fcsr_rm, T_756) + wire req : { cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} + req is invalid + req <- ex_ctrl + req.rm <= ex_rm infer mport T_802 = regfile[ex_ra1], clk - req.in1 <= T_802 @[fpu.scala 555:11] + req.in1 <= T_802 infer mport T_803 = regfile[ex_ra2], clk - req.in2 <= T_803 @[fpu.scala 556:11] + req.in2 <= T_803 infer mport T_804 = regfile[ex_ra3], clk - req.in3 <= T_804 @[fpu.scala 557:11] - node T_805 = bits(ex_reg_inst, 21, 20) @[fpu.scala 558:25] - req.typ <= T_805 @[fpu.scala 558:11] - when ex_cp_valid : @[fpu.scala 559:22] - req <- io.cp_req.bits @[fpu.scala 560:9] - when io.cp_req.bits.swap23 : @[fpu.scala 561:34] - req.in2 <= io.cp_req.bits.in3 @[fpu.scala 562:15] - req.in3 <= io.cp_req.bits.in2 @[fpu.scala 563:15] - skip @[fpu.scala 561:34] - skip @[fpu.scala 559:22] - inst sfma of FPUFMAPipe @[fpu.scala 567:20] + req.in3 <= T_804 + node T_805 = bits(ex_reg_inst, 21, 20) + req.typ <= T_805 + when ex_cp_valid : + req <- io.cp_req.bits + when io.cp_req.bits.swap23 : + req.in2 <= io.cp_req.bits.in3 + req.in3 <= io.cp_req.bits.in2 + inst sfma of FPUFMAPipe sfma.io is invalid sfma.clk <= clk sfma.reset <= reset - node T_806 = and(req_valid, ex_ctrl.fma) @[fpu.scala 568:33] - node T_807 = and(T_806, ex_ctrl.single) @[fpu.scala 568:48] - sfma.io.in.valid <= T_807 @[fpu.scala 568:20] - sfma.io.in.bits <- req @[fpu.scala 569:19] - inst fpiu of FPToInt @[fpu.scala 571:20] + node T_806 = and(req_valid, ex_ctrl.fma) + node T_807 = and(T_806, ex_ctrl.single) + sfma.io.in.valid <= T_807 + sfma.io.in.bits <- req + inst fpiu of FPToInt fpiu.io is invalid fpiu.clk <= clk fpiu.reset <= reset - node T_808 = or(ex_ctrl.toint, ex_ctrl.div) @[fpu.scala 572:51] - node T_809 = or(T_808, ex_ctrl.sqrt) @[fpu.scala 572:66] - node T_812 = and(ex_ctrl.cmd, UInt<4>("h0d")) @[fpu.scala 572:97] - node T_813 = eq(UInt<5>("h05"), T_812) @[fpu.scala 572:97] - node T_814 = or(T_809, T_813) @[fpu.scala 572:82] - node T_815 = and(req_valid, T_814) @[fpu.scala 572:33] - fpiu.io.in.valid <= T_815 @[fpu.scala 572:20] - fpiu.io.in.bits <- req @[fpu.scala 573:19] - io.store_data <= fpiu.io.out.bits.store @[fpu.scala 574:17] - io.toint_data <= fpiu.io.out.bits.toint @[fpu.scala 575:17] - node T_816 = and(fpiu.io.out.valid, mem_cp_valid) @[fpu.scala 576:26] - node T_817 = and(T_816, mem_ctrl.toint) @[fpu.scala 576:42] - when T_817 : @[fpu.scala 576:60] - io.cp_resp.bits.data <= fpiu.io.out.bits.toint @[fpu.scala 577:26] - io.cp_resp.valid <= UInt<1>("h01") @[fpu.scala 578:22] - skip @[fpu.scala 576:60] - inst ifpu of IntToFP @[fpu.scala 581:20] + node T_808 = or(ex_ctrl.toint, ex_ctrl.div) + node T_809 = or(T_808, ex_ctrl.sqrt) + node T_812 = and(ex_ctrl.cmd, UInt<4>("hd")) + node T_813 = eq(UInt<5>("h5"), T_812) + node T_814 = or(T_809, T_813) + node T_815 = and(req_valid, T_814) + fpiu.io.in.valid <= T_815 + fpiu.io.in.bits <- req + io.store_data <= fpiu.io.out.bits.store + io.toint_data <= fpiu.io.out.bits.toint + node T_816 = and(fpiu.io.out.valid, mem_cp_valid) + node T_817 = and(T_816, mem_ctrl.toint) + when T_817 : + io.cp_resp.bits.data <= fpiu.io.out.bits.toint + io.cp_resp.valid <= UInt<1>("h1") + inst ifpu of IntToFP ifpu.io is invalid ifpu.clk <= clk ifpu.reset <= reset - node T_819 = and(req_valid, ex_ctrl.fromint) @[fpu.scala 582:33] - ifpu.io.in.valid <= T_819 @[fpu.scala 582:20] - ifpu.io.in.bits <- req @[fpu.scala 583:19] - node T_820 = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) @[fpu.scala 584:29] - ifpu.io.in.bits.in1 <= T_820 @[fpu.scala 584:23] - inst fpmu of FPToFP @[fpu.scala 586:20] + node T_819 = and(req_valid, ex_ctrl.fromint) + ifpu.io.in.valid <= T_819 + ifpu.io.in.bits <- req + node T_820 = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) + ifpu.io.in.bits.in1 <= T_820 + inst fpmu of FPToFP fpmu.io is invalid fpmu.clk <= clk fpmu.reset <= reset - node T_821 = and(req_valid, ex_ctrl.fastpipe) @[fpu.scala 587:33] - fpmu.io.in.valid <= T_821 @[fpu.scala 587:20] - fpmu.io.in.bits <- req @[fpu.scala 588:19] - fpmu.io.lt <= fpiu.io.out.bits.lt @[fpu.scala 589:14] - reg divSqrt_wen : UInt<1>, clk - divSqrt_wen <= UInt<1>("h00") + node T_821 = and(req_valid, ex_ctrl.fastpipe) + fpmu.io.in.valid <= T_821 + fpmu.io.in.bits <- req + fpmu.io.lt <= fpiu.io.out.bits.lt + reg divSqrt_wen : UInt<1>, clk with : + reset => (UInt<1>("h0"), divSqrt_wen) + divSqrt_wen <= UInt<1>("h0") wire divSqrt_inReady : UInt<1> divSqrt_inReady is invalid - divSqrt_inReady <= UInt<1>("h00") - reg divSqrt_waddr : UInt<5>, clk - wire divSqrt_wdata : UInt<65> @[fpu.scala 594:27] - divSqrt_wdata is invalid @[fpu.scala 594:27] - wire divSqrt_flags : UInt<5> @[fpu.scala 595:27] - divSqrt_flags is invalid @[fpu.scala 595:27] - reg divSqrt_in_flight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg divSqrt_killed : UInt<1>, clk - inst FPUFMAPipe_1_1 of FPUFMAPipe_1 @[fpu.scala 606:28] + divSqrt_inReady <= UInt<1>("h0") + reg divSqrt_waddr : UInt<5>, clk with : + reset => (UInt<1>("h0"), divSqrt_waddr) + wire divSqrt_wdata : UInt<65> + divSqrt_wdata is invalid + wire divSqrt_flags : UInt<5> + divSqrt_flags is invalid + reg divSqrt_in_flight : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg divSqrt_killed : UInt<1>, clk with : + reset => (UInt<1>("h0"), divSqrt_killed) + inst FPUFMAPipe_1_1 of FPUFMAPipe_1 FPUFMAPipe_1_1.io is invalid FPUFMAPipe_1_1.clk <= clk FPUFMAPipe_1_1.reset <= reset - node T_829 = and(req_valid, ex_ctrl.fma) @[fpu.scala 607:41] - node T_831 = eq(ex_ctrl.single, UInt<1>("h00")) @[fpu.scala 607:59] - node T_832 = and(T_829, T_831) @[fpu.scala 607:56] - FPUFMAPipe_1_1.io.in.valid <= T_832 @[fpu.scala 607:28] - FPUFMAPipe_1_1.io.in.bits <- req @[fpu.scala 608:27] - node T_835 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_838 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_839 = and(mem_ctrl.fma, mem_ctrl.single) @[fpu.scala 604:56] - node T_842 = mux(T_839, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_844 = eq(mem_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_845 = and(mem_ctrl.fma, T_844) @[fpu.scala 609:62] - node T_848 = mux(T_845, UInt<3>("h04"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_849 = or(T_835, T_838) @[fpu.scala 613:78] - node T_850 = or(T_849, T_842) @[fpu.scala 613:78] - node memLatencyMask = or(T_850, T_848) @[fpu.scala 613:78] - reg wen : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg wbInfo : {rd : UInt<5>, single : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clk - node T_907 = or(mem_ctrl.fma, mem_ctrl.fastpipe) @[fpu.scala 629:48] - node T_908 = or(T_907, mem_ctrl.fromint) @[fpu.scala 629:69] - node mem_wen = and(mem_reg_valid, T_908) @[fpu.scala 629:31] - node T_911 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_914 = mux(ex_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_915 = and(ex_ctrl.fma, ex_ctrl.single) @[fpu.scala 604:56] - node T_918 = mux(T_915, UInt<3>("h04"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_920 = eq(ex_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_921 = and(ex_ctrl.fma, T_920) @[fpu.scala 609:62] - node T_924 = mux(T_921, UInt<4>("h08"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_925 = or(T_911, T_914) @[fpu.scala 613:78] - node T_926 = or(T_925, T_918) @[fpu.scala 613:78] - node T_927 = or(T_926, T_924) @[fpu.scala 613:78] - node T_928 = and(memLatencyMask, T_927) @[fpu.scala 630:62] - node T_930 = neq(T_928, UInt<1>("h00")) @[fpu.scala 630:89] - node T_931 = and(mem_wen, T_930) @[fpu.scala 630:43] - node T_934 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_937 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_938 = and(ex_ctrl.fma, ex_ctrl.single) @[fpu.scala 604:56] - node T_941 = mux(T_938, UInt<4>("h08"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_943 = eq(ex_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_944 = and(ex_ctrl.fma, T_943) @[fpu.scala 609:62] - node T_947 = mux(T_944, UInt<5>("h010"), UInt<1>("h00")) @[fpu.scala 613:23] - node T_948 = or(T_934, T_937) @[fpu.scala 613:78] - node T_949 = or(T_948, T_941) @[fpu.scala 613:78] - node T_950 = or(T_949, T_947) @[fpu.scala 613:78] - node T_951 = and(wen, T_950) @[fpu.scala 630:101] - node T_953 = neq(T_951, UInt<1>("h00")) @[fpu.scala 630:128] - node T_954 = or(T_931, T_953) @[fpu.scala 630:93] - reg write_port_busy : UInt<1>, clk - when req_valid : @[Reg.scala 29:19] - write_port_busy <= T_954 @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_955 = bits(wen, 1, 1) @[fpu.scala 633:14] - when T_955 : @[fpu.scala 633:21] - wbInfo[0] <- wbInfo[1] @[fpu.scala 633:33] - skip @[fpu.scala 633:21] - node T_956 = bits(wen, 2, 2) @[fpu.scala 633:14] - when T_956 : @[fpu.scala 633:21] - wbInfo[1] <- wbInfo[2] @[fpu.scala 633:33] - skip @[fpu.scala 633:21] - node T_957 = shr(wen, 1) @[fpu.scala 635:14] - wen <= T_957 @[fpu.scala 635:7] - when mem_wen : @[fpu.scala 636:18] - node T_959 = eq(killm, UInt<1>("h00")) @[fpu.scala 637:11] - when T_959 : @[fpu.scala 637:19] - node T_960 = shr(wen, 1) @[fpu.scala 638:18] - node T_961 = or(T_960, memLatencyMask) @[fpu.scala 638:23] - wen <= T_961 @[fpu.scala 638:11] - skip @[fpu.scala 637:19] - node T_963 = eq(write_port_busy, UInt<1>("h00")) @[fpu.scala 641:13] - node T_964 = bits(memLatencyMask, 0, 0) @[fpu.scala 641:47] - node T_965 = and(T_963, T_964) @[fpu.scala 641:30] - when T_965 : @[fpu.scala 641:52] - wbInfo[0].cp <= mem_cp_valid @[fpu.scala 642:22] - wbInfo[0].single <= mem_ctrl.single @[fpu.scala 643:26] - node T_968 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_971 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_972 = and(mem_ctrl.fma, mem_ctrl.single) @[fpu.scala 604:56] - node T_975 = mux(T_972, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_977 = eq(mem_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_978 = and(mem_ctrl.fma, T_977) @[fpu.scala 609:62] - node T_981 = mux(T_978, UInt<2>("h03"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_982 = or(T_968, T_971) @[fpu.scala 615:108] - node T_983 = or(T_982, T_975) @[fpu.scala 615:108] - node T_984 = or(T_983, T_981) @[fpu.scala 615:108] - wbInfo[0].pipeid <= T_984 @[fpu.scala 644:26] - node T_985 = bits(mem_reg_inst, 11, 7) @[fpu.scala 645:37] - wbInfo[0].rd <= T_985 @[fpu.scala 645:22] - skip @[fpu.scala 641:52] - node T_987 = eq(write_port_busy, UInt<1>("h00")) @[fpu.scala 641:13] - node T_988 = bits(memLatencyMask, 1, 1) @[fpu.scala 641:47] - node T_989 = and(T_987, T_988) @[fpu.scala 641:30] - when T_989 : @[fpu.scala 641:52] - wbInfo[1].cp <= mem_cp_valid @[fpu.scala 642:22] - wbInfo[1].single <= mem_ctrl.single @[fpu.scala 643:26] - node T_992 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_995 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_996 = and(mem_ctrl.fma, mem_ctrl.single) @[fpu.scala 604:56] - node T_999 = mux(T_996, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1001 = eq(mem_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_1002 = and(mem_ctrl.fma, T_1001) @[fpu.scala 609:62] - node T_1005 = mux(T_1002, UInt<2>("h03"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1006 = or(T_992, T_995) @[fpu.scala 615:108] - node T_1007 = or(T_1006, T_999) @[fpu.scala 615:108] - node T_1008 = or(T_1007, T_1005) @[fpu.scala 615:108] - wbInfo[1].pipeid <= T_1008 @[fpu.scala 644:26] - node T_1009 = bits(mem_reg_inst, 11, 7) @[fpu.scala 645:37] - wbInfo[1].rd <= T_1009 @[fpu.scala 645:22] - skip @[fpu.scala 641:52] - node T_1011 = eq(write_port_busy, UInt<1>("h00")) @[fpu.scala 641:13] - node T_1012 = bits(memLatencyMask, 2, 2) @[fpu.scala 641:47] - node T_1013 = and(T_1011, T_1012) @[fpu.scala 641:30] - when T_1013 : @[fpu.scala 641:52] - wbInfo[2].cp <= mem_cp_valid @[fpu.scala 642:22] - wbInfo[2].single <= mem_ctrl.single @[fpu.scala 643:26] - node T_1016 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1019 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1020 = and(mem_ctrl.fma, mem_ctrl.single) @[fpu.scala 604:56] - node T_1023 = mux(T_1020, UInt<2>("h02"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1025 = eq(mem_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_1026 = and(mem_ctrl.fma, T_1025) @[fpu.scala 609:62] - node T_1029 = mux(T_1026, UInt<2>("h03"), UInt<1>("h00")) @[fpu.scala 615:63] - node T_1030 = or(T_1016, T_1019) @[fpu.scala 615:108] - node T_1031 = or(T_1030, T_1023) @[fpu.scala 615:108] - node T_1032 = or(T_1031, T_1029) @[fpu.scala 615:108] - wbInfo[2].pipeid <= T_1032 @[fpu.scala 644:26] - node T_1033 = bits(mem_reg_inst, 11, 7) @[fpu.scala 645:37] - wbInfo[2].rd <= T_1033 @[fpu.scala 645:22] - skip @[fpu.scala 641:52] - skip @[fpu.scala 636:18] - node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) @[fpu.scala 650:18] - node T_1035 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] - node T_1037 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] - node T_1039 = and(T_1035, UInt<1>("h00")) @[Package.scala 18:26] - node T_1041 = geq(T_1035, UInt<1>("h01")) @[Package.scala 19:17] - node T_1042 = mux(T_1041, FPUFMAPipe_1_1.io.out.bits.data, sfma.io.out.bits.data) @[Package.scala 19:12] - node T_1044 = and(T_1035, UInt<1>("h00")) @[Package.scala 18:26] - node T_1046 = geq(T_1035, UInt<1>("h01")) @[Package.scala 19:17] - node T_1047 = mux(T_1046, ifpu.io.out.bits.data, fpmu.io.out.bits.data) @[Package.scala 19:12] - node T_1048 = mux(T_1037, T_1042, T_1047) @[Package.scala 19:12] - node wdata = mux(divSqrt_wen, divSqrt_wdata, T_1048) @[fpu.scala 651:18] - node T_1050 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] - node T_1052 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] - node T_1054 = and(T_1050, UInt<1>("h00")) @[Package.scala 18:26] - node T_1056 = geq(T_1050, UInt<1>("h01")) @[Package.scala 19:17] - node T_1057 = mux(T_1056, FPUFMAPipe_1_1.io.out.bits.exc, sfma.io.out.bits.exc) @[Package.scala 19:12] - node T_1059 = and(T_1050, UInt<1>("h00")) @[Package.scala 18:26] - node T_1061 = geq(T_1050, UInt<1>("h01")) @[Package.scala 19:17] - node T_1062 = mux(T_1061, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) @[Package.scala 19:12] - node wexc = mux(T_1052, T_1057, T_1062) @[Package.scala 19:12] - node T_1064 = eq(wbInfo[0].cp, UInt<1>("h00")) @[fpu.scala 653:10] - node T_1065 = bits(wen, 0, 0) @[fpu.scala 653:30] - node T_1066 = and(T_1064, T_1065) @[fpu.scala 653:24] - node T_1067 = or(T_1066, divSqrt_wen) @[fpu.scala 653:35] - when T_1067 : @[fpu.scala 653:51] + node T_829 = and(req_valid, ex_ctrl.fma) + node T_831 = eq(ex_ctrl.single, UInt<1>("h0")) + node T_832 = and(T_829, T_831) + FPUFMAPipe_1_1.io.in.valid <= T_832 + FPUFMAPipe_1_1.io.in.bits <- req + node T_835 = mux(mem_ctrl.fastpipe, UInt<1>("h1"), UInt<1>("h0")) + node T_838 = mux(mem_ctrl.fromint, UInt<1>("h1"), UInt<1>("h0")) + node T_839 = and(mem_ctrl.fma, mem_ctrl.single) + node T_842 = mux(T_839, UInt<2>("h2"), UInt<1>("h0")) + node T_844 = eq(mem_ctrl.single, UInt<1>("h0")) + node T_845 = and(mem_ctrl.fma, T_844) + node T_848 = mux(T_845, UInt<3>("h4"), UInt<1>("h0")) + node T_849 = or(T_835, T_838) + node T_850 = or(T_849, T_842) + node memLatencyMask = or(T_850, T_848) + reg wen : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg wbInfo : { rd : UInt<5>, single : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clk with : + reset => (UInt<1>("h0"), wbInfo) + node T_907 = or(mem_ctrl.fma, mem_ctrl.fastpipe) + node T_908 = or(T_907, mem_ctrl.fromint) + node mem_wen = and(mem_reg_valid, T_908) + node T_911 = mux(ex_ctrl.fastpipe, UInt<2>("h2"), UInt<1>("h0")) + node T_914 = mux(ex_ctrl.fromint, UInt<2>("h2"), UInt<1>("h0")) + node T_915 = and(ex_ctrl.fma, ex_ctrl.single) + node T_918 = mux(T_915, UInt<3>("h4"), UInt<1>("h0")) + node T_920 = eq(ex_ctrl.single, UInt<1>("h0")) + node T_921 = and(ex_ctrl.fma, T_920) + node T_924 = mux(T_921, UInt<4>("h8"), UInt<1>("h0")) + node T_925 = or(T_911, T_914) + node T_926 = or(T_925, T_918) + node T_927 = or(T_926, T_924) + node T_928 = and(memLatencyMask, T_927) + node T_930 = neq(T_928, UInt<1>("h0")) + node T_931 = and(mem_wen, T_930) + node T_934 = mux(ex_ctrl.fastpipe, UInt<3>("h4"), UInt<1>("h0")) + node T_937 = mux(ex_ctrl.fromint, UInt<3>("h4"), UInt<1>("h0")) + node T_938 = and(ex_ctrl.fma, ex_ctrl.single) + node T_941 = mux(T_938, UInt<4>("h8"), UInt<1>("h0")) + node T_943 = eq(ex_ctrl.single, UInt<1>("h0")) + node T_944 = and(ex_ctrl.fma, T_943) + node T_947 = mux(T_944, UInt<5>("h10"), UInt<1>("h0")) + node T_948 = or(T_934, T_937) + node T_949 = or(T_948, T_941) + node T_950 = or(T_949, T_947) + node T_951 = and(wen, T_950) + node T_953 = neq(T_951, UInt<1>("h0")) + node T_954 = or(T_931, T_953) + reg write_port_busy : UInt<1>, clk with : + reset => (UInt<1>("h0"), write_port_busy) + when req_valid : + write_port_busy <= T_954 + node T_955 = bits(wen, 1, 1) + when T_955 : + wbInfo[0] <- wbInfo[1] + node T_956 = bits(wen, 2, 2) + when T_956 : + wbInfo[1] <- wbInfo[2] + node T_957 = shr(wen, 1) + wen <= T_957 + when mem_wen : + node T_959 = eq(killm, UInt<1>("h0")) + when T_959 : + node T_960 = shr(wen, 1) + node T_961 = or(T_960, memLatencyMask) + wen <= T_961 + node T_963 = eq(write_port_busy, UInt<1>("h0")) + node T_964 = bits(memLatencyMask, 0, 0) + node T_965 = and(T_963, T_964) + when T_965 : + wbInfo[0].cp <= mem_cp_valid + wbInfo[0].single <= mem_ctrl.single + node T_968 = mux(mem_ctrl.fastpipe, UInt<1>("h0"), UInt<1>("h0")) + node T_971 = mux(mem_ctrl.fromint, UInt<1>("h1"), UInt<1>("h0")) + node T_972 = and(mem_ctrl.fma, mem_ctrl.single) + node T_975 = mux(T_972, UInt<2>("h2"), UInt<1>("h0")) + node T_977 = eq(mem_ctrl.single, UInt<1>("h0")) + node T_978 = and(mem_ctrl.fma, T_977) + node T_981 = mux(T_978, UInt<2>("h3"), UInt<1>("h0")) + node T_982 = or(T_968, T_971) + node T_983 = or(T_982, T_975) + node T_984 = or(T_983, T_981) + wbInfo[0].pipeid <= T_984 + node T_985 = bits(mem_reg_inst, 11, 7) + wbInfo[0].rd <= T_985 + node T_987 = eq(write_port_busy, UInt<1>("h0")) + node T_988 = bits(memLatencyMask, 1, 1) + node T_989 = and(T_987, T_988) + when T_989 : + wbInfo[1].cp <= mem_cp_valid + wbInfo[1].single <= mem_ctrl.single + node T_992 = mux(mem_ctrl.fastpipe, UInt<1>("h0"), UInt<1>("h0")) + node T_995 = mux(mem_ctrl.fromint, UInt<1>("h1"), UInt<1>("h0")) + node T_996 = and(mem_ctrl.fma, mem_ctrl.single) + node T_999 = mux(T_996, UInt<2>("h2"), UInt<1>("h0")) + node T_1001 = eq(mem_ctrl.single, UInt<1>("h0")) + node T_1002 = and(mem_ctrl.fma, T_1001) + node T_1005 = mux(T_1002, UInt<2>("h3"), UInt<1>("h0")) + node T_1006 = or(T_992, T_995) + node T_1007 = or(T_1006, T_999) + node T_1008 = or(T_1007, T_1005) + wbInfo[1].pipeid <= T_1008 + node T_1009 = bits(mem_reg_inst, 11, 7) + wbInfo[1].rd <= T_1009 + node T_1011 = eq(write_port_busy, UInt<1>("h0")) + node T_1012 = bits(memLatencyMask, 2, 2) + node T_1013 = and(T_1011, T_1012) + when T_1013 : + wbInfo[2].cp <= mem_cp_valid + wbInfo[2].single <= mem_ctrl.single + node T_1016 = mux(mem_ctrl.fastpipe, UInt<1>("h0"), UInt<1>("h0")) + node T_1019 = mux(mem_ctrl.fromint, UInt<1>("h1"), UInt<1>("h0")) + node T_1020 = and(mem_ctrl.fma, mem_ctrl.single) + node T_1023 = mux(T_1020, UInt<2>("h2"), UInt<1>("h0")) + node T_1025 = eq(mem_ctrl.single, UInt<1>("h0")) + node T_1026 = and(mem_ctrl.fma, T_1025) + node T_1029 = mux(T_1026, UInt<2>("h3"), UInt<1>("h0")) + node T_1030 = or(T_1016, T_1019) + node T_1031 = or(T_1030, T_1023) + node T_1032 = or(T_1031, T_1029) + wbInfo[2].pipeid <= T_1032 + node T_1033 = bits(mem_reg_inst, 11, 7) + wbInfo[2].rd <= T_1033 + node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) + node T_1035 = and(wbInfo[0].pipeid, UInt<1>("h1")) + node T_1037 = geq(wbInfo[0].pipeid, UInt<2>("h2")) + node T_1039 = and(T_1035, UInt<1>("h0")) + node T_1041 = geq(T_1035, UInt<1>("h1")) + node T_1042 = mux(T_1041, FPUFMAPipe_1_1.io.out.bits.data, sfma.io.out.bits.data) + node T_1044 = and(T_1035, UInt<1>("h0")) + node T_1046 = geq(T_1035, UInt<1>("h1")) + node T_1047 = mux(T_1046, ifpu.io.out.bits.data, fpmu.io.out.bits.data) + node T_1048 = mux(T_1037, T_1042, T_1047) + node wdata = mux(divSqrt_wen, divSqrt_wdata, T_1048) + node T_1050 = and(wbInfo[0].pipeid, UInt<1>("h1")) + node T_1052 = geq(wbInfo[0].pipeid, UInt<2>("h2")) + node T_1054 = and(T_1050, UInt<1>("h0")) + node T_1056 = geq(T_1050, UInt<1>("h1")) + node T_1057 = mux(T_1056, FPUFMAPipe_1_1.io.out.bits.exc, sfma.io.out.bits.exc) + node T_1059 = and(T_1050, UInt<1>("h0")) + node T_1061 = geq(T_1050, UInt<1>("h1")) + node T_1062 = mux(T_1061, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) + node wexc = mux(T_1052, T_1057, T_1062) + node T_1064 = eq(wbInfo[0].cp, UInt<1>("h0")) + node T_1065 = bits(wen, 0, 0) + node T_1066 = and(T_1064, T_1065) + node T_1067 = or(T_1066, divSqrt_wen) + when T_1067 : infer mport T_1068 = regfile[waddr], clk - T_1068 <= wdata @[fpu.scala 654:20] - skip @[fpu.scala 653:51] - node T_1069 = bits(wen, 0, 0) @[fpu.scala 666:28] - node T_1070 = and(wbInfo[0].cp, T_1069) @[fpu.scala 666:22] - when T_1070 : @[fpu.scala 666:33] - io.cp_resp.bits.data <= wdata @[fpu.scala 667:26] - io.cp_resp.valid <= UInt<1>("h01") @[fpu.scala 668:22] - skip @[fpu.scala 666:33] - node T_1073 = eq(ex_reg_valid, UInt<1>("h00")) @[fpu.scala 670:22] - io.cp_req.ready <= T_1073 @[fpu.scala 670:19] - node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) @[fpu.scala 672:37] - reg wb_toint_exc : UInt<5>, clk - when mem_ctrl.toint : @[Reg.scala 29:19] - wb_toint_exc <= fpiu.io.out.bits.exc @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_1074 = or(wb_toint_valid, divSqrt_wen) @[fpu.scala 674:41] - node T_1075 = bits(wen, 0, 0) @[fpu.scala 674:62] - node T_1076 = or(T_1074, T_1075) @[fpu.scala 674:56] - io.fcsr_flags.valid <= T_1076 @[fpu.scala 674:23] - node T_1078 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) @[fpu.scala 676:8] - node T_1080 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) @[fpu.scala 677:8] - node T_1081 = or(T_1078, T_1080) @[fpu.scala 676:48] - node T_1082 = bits(wen, 0, 0) @[fpu.scala 678:12] - node T_1084 = mux(T_1082, wexc, UInt<1>("h00")) @[fpu.scala 678:8] - node T_1085 = or(T_1081, T_1084) @[fpu.scala 677:46] - io.fcsr_flags.bits <= T_1085 @[fpu.scala 675:22] - node T_1086 = or(mem_ctrl.div, mem_ctrl.sqrt) @[fpu.scala 680:51] - node T_1087 = and(mem_reg_valid, T_1086) @[fpu.scala 680:34] - node T_1089 = eq(divSqrt_inReady, UInt<1>("h00")) @[fpu.scala 680:73] - node T_1091 = neq(wen, UInt<1>("h00")) @[fpu.scala 680:97] - node T_1092 = or(T_1089, T_1091) @[fpu.scala 680:90] - node units_busy = and(T_1087, T_1092) @[fpu.scala 680:69] - node T_1093 = and(ex_reg_valid, ex_ctrl.wflags) @[fpu.scala 681:33] - node T_1094 = and(mem_reg_valid, mem_ctrl.wflags) @[fpu.scala 681:68] - node T_1095 = or(T_1093, T_1094) @[fpu.scala 681:51] - node T_1096 = and(wb_reg_valid, wb_ctrl.toint) @[fpu.scala 681:103] - node T_1097 = or(T_1095, T_1096) @[fpu.scala 681:87] - node T_1099 = neq(wen, UInt<1>("h00")) @[fpu.scala 681:127] - node T_1100 = or(T_1097, T_1099) @[fpu.scala 681:120] - node T_1101 = or(T_1100, divSqrt_in_flight) @[fpu.scala 681:131] - node T_1103 = eq(T_1101, UInt<1>("h00")) @[fpu.scala 681:18] - io.fcsr_rdy <= T_1103 @[fpu.scala 681:15] - node T_1104 = or(units_busy, write_port_busy) @[fpu.scala 682:29] - node T_1105 = or(T_1104, divSqrt_in_flight) @[fpu.scala 682:48] - io.nack_mem <= T_1105 @[fpu.scala 682:15] - io.dec <- fp_decoder.io.sigs @[fpu.scala 683:10] - node T_1107 = eq(wb_cp_valid, UInt<1>("h00")) @[fpu.scala 685:36] - node T_1108 = and(wb_reg_valid, T_1107) @[fpu.scala 685:33] - node T_1110 = eq(mem_ctrl.single, UInt<1>("h00")) @[fpu.scala 609:65] - node T_1111 = and(mem_ctrl.fma, T_1110) @[fpu.scala 609:62] - node T_1113 = or(UInt<1>("h00"), T_1111) @[fpu.scala 684:123] - node T_1114 = or(T_1113, mem_ctrl.div) @[fpu.scala 685:96] - node T_1115 = or(T_1114, mem_ctrl.sqrt) @[fpu.scala 685:112] - reg T_1116 : UInt<1>, clk + T_1068 <= wdata + node T_1069 = bits(wen, 0, 0) + node T_1070 = and(wbInfo[0].cp, T_1069) + when T_1070 : + io.cp_resp.bits.data <= wdata + io.cp_resp.valid <= UInt<1>("h1") + node T_1073 = eq(ex_reg_valid, UInt<1>("h0")) + io.cp_req.ready <= T_1073 + node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) + reg wb_toint_exc : UInt<5>, clk with : + reset => (UInt<1>("h0"), wb_toint_exc) + when mem_ctrl.toint : + wb_toint_exc <= fpiu.io.out.bits.exc + node T_1074 = or(wb_toint_valid, divSqrt_wen) + node T_1075 = bits(wen, 0, 0) + node T_1076 = or(T_1074, T_1075) + io.fcsr_flags.valid <= T_1076 + node T_1078 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h0")) + node T_1080 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h0")) + node T_1081 = or(T_1078, T_1080) + node T_1082 = bits(wen, 0, 0) + node T_1084 = mux(T_1082, wexc, UInt<1>("h0")) + node T_1085 = or(T_1081, T_1084) + io.fcsr_flags.bits <= T_1085 + node T_1086 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_1087 = and(mem_reg_valid, T_1086) + node T_1089 = eq(divSqrt_inReady, UInt<1>("h0")) + node T_1091 = neq(wen, UInt<1>("h0")) + node T_1092 = or(T_1089, T_1091) + node units_busy = and(T_1087, T_1092) + node T_1093 = and(ex_reg_valid, ex_ctrl.wflags) + node T_1094 = and(mem_reg_valid, mem_ctrl.wflags) + node T_1095 = or(T_1093, T_1094) + node T_1096 = and(wb_reg_valid, wb_ctrl.toint) + node T_1097 = or(T_1095, T_1096) + node T_1099 = neq(wen, UInt<1>("h0")) + node T_1100 = or(T_1097, T_1099) + node T_1101 = or(T_1100, divSqrt_in_flight) + node T_1103 = eq(T_1101, UInt<1>("h0")) + io.fcsr_rdy <= T_1103 + node T_1104 = or(units_busy, write_port_busy) + node T_1105 = or(T_1104, divSqrt_in_flight) + io.nack_mem <= T_1105 + io.dec <- fp_decoder.io.sigs + node T_1107 = eq(wb_cp_valid, UInt<1>("h0")) + node T_1108 = and(wb_reg_valid, T_1107) + node T_1110 = eq(mem_ctrl.single, UInt<1>("h0")) + node T_1111 = and(mem_ctrl.fma, T_1110) + node T_1113 = or(UInt<1>("h0"), T_1111) + node T_1114 = or(T_1113, mem_ctrl.div) + node T_1115 = or(T_1114, mem_ctrl.sqrt) + reg T_1116 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_1116) T_1116 <= T_1115 - node T_1117 = and(T_1108, T_1116) @[fpu.scala 685:49] - io.sboard_set <= T_1117 @[fpu.scala 685:17] - node T_1119 = eq(wb_cp_valid, UInt<1>("h00")) @[fpu.scala 686:20] - node T_1120 = bits(wen, 0, 0) @[fpu.scala 686:56] - node T_1122 = eq(wbInfo[0].pipeid, UInt<2>("h03")) @[fpu.scala 686:99] - node T_1124 = or(UInt<1>("h00"), T_1122) @[fpu.scala 684:123] - node T_1125 = and(T_1120, T_1124) @[fpu.scala 686:60] - node T_1126 = or(divSqrt_wen, T_1125) @[fpu.scala 686:49] - node T_1127 = and(T_1119, T_1126) @[fpu.scala 686:33] - io.sboard_clr <= T_1127 @[fpu.scala 686:17] - io.sboard_clra <= waddr @[fpu.scala 687:18] - node T_1128 = bits(ex_rm, 2, 2) @[fpu.scala 689:25] - node T_1129 = and(T_1128, ex_ctrl.round) @[fpu.scala 689:29] - io.illegal_rm <= T_1129 @[fpu.scala 689:17] - divSqrt_wdata <= UInt<1>("h00") @[fpu.scala 691:17] - divSqrt_flags <= UInt<1>("h00") @[fpu.scala 692:17] - reg T_1133 : UInt<1>, clk - reg T_1135 : UInt, clk - reg T_1137 : UInt, clk - reg T_1139 : UInt, clk - inst DivSqrtRecF64_1 of DivSqrtRecF64 @[fpu.scala 700:25] + node T_1117 = and(T_1108, T_1116) + io.sboard_set <= T_1117 + node T_1119 = eq(wb_cp_valid, UInt<1>("h0")) + node T_1120 = bits(wen, 0, 0) + node T_1122 = eq(wbInfo[0].pipeid, UInt<2>("h3")) + node T_1124 = or(UInt<1>("h0"), T_1122) + node T_1125 = and(T_1120, T_1124) + node T_1126 = or(divSqrt_wen, T_1125) + node T_1127 = and(T_1119, T_1126) + io.sboard_clr <= T_1127 + io.sboard_clra <= waddr + node T_1128 = bits(ex_rm, 2, 2) + node T_1129 = and(T_1128, ex_ctrl.round) + io.illegal_rm <= T_1129 + divSqrt_wdata <= UInt<1>("h0") + divSqrt_flags <= UInt<1>("h0") + reg T_1133 : UInt<1>, clk with : + reset => (UInt<1>("h0"), T_1133) + reg T_1135 : UInt, clk with : + reset => (UInt<1>("h0"), T_1135) + reg T_1137 : UInt, clk with : + reset => (UInt<1>("h0"), T_1137) + reg T_1139 : UInt, clk with : + reset => (UInt<1>("h0"), T_1139) + inst DivSqrtRecF64_1 of DivSqrtRecF64 DivSqrtRecF64_1.io is invalid DivSqrtRecF64_1.clk <= clk DivSqrtRecF64_1.reset <= reset - node T_1140 = mux(DivSqrtRecF64_1.io.sqrtOp, DivSqrtRecF64_1.io.inReady_sqrt, DivSqrtRecF64_1.io.inReady_div) @[fpu.scala 701:27] - divSqrt_inReady <= T_1140 @[fpu.scala 701:21] - node T_1141 = or(DivSqrtRecF64_1.io.outValid_div, DivSqrtRecF64_1.io.outValid_sqrt) @[fpu.scala 702:52] - node T_1142 = or(mem_ctrl.div, mem_ctrl.sqrt) @[fpu.scala 703:58] - node T_1143 = and(mem_reg_valid, T_1142) @[fpu.scala 703:41] - node T_1145 = eq(divSqrt_in_flight, UInt<1>("h00")) @[fpu.scala 703:79] - node T_1146 = and(T_1143, T_1145) @[fpu.scala 703:76] - DivSqrtRecF64_1.io.inValid <= T_1146 @[fpu.scala 703:24] - DivSqrtRecF64_1.io.sqrtOp <= mem_ctrl.sqrt @[fpu.scala 704:23] - DivSqrtRecF64_1.io.a <= fpiu.io.as_double.in1 @[fpu.scala 705:18] - DivSqrtRecF64_1.io.b <= fpiu.io.as_double.in2 @[fpu.scala 706:18] - DivSqrtRecF64_1.io.roundingMode <= fpiu.io.as_double.rm @[fpu.scala 707:29] - node T_1147 = and(DivSqrtRecF64_1.io.inValid, divSqrt_inReady) @[fpu.scala 709:30] - when T_1147 : @[fpu.scala 709:50] - divSqrt_in_flight <= UInt<1>("h01") @[fpu.scala 710:25] - divSqrt_killed <= killm @[fpu.scala 711:22] - T_1133 <= mem_ctrl.single @[fpu.scala 712:22] - node T_1149 = bits(mem_reg_inst, 11, 7) @[fpu.scala 713:36] - divSqrt_waddr <= T_1149 @[fpu.scala 713:21] - T_1135 <= DivSqrtRecF64_1.io.roundingMode @[fpu.scala 714:18] - skip @[fpu.scala 709:50] - when T_1141 : @[fpu.scala 717:29] - node T_1151 = eq(divSqrt_killed, UInt<1>("h00")) @[fpu.scala 718:22] - divSqrt_wen <= T_1151 @[fpu.scala 718:19] - T_1139 <= DivSqrtRecF64_1.io.out @[fpu.scala 719:28] - divSqrt_in_flight <= UInt<1>("h00") @[fpu.scala 720:25] - T_1137 <= DivSqrtRecF64_1.io.exceptionFlags @[fpu.scala 721:28] - skip @[fpu.scala 717:29] - inst RecFNToRecFN_2_1 of RecFNToRecFN_2 @[fpu.scala 724:34] + node T_1140 = mux(DivSqrtRecF64_1.io.sqrtOp, DivSqrtRecF64_1.io.inReady_sqrt, DivSqrtRecF64_1.io.inReady_div) + divSqrt_inReady <= T_1140 + node T_1141 = or(DivSqrtRecF64_1.io.outValid_div, DivSqrtRecF64_1.io.outValid_sqrt) + node T_1142 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_1143 = and(mem_reg_valid, T_1142) + node T_1145 = eq(divSqrt_in_flight, UInt<1>("h0")) + node T_1146 = and(T_1143, T_1145) + DivSqrtRecF64_1.io.inValid <= T_1146 + DivSqrtRecF64_1.io.sqrtOp <= mem_ctrl.sqrt + DivSqrtRecF64_1.io.a <= fpiu.io.as_double.in1 + DivSqrtRecF64_1.io.b <= fpiu.io.as_double.in2 + DivSqrtRecF64_1.io.roundingMode <= fpiu.io.as_double.rm + node T_1147 = and(DivSqrtRecF64_1.io.inValid, divSqrt_inReady) + when T_1147 : + divSqrt_in_flight <= UInt<1>("h1") + divSqrt_killed <= killm + T_1133 <= mem_ctrl.single + node T_1149 = bits(mem_reg_inst, 11, 7) + divSqrt_waddr <= T_1149 + T_1135 <= DivSqrtRecF64_1.io.roundingMode + when T_1141 : + node T_1151 = eq(divSqrt_killed, UInt<1>("h0")) + divSqrt_wen <= T_1151 + T_1139 <= DivSqrtRecF64_1.io.out + divSqrt_in_flight <= UInt<1>("h0") + T_1137 <= DivSqrtRecF64_1.io.exceptionFlags + inst RecFNToRecFN_2_1 of RecFNToRecFN_2 RecFNToRecFN_2_1.io is invalid RecFNToRecFN_2_1.clk <= clk RecFNToRecFN_2_1.reset <= reset - RecFNToRecFN_2_1.io.in <= T_1139 @[fpu.scala 725:28] - RecFNToRecFN_2_1.io.roundingMode <= T_1135 @[fpu.scala 726:38] - node T_1153 = mux(T_1133, RecFNToRecFN_2_1.io.out, T_1139) @[fpu.scala 727:25] - divSqrt_wdata <= T_1153 @[fpu.scala 727:19] - node T_1155 = mux(T_1133, RecFNToRecFN_2_1.io.exceptionFlags, UInt<1>("h00")) @[fpu.scala 728:48] - node T_1156 = or(T_1137, T_1155) @[fpu.scala 728:43] - divSqrt_flags <= T_1156 @[fpu.scala 728:19] - - module ClientUncachedTileLinkIOArbiter : + RecFNToRecFN_2_1.io.in <= T_1139 + RecFNToRecFN_2_1.io.roundingMode <= T_1135 + node T_1153 = mux(T_1133, RecFNToRecFN_2_1.io.out, T_1139) + divSqrt_wdata <= T_1153 + node T_1155 = mux(T_1133, RecFNToRecFN_2_1.io.exceptionFlags, UInt<1>("h0")) + node T_1156 = or(T_1137, T_1155) + divSqrt_flags <= T_1156 + + module ClientUncachedTileLinkIOArbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - io.out <- io.in[0] @[Arbiters.scala 181:19] - - module RRArbiter : + io.out <- io.in[0] + + module RRArbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<1>("h01") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - node T_220 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<1>, clk - when T_220 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node T_223 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_224 = or(T_223, io.in[0].valid) @[Arbiter.scala 23:72] - node T_226 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_228 = eq(T_223, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_230 = eq(T_224, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_231 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_232 = or(T_231, T_228) @[Arbiter.scala 64:50] - node T_233 = and(T_226, grantMask_1) @[Arbiter.scala 64:34] - node T_234 = or(T_233, T_230) @[Arbiter.scala 64:50] - node T_235 = and(T_232, io.out.ready) @[Arbiter.scala 52:21] - io.in[0].ready <= T_235 @[Arbiter.scala 52:16] - node T_236 = and(T_234, io.out.ready) @[Arbiter.scala 52:21] - io.in[1].ready <= T_236 @[Arbiter.scala 52:16] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module PTW : + choice <= UInt<1>("h1") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + node T_220 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<1>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_220 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node T_223 = or(validMask_0, validMask_1) + node T_224 = or(T_223, io.in[0].valid) + node T_226 = eq(validMask_0, UInt<1>("h0")) + node T_228 = eq(T_223, UInt<1>("h0")) + node T_230 = eq(T_224, UInt<1>("h0")) + node T_231 = and(UInt<1>("h1"), grantMask_0) + node T_232 = or(T_231, T_228) + node T_233 = and(T_226, grantMask_1) + node T_234 = or(T_233, T_230) + node T_235 = and(T_232, io.out.ready) + io.in[0].ready <= T_235 + node T_236 = and(T_234, io.out.ready) + io.in[1].ready <= T_236 + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_1 : + choice <= UInt<1>("h1") + + module PTW : input clk : Clock input reset : UInt<1> - output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : {asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} - + output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}}, flip resp : { valid : UInt<1>, bits : { pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}}, flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : { flip ptbr : { asid : UInt<7>, ppn : UInt<38>}, flip invalidate : UInt<1>, flip status : { debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero3 : UInt<31>, sd_rv32 : UInt<1>, zero2 : UInt<2>, vm : UInt<5>, zero1 : UInt<4>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} + io is invalid - reg state : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg count : UInt<2>, clk - reg s1_kill : UInt<1>, clk - s1_kill <= UInt<1>("h00") - reg r_req : {prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}, clk - reg r_req_dest : UInt, clk - reg r_pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clk - node T_2207 = shr(r_req.addr, 18) @[ptw.scala 86:58] - node vpn_idxs_0 = bits(T_2207, 8, 0) @[ptw.scala 86:88] - node T_2208 = shr(r_req.addr, 9) @[ptw.scala 86:58] - node vpn_idxs_1 = bits(T_2208, 8, 0) @[ptw.scala 86:88] - node T_2209 = shr(r_req.addr, 0) @[ptw.scala 86:58] - node vpn_idxs_2 = bits(T_2209, 8, 0) @[ptw.scala 86:88] - node T_2211 = and(count, UInt<1>("h01")) @[Package.scala 18:26] - node T_2213 = geq(count, UInt<2>("h02")) @[Package.scala 19:17] - node T_2215 = and(T_2211, UInt<1>("h00")) @[Package.scala 18:26] - node T_2217 = geq(T_2211, UInt<1>("h01")) @[Package.scala 19:17] - node T_2218 = mux(T_2217, vpn_idxs_1, vpn_idxs_0) @[Package.scala 19:12] - node vpn_idx = mux(T_2213, vpn_idxs_2, T_2218) @[Package.scala 19:12] - inst arb of RRArbiter @[ptw.scala 89:19] + reg state : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg count : UInt<2>, clk with : + reset => (UInt<1>("h0"), count) + reg s1_kill : UInt<1>, clk with : + reset => (UInt<1>("h0"), s1_kill) + s1_kill <= UInt<1>("h0") + reg r_req : { prv : UInt<2>, pum : UInt<1>, mxr : UInt<1>, addr : UInt<27>, store : UInt<1>, fetch : UInt<1>}, clk with : + reset => (UInt<1>("h0"), r_req) + reg r_req_dest : UInt, clk with : + reset => (UInt<1>("h0"), r_req_dest) + reg r_pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clk with : + reset => (UInt<1>("h0"), r_pte) + node T_2207 = shr(r_req.addr, 18) + node vpn_idxs_0 = bits(T_2207, 8, 0) + node T_2208 = shr(r_req.addr, 9) + node vpn_idxs_1 = bits(T_2208, 8, 0) + node T_2209 = shr(r_req.addr, 0) + node vpn_idxs_2 = bits(T_2209, 8, 0) + node T_2211 = and(count, UInt<1>("h1")) + node T_2213 = geq(count, UInt<2>("h2")) + node T_2215 = and(T_2211, UInt<1>("h0")) + node T_2217 = geq(T_2211, UInt<1>("h1")) + node T_2218 = mux(T_2217, vpn_idxs_1, vpn_idxs_0) + node vpn_idx = mux(T_2213, vpn_idxs_2, T_2218) + inst arb of RRArbiter arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in[0] <- io.requestor[0].req @[ptw.scala 90:13] - arb.io.in[1] <- io.requestor[1].req @[ptw.scala 90:13] - node T_2226 = eq(state, UInt<3>("h00")) @[ptw.scala 91:29] - arb.io.out.ready <= T_2226 @[ptw.scala 91:20] - wire T_2251 : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[ptw.scala 94:33] - T_2251 is invalid @[ptw.scala 94:33] - node T_2263 = bits(io.mem.resp.bits.data, 0, 0) @[ptw.scala 94:33] - T_2251.v <= T_2263 @[ptw.scala 94:33] - node T_2264 = bits(io.mem.resp.bits.data, 1, 1) @[ptw.scala 94:33] - T_2251.r <= T_2264 @[ptw.scala 94:33] - node T_2265 = bits(io.mem.resp.bits.data, 2, 2) @[ptw.scala 94:33] - T_2251.w <= T_2265 @[ptw.scala 94:33] - node T_2266 = bits(io.mem.resp.bits.data, 3, 3) @[ptw.scala 94:33] - T_2251.x <= T_2266 @[ptw.scala 94:33] - node T_2267 = bits(io.mem.resp.bits.data, 4, 4) @[ptw.scala 94:33] - T_2251.u <= T_2267 @[ptw.scala 94:33] - node T_2268 = bits(io.mem.resp.bits.data, 5, 5) @[ptw.scala 94:33] - T_2251.g <= T_2268 @[ptw.scala 94:33] - node T_2269 = bits(io.mem.resp.bits.data, 6, 6) @[ptw.scala 94:33] - T_2251.a <= T_2269 @[ptw.scala 94:33] - node T_2270 = bits(io.mem.resp.bits.data, 7, 7) @[ptw.scala 94:33] - T_2251.d <= T_2270 @[ptw.scala 94:33] - node T_2271 = bits(io.mem.resp.bits.data, 9, 8) @[ptw.scala 94:33] - T_2251.reserved_for_software <= T_2271 @[ptw.scala 94:33] - node T_2272 = bits(io.mem.resp.bits.data, 47, 10) @[ptw.scala 94:33] - T_2251.ppn <= T_2272 @[ptw.scala 94:33] - node T_2273 = bits(io.mem.resp.bits.data, 63, 48) @[ptw.scala 94:33] - T_2251.reserved_for_hardware <= T_2273 @[ptw.scala 94:33] - wire T_2298 : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[ptw.scala 95:45] - T_2298 is invalid @[ptw.scala 95:45] - node T_2310 = bits(io.mem.resp.bits.data, 0, 0) @[ptw.scala 95:45] - T_2298.v <= T_2310 @[ptw.scala 95:45] - node T_2311 = bits(io.mem.resp.bits.data, 1, 1) @[ptw.scala 95:45] - T_2298.r <= T_2311 @[ptw.scala 95:45] - node T_2312 = bits(io.mem.resp.bits.data, 2, 2) @[ptw.scala 95:45] - T_2298.w <= T_2312 @[ptw.scala 95:45] - node T_2313 = bits(io.mem.resp.bits.data, 3, 3) @[ptw.scala 95:45] - T_2298.x <= T_2313 @[ptw.scala 95:45] - node T_2314 = bits(io.mem.resp.bits.data, 4, 4) @[ptw.scala 95:45] - T_2298.u <= T_2314 @[ptw.scala 95:45] - node T_2315 = bits(io.mem.resp.bits.data, 5, 5) @[ptw.scala 95:45] - T_2298.g <= T_2315 @[ptw.scala 95:45] - node T_2316 = bits(io.mem.resp.bits.data, 6, 6) @[ptw.scala 95:45] - T_2298.a <= T_2316 @[ptw.scala 95:45] - node T_2317 = bits(io.mem.resp.bits.data, 7, 7) @[ptw.scala 95:45] - T_2298.d <= T_2317 @[ptw.scala 95:45] - node T_2318 = bits(io.mem.resp.bits.data, 9, 8) @[ptw.scala 95:45] - T_2298.reserved_for_software <= T_2318 @[ptw.scala 95:45] - node T_2319 = bits(io.mem.resp.bits.data, 47, 10) @[ptw.scala 95:45] - T_2298.ppn <= T_2319 @[ptw.scala 95:45] - node T_2320 = bits(io.mem.resp.bits.data, 63, 48) @[ptw.scala 95:45] - T_2298.reserved_for_hardware <= T_2320 @[ptw.scala 95:45] - wire pte : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + arb.io.in[0] <- io.requestor[0].req + arb.io.in[1] <- io.requestor[1].req + node T_2226 = eq(state, UInt<3>("h0")) + arb.io.out.ready <= T_2226 + wire T_2251 : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + T_2251 is invalid + node T_2263 = bits(io.mem.resp.bits.data, 0, 0) + T_2251.v <= T_2263 + node T_2264 = bits(io.mem.resp.bits.data, 1, 1) + T_2251.r <= T_2264 + node T_2265 = bits(io.mem.resp.bits.data, 2, 2) + T_2251.w <= T_2265 + node T_2266 = bits(io.mem.resp.bits.data, 3, 3) + T_2251.x <= T_2266 + node T_2267 = bits(io.mem.resp.bits.data, 4, 4) + T_2251.u <= T_2267 + node T_2268 = bits(io.mem.resp.bits.data, 5, 5) + T_2251.g <= T_2268 + node T_2269 = bits(io.mem.resp.bits.data, 6, 6) + T_2251.a <= T_2269 + node T_2270 = bits(io.mem.resp.bits.data, 7, 7) + T_2251.d <= T_2270 + node T_2271 = bits(io.mem.resp.bits.data, 9, 8) + T_2251.reserved_for_software <= T_2271 + node T_2272 = bits(io.mem.resp.bits.data, 47, 10) + T_2251.ppn <= T_2272 + node T_2273 = bits(io.mem.resp.bits.data, 63, 48) + T_2251.reserved_for_hardware <= T_2273 + wire T_2298 : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + T_2298 is invalid + node T_2310 = bits(io.mem.resp.bits.data, 0, 0) + T_2298.v <= T_2310 + node T_2311 = bits(io.mem.resp.bits.data, 1, 1) + T_2298.r <= T_2311 + node T_2312 = bits(io.mem.resp.bits.data, 2, 2) + T_2298.w <= T_2312 + node T_2313 = bits(io.mem.resp.bits.data, 3, 3) + T_2298.x <= T_2313 + node T_2314 = bits(io.mem.resp.bits.data, 4, 4) + T_2298.u <= T_2314 + node T_2315 = bits(io.mem.resp.bits.data, 5, 5) + T_2298.g <= T_2315 + node T_2316 = bits(io.mem.resp.bits.data, 6, 6) + T_2298.a <= T_2316 + node T_2317 = bits(io.mem.resp.bits.data, 7, 7) + T_2298.d <= T_2317 + node T_2318 = bits(io.mem.resp.bits.data, 9, 8) + T_2298.reserved_for_software <= T_2318 + node T_2319 = bits(io.mem.resp.bits.data, 47, 10) + T_2298.ppn <= T_2319 + node T_2320 = bits(io.mem.resp.bits.data, 63, 48) + T_2298.reserved_for_hardware <= T_2320 + wire pte : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} pte is invalid pte <- T_2298 - node T_2332 = bits(T_2251.ppn, 19, 0) @[ptw.scala 96:23] - pte.ppn <= T_2332 @[ptw.scala 96:13] - node T_2333 = shr(T_2251.ppn, 20) @[ptw.scala 97:20] - node T_2335 = neq(T_2333, UInt<1>("h00")) @[ptw.scala 97:32] - when T_2335 : @[ptw.scala 97:39] - pte.v <= UInt<1>("h00") @[ptw.scala 97:47] - skip @[ptw.scala 97:39] - node T_2337 = cat(r_pte.ppn, vpn_idx) @[Cat.scala 20:58] - node pte_addr = shl(T_2337, 3) @[ptw.scala 100:42] - node T_2338 = and(arb.io.out.ready, arb.io.out.valid) @[Decoupled.scala 21:42] - when T_2338 : @[ptw.scala 102:28] - r_req <- arb.io.out.bits @[ptw.scala 103:11] - r_req_dest <= arb.io.chosen @[ptw.scala 104:16] - r_pte.ppn <= io.dpath.ptbr.ppn @[ptw.scala 105:15] - skip @[ptw.scala 102:28] - reg T_2340 : UInt<8>, clk - reg T_2342 : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg T_2349 : UInt<32>[8], clk - reg T_2357 : UInt<20>[8], clk - node T_2359 = eq(T_2349[0], pte_addr) @[ptw.scala 115:27] - node T_2360 = eq(T_2349[1], pte_addr) @[ptw.scala 115:27] - node T_2361 = eq(T_2349[2], pte_addr) @[ptw.scala 115:27] - node T_2362 = eq(T_2349[3], pte_addr) @[ptw.scala 115:27] - node T_2363 = eq(T_2349[4], pte_addr) @[ptw.scala 115:27] - node T_2364 = eq(T_2349[5], pte_addr) @[ptw.scala 115:27] - node T_2365 = eq(T_2349[6], pte_addr) @[ptw.scala 115:27] - node T_2366 = eq(T_2349[7], pte_addr) @[ptw.scala 115:27] - node T_2367 = cat(T_2360, T_2359) @[Cat.scala 20:58] - node T_2368 = cat(T_2362, T_2361) @[Cat.scala 20:58] - node T_2369 = cat(T_2368, T_2367) @[Cat.scala 20:58] - node T_2370 = cat(T_2364, T_2363) @[Cat.scala 20:58] - node T_2371 = cat(T_2366, T_2365) @[Cat.scala 20:58] - node T_2372 = cat(T_2371, T_2370) @[Cat.scala 20:58] - node T_2373 = cat(T_2372, T_2369) @[Cat.scala 20:58] - node T_2374 = and(T_2373, T_2342) @[ptw.scala 115:48] - node T_2376 = neq(T_2374, UInt<1>("h00")) @[ptw.scala 116:20] - node T_2378 = eq(pte.r, UInt<1>("h00")) @[ptw.scala 52:36] - node T_2379 = and(pte.v, T_2378) @[ptw.scala 52:33] - node T_2381 = eq(pte.w, UInt<1>("h00")) @[ptw.scala 52:42] - node T_2382 = and(T_2379, T_2381) @[ptw.scala 52:39] - node T_2384 = eq(pte.x, UInt<1>("h00")) @[ptw.scala 52:48] - node T_2385 = and(T_2382, T_2384) @[ptw.scala 52:45] - node T_2386 = and(io.mem.resp.valid, T_2385) @[ptw.scala 117:29] - node T_2388 = eq(T_2376, UInt<1>("h00")) @[ptw.scala 117:47] - node T_2389 = and(T_2386, T_2388) @[ptw.scala 117:44] - when T_2389 : @[ptw.scala 117:53] - node T_2390 = not(T_2342) @[ptw.scala 118:25] - node T_2392 = eq(T_2390, UInt<1>("h00")) @[ptw.scala 118:25] - node T_2394 = dshr(T_2340, UInt<1>("h01")) @[Cache.scala 104:27] - node T_2395 = bits(T_2394, 0, 0) @[Cache.scala 104:27] - node T_2396 = cat(UInt<1>("h01"), T_2395) @[Cat.scala 20:58] - node T_2397 = dshr(T_2340, T_2396) @[Cache.scala 104:27] - node T_2398 = bits(T_2397, 0, 0) @[Cache.scala 104:27] - node T_2399 = cat(T_2396, T_2398) @[Cat.scala 20:58] - node T_2400 = dshr(T_2340, T_2399) @[Cache.scala 104:27] - node T_2401 = bits(T_2400, 0, 0) @[Cache.scala 104:27] - node T_2402 = cat(T_2399, T_2401) @[Cat.scala 20:58] - node T_2403 = bits(T_2402, 2, 0) @[Cache.scala 105:8] - node T_2404 = not(T_2342) @[ptw.scala 118:61] - node T_2405 = bits(T_2404, 0, 0) @[OneHot.scala 35:40] - node T_2406 = bits(T_2404, 1, 1) @[OneHot.scala 35:40] - node T_2407 = bits(T_2404, 2, 2) @[OneHot.scala 35:40] - node T_2408 = bits(T_2404, 3, 3) @[OneHot.scala 35:40] - node T_2409 = bits(T_2404, 4, 4) @[OneHot.scala 35:40] - node T_2410 = bits(T_2404, 5, 5) @[OneHot.scala 35:40] - node T_2411 = bits(T_2404, 6, 6) @[OneHot.scala 35:40] - node T_2412 = bits(T_2404, 7, 7) @[OneHot.scala 35:40] - node T_2421 = mux(T_2411, UInt<3>("h06"), UInt<3>("h07")) @[Mux.scala 31:69] - node T_2422 = mux(T_2410, UInt<3>("h05"), T_2421) @[Mux.scala 31:69] - node T_2423 = mux(T_2409, UInt<3>("h04"), T_2422) @[Mux.scala 31:69] - node T_2424 = mux(T_2408, UInt<2>("h03"), T_2423) @[Mux.scala 31:69] - node T_2425 = mux(T_2407, UInt<2>("h02"), T_2424) @[Mux.scala 31:69] - node T_2426 = mux(T_2406, UInt<1>("h01"), T_2425) @[Mux.scala 31:69] - node T_2427 = mux(T_2405, UInt<1>("h00"), T_2426) @[Mux.scala 31:69] - node T_2428 = mux(T_2392, T_2403, T_2427) @[ptw.scala 118:18] - node T_2430 = dshl(UInt<1>("h01"), T_2428) @[OneHot.scala 44:15] - node T_2431 = or(T_2342, T_2430) @[ptw.scala 119:22] - T_2342 <= T_2431 @[ptw.scala 119:13] - T_2349[T_2428] <= pte_addr @[ptw.scala 120:15] - T_2357[T_2428] <= pte.ppn @[ptw.scala 121:15] - skip @[ptw.scala 117:53] - node T_2432 = eq(state, UInt<3>("h01")) @[ptw.scala 123:24] - node T_2433 = and(T_2376, T_2432) @[ptw.scala 123:15] - when T_2433 : @[ptw.scala 123:35] - node T_2434 = bits(T_2374, 7, 4) @[OneHot.scala 22:18] - node T_2435 = bits(T_2374, 3, 0) @[OneHot.scala 23:18] - node T_2437 = neq(T_2434, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2438 = or(T_2434, T_2435) @[OneHot.scala 24:28] - node T_2439 = bits(T_2438, 3, 2) @[OneHot.scala 22:18] - node T_2440 = bits(T_2438, 1, 0) @[OneHot.scala 23:18] - node T_2442 = neq(T_2439, UInt<1>("h00")) @[OneHot.scala 24:14] - node T_2443 = or(T_2439, T_2440) @[OneHot.scala 24:28] - node T_2444 = bits(T_2443, 1, 1) @[CircuitMath.scala 21:8] - node T_2445 = cat(T_2442, T_2444) @[Cat.scala 20:58] - node T_2446 = cat(T_2437, T_2445) @[Cat.scala 20:58] - node T_2448 = bits(T_2446, 2, 2) @[Cache.scala 94:20] - node T_2450 = eq(T_2448, UInt<1>("h00")) @[Cache.scala 95:43] - node T_2452 = dshl(UInt<1>("h01"), UInt<1>("h01")) @[Cache.scala 95:37] - node T_2453 = or(T_2340, T_2452) @[Cache.scala 95:37] - node T_2454 = not(T_2340) @[Cache.scala 95:37] - node T_2455 = or(T_2454, T_2452) @[Cache.scala 95:37] - node T_2456 = not(T_2455) @[Cache.scala 95:37] - node T_2457 = mux(T_2450, T_2453, T_2456) @[Cache.scala 95:37] - node T_2458 = cat(UInt<1>("h01"), T_2448) @[Cat.scala 20:58] - node T_2459 = bits(T_2446, 1, 1) @[Cache.scala 94:20] - node T_2461 = eq(T_2459, UInt<1>("h00")) @[Cache.scala 95:43] - node T_2463 = dshl(UInt<1>("h01"), T_2458) @[Cache.scala 95:37] - node T_2464 = or(T_2457, T_2463) @[Cache.scala 95:37] - node T_2465 = not(T_2457) @[Cache.scala 95:37] - node T_2466 = or(T_2465, T_2463) @[Cache.scala 95:37] - node T_2467 = not(T_2466) @[Cache.scala 95:37] - node T_2468 = mux(T_2461, T_2464, T_2467) @[Cache.scala 95:37] - node T_2469 = cat(T_2458, T_2459) @[Cat.scala 20:58] - node T_2470 = bits(T_2446, 0, 0) @[Cache.scala 94:20] - node T_2472 = eq(T_2470, UInt<1>("h00")) @[Cache.scala 95:43] - node T_2474 = dshl(UInt<1>("h01"), T_2469) @[Cache.scala 95:37] - node T_2475 = or(T_2468, T_2474) @[Cache.scala 95:37] - node T_2476 = not(T_2468) @[Cache.scala 95:37] - node T_2477 = or(T_2476, T_2474) @[Cache.scala 95:37] - node T_2478 = not(T_2477) @[Cache.scala 95:37] - node T_2479 = mux(T_2472, T_2475, T_2478) @[Cache.scala 95:37] - node T_2480 = cat(T_2469, T_2470) @[Cat.scala 20:58] - T_2340 <= T_2479 @[Cache.scala 88:15] - skip @[ptw.scala 123:35] - when io.dpath.invalidate : @[ptw.scala 124:32] - T_2342 <= UInt<1>("h00") @[ptw.scala 124:40] - skip @[ptw.scala 124:32] - node T_2483 = lt(count, UInt<2>("h02")) @[ptw.scala 126:19] - node pte_cache_hit = and(T_2376, T_2483) @[ptw.scala 126:10] - node T_2484 = bits(T_2374, 0, 0) @[Mux.scala 20:36] - node T_2485 = bits(T_2374, 1, 1) @[Mux.scala 20:36] - node T_2486 = bits(T_2374, 2, 2) @[Mux.scala 20:36] - node T_2487 = bits(T_2374, 3, 3) @[Mux.scala 20:36] - node T_2488 = bits(T_2374, 4, 4) @[Mux.scala 20:36] - node T_2489 = bits(T_2374, 5, 5) @[Mux.scala 20:36] - node T_2490 = bits(T_2374, 6, 6) @[Mux.scala 20:36] - node T_2491 = bits(T_2374, 7, 7) @[Mux.scala 20:36] - node T_2493 = mux(T_2484, T_2357[0], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2495 = mux(T_2485, T_2357[1], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2497 = mux(T_2486, T_2357[2], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2499 = mux(T_2487, T_2357[3], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2501 = mux(T_2488, T_2357[4], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2503 = mux(T_2489, T_2357[5], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2505 = mux(T_2490, T_2357[6], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2507 = mux(T_2491, T_2357[7], UInt<1>("h00")) @[Mux.scala 18:72] - node T_2509 = or(T_2493, T_2495) @[Mux.scala 18:72] - node T_2510 = or(T_2509, T_2497) @[Mux.scala 18:72] - node T_2511 = or(T_2510, T_2499) @[Mux.scala 18:72] - node T_2512 = or(T_2511, T_2501) @[Mux.scala 18:72] - node T_2513 = or(T_2512, T_2503) @[Mux.scala 18:72] - node T_2514 = or(T_2513, T_2505) @[Mux.scala 18:72] - node T_2515 = or(T_2514, T_2507) @[Mux.scala 18:72] + node T_2332 = bits(T_2251.ppn, 19, 0) + pte.ppn <= T_2332 + node T_2333 = shr(T_2251.ppn, 20) + node T_2335 = neq(T_2333, UInt<1>("h0")) + when T_2335 : + pte.v <= UInt<1>("h0") + node T_2337 = cat(r_pte.ppn, vpn_idx) + node pte_addr = shl(T_2337, 3) + node T_2338 = and(arb.io.out.ready, arb.io.out.valid) + when T_2338 : + r_req <- arb.io.out.bits + r_req_dest <= arb.io.chosen + r_pte.ppn <= io.dpath.ptbr.ppn + reg T_2340 : UInt<8>, clk with : + reset => (UInt<1>("h0"), T_2340) + reg T_2342 : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg T_2349 : UInt<32>[8], clk with : + reset => (UInt<1>("h0"), T_2349) + reg T_2357 : UInt<20>[8], clk with : + reset => (UInt<1>("h0"), T_2357) + node T_2359 = eq(T_2349[0], pte_addr) + node T_2360 = eq(T_2349[1], pte_addr) + node T_2361 = eq(T_2349[2], pte_addr) + node T_2362 = eq(T_2349[3], pte_addr) + node T_2363 = eq(T_2349[4], pte_addr) + node T_2364 = eq(T_2349[5], pte_addr) + node T_2365 = eq(T_2349[6], pte_addr) + node T_2366 = eq(T_2349[7], pte_addr) + node T_2367 = cat(T_2360, T_2359) + node T_2368 = cat(T_2362, T_2361) + node T_2369 = cat(T_2368, T_2367) + node T_2370 = cat(T_2364, T_2363) + node T_2371 = cat(T_2366, T_2365) + node T_2372 = cat(T_2371, T_2370) + node T_2373 = cat(T_2372, T_2369) + node T_2374 = and(T_2373, T_2342) + node T_2376 = neq(T_2374, UInt<1>("h0")) + node T_2378 = eq(pte.r, UInt<1>("h0")) + node T_2379 = and(pte.v, T_2378) + node T_2381 = eq(pte.w, UInt<1>("h0")) + node T_2382 = and(T_2379, T_2381) + node T_2384 = eq(pte.x, UInt<1>("h0")) + node T_2385 = and(T_2382, T_2384) + node T_2386 = and(io.mem.resp.valid, T_2385) + node T_2388 = eq(T_2376, UInt<1>("h0")) + node T_2389 = and(T_2386, T_2388) + when T_2389 : + node T_2390 = not(T_2342) + node T_2392 = eq(T_2390, UInt<1>("h0")) + node T_2394 = dshr(T_2340, UInt<1>("h1")) + node T_2395 = bits(T_2394, 0, 0) + node T_2396 = cat(UInt<1>("h1"), T_2395) + node T_2397 = dshr(T_2340, T_2396) + node T_2398 = bits(T_2397, 0, 0) + node T_2399 = cat(T_2396, T_2398) + node T_2400 = dshr(T_2340, T_2399) + node T_2401 = bits(T_2400, 0, 0) + node T_2402 = cat(T_2399, T_2401) + node T_2403 = bits(T_2402, 2, 0) + node T_2404 = not(T_2342) + node T_2405 = bits(T_2404, 0, 0) + node T_2406 = bits(T_2404, 1, 1) + node T_2407 = bits(T_2404, 2, 2) + node T_2408 = bits(T_2404, 3, 3) + node T_2409 = bits(T_2404, 4, 4) + node T_2410 = bits(T_2404, 5, 5) + node T_2411 = bits(T_2404, 6, 6) + node T_2412 = bits(T_2404, 7, 7) + node T_2421 = mux(T_2411, UInt<3>("h6"), UInt<3>("h7")) + node T_2422 = mux(T_2410, UInt<3>("h5"), T_2421) + node T_2423 = mux(T_2409, UInt<3>("h4"), T_2422) + node T_2424 = mux(T_2408, UInt<2>("h3"), T_2423) + node T_2425 = mux(T_2407, UInt<2>("h2"), T_2424) + node T_2426 = mux(T_2406, UInt<1>("h1"), T_2425) + node T_2427 = mux(T_2405, UInt<1>("h0"), T_2426) + node T_2428 = mux(T_2392, T_2403, T_2427) + node T_2430 = dshl(UInt<1>("h1"), T_2428) + node T_2431 = or(T_2342, T_2430) + T_2342 <= T_2431 + T_2349[T_2428] <= pte_addr + T_2357[T_2428] <= pte.ppn + node T_2432 = eq(state, UInt<3>("h1")) + node T_2433 = and(T_2376, T_2432) + when T_2433 : + node T_2434 = bits(T_2374, 7, 4) + node T_2435 = bits(T_2374, 3, 0) + node T_2437 = neq(T_2434, UInt<1>("h0")) + node T_2438 = or(T_2434, T_2435) + node T_2439 = bits(T_2438, 3, 2) + node T_2440 = bits(T_2438, 1, 0) + node T_2442 = neq(T_2439, UInt<1>("h0")) + node T_2443 = or(T_2439, T_2440) + node T_2444 = bits(T_2443, 1, 1) + node T_2445 = cat(T_2442, T_2444) + node T_2446 = cat(T_2437, T_2445) + node T_2448 = bits(T_2446, 2, 2) + node T_2450 = eq(T_2448, UInt<1>("h0")) + node T_2452 = dshl(UInt<1>("h1"), UInt<1>("h1")) + node T_2453 = or(T_2340, T_2452) + node T_2454 = not(T_2340) + node T_2455 = or(T_2454, T_2452) + node T_2456 = not(T_2455) + node T_2457 = mux(T_2450, T_2453, T_2456) + node T_2458 = cat(UInt<1>("h1"), T_2448) + node T_2459 = bits(T_2446, 1, 1) + node T_2461 = eq(T_2459, UInt<1>("h0")) + node T_2463 = dshl(UInt<1>("h1"), T_2458) + node T_2464 = or(T_2457, T_2463) + node T_2465 = not(T_2457) + node T_2466 = or(T_2465, T_2463) + node T_2467 = not(T_2466) + node T_2468 = mux(T_2461, T_2464, T_2467) + node T_2469 = cat(T_2458, T_2459) + node T_2470 = bits(T_2446, 0, 0) + node T_2472 = eq(T_2470, UInt<1>("h0")) + node T_2474 = dshl(UInt<1>("h1"), T_2469) + node T_2475 = or(T_2468, T_2474) + node T_2476 = not(T_2468) + node T_2477 = or(T_2476, T_2474) + node T_2478 = not(T_2477) + node T_2479 = mux(T_2472, T_2475, T_2478) + node T_2480 = cat(T_2469, T_2470) + T_2340 <= T_2479 + when io.dpath.invalidate : + T_2342 <= UInt<1>("h0") + node T_2483 = lt(count, UInt<2>("h2")) + node pte_cache_hit = and(T_2376, T_2483) + node T_2484 = bits(T_2374, 0, 0) + node T_2485 = bits(T_2374, 1, 1) + node T_2486 = bits(T_2374, 2, 2) + node T_2487 = bits(T_2374, 3, 3) + node T_2488 = bits(T_2374, 4, 4) + node T_2489 = bits(T_2374, 5, 5) + node T_2490 = bits(T_2374, 6, 6) + node T_2491 = bits(T_2374, 7, 7) + node T_2493 = mux(T_2484, T_2357[0], UInt<1>("h0")) + node T_2495 = mux(T_2485, T_2357[1], UInt<1>("h0")) + node T_2497 = mux(T_2486, T_2357[2], UInt<1>("h0")) + node T_2499 = mux(T_2487, T_2357[3], UInt<1>("h0")) + node T_2501 = mux(T_2488, T_2357[4], UInt<1>("h0")) + node T_2503 = mux(T_2489, T_2357[5], UInt<1>("h0")) + node T_2505 = mux(T_2490, T_2357[6], UInt<1>("h0")) + node T_2507 = mux(T_2491, T_2357[7], UInt<1>("h0")) + node T_2509 = or(T_2493, T_2495) + node T_2510 = or(T_2509, T_2497) + node T_2511 = or(T_2510, T_2499) + node T_2512 = or(T_2511, T_2501) + node T_2513 = or(T_2512, T_2503) + node T_2514 = or(T_2513, T_2505) + node T_2515 = or(T_2514, T_2507) wire pte_cache_data : UInt<20> pte_cache_data is invalid - pte_cache_data <= T_2515 @[Mux.scala 18:72] - wire T_2541 : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[ptw.scala 129:47] - T_2541 is invalid @[ptw.scala 129:47] + pte_cache_data <= T_2515 + wire T_2541 : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + T_2541 is invalid wire T_2554 : UInt<64> T_2554 is invalid - T_2554 <= UInt<1>("h00") - node T_2555 = bits(T_2554, 0, 0) @[ptw.scala 129:47] - T_2541.v <= T_2555 @[ptw.scala 129:47] - node T_2556 = bits(T_2554, 1, 1) @[ptw.scala 129:47] - T_2541.r <= T_2556 @[ptw.scala 129:47] - node T_2557 = bits(T_2554, 2, 2) @[ptw.scala 129:47] - T_2541.w <= T_2557 @[ptw.scala 129:47] - node T_2558 = bits(T_2554, 3, 3) @[ptw.scala 129:47] - T_2541.x <= T_2558 @[ptw.scala 129:47] - node T_2559 = bits(T_2554, 4, 4) @[ptw.scala 129:47] - T_2541.u <= T_2559 @[ptw.scala 129:47] - node T_2560 = bits(T_2554, 5, 5) @[ptw.scala 129:47] - T_2541.g <= T_2560 @[ptw.scala 129:47] - node T_2561 = bits(T_2554, 6, 6) @[ptw.scala 129:47] - T_2541.a <= T_2561 @[ptw.scala 129:47] - node T_2562 = bits(T_2554, 7, 7) @[ptw.scala 129:47] - T_2541.d <= T_2562 @[ptw.scala 129:47] - node T_2563 = bits(T_2554, 9, 8) @[ptw.scala 129:47] - T_2541.reserved_for_software <= T_2563 @[ptw.scala 129:47] - node T_2564 = bits(T_2554, 47, 10) @[ptw.scala 129:47] - T_2541.ppn <= T_2564 @[ptw.scala 129:47] - node T_2565 = bits(T_2554, 63, 48) @[ptw.scala 129:47] - T_2541.reserved_for_hardware <= T_2565 @[ptw.scala 129:47] - wire pte_wdata : {reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} + T_2554 <= UInt<1>("h0") + node T_2555 = bits(T_2554, 0, 0) + T_2541.v <= T_2555 + node T_2556 = bits(T_2554, 1, 1) + T_2541.r <= T_2556 + node T_2557 = bits(T_2554, 2, 2) + T_2541.w <= T_2557 + node T_2558 = bits(T_2554, 3, 3) + T_2541.x <= T_2558 + node T_2559 = bits(T_2554, 4, 4) + T_2541.u <= T_2559 + node T_2560 = bits(T_2554, 5, 5) + T_2541.g <= T_2560 + node T_2561 = bits(T_2554, 6, 6) + T_2541.a <= T_2561 + node T_2562 = bits(T_2554, 7, 7) + T_2541.d <= T_2562 + node T_2563 = bits(T_2554, 9, 8) + T_2541.reserved_for_software <= T_2563 + node T_2564 = bits(T_2554, 47, 10) + T_2541.ppn <= T_2564 + node T_2565 = bits(T_2554, 63, 48) + T_2541.reserved_for_hardware <= T_2565 + wire pte_wdata : { reserved_for_hardware : UInt<16>, ppn : UInt<38>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} pte_wdata is invalid pte_wdata <- T_2541 - pte_wdata.a <= UInt<1>("h01") @[ptw.scala 130:15] - pte_wdata.d <= r_req.store @[ptw.scala 131:15] - node T_2578 = eq(state, UInt<3>("h01")) @[Package.scala 7:47] - node T_2579 = eq(state, UInt<3>("h04")) @[Package.scala 7:47] - node T_2580 = or(T_2578, T_2579) @[Package.scala 7:62] - io.mem.req.valid <= T_2580 @[ptw.scala 133:24] - io.mem.req.bits.phys <= UInt<1>("h01") @[ptw.scala 134:24] - node T_2582 = eq(state, UInt<3>("h04")) @[ptw.scala 135:37] - node T_2583 = mux(T_2582, UInt<5>("h0a"), UInt<5>("h00")) @[ptw.scala 135:30] - io.mem.req.bits.cmd <= T_2583 @[ptw.scala 135:24] - io.mem.req.bits.typ <= UInt<2>("h03") @[ptw.scala 136:24] - io.mem.req.bits.addr <= pte_addr @[ptw.scala 137:24] - node T_2585 = cat(pte_wdata.r, pte_wdata.v) @[ptw.scala 138:31] - node T_2586 = cat(pte_wdata.u, pte_wdata.x) @[ptw.scala 138:31] - node T_2587 = cat(T_2586, pte_wdata.w) @[ptw.scala 138:31] - node T_2588 = cat(T_2587, T_2585) @[ptw.scala 138:31] - node T_2589 = cat(pte_wdata.d, pte_wdata.a) @[ptw.scala 138:31] - node T_2590 = cat(T_2589, pte_wdata.g) @[ptw.scala 138:31] - node T_2591 = cat(pte_wdata.reserved_for_hardware, pte_wdata.ppn) @[ptw.scala 138:31] - node T_2592 = cat(T_2591, pte_wdata.reserved_for_software) @[ptw.scala 138:31] - node T_2593 = cat(T_2592, T_2590) @[ptw.scala 138:31] - node T_2594 = cat(T_2593, T_2588) @[ptw.scala 138:31] - io.mem.s1_data <= T_2594 @[ptw.scala 138:18] - io.mem.s1_kill <= s1_kill @[ptw.scala 139:18] - io.mem.invalidate_lr <= UInt<1>("h00") @[ptw.scala 140:24] - node T_2596 = shr(pte_addr, 30) @[ptw.scala 142:62] - node T_2597 = bits(r_req.addr, 17, 0) @[ptw.scala 142:117] - node resp_ppns_0 = cat(T_2596, T_2597) @[Cat.scala 20:58] - node T_2598 = shr(pte_addr, 21) @[ptw.scala 142:62] - node T_2599 = bits(r_req.addr, 8, 0) @[ptw.scala 142:117] - node resp_ppns_1 = cat(T_2598, T_2599) @[Cat.scala 20:58] - node resp_ppns_2 = shr(pte_addr, 12) @[ptw.scala 142:165] - node T_2600 = eq(state, UInt<3>("h07")) @[ptw.scala 144:41] - node T_2602 = eq(r_req_dest, UInt<1>("h00")) @[ptw.scala 144:67] - node T_2603 = and(T_2600, T_2602) @[ptw.scala 144:52] - io.requestor[0].resp.valid <= T_2603 @[ptw.scala 144:32] - io.requestor[0].resp.bits.pte <- r_pte @[ptw.scala 145:35] - node T_2605 = and(count, UInt<1>("h01")) @[Package.scala 18:26] - node T_2607 = geq(count, UInt<2>("h02")) @[Package.scala 19:17] - node T_2609 = and(T_2605, UInt<1>("h00")) @[Package.scala 18:26] - node T_2611 = geq(T_2605, UInt<1>("h01")) @[Package.scala 19:17] - node T_2612 = mux(T_2611, resp_ppns_1, resp_ppns_0) @[Package.scala 19:12] - node T_2613 = mux(T_2607, resp_ppns_2, T_2612) @[Package.scala 19:12] - io.requestor[0].resp.bits.pte.ppn <= T_2613 @[ptw.scala 146:39] - io.requestor[0].ptbr <- io.dpath.ptbr @[ptw.scala 147:26] - io.requestor[0].invalidate <= io.dpath.invalidate @[ptw.scala 148:32] - io.requestor[0].status <- io.dpath.status @[ptw.scala 149:28] - node T_2614 = eq(state, UInt<3>("h07")) @[ptw.scala 144:41] - node T_2616 = eq(r_req_dest, UInt<1>("h01")) @[ptw.scala 144:67] - node T_2617 = and(T_2614, T_2616) @[ptw.scala 144:52] - io.requestor[1].resp.valid <= T_2617 @[ptw.scala 144:32] - io.requestor[1].resp.bits.pte <- r_pte @[ptw.scala 145:35] - node T_2619 = and(count, UInt<1>("h01")) @[Package.scala 18:26] - node T_2621 = geq(count, UInt<2>("h02")) @[Package.scala 19:17] - node T_2623 = and(T_2619, UInt<1>("h00")) @[Package.scala 18:26] - node T_2625 = geq(T_2619, UInt<1>("h01")) @[Package.scala 19:17] - node T_2626 = mux(T_2625, resp_ppns_1, resp_ppns_0) @[Package.scala 19:12] - node T_2627 = mux(T_2621, resp_ppns_2, T_2626) @[Package.scala 19:12] - io.requestor[1].resp.bits.pte.ppn <= T_2627 @[ptw.scala 146:39] - io.requestor[1].ptbr <- io.dpath.ptbr @[ptw.scala 147:26] - io.requestor[1].invalidate <= io.dpath.invalidate @[ptw.scala 148:32] - io.requestor[1].status <- io.dpath.status @[ptw.scala 149:28] - node T_2628 = eq(UInt<3>("h00"), state) @[Conditional.scala 24:42] - when T_2628 : @[Conditional.scala 24:73] - when arb.io.out.valid : @[ptw.scala 155:31] - state <= UInt<3>("h01") @[ptw.scala 156:15] - skip @[ptw.scala 155:31] - count <= UInt<1>("h00") @[ptw.scala 158:13] - skip @[Conditional.scala 24:73] - node T_2630 = eq(UInt<3>("h01"), state) @[Conditional.scala 24:42] - when T_2630 : @[Conditional.scala 24:73] - when pte_cache_hit : @[ptw.scala 161:28] - s1_kill <= UInt<1>("h01") @[ptw.scala 162:17] - state <= UInt<3>("h01") @[ptw.scala 163:15] - node T_2633 = add(count, UInt<1>("h01")) @[ptw.scala 164:24] - node T_2634 = tail(T_2633, 1) @[ptw.scala 164:24] - count <= T_2634 @[ptw.scala 164:15] - r_pte.ppn <= pte_cache_data @[ptw.scala 165:19] - skip @[ptw.scala 161:28] - node T_2636 = eq(pte_cache_hit, UInt<1>("h00")) @[ptw.scala 161:28] - node T_2637 = and(T_2636, io.mem.req.ready) @[ptw.scala 166:37] - when T_2637 : @[ptw.scala 166:37] - state <= UInt<3>("h02") @[ptw.scala 167:15] - skip @[ptw.scala 166:37] - skip @[Conditional.scala 24:73] - node T_2638 = eq(UInt<3>("h02"), state) @[Conditional.scala 24:42] - when T_2638 : @[Conditional.scala 24:73] - state <= UInt<3>("h03") @[ptw.scala 171:13] - when io.mem.xcpt.pf.ld : @[ptw.scala 172:32] - r_pte.v <= UInt<1>("h00") @[ptw.scala 173:17] - state <= UInt<3>("h07") @[ptw.scala 174:15] - skip @[ptw.scala 172:32] - skip @[Conditional.scala 24:73] - node T_2640 = eq(UInt<3>("h03"), state) @[Conditional.scala 24:42] - when T_2640 : @[Conditional.scala 24:73] - when io.mem.s2_nack : @[ptw.scala 178:29] - state <= UInt<3>("h01") @[ptw.scala 179:15] - skip @[ptw.scala 178:29] - when io.mem.resp.valid : @[ptw.scala 181:32] - state <= UInt<3>("h07") @[ptw.scala 182:15] - node T_2641 = and(pte.x, r_req.mxr) @[ptw.scala 62:63] - node T_2642 = or(pte.r, T_2641) @[ptw.scala 62:57] - node T_2643 = mux(r_req.store, pte.w, T_2642) @[ptw.scala 62:40] - node T_2644 = mux(r_req.fetch, pte.x, T_2643) @[ptw.scala 62:22] - node T_2646 = eq(r_req.pum, UInt<1>("h00")) @[ptw.scala 63:26] - node T_2647 = bits(r_req.prv, 0, 0) @[ptw.scala 63:43] - node T_2648 = mux(pte.u, T_2646, T_2647) @[ptw.scala 63:22] - node T_2650 = eq(pte.w, UInt<1>("h00")) @[ptw.scala 53:47] - node T_2651 = and(pte.x, T_2650) @[ptw.scala 53:44] - node T_2652 = or(pte.r, T_2651) @[ptw.scala 53:38] - node T_2653 = and(pte.v, T_2652) @[ptw.scala 53:32] - node T_2654 = and(T_2653, T_2648) @[ptw.scala 64:12] - node T_2655 = and(T_2654, T_2644) @[ptw.scala 64:23] - node T_2657 = eq(pte.a, UInt<1>("h00")) @[ptw.scala 183:40] - node T_2659 = eq(pte.d, UInt<1>("h00")) @[ptw.scala 183:66] - node T_2660 = and(r_req.store, T_2659) @[ptw.scala 183:63] - node T_2661 = or(T_2657, T_2660) @[ptw.scala 183:47] - node T_2662 = and(T_2655, T_2661) @[ptw.scala 183:36] - when T_2662 : @[ptw.scala 183:76] - state <= UInt<3>("h04") @[ptw.scala 184:17] - skip @[ptw.scala 183:76] - node T_2664 = eq(T_2662, UInt<1>("h00")) @[ptw.scala 183:76] - when T_2664 : @[ptw.scala 185:21] - r_pte <- pte @[ptw.scala 186:17] - skip @[ptw.scala 185:21] - node T_2666 = eq(pte.r, UInt<1>("h00")) @[ptw.scala 52:36] - node T_2667 = and(pte.v, T_2666) @[ptw.scala 52:33] - node T_2669 = eq(pte.w, UInt<1>("h00")) @[ptw.scala 52:42] - node T_2670 = and(T_2667, T_2669) @[ptw.scala 52:39] - node T_2672 = eq(pte.x, UInt<1>("h00")) @[ptw.scala 52:48] - node T_2673 = and(T_2670, T_2672) @[ptw.scala 52:45] - node T_2675 = lt(count, UInt<2>("h02")) @[ptw.scala 188:36] - node T_2676 = and(T_2673, T_2675) @[ptw.scala 188:27] - when T_2676 : @[ptw.scala 188:50] - state <= UInt<3>("h01") @[ptw.scala 189:17] - node T_2678 = add(count, UInt<1>("h01")) @[ptw.scala 190:26] - node T_2679 = tail(T_2678, 1) @[ptw.scala 190:26] - count <= T_2679 @[ptw.scala 190:17] - skip @[ptw.scala 188:50] - skip @[ptw.scala 181:32] - skip @[Conditional.scala 24:73] - node T_2680 = eq(UInt<3>("h04"), state) @[Conditional.scala 24:42] - when T_2680 : @[Conditional.scala 24:73] - when io.mem.req.ready : @[ptw.scala 195:31] - state <= UInt<3>("h05") @[ptw.scala 196:15] - skip @[ptw.scala 195:31] - skip @[Conditional.scala 24:73] - node T_2681 = eq(UInt<3>("h05"), state) @[Conditional.scala 24:42] - when T_2681 : @[Conditional.scala 24:73] - state <= UInt<3>("h06") @[ptw.scala 200:13] - when io.mem.xcpt.pf.st : @[ptw.scala 201:32] - r_pte.v <= UInt<1>("h00") @[ptw.scala 202:17] - state <= UInt<3>("h07") @[ptw.scala 203:15] - skip @[ptw.scala 201:32] - skip @[Conditional.scala 24:73] - node T_2683 = eq(UInt<3>("h06"), state) @[Conditional.scala 24:42] - when T_2683 : @[Conditional.scala 24:73] - when io.mem.s2_nack : @[ptw.scala 207:29] - state <= UInt<3>("h04") @[ptw.scala 208:15] - skip @[ptw.scala 207:29] - when io.mem.resp.valid : @[ptw.scala 210:32] - state <= UInt<3>("h01") @[ptw.scala 211:15] - skip @[ptw.scala 210:32] - skip @[Conditional.scala 24:73] - node T_2684 = eq(UInt<3>("h07"), state) @[Conditional.scala 24:42] - when T_2684 : @[Conditional.scala 24:73] - state <= UInt<3>("h00") @[ptw.scala 215:13] - skip @[Conditional.scala 24:73] - - module HellaCacheArbiter : + pte_wdata.a <= UInt<1>("h1") + pte_wdata.d <= r_req.store + node T_2578 = eq(state, UInt<3>("h1")) + node T_2579 = eq(state, UInt<3>("h4")) + node T_2580 = or(T_2578, T_2579) + io.mem.req.valid <= T_2580 + io.mem.req.bits.phys <= UInt<1>("h1") + node T_2582 = eq(state, UInt<3>("h4")) + node T_2583 = mux(T_2582, UInt<5>("ha"), UInt<5>("h0")) + io.mem.req.bits.cmd <= T_2583 + io.mem.req.bits.typ <= UInt<2>("h3") + io.mem.req.bits.addr <= pte_addr + node T_2585 = cat(pte_wdata.r, pte_wdata.v) + node T_2586 = cat(pte_wdata.u, pte_wdata.x) + node T_2587 = cat(T_2586, pte_wdata.w) + node T_2588 = cat(T_2587, T_2585) + node T_2589 = cat(pte_wdata.d, pte_wdata.a) + node T_2590 = cat(T_2589, pte_wdata.g) + node T_2591 = cat(pte_wdata.reserved_for_hardware, pte_wdata.ppn) + node T_2592 = cat(T_2591, pte_wdata.reserved_for_software) + node T_2593 = cat(T_2592, T_2590) + node T_2594 = cat(T_2593, T_2588) + io.mem.s1_data <= T_2594 + io.mem.s1_kill <= s1_kill + io.mem.invalidate_lr <= UInt<1>("h0") + node T_2596 = shr(pte_addr, 30) + node T_2597 = bits(r_req.addr, 17, 0) + node resp_ppns_0 = cat(T_2596, T_2597) + node T_2598 = shr(pte_addr, 21) + node T_2599 = bits(r_req.addr, 8, 0) + node resp_ppns_1 = cat(T_2598, T_2599) + node resp_ppns_2 = shr(pte_addr, 12) + node T_2600 = eq(state, UInt<3>("h7")) + node T_2602 = eq(r_req_dest, UInt<1>("h0")) + node T_2603 = and(T_2600, T_2602) + io.requestor[0].resp.valid <= T_2603 + io.requestor[0].resp.bits.pte <- r_pte + node T_2605 = and(count, UInt<1>("h1")) + node T_2607 = geq(count, UInt<2>("h2")) + node T_2609 = and(T_2605, UInt<1>("h0")) + node T_2611 = geq(T_2605, UInt<1>("h1")) + node T_2612 = mux(T_2611, resp_ppns_1, resp_ppns_0) + node T_2613 = mux(T_2607, resp_ppns_2, T_2612) + io.requestor[0].resp.bits.pte.ppn <= T_2613 + io.requestor[0].ptbr <- io.dpath.ptbr + io.requestor[0].invalidate <= io.dpath.invalidate + io.requestor[0].status <- io.dpath.status + node T_2614 = eq(state, UInt<3>("h7")) + node T_2616 = eq(r_req_dest, UInt<1>("h1")) + node T_2617 = and(T_2614, T_2616) + io.requestor[1].resp.valid <= T_2617 + io.requestor[1].resp.bits.pte <- r_pte + node T_2619 = and(count, UInt<1>("h1")) + node T_2621 = geq(count, UInt<2>("h2")) + node T_2623 = and(T_2619, UInt<1>("h0")) + node T_2625 = geq(T_2619, UInt<1>("h1")) + node T_2626 = mux(T_2625, resp_ppns_1, resp_ppns_0) + node T_2627 = mux(T_2621, resp_ppns_2, T_2626) + io.requestor[1].resp.bits.pte.ppn <= T_2627 + io.requestor[1].ptbr <- io.dpath.ptbr + io.requestor[1].invalidate <= io.dpath.invalidate + io.requestor[1].status <- io.dpath.status + node T_2628 = eq(UInt<3>("h0"), state) + when T_2628 : + when arb.io.out.valid : + state <= UInt<3>("h1") + count <= UInt<1>("h0") + node T_2630 = eq(UInt<3>("h1"), state) + when T_2630 : + when pte_cache_hit : + s1_kill <= UInt<1>("h1") + state <= UInt<3>("h1") + node T_2633 = add(count, UInt<1>("h1")) + node T_2634 = tail(T_2633, 1) + count <= T_2634 + r_pte.ppn <= pte_cache_data + node T_2636 = eq(pte_cache_hit, UInt<1>("h0")) + node T_2637 = and(T_2636, io.mem.req.ready) + when T_2637 : + state <= UInt<3>("h2") + node T_2638 = eq(UInt<3>("h2"), state) + when T_2638 : + state <= UInt<3>("h3") + when io.mem.xcpt.pf.ld : + r_pte.v <= UInt<1>("h0") + state <= UInt<3>("h7") + node T_2640 = eq(UInt<3>("h3"), state) + when T_2640 : + when io.mem.s2_nack : + state <= UInt<3>("h1") + when io.mem.resp.valid : + state <= UInt<3>("h7") + node T_2641 = and(pte.x, r_req.mxr) + node T_2642 = or(pte.r, T_2641) + node T_2643 = mux(r_req.store, pte.w, T_2642) + node T_2644 = mux(r_req.fetch, pte.x, T_2643) + node T_2646 = eq(r_req.pum, UInt<1>("h0")) + node T_2647 = bits(r_req.prv, 0, 0) + node T_2648 = mux(pte.u, T_2646, T_2647) + node T_2650 = eq(pte.w, UInt<1>("h0")) + node T_2651 = and(pte.x, T_2650) + node T_2652 = or(pte.r, T_2651) + node T_2653 = and(pte.v, T_2652) + node T_2654 = and(T_2653, T_2648) + node T_2655 = and(T_2654, T_2644) + node T_2657 = eq(pte.a, UInt<1>("h0")) + node T_2659 = eq(pte.d, UInt<1>("h0")) + node T_2660 = and(r_req.store, T_2659) + node T_2661 = or(T_2657, T_2660) + node T_2662 = and(T_2655, T_2661) + when T_2662 : + state <= UInt<3>("h4") + node T_2664 = eq(T_2662, UInt<1>("h0")) + when T_2664 : + r_pte <- pte + node T_2666 = eq(pte.r, UInt<1>("h0")) + node T_2667 = and(pte.v, T_2666) + node T_2669 = eq(pte.w, UInt<1>("h0")) + node T_2670 = and(T_2667, T_2669) + node T_2672 = eq(pte.x, UInt<1>("h0")) + node T_2673 = and(T_2670, T_2672) + node T_2675 = lt(count, UInt<2>("h2")) + node T_2676 = and(T_2673, T_2675) + when T_2676 : + state <= UInt<3>("h1") + node T_2678 = add(count, UInt<1>("h1")) + node T_2679 = tail(T_2678, 1) + count <= T_2679 + node T_2680 = eq(UInt<3>("h4"), state) + when T_2680 : + when io.mem.req.ready : + state <= UInt<3>("h5") + node T_2681 = eq(UInt<3>("h5"), state) + when T_2681 : + state <= UInt<3>("h6") + when io.mem.xcpt.pf.st : + r_pte.v <= UInt<1>("h0") + state <= UInt<3>("h7") + node T_2683 = eq(UInt<3>("h6"), state) + when T_2683 : + when io.mem.s2_nack : + state <= UInt<3>("h4") + when io.mem.resp.valid : + state <= UInt<3>("h1") + node T_2684 = eq(UInt<3>("h7"), state) + when T_2684 : + state <= UInt<3>("h0") + + module HellaCacheArbiter : input clk : Clock input reset : UInt<1> - output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} - + output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} + io is invalid - reg T_6368 : UInt, clk - reg T_6369 : UInt, clk + reg T_6368 : UInt, clk with : + reset => (UInt<1>("h0"), T_6368) + reg T_6369 : UInt, clk with : + reset => (UInt<1>("h0"), T_6369) T_6369 <= T_6368 - node T_6370 = or(io.requestor[0].invalidate_lr, io.requestor[1].invalidate_lr) @[arbiter.scala 22:71] - io.mem.invalidate_lr <= T_6370 @[arbiter.scala 22:26] - node T_6371 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) @[arbiter.scala 23:63] - io.mem.req.valid <= T_6371 @[arbiter.scala 23:22] - io.requestor[0].req.ready <= io.mem.req.ready @[arbiter.scala 24:31] - node T_6373 = eq(io.requestor[0].req.valid, UInt<1>("h00")) @[arbiter.scala 26:67] - node T_6374 = and(io.requestor[0].req.ready, T_6373) @[arbiter.scala 26:64] - io.requestor[1].req.ready <= T_6374 @[arbiter.scala 26:33] - io.mem.req.bits.cmd <= io.requestor[1].req.bits.cmd @[arbiter.scala 31:29] - io.mem.req.bits.typ <= io.requestor[1].req.bits.typ @[arbiter.scala 32:29] - io.mem.req.bits.addr <= io.requestor[1].req.bits.addr @[arbiter.scala 33:30] - io.mem.req.bits.phys <= io.requestor[1].req.bits.phys @[arbiter.scala 34:30] - node T_6376 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01")) @[Cat.scala 20:58] - io.mem.req.bits.tag <= T_6376 @[arbiter.scala 35:29] - T_6368 <= UInt<1>("h01") @[arbiter.scala 36:15] - io.mem.s1_kill <= io.requestor[1].s1_kill @[arbiter.scala 39:24] - io.mem.s1_data <= io.requestor[1].s1_data @[arbiter.scala 40:24] - when io.requestor[0].req.valid : @[arbiter.scala 47:26] - io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd @[arbiter.scala 31:29] - io.mem.req.bits.typ <= io.requestor[0].req.bits.typ @[arbiter.scala 32:29] - io.mem.req.bits.addr <= io.requestor[0].req.bits.addr @[arbiter.scala 33:30] - io.mem.req.bits.phys <= io.requestor[0].req.bits.phys @[arbiter.scala 34:30] - node T_6379 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00")) @[Cat.scala 20:58] - io.mem.req.bits.tag <= T_6379 @[arbiter.scala 35:29] - T_6368 <= UInt<1>("h00") @[arbiter.scala 36:15] - skip @[arbiter.scala 47:26] - node T_6382 = eq(T_6368, UInt<1>("h00")) @[arbiter.scala 48:21] - when T_6382 : @[arbiter.scala 48:34] - io.mem.s1_kill <= io.requestor[0].s1_kill @[arbiter.scala 39:24] - io.mem.s1_data <= io.requestor[0].s1_data @[arbiter.scala 40:24] - skip @[arbiter.scala 48:34] - node T_6383 = bits(io.mem.resp.bits.tag, 0, 0) @[arbiter.scala 54:41] - node T_6385 = eq(T_6383, UInt<1>("h00")) @[arbiter.scala 54:57] - node T_6386 = and(io.mem.resp.valid, T_6385) @[arbiter.scala 55:39] - io.requestor[0].resp.valid <= T_6386 @[arbiter.scala 55:18] - io.requestor[0].xcpt <- io.mem.xcpt @[arbiter.scala 56:28] - io.requestor[0].ordered <= io.mem.ordered @[arbiter.scala 57:31] - node T_6388 = eq(T_6369, UInt<1>("h00")) @[arbiter.scala 58:58] - node T_6389 = and(io.mem.s2_nack, T_6388) @[arbiter.scala 58:49] - io.requestor[0].s2_nack <= T_6389 @[arbiter.scala 58:31] - io.requestor[0].resp.bits <- io.mem.resp.bits @[arbiter.scala 59:17] - node T_6390 = shr(io.mem.resp.bits.tag, 1) @[arbiter.scala 60:45] - io.requestor[0].resp.bits.tag <= T_6390 @[arbiter.scala 60:21] - io.requestor[0].replay_next <= io.mem.replay_next @[arbiter.scala 62:35] - node T_6391 = bits(io.mem.resp.bits.tag, 0, 0) @[arbiter.scala 54:41] - node T_6393 = eq(T_6391, UInt<1>("h01")) @[arbiter.scala 54:57] - node T_6394 = and(io.mem.resp.valid, T_6393) @[arbiter.scala 55:39] - io.requestor[1].resp.valid <= T_6394 @[arbiter.scala 55:18] - io.requestor[1].xcpt <- io.mem.xcpt @[arbiter.scala 56:28] - io.requestor[1].ordered <= io.mem.ordered @[arbiter.scala 57:31] - node T_6396 = eq(T_6369, UInt<1>("h01")) @[arbiter.scala 58:58] - node T_6397 = and(io.mem.s2_nack, T_6396) @[arbiter.scala 58:49] - io.requestor[1].s2_nack <= T_6397 @[arbiter.scala 58:31] - io.requestor[1].resp.bits <- io.mem.resp.bits @[arbiter.scala 59:17] - node T_6398 = shr(io.mem.resp.bits.tag, 1) @[arbiter.scala 60:45] - io.requestor[1].resp.bits.tag <= T_6398 @[arbiter.scala 60:21] - io.requestor[1].replay_next <= io.mem.replay_next @[arbiter.scala 62:35] - - module RocketTile : + node T_6370 = or(io.requestor[0].invalidate_lr, io.requestor[1].invalidate_lr) + io.mem.invalidate_lr <= T_6370 + node T_6371 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) + io.mem.req.valid <= T_6371 + io.requestor[0].req.ready <= io.mem.req.ready + node T_6373 = eq(io.requestor[0].req.valid, UInt<1>("h0")) + node T_6374 = and(io.requestor[0].req.ready, T_6373) + io.requestor[1].req.ready <= T_6374 + io.mem.req.bits.cmd <= io.requestor[1].req.bits.cmd + io.mem.req.bits.typ <= io.requestor[1].req.bits.typ + io.mem.req.bits.addr <= io.requestor[1].req.bits.addr + io.mem.req.bits.phys <= io.requestor[1].req.bits.phys + node T_6376 = cat(io.requestor[1].req.bits.tag, UInt<1>("h1")) + io.mem.req.bits.tag <= T_6376 + T_6368 <= UInt<1>("h1") + io.mem.s1_kill <= io.requestor[1].s1_kill + io.mem.s1_data <= io.requestor[1].s1_data + when io.requestor[0].req.valid : + io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd + io.mem.req.bits.typ <= io.requestor[0].req.bits.typ + io.mem.req.bits.addr <= io.requestor[0].req.bits.addr + io.mem.req.bits.phys <= io.requestor[0].req.bits.phys + node T_6379 = cat(io.requestor[0].req.bits.tag, UInt<1>("h0")) + io.mem.req.bits.tag <= T_6379 + T_6368 <= UInt<1>("h0") + node T_6382 = eq(T_6368, UInt<1>("h0")) + when T_6382 : + io.mem.s1_kill <= io.requestor[0].s1_kill + io.mem.s1_data <= io.requestor[0].s1_data + node T_6383 = bits(io.mem.resp.bits.tag, 0, 0) + node T_6385 = eq(T_6383, UInt<1>("h0")) + node T_6386 = and(io.mem.resp.valid, T_6385) + io.requestor[0].resp.valid <= T_6386 + io.requestor[0].xcpt <- io.mem.xcpt + io.requestor[0].ordered <= io.mem.ordered + node T_6388 = eq(T_6369, UInt<1>("h0")) + node T_6389 = and(io.mem.s2_nack, T_6388) + io.requestor[0].s2_nack <= T_6389 + io.requestor[0].resp.bits <- io.mem.resp.bits + node T_6390 = shr(io.mem.resp.bits.tag, 1) + io.requestor[0].resp.bits.tag <= T_6390 + io.requestor[0].replay_next <= io.mem.replay_next + node T_6391 = bits(io.mem.resp.bits.tag, 0, 0) + node T_6393 = eq(T_6391, UInt<1>("h1")) + node T_6394 = and(io.mem.resp.valid, T_6393) + io.requestor[1].resp.valid <= T_6394 + io.requestor[1].xcpt <- io.mem.xcpt + io.requestor[1].ordered <= io.mem.ordered + node T_6396 = eq(T_6369, UInt<1>("h1")) + node T_6397 = and(io.mem.s2_nack, T_6396) + io.requestor[1].s2_nack <= T_6397 + io.requestor[1].resp.bits <- io.mem.resp.bits + node T_6398 = shr(io.mem.resp.bits.tag, 1) + io.requestor[1].resp.bits.tag <= T_6398 + io.requestor[1].replay_next <= io.mem.replay_next + + module RocketTile : input clk : Clock input reset : UInt<1> - output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}}[1], uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], flip prci : {reset : UInt<1>, id : UInt<1>, interrupts : {meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}} - + output io : { cached : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}}[1], uncached : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], flip prci : { reset : UInt<1>, id : UInt<1>, interrupts : { meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}} + io is invalid - inst core of Rocket @[tile.scala 48:20] + inst core of Rocket core.io is invalid core.clk <= clk core.reset <= reset - inst icache of Frontend @[tile.scala 49:22] + inst icache of Frontend icache.io is invalid icache.clk <= clk icache.reset <= reset - inst DCache_1 of DCache @[nbdcache.scala 1240:32] + inst DCache_1 of DCache DCache_1.io is invalid DCache_1.clk <= clk DCache_1.reset <= reset - core.io.prci <- io.prci @[tile.scala 57:16] - icache.io.cpu <- core.io.imem @[tile.scala 58:17] - inst fpuOpt of FPU @[tile.scala 60:43] + core.io.prci <- io.prci + icache.io.cpu <- core.io.imem + inst fpuOpt of FPU fpuOpt.io is invalid fpuOpt.clk <= clk fpuOpt.reset <= reset - core.io.fpu <- fpuOpt.io @[tile.scala 61:37] - inst uncachedArb of ClientUncachedTileLinkIOArbiter @[tile.scala 108:27] + core.io.fpu <- fpuOpt.io + inst uncachedArb of ClientUncachedTileLinkIOArbiter uncachedArb.io is invalid uncachedArb.clk <= clk uncachedArb.reset <= reset - uncachedArb.io.in[0] <- icache.io.mem @[tile.scala 109:21] - io.uncached[0] <- uncachedArb.io.out @[tile.scala 113:15] - io.cached[0] <- DCache_1.io.mem @[tile.scala 114:13] - inst PTW_1 of PTW @[tile.scala 120:21] + uncachedArb.io.in[0] <- icache.io.mem + io.uncached[0] <- uncachedArb.io.out + io.cached[0] <- DCache_1.io.mem + inst PTW_1 of PTW PTW_1.io is invalid PTW_1.clk <= clk PTW_1.reset <= reset - PTW_1.io.requestor[0] <- icache.io.ptw @[tile.scala 121:22] - PTW_1.io.requestor[1] <- DCache_1.io.ptw @[tile.scala 121:22] - core.io.ptw <- PTW_1.io.dpath @[tile.scala 123:17] - inst dcArb of HellaCacheArbiter @[tile.scala 133:21] + PTW_1.io.requestor[0] <- icache.io.ptw + PTW_1.io.requestor[1] <- DCache_1.io.ptw + core.io.ptw <- PTW_1.io.dpath + inst dcArb of HellaCacheArbiter dcArb.io is invalid dcArb.clk <= clk dcArb.reset <= reset - dcArb.io.requestor[0] <- PTW_1.io.mem @[tile.scala 134:22] - dcArb.io.requestor[1] <- core.io.dmem @[tile.scala 134:22] - DCache_1.io.cpu <- dcArb.io.mem @[tile.scala 135:14] - fpuOpt.io.cp_req.valid <= UInt<1>("h00") @[tile.scala 139:27] - fpuOpt.io.cp_resp.ready <= UInt<1>("h00") @[tile.scala 140:28] - - module Queue : + dcArb.io.requestor[0] <- PTW_1.io.mem + dcArb.io.requestor[1] <- core.io.dmem + DCache_1.io.cpu <- dcArb.io.mem + fpuOpt.io.cp_req.valid <= UInt<1>("h0") + fpuOpt.io.cp_resp.ready <= UInt<1>("h0") + + module Queue : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, count : UInt<1>} + io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_1022 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_1022) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_1023 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1022 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_1022) + node full = and(ptr_match, maybe_full) + node T_1023 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_1023 - node T_1024 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_1024 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_1024 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_1025 = ram[UInt<1>("h00")], clk - T_1025 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_1139 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_1139 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_1141 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_1141 @[Decoupled.scala 184:16] - node T_1143 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_1143 @[Decoupled.scala 185:16] - infer mport T_1144 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_1144 @[Decoupled.scala 186:15] - node T_1256 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_1256, 1) @[Decoupled.scala 201:32] - node T_1257 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_1258 = cat(T_1257, ptr_diff) @[Cat.scala 20:58] - io.count <= T_1258 @[Decoupled.scala 203:14] - - module Queue_1 : + when do_enq : + infer mport T_1025 = ram[UInt<1>("h0")], clk + T_1025 <- io.enq.bits + when do_deq : + skip + node T_1139 = neq(do_enq, do_deq) + when T_1139 : + maybe_full <= do_enq + node T_1141 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_1141 + node T_1143 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_1143 + infer mport T_1144 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_1144 + node T_1256 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_1256, 1) + node T_1257 = and(maybe_full, ptr_match) + node T_1258 = cat(T_1257, ptr_diff) + io.count <= T_1258 + + module Queue_1 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<1>} + io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_977 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_977) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_978 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_977 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_977) + node full = and(ptr_match, maybe_full) + node T_978 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_978 - node T_979 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_979 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_979 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_980 = ram[UInt<1>("h00")], clk - T_980 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_1089 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_1089 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_1091 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_1091 @[Decoupled.scala 184:16] - node T_1093 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_1093 @[Decoupled.scala 185:16] - infer mport T_1094 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_1094 @[Decoupled.scala 186:15] - node T_1201 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_1201, 1) @[Decoupled.scala 201:32] - node T_1202 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_1203 = cat(T_1202, ptr_diff) @[Cat.scala 20:58] - io.count <= T_1203 @[Decoupled.scala 203:14] - - module Queue_2 : + when do_enq : + infer mport T_980 = ram[UInt<1>("h0")], clk + T_980 <- io.enq.bits + when do_deq : + skip + node T_1089 = neq(do_enq, do_deq) + when T_1089 : + maybe_full <= do_enq + node T_1091 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_1091 + node T_1093 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_1093 + infer mport T_1094 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_1094 + node T_1201 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_1201, 1) + node T_1202 = and(maybe_full, ptr_match) + node T_1203 = cat(T_1202, ptr_diff) + io.count <= T_1203 + + module Queue_2 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, count : UInt<2>} + io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}[2] @[Decoupled.scala 162:16] - reg T_1010 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1012 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1010, T_1012) @[Decoupled.scala 167:33] - node T_1015 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_1015) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_1016 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}} [2] + reg T_1010 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_1012 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_1010, T_1012) + node T_1015 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_1015) + node full = and(ptr_match, maybe_full) + node T_1016 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_1016 - node T_1017 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_1017 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_1017 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_1018 = ram[T_1010], clk - T_1018 <- io.enq.bits @[Decoupled.scala 174:24] - node T_1130 = eq(T_1010, UInt<1>("h01")) @[Counter.scala 20:24] - node T_1132 = add(T_1010, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1133 = tail(T_1132, 1) @[Counter.scala 21:22] - T_1010 <= T_1133 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_1135 = eq(T_1012, UInt<1>("h01")) @[Counter.scala 20:24] - node T_1137 = add(T_1012, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1138 = tail(T_1137, 1) @[Counter.scala 21:22] - T_1012 <= T_1138 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_1139 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_1139 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_1141 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_1141 @[Decoupled.scala 184:16] - node T_1143 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_1143 @[Decoupled.scala 185:16] + T_1018 <- io.enq.bits + node T_1130 = eq(T_1010, UInt<1>("h1")) + node T_1132 = add(T_1010, UInt<1>("h1")) + node T_1133 = tail(T_1132, 1) + T_1010 <= T_1133 + when do_deq : + node T_1135 = eq(T_1012, UInt<1>("h1")) + node T_1137 = add(T_1012, UInt<1>("h1")) + node T_1138 = tail(T_1137, 1) + T_1012 <= T_1138 + node T_1139 = neq(do_enq, do_deq) + when T_1139 : + maybe_full <= do_enq + node T_1141 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_1141 + node T_1143 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_1143 infer mport T_1144 = ram[T_1012], clk - io.deq.bits <- T_1144 @[Decoupled.scala 186:15] - node T_1255 = sub(T_1010, T_1012) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_1255, 1) @[Decoupled.scala 201:32] - node T_1256 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_1257 = cat(T_1256, ptr_diff) @[Cat.scala 20:58] - io.count <= T_1257 @[Decoupled.scala 203:14] - - module Queue_3 : + io.deq.bits <- T_1144 + node T_1255 = sub(T_1010, T_1012) + node ptr_diff = tail(T_1255, 1) + node T_1256 = and(maybe_full, ptr_match) + node T_1257 = cat(T_1256, ptr_diff) + io.count <= T_1257 + + module Queue_3 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, count : UInt<2>} + io is invalid - cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}[2] @[Decoupled.scala 162:16] - reg T_1010 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_1012 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_1010, T_1012) @[Decoupled.scala 167:33] - node T_1015 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_1015) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_1016 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}} [2] + reg T_1010 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_1012 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_1010, T_1012) + node T_1015 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_1015) + node full = and(ptr_match, maybe_full) + node T_1016 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_1016 - node T_1017 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_1017 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_1017 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_1018 = ram[T_1010], clk - T_1018 <- io.enq.bits @[Decoupled.scala 174:24] - node T_1130 = eq(T_1010, UInt<1>("h01")) @[Counter.scala 20:24] - node T_1132 = add(T_1010, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1133 = tail(T_1132, 1) @[Counter.scala 21:22] - T_1010 <= T_1133 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_1135 = eq(T_1012, UInt<1>("h01")) @[Counter.scala 20:24] - node T_1137 = add(T_1012, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1138 = tail(T_1137, 1) @[Counter.scala 21:22] - T_1012 <= T_1138 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_1139 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_1139 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_1141 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_1141 @[Decoupled.scala 184:16] - node T_1143 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_1143 @[Decoupled.scala 185:16] + T_1018 <- io.enq.bits + node T_1130 = eq(T_1010, UInt<1>("h1")) + node T_1132 = add(T_1010, UInt<1>("h1")) + node T_1133 = tail(T_1132, 1) + T_1010 <= T_1133 + when do_deq : + node T_1135 = eq(T_1012, UInt<1>("h1")) + node T_1137 = add(T_1012, UInt<1>("h1")) + node T_1138 = tail(T_1137, 1) + T_1012 <= T_1138 + node T_1139 = neq(do_enq, do_deq) + when T_1139 : + maybe_full <= do_enq + node T_1141 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_1141 + node T_1143 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_1143 infer mport T_1144 = ram[T_1012], clk - io.deq.bits <- T_1144 @[Decoupled.scala 186:15] - node T_1255 = sub(T_1010, T_1012) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_1255, 1) @[Decoupled.scala 201:32] - node T_1256 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_1257 = cat(T_1256, ptr_diff) @[Cat.scala 20:58] - io.count <= T_1257 @[Decoupled.scala 203:14] - - module TileLinkEnqueuer : + io.deq.bits <- T_1144 + node T_1255 = sub(T_1010, T_1012) + node ptr_diff = tail(T_1255, 1) + node T_1256 = and(maybe_full, ptr_match) + node T_1257 = cat(T_1256, ptr_diff) + io.count <= T_1257 + + module TileLinkEnqueuer : input clk : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip client : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - inst Queue_4 of Queue @[Decoupled.scala 228:19] + inst Queue_4 of Queue Queue_4.io is invalid Queue_4.clk <= clk Queue_4.reset <= reset - Queue_4.io.enq.valid <= io.client.acquire.valid @[Decoupled.scala 229:20] - Queue_4.io.enq.bits <- io.client.acquire.bits @[Decoupled.scala 230:19] - io.client.acquire.ready <= Queue_4.io.enq.ready @[Decoupled.scala 231:15] - io.manager.acquire <- Queue_4.io.deq @[Enqueuer.scala 17:22] - inst Queue_1_1 of Queue_1 @[Decoupled.scala 228:19] + Queue_4.io.enq.valid <= io.client.acquire.valid + Queue_4.io.enq.bits <- io.client.acquire.bits + io.client.acquire.ready <= Queue_4.io.enq.ready + io.manager.acquire <- Queue_4.io.deq + inst Queue_1_1 of Queue_1 Queue_1_1.io is invalid Queue_1_1.clk <= clk Queue_1_1.reset <= reset - Queue_1_1.io.enq.valid <= io.manager.probe.valid @[Decoupled.scala 229:20] - Queue_1_1.io.enq.bits <- io.manager.probe.bits @[Decoupled.scala 230:19] - io.manager.probe.ready <= Queue_1_1.io.enq.ready @[Decoupled.scala 231:15] - io.client.probe <- Queue_1_1.io.deq @[Enqueuer.scala 18:22] - inst Queue_2_1 of Queue_2 @[Decoupled.scala 228:19] + Queue_1_1.io.enq.valid <= io.manager.probe.valid + Queue_1_1.io.enq.bits <- io.manager.probe.bits + io.manager.probe.ready <= Queue_1_1.io.enq.ready + io.client.probe <- Queue_1_1.io.deq + inst Queue_2_1 of Queue_2 Queue_2_1.io is invalid Queue_2_1.clk <= clk Queue_2_1.reset <= reset - Queue_2_1.io.enq.valid <= io.client.release.valid @[Decoupled.scala 229:20] - Queue_2_1.io.enq.bits <- io.client.release.bits @[Decoupled.scala 230:19] - io.client.release.ready <= Queue_2_1.io.enq.ready @[Decoupled.scala 231:15] - io.manager.release <- Queue_2_1.io.deq @[Enqueuer.scala 19:22] - inst Queue_3_1 of Queue_3 @[Decoupled.scala 228:19] + Queue_2_1.io.enq.valid <= io.client.release.valid + Queue_2_1.io.enq.bits <- io.client.release.bits + io.client.release.ready <= Queue_2_1.io.enq.ready + io.manager.release <- Queue_2_1.io.deq + inst Queue_3_1 of Queue_3 Queue_3_1.io is invalid Queue_3_1.clk <= clk Queue_3_1.reset <= reset - Queue_3_1.io.enq.valid <= io.manager.grant.valid @[Decoupled.scala 229:20] - Queue_3_1.io.enq.bits <- io.manager.grant.bits @[Decoupled.scala 230:19] - io.manager.grant.ready <= Queue_3_1.io.enq.ready @[Decoupled.scala 231:15] - io.client.grant <- Queue_3_1.io.deq @[Enqueuer.scala 20:22] - io.manager.finish <- io.client.finish @[Enqueuer.scala 21:22] - - module ClientTileLinkNetworkPort : + Queue_3_1.io.enq.valid <= io.manager.grant.valid + Queue_3_1.io.enq.bits <- io.manager.grant.bits + io.manager.grant.ready <= Queue_3_1.io.enq.ready + io.client.grant <- Queue_3_1.io.deq + io.manager.finish <- io.client.finish + + module ClientTileLinkNetworkPort : input clk : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip client : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}}, network : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 259:19] - acq_with_header is invalid @[Network.scala 259:19] - acq_with_header.bits.payload <- io.client.acquire.bits @[Network.scala 260:22] - acq_with_header.bits.header.src <= UInt<1>("h00") @[Network.scala 261:25] - node T_3894 = shl(io.client.acquire.bits.addr_block, 6) @[Coreplex.scala 94:59] - node T_3896 = leq(UInt<32>("h080000000"), T_3894) @[addrmap.scala 26:46] - node T_3898 = lt(T_3894, UInt<32>("h090000000")) @[addrmap.scala 26:56] - node T_3899 = and(T_3896, T_3898) @[addrmap.scala 26:51] - node T_3902 = mux(T_3899, UInt<1>("h00"), UInt<1>("h01")) @[Coreplex.scala 95:10] - acq_with_header.bits.header.dst <= T_3902 @[Network.scala 262:25] - acq_with_header.valid <= io.client.acquire.valid @[Network.scala 263:15] - io.client.acquire.ready <= acq_with_header.ready @[Network.scala 264:14] - wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} @[Network.scala 259:19] - rel_with_header is invalid @[Network.scala 259:19] - rel_with_header.bits.payload <- io.client.release.bits @[Network.scala 260:22] - rel_with_header.bits.header.src <= UInt<1>("h00") @[Network.scala 261:25] - node T_4464 = shl(io.client.release.bits.addr_block, 6) @[Coreplex.scala 94:59] - node T_4466 = leq(UInt<32>("h080000000"), T_4464) @[addrmap.scala 26:46] - node T_4468 = lt(T_4464, UInt<32>("h090000000")) @[addrmap.scala 26:56] - node T_4469 = and(T_4466, T_4468) @[addrmap.scala 26:51] - node T_4472 = mux(T_4469, UInt<1>("h00"), UInt<1>("h01")) @[Coreplex.scala 95:10] - rel_with_header.bits.header.dst <= T_4472 @[Network.scala 262:25] - rel_with_header.valid <= io.client.release.valid @[Network.scala 263:15] - io.client.release.ready <= rel_with_header.ready @[Network.scala 264:14] - wire fin_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}} @[Network.scala 246:19] - fin_with_header is invalid @[Network.scala 246:19] - fin_with_header.bits.payload <- io.client.finish.bits @[Network.scala 247:22] - fin_with_header.bits.header.src <= UInt<1>("h00") @[Network.scala 248:25] - fin_with_header.bits.header.dst <= io.client.finish.bits.manager_id @[Network.scala 249:25] - fin_with_header.valid <= io.client.finish.valid @[Network.scala 250:15] - io.client.finish.ready <= fin_with_header.ready @[Network.scala 251:14] - wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} @[Network.scala 94:19] - prb_without_header is invalid @[Network.scala 94:19] - prb_without_header.valid <= io.network.probe.valid @[Network.scala 95:15] - prb_without_header.bits <- io.network.probe.bits.payload @[Network.scala 96:14] - io.network.probe.ready <= prb_without_header.ready @[Network.scala 97:14] - wire gnt_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}} @[Network.scala 94:19] - gnt_without_header is invalid @[Network.scala 94:19] - gnt_without_header.valid <= io.network.grant.valid @[Network.scala 95:15] - gnt_without_header.bits <- io.network.grant.bits.payload @[Network.scala 96:14] - io.network.grant.ready <= gnt_without_header.ready @[Network.scala 97:14] - io.network.acquire <- acq_with_header @[Network.scala 202:22] - io.network.release <- rel_with_header @[Network.scala 203:22] - io.network.finish <- fin_with_header @[Network.scala 204:21] - io.client.probe <- prb_without_header @[Network.scala 205:19] - io.client.grant.bits.manager_id <= io.network.grant.bits.header.src @[Network.scala 206:35] - io.client.grant <- gnt_without_header @[Network.scala 207:19] - - module TileLinkEnqueuer_1 : + wire acq_with_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + acq_with_header is invalid + acq_with_header.bits.payload <- io.client.acquire.bits + acq_with_header.bits.header.src <= UInt<1>("h0") + node T_3894 = shl(io.client.acquire.bits.addr_block, 6) + node T_3896 = leq(UInt<32>("h80000000"), T_3894) + node T_3898 = lt(T_3894, UInt<32>("h90000000")) + node T_3899 = and(T_3896, T_3898) + node T_3902 = mux(T_3899, UInt<1>("h0"), UInt<1>("h1")) + acq_with_header.bits.header.dst <= T_3902 + acq_with_header.valid <= io.client.acquire.valid + io.client.acquire.ready <= acq_with_header.ready + wire rel_with_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} + rel_with_header is invalid + rel_with_header.bits.payload <- io.client.release.bits + rel_with_header.bits.header.src <= UInt<1>("h0") + node T_4464 = shl(io.client.release.bits.addr_block, 6) + node T_4466 = leq(UInt<32>("h80000000"), T_4464) + node T_4468 = lt(T_4464, UInt<32>("h90000000")) + node T_4469 = and(T_4466, T_4468) + node T_4472 = mux(T_4469, UInt<1>("h0"), UInt<1>("h1")) + rel_with_header.bits.header.dst <= T_4472 + rel_with_header.valid <= io.client.release.valid + io.client.release.ready <= rel_with_header.ready + wire fin_with_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}} + fin_with_header is invalid + fin_with_header.bits.payload <- io.client.finish.bits + fin_with_header.bits.header.src <= UInt<1>("h0") + fin_with_header.bits.header.dst <= io.client.finish.bits.manager_id + fin_with_header.valid <= io.client.finish.valid + io.client.finish.ready <= fin_with_header.ready + wire prb_without_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}} + prb_without_header is invalid + prb_without_header.valid <= io.network.probe.valid + prb_without_header.bits <- io.network.probe.bits.payload + io.network.probe.ready <= prb_without_header.ready + wire gnt_without_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}} + gnt_without_header is invalid + gnt_without_header.valid <= io.network.grant.valid + gnt_without_header.bits <- io.network.grant.bits.payload + io.network.grant.ready <= gnt_without_header.ready + io.network.acquire <- acq_with_header + io.network.release <- rel_with_header + io.network.finish <- fin_with_header + io.client.probe <- prb_without_header + io.client.grant.bits.manager_id <= io.network.grant.bits.header.src + io.client.grant <- gnt_without_header + + module TileLinkEnqueuer_1 : input clk : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip client : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - inst Queue_4_1 of Queue @[Decoupled.scala 228:19] + inst Queue_4_1 of Queue Queue_4_1.io is invalid Queue_4_1.clk <= clk Queue_4_1.reset <= reset - Queue_4_1.io.enq.valid <= io.client.acquire.valid @[Decoupled.scala 229:20] - Queue_4_1.io.enq.bits <- io.client.acquire.bits @[Decoupled.scala 230:19] - io.client.acquire.ready <= Queue_4_1.io.enq.ready @[Decoupled.scala 231:15] - io.manager.acquire <- Queue_4_1.io.deq @[Enqueuer.scala 17:22] - inst Queue_5_1 of Queue_1 @[Decoupled.scala 228:19] + Queue_4_1.io.enq.valid <= io.client.acquire.valid + Queue_4_1.io.enq.bits <- io.client.acquire.bits + io.client.acquire.ready <= Queue_4_1.io.enq.ready + io.manager.acquire <- Queue_4_1.io.deq + inst Queue_5_1 of Queue_1 Queue_5_1.io is invalid Queue_5_1.clk <= clk Queue_5_1.reset <= reset - Queue_5_1.io.enq.valid <= io.manager.probe.valid @[Decoupled.scala 229:20] - Queue_5_1.io.enq.bits <- io.manager.probe.bits @[Decoupled.scala 230:19] - io.manager.probe.ready <= Queue_5_1.io.enq.ready @[Decoupled.scala 231:15] - io.client.probe <- Queue_5_1.io.deq @[Enqueuer.scala 18:22] - inst Queue_6_1 of Queue_2 @[Decoupled.scala 228:19] + Queue_5_1.io.enq.valid <= io.manager.probe.valid + Queue_5_1.io.enq.bits <- io.manager.probe.bits + io.manager.probe.ready <= Queue_5_1.io.enq.ready + io.client.probe <- Queue_5_1.io.deq + inst Queue_6_1 of Queue_2 Queue_6_1.io is invalid Queue_6_1.clk <= clk Queue_6_1.reset <= reset - Queue_6_1.io.enq.valid <= io.client.release.valid @[Decoupled.scala 229:20] - Queue_6_1.io.enq.bits <- io.client.release.bits @[Decoupled.scala 230:19] - io.client.release.ready <= Queue_6_1.io.enq.ready @[Decoupled.scala 231:15] - io.manager.release <- Queue_6_1.io.deq @[Enqueuer.scala 19:22] - inst Queue_7_1 of Queue_3 @[Decoupled.scala 228:19] + Queue_6_1.io.enq.valid <= io.client.release.valid + Queue_6_1.io.enq.bits <- io.client.release.bits + io.client.release.ready <= Queue_6_1.io.enq.ready + io.manager.release <- Queue_6_1.io.deq + inst Queue_7_1 of Queue_3 Queue_7_1.io is invalid Queue_7_1.clk <= clk Queue_7_1.reset <= reset - Queue_7_1.io.enq.valid <= io.manager.grant.valid @[Decoupled.scala 229:20] - Queue_7_1.io.enq.bits <- io.manager.grant.bits @[Decoupled.scala 230:19] - io.manager.grant.ready <= Queue_7_1.io.enq.ready @[Decoupled.scala 231:15] - io.client.grant <- Queue_7_1.io.deq @[Enqueuer.scala 20:22] - io.manager.finish <- io.client.finish @[Enqueuer.scala 21:22] - - module FinishQueue_1 : + Queue_7_1.io.enq.valid <= io.manager.grant.valid + Queue_7_1.io.enq.bits <- io.manager.grant.bits + io.manager.grant.ready <= Queue_7_1.io.enq.ready + io.client.grant <- Queue_7_1.io.deq + io.manager.finish <- io.client.finish + + module FinishQueue_1 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}, count : UInt<2>} + io is invalid - cmem ram : {manager_xact_id : UInt<4>, manager_id : UInt<1>}[2] @[Decoupled.scala 162:16] - reg T_218 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_220 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_218, T_220) @[Decoupled.scala 167:33] - node T_223 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_223) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_224 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { manager_xact_id : UInt<4>, manager_id : UInt<1>} [2] + reg T_218 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_220 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_218, T_220) + node T_223 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_223) + node full = and(ptr_match, maybe_full) + node T_224 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_224 - node T_225 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_225 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_225 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_226 = ram[T_218], clk - T_226 <- io.enq.bits @[Decoupled.scala 174:24] - node T_250 = eq(T_218, UInt<1>("h01")) @[Counter.scala 20:24] - node T_252 = add(T_218, UInt<1>("h01")) @[Counter.scala 21:22] - node T_253 = tail(T_252, 1) @[Counter.scala 21:22] - T_218 <= T_253 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_255 = eq(T_220, UInt<1>("h01")) @[Counter.scala 20:24] - node T_257 = add(T_220, UInt<1>("h01")) @[Counter.scala 21:22] - node T_258 = tail(T_257, 1) @[Counter.scala 21:22] - T_220 <= T_258 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_259 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_259 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_261 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_261 @[Decoupled.scala 184:16] - node T_263 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_263 @[Decoupled.scala 185:16] + T_226 <- io.enq.bits + node T_250 = eq(T_218, UInt<1>("h1")) + node T_252 = add(T_218, UInt<1>("h1")) + node T_253 = tail(T_252, 1) + T_218 <= T_253 + when do_deq : + node T_255 = eq(T_220, UInt<1>("h1")) + node T_257 = add(T_220, UInt<1>("h1")) + node T_258 = tail(T_257, 1) + T_220 <= T_258 + node T_259 = neq(do_enq, do_deq) + when T_259 : + maybe_full <= do_enq + node T_261 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_261 + node T_263 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_263 infer mport T_264 = ram[T_220], clk - io.deq.bits <- T_264 @[Decoupled.scala 186:15] - node T_287 = sub(T_218, T_220) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_287, 1) @[Decoupled.scala 201:32] - node T_288 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_289 = cat(T_288, ptr_diff) @[Cat.scala 20:58] - io.count <= T_289 @[Decoupled.scala 203:14] - - module FinishUnit : + io.deq.bits <- T_264 + node T_287 = sub(T_218, T_220) + node ptr_diff = tail(T_287, 1) + node T_288 = and(maybe_full, ptr_match) + node T_289 = cat(T_288, ptr_diff) + io.count <= T_289 + + module FinishUnit : input clk : Clock input reset : UInt<1> - output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - + output io : { flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, ready : UInt<1>} + + wire T_1054 : UInt<1> + T_1054 is invalid io is invalid - node T_1035 = and(io.grant.ready, io.grant.valid) @[Decoupled.scala 21:42] - wire T_1044 : UInt<3>[1] @[Definitions.scala 853:34] - T_1044 is invalid @[Definitions.scala 853:34] - T_1044[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1046 = eq(io.grant.bits.payload.g_type, T_1044[0]) @[Package.scala 7:47] - node T_1047 = eq(io.grant.bits.payload.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1048 = mux(io.grant.bits.payload.is_builtin_type, T_1046, T_1047) @[Definitions.scala 274:33] - node T_1049 = and(UInt<1>("h01"), T_1048) @[Definitions.scala 274:27] - node T_1050 = and(T_1035, T_1049) @[Counters.scala 67:47] - reg T_1052 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_1050 : @[Counter.scala 43:17] - node T_1054 = eq(T_1052, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1056 = add(T_1052, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1057 = tail(T_1056, 1) @[Counter.scala 21:22] - T_1052 <= T_1057 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_1058 = and(T_1050, T_1054) @[Counter.scala 44:20] - node T_1059 = mux(T_1049, T_1052, UInt<1>("h00")) @[Counters.scala 68:18] - node T_1060 = mux(T_1049, T_1058, T_1035) @[Counters.scala 69:19] - inst FinishQueue_1_1 of FinishQueue_1 @[Network.scala 158:19] + node T_1035 = and(io.grant.ready, io.grant.valid) + wire T_1044 : UInt<3>[1] + T_1044 is invalid + T_1044[0] <= UInt<3>("h5") + node T_1046 = eq(io.grant.bits.payload.g_type, T_1044[0]) + node T_1047 = eq(io.grant.bits.payload.g_type, UInt<1>("h0")) + node T_1048 = mux(io.grant.bits.payload.is_builtin_type, T_1046, T_1047) + node T_1049 = and(UInt<1>("h1"), T_1048) + node T_1050 = and(T_1035, T_1049) + reg T_1052 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_1050 : + T_1054 <= eq(T_1052, UInt<3>("h7")) + node T_1056 = add(T_1052, UInt<1>("h1")) + node T_1057 = tail(T_1056, 1) + T_1052 <= T_1057 + node T_1058 = and(T_1050, T_1054) + node T_1059 = mux(T_1049, T_1052, UInt<1>("h0")) + node T_1060 = mux(T_1049, T_1058, T_1035) + inst FinishQueue_1_1 of FinishQueue_1 FinishQueue_1_1.io is invalid FinishQueue_1_1.clk <= clk FinishQueue_1_1.reset <= reset - node T_1084 = and(io.grant.ready, io.grant.valid) @[Decoupled.scala 21:42] - node T_1087 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_1089 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_1090 = and(io.grant.bits.payload.is_builtin_type, T_1089) @[Definitions.scala 277:59] - node T_1092 = eq(T_1090, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_1093 = and(T_1087, T_1092) @[Definitions.scala 278:89] - node T_1094 = and(T_1084, T_1093) @[Network.scala 159:39] - wire T_1102 : UInt<3>[1] @[Definitions.scala 853:34] - T_1102 is invalid @[Definitions.scala 853:34] - T_1102[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1104 = eq(io.grant.bits.payload.g_type, T_1102[0]) @[Package.scala 7:47] - node T_1105 = eq(io.grant.bits.payload.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1106 = mux(io.grant.bits.payload.is_builtin_type, T_1104, T_1105) @[Definitions.scala 274:33] - node T_1107 = and(UInt<1>("h01"), T_1106) @[Definitions.scala 274:27] - node T_1109 = eq(T_1107, UInt<1>("h00")) @[Network.scala 159:62] - node T_1110 = or(T_1109, T_1060) @[Network.scala 159:84] - node T_1111 = and(T_1094, T_1110) @[Network.scala 159:58] - FinishQueue_1_1.io.enq.valid <= T_1111 @[Network.scala 159:20] - wire T_1134 : {manager_xact_id : UInt<4>} @[Definitions.scala 798:17] - T_1134 is invalid @[Definitions.scala 798:17] - T_1134.manager_xact_id <= io.grant.bits.payload.manager_xact_id @[Definitions.scala 799:23] - FinishQueue_1_1.io.enq.bits <- T_1134 @[Network.scala 160:19] - FinishQueue_1_1.io.enq.bits.manager_id <= io.grant.bits.header.src @[Network.scala 161:30] - io.finish.bits.header.src <= UInt<1>("h01") @[Network.scala 163:31] - io.finish.bits.header.dst <= FinishQueue_1_1.io.deq.bits.manager_id @[Network.scala 164:31] - io.finish.bits.payload <- FinishQueue_1_1.io.deq.bits @[Network.scala 165:28] - io.finish.valid <= FinishQueue_1_1.io.deq.valid @[Network.scala 166:21] - FinishQueue_1_1.io.deq.ready <= io.finish.ready @[Network.scala 167:20] - node T_1159 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_1161 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_1162 = and(io.grant.bits.payload.is_builtin_type, T_1161) @[Definitions.scala 277:59] - node T_1164 = eq(T_1162, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_1165 = and(T_1159, T_1164) @[Definitions.scala 278:89] - node T_1167 = eq(T_1165, UInt<1>("h00")) @[Network.scala 169:43] - node T_1168 = or(FinishQueue_1_1.io.enq.ready, T_1167) @[Network.scala 169:40] - node T_1169 = and(T_1168, io.grant.valid) @[Network.scala 169:61] - io.refill.valid <= T_1169 @[Network.scala 169:21] - io.refill.bits <- io.grant.bits.payload @[Network.scala 170:20] - node T_1172 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_1174 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_1175 = and(io.grant.bits.payload.is_builtin_type, T_1174) @[Definitions.scala 277:59] - node T_1177 = eq(T_1175, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_1178 = and(T_1172, T_1177) @[Definitions.scala 278:89] - node T_1180 = eq(T_1178, UInt<1>("h00")) @[Network.scala 171:42] - node T_1181 = or(FinishQueue_1_1.io.enq.ready, T_1180) @[Network.scala 171:39] - node T_1182 = and(T_1181, io.refill.ready) @[Network.scala 171:60] - io.grant.ready <= T_1182 @[Network.scala 171:20] - io.ready <= FinishQueue_1_1.io.enq.ready @[Network.scala 172:14] - - module ClientUncachedTileLinkNetworkPort : + node T_1084 = and(io.grant.ready, io.grant.valid) + node T_1087 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1089 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) + node T_1090 = and(io.grant.bits.payload.is_builtin_type, T_1089) + node T_1092 = eq(T_1090, UInt<1>("h0")) + node T_1093 = and(T_1087, T_1092) + node T_1094 = and(T_1084, T_1093) + wire T_1102 : UInt<3>[1] + T_1102 is invalid + T_1102[0] <= UInt<3>("h5") + node T_1104 = eq(io.grant.bits.payload.g_type, T_1102[0]) + node T_1105 = eq(io.grant.bits.payload.g_type, UInt<1>("h0")) + node T_1106 = mux(io.grant.bits.payload.is_builtin_type, T_1104, T_1105) + node T_1107 = and(UInt<1>("h1"), T_1106) + node T_1109 = eq(T_1107, UInt<1>("h0")) + node T_1110 = or(T_1109, T_1060) + node T_1111 = and(T_1094, T_1110) + FinishQueue_1_1.io.enq.valid <= T_1111 + wire T_1134 : { manager_xact_id : UInt<4>} + T_1134 is invalid + T_1134.manager_xact_id <= io.grant.bits.payload.manager_xact_id + FinishQueue_1_1.io.enq.bits <- T_1134 + FinishQueue_1_1.io.enq.bits.manager_id <= io.grant.bits.header.src + io.finish.bits.header.src <= UInt<1>("h1") + io.finish.bits.header.dst <= FinishQueue_1_1.io.deq.bits.manager_id + io.finish.bits.payload <- FinishQueue_1_1.io.deq.bits + io.finish.valid <= FinishQueue_1_1.io.deq.valid + FinishQueue_1_1.io.deq.ready <= io.finish.ready + node T_1159 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1161 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) + node T_1162 = and(io.grant.bits.payload.is_builtin_type, T_1161) + node T_1164 = eq(T_1162, UInt<1>("h0")) + node T_1165 = and(T_1159, T_1164) + node T_1167 = eq(T_1165, UInt<1>("h0")) + node T_1168 = or(FinishQueue_1_1.io.enq.ready, T_1167) + node T_1169 = and(T_1168, io.grant.valid) + io.refill.valid <= T_1169 + io.refill.bits <- io.grant.bits.payload + node T_1172 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1174 = eq(io.grant.bits.payload.g_type, UInt<3>("h0")) + node T_1175 = and(io.grant.bits.payload.is_builtin_type, T_1174) + node T_1177 = eq(T_1175, UInt<1>("h0")) + node T_1178 = and(T_1172, T_1177) + node T_1180 = eq(T_1178, UInt<1>("h0")) + node T_1181 = or(FinishQueue_1_1.io.enq.ready, T_1180) + node T_1182 = and(T_1181, io.refill.ready) + io.grant.ready <= T_1182 + io.ready <= FinishQueue_1_1.io.enq.ready + + module ClientUncachedTileLinkNetworkPort : input clk : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip client : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, network : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - inst finisher of FinishUnit @[Network.scala 226:24] + inst finisher of FinishUnit finisher.io is invalid finisher.clk <= clk finisher.reset <= reset - finisher.io.grant <- io.network.grant @[Network.scala 227:21] - io.network.finish <- finisher.io.finish @[Network.scala 228:21] - wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 259:19] - acq_with_header is invalid @[Network.scala 259:19] - acq_with_header.bits.payload <- io.client.acquire.bits @[Network.scala 260:22] - acq_with_header.bits.header.src <= UInt<1>("h01") @[Network.scala 261:25] - node T_3330 = shl(io.client.acquire.bits.addr_block, 6) @[Coreplex.scala 94:59] - node T_3332 = leq(UInt<32>("h080000000"), T_3330) @[addrmap.scala 26:46] - node T_3334 = lt(T_3330, UInt<32>("h090000000")) @[addrmap.scala 26:56] - node T_3335 = and(T_3332, T_3334) @[addrmap.scala 26:51] - node T_3338 = mux(T_3335, UInt<1>("h00"), UInt<1>("h01")) @[Coreplex.scala 95:10] - acq_with_header.bits.header.dst <= T_3338 @[Network.scala 262:25] - acq_with_header.valid <= io.client.acquire.valid @[Network.scala 263:15] - io.client.acquire.ready <= acq_with_header.ready @[Network.scala 264:14] - io.network.acquire.bits <- acq_with_header.bits @[Network.scala 233:27] - node T_3339 = and(acq_with_header.valid, finisher.io.ready) @[Network.scala 234:53] - io.network.acquire.valid <= T_3339 @[Network.scala 234:28] - node T_3340 = and(io.network.acquire.ready, finisher.io.ready) @[Network.scala 235:53] - acq_with_header.ready <= T_3340 @[Network.scala 235:25] - io.client.grant <- finisher.io.refill @[Network.scala 236:19] - io.network.probe.ready <= UInt<1>("h00") @[Network.scala 237:26] - io.network.release.valid <= UInt<1>("h00") @[Network.scala 238:28] - - module ManagerTileLinkNetworkPort : + finisher.io.grant <- io.network.grant + io.network.finish <- finisher.io.finish + wire acq_with_header : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + acq_with_header is invalid + acq_with_header.bits.payload <- io.client.acquire.bits + acq_with_header.bits.header.src <= UInt<1>("h1") + node T_3330 = shl(io.client.acquire.bits.addr_block, 6) + node T_3332 = leq(UInt<32>("h80000000"), T_3330) + node T_3334 = lt(T_3330, UInt<32>("h90000000")) + node T_3335 = and(T_3332, T_3334) + node T_3338 = mux(T_3335, UInt<1>("h0"), UInt<1>("h1")) + acq_with_header.bits.header.dst <= T_3338 + acq_with_header.valid <= io.client.acquire.valid + io.client.acquire.ready <= acq_with_header.ready + io.network.acquire.bits <- acq_with_header.bits + node T_3339 = and(acq_with_header.valid, finisher.io.ready) + io.network.acquire.valid <= T_3339 + node T_3340 = and(io.network.acquire.ready, finisher.io.ready) + acq_with_header.ready <= T_3340 + io.client.grant <- finisher.io.refill + io.network.probe.ready <= UInt<1>("h0") + io.network.release.valid <= UInt<1>("h0") + + module ManagerTileLinkNetworkPort : input clk : Clock input reset : UInt<1> - output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip manager : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip network : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - wire T_6043 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}} @[Network.scala 300:19] - T_6043 is invalid @[Network.scala 300:19] - T_6043.bits.payload <- io.manager.grant.bits @[Network.scala 301:22] - T_6043.bits.header.src <= UInt<1>("h00") @[Network.scala 302:25] - T_6043.bits.header.dst <= io.manager.grant.bits.client_id @[Network.scala 303:25] - T_6043.valid <= io.manager.grant.valid @[Network.scala 304:15] - io.manager.grant.ready <= T_6043.ready @[Network.scala 305:14] - io.network.grant <- T_6043 @[Network.scala 285:20] - wire T_6598 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} @[Network.scala 300:19] - T_6598 is invalid @[Network.scala 300:19] - T_6598.bits.payload <- io.manager.probe.bits @[Network.scala 301:22] - T_6598.bits.header.src <= UInt<1>("h00") @[Network.scala 302:25] - T_6598.bits.header.dst <= io.manager.probe.bits.client_id @[Network.scala 303:25] - T_6598.valid <= io.manager.probe.valid @[Network.scala 304:15] - io.manager.probe.ready <= T_6598.ready @[Network.scala 305:14] - io.network.probe <- T_6598 @[Network.scala 286:20] - wire T_6877 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}} @[Network.scala 94:19] - T_6877 is invalid @[Network.scala 94:19] - T_6877.valid <= io.network.acquire.valid @[Network.scala 95:15] - T_6877.bits <- io.network.acquire.bits.payload @[Network.scala 96:14] - io.network.acquire.ready <= T_6877.ready @[Network.scala 97:14] - io.manager.acquire <- T_6877 @[Network.scala 287:22] - io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src @[Network.scala 288:37] - wire T_6993 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}} @[Network.scala 94:19] - T_6993 is invalid @[Network.scala 94:19] - T_6993.valid <= io.network.release.valid @[Network.scala 95:15] - T_6993.bits <- io.network.release.bits.payload @[Network.scala 96:14] - io.network.release.ready <= T_6993.ready @[Network.scala 97:14] - io.manager.release <- T_6993 @[Network.scala 289:22] - io.manager.release.bits.client_id <= io.network.release.bits.header.src @[Network.scala 290:37] - wire T_7097 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} @[Network.scala 94:19] - T_7097 is invalid @[Network.scala 94:19] - T_7097.valid <= io.network.finish.valid @[Network.scala 95:15] - T_7097.bits <- io.network.finish.bits.payload @[Network.scala 96:14] - io.network.finish.ready <= T_7097.ready @[Network.scala 97:14] - io.manager.finish <- T_7097 @[Network.scala 291:21] - - module TileLinkEnqueuer_2 : + wire T_6043 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}} + T_6043 is invalid + T_6043.bits.payload <- io.manager.grant.bits + T_6043.bits.header.src <= UInt<1>("h0") + T_6043.bits.header.dst <= io.manager.grant.bits.client_id + T_6043.valid <= io.manager.grant.valid + io.manager.grant.ready <= T_6043.ready + io.network.grant <- T_6043 + wire T_6598 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} + T_6598 is invalid + T_6598.bits.payload <- io.manager.probe.bits + T_6598.bits.header.src <= UInt<1>("h0") + T_6598.bits.header.dst <= io.manager.probe.bits.client_id + T_6598.valid <= io.manager.probe.valid + io.manager.probe.ready <= T_6598.ready + io.network.probe <- T_6598 + wire T_6877 : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}} + T_6877 is invalid + T_6877.valid <= io.network.acquire.valid + T_6877.bits <- io.network.acquire.bits.payload + io.network.acquire.ready <= T_6877.ready + io.manager.acquire <- T_6877 + io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src + wire T_6993 : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}} + T_6993 is invalid + T_6993.valid <= io.network.release.valid + T_6993.bits <- io.network.release.bits.payload + io.network.release.ready <= T_6993.ready + io.manager.release <- T_6993 + io.manager.release.bits.client_id <= io.network.release.bits.header.src + wire T_7097 : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}} + T_7097 is invalid + T_7097.valid <= io.network.finish.valid + T_7097.bits <- io.network.finish.bits.payload + io.network.finish.ready <= T_7097.ready + io.manager.finish <- T_7097 + + module TileLinkEnqueuer_2 : input clk : Clock input reset : UInt<1> - output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip client : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}, manager : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - io.manager.acquire <- io.client.acquire @[Enqueuer.scala 17:22] - io.client.probe <- io.manager.probe @[Enqueuer.scala 18:22] - io.manager.release <- io.client.release @[Enqueuer.scala 19:22] - io.client.grant <- io.manager.grant @[Enqueuer.scala 20:22] - io.manager.finish <- io.client.finish @[Enqueuer.scala 21:22] - - module ManagerTileLinkNetworkPort_1 : + io.manager.acquire <- io.client.acquire + io.client.probe <- io.manager.probe + io.manager.release <- io.client.release + io.client.grant <- io.manager.grant + io.manager.finish <- io.client.finish + + module ManagerTileLinkNetworkPort_1 : input clk : Clock input reset : UInt<1> - output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} - + output io : { flip manager : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip network : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}}} + io is invalid - wire T_6043 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}} @[Network.scala 300:19] - T_6043 is invalid @[Network.scala 300:19] - T_6043.bits.payload <- io.manager.grant.bits @[Network.scala 301:22] - T_6043.bits.header.src <= UInt<1>("h01") @[Network.scala 302:25] - T_6043.bits.header.dst <= io.manager.grant.bits.client_id @[Network.scala 303:25] - T_6043.valid <= io.manager.grant.valid @[Network.scala 304:15] - io.manager.grant.ready <= T_6043.ready @[Network.scala 305:14] - io.network.grant <- T_6043 @[Network.scala 285:20] - wire T_6598 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} @[Network.scala 300:19] - T_6598 is invalid @[Network.scala 300:19] - T_6598.bits.payload <- io.manager.probe.bits @[Network.scala 301:22] - T_6598.bits.header.src <= UInt<1>("h01") @[Network.scala 302:25] - T_6598.bits.header.dst <= io.manager.probe.bits.client_id @[Network.scala 303:25] - T_6598.valid <= io.manager.probe.valid @[Network.scala 304:15] - io.manager.probe.ready <= T_6598.ready @[Network.scala 305:14] - io.network.probe <- T_6598 @[Network.scala 286:20] - wire T_6877 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}} @[Network.scala 94:19] - T_6877 is invalid @[Network.scala 94:19] - T_6877.valid <= io.network.acquire.valid @[Network.scala 95:15] - T_6877.bits <- io.network.acquire.bits.payload @[Network.scala 96:14] - io.network.acquire.ready <= T_6877.ready @[Network.scala 97:14] - io.manager.acquire <- T_6877 @[Network.scala 287:22] - io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src @[Network.scala 288:37] - wire T_6993 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}} @[Network.scala 94:19] - T_6993 is invalid @[Network.scala 94:19] - T_6993.valid <= io.network.release.valid @[Network.scala 95:15] - T_6993.bits <- io.network.release.bits.payload @[Network.scala 96:14] - io.network.release.ready <= T_6993.ready @[Network.scala 97:14] - io.manager.release <- T_6993 @[Network.scala 289:22] - io.manager.release.bits.client_id <= io.network.release.bits.header.src @[Network.scala 290:37] - wire T_7097 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} @[Network.scala 94:19] - T_7097 is invalid @[Network.scala 94:19] - T_7097.valid <= io.network.finish.valid @[Network.scala 95:15] - T_7097.bits <- io.network.finish.bits.payload @[Network.scala 96:14] - io.network.finish.ready <= T_7097.ready @[Network.scala 97:14] - io.manager.finish <- T_7097 @[Network.scala 291:21] - - module LockingRRArbiter : + wire T_6043 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}} + T_6043 is invalid + T_6043.bits.payload <- io.manager.grant.bits + T_6043.bits.header.src <= UInt<1>("h1") + T_6043.bits.header.dst <= io.manager.grant.bits.client_id + T_6043.valid <= io.manager.grant.valid + io.manager.grant.ready <= T_6043.ready + io.network.grant <- T_6043 + wire T_6598 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} + T_6598 is invalid + T_6598.bits.payload <- io.manager.probe.bits + T_6598.bits.header.src <= UInt<1>("h1") + T_6598.bits.header.dst <= io.manager.probe.bits.client_id + T_6598.valid <= io.manager.probe.valid + io.manager.probe.ready <= T_6598.ready + io.network.probe <- T_6598 + wire T_6877 : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}} + T_6877 is invalid + T_6877.valid <= io.network.acquire.valid + T_6877.bits <- io.network.acquire.bits.payload + io.network.acquire.ready <= T_6877.ready + io.manager.acquire <- T_6877 + io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src + wire T_6993 : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}} + T_6993 is invalid + T_6993.valid <= io.network.release.valid + T_6993.bits <- io.network.release.bits.payload + io.network.release.ready <= T_6993.ready + io.manager.release <- T_6993 + io.manager.release.bits.client_id <= io.network.release.bits.header.src + wire T_7097 : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}} + T_7097 is invalid + T_7097.valid <= io.network.finish.valid + T_7097.bits <- io.network.finish.bits.payload + io.network.finish.ready <= T_7097.ready + io.manager.finish <- T_7097 + + module LockingRRArbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1134 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1136 : UInt, clk - node T_1138 = neq(T_1134, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_1140 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type) @[Definitions.scala 231:70] - wire T_1147 : UInt<3>[1] @[Definitions.scala 355:35] - T_1147 is invalid @[Definitions.scala 355:35] - T_1147[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1149 = eq(io.out.bits.payload.a_type, T_1147[0]) @[Package.scala 7:47] - node T_1150 = and(T_1140, T_1149) @[Definitions.scala 231:89] - node T_1151 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1152 = and(T_1151, T_1150) @[Arbiter.scala 42:25] - when T_1152 : @[Arbiter.scala 42:39] - T_1136 <= io.chosen @[Arbiter.scala 43:15] - node T_1154 = eq(T_1134, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1156 = add(T_1134, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1157 = tail(T_1156, 1) @[Counter.scala 21:22] - T_1134 <= T_1157 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1138 : @[Arbiter.scala 47:19] - io.chosen <= T_1136 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1159 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_1159 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_1164 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1165 = or(T_1164, validMask_2) @[Arbiter.scala 23:72] - node T_1166 = or(T_1165, validMask_3) @[Arbiter.scala 23:72] - node T_1167 = or(T_1166, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1168 = or(T_1167, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1169 = or(T_1168, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1171 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1173 = eq(T_1164, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1175 = eq(T_1165, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1177 = eq(T_1166, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1179 = eq(T_1167, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1181 = eq(T_1168, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1183 = eq(T_1169, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1184 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1185 = or(T_1184, T_1177) @[Arbiter.scala 64:50] - node T_1186 = and(T_1171, grantMask_1) @[Arbiter.scala 64:34] - node T_1187 = or(T_1186, T_1179) @[Arbiter.scala 64:50] - node T_1188 = and(T_1173, grantMask_2) @[Arbiter.scala 64:34] - node T_1189 = or(T_1188, T_1181) @[Arbiter.scala 64:50] - node T_1190 = and(T_1175, grantMask_3) @[Arbiter.scala 64:34] - node T_1191 = or(T_1190, T_1183) @[Arbiter.scala 64:50] - node T_1193 = eq(T_1136, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1194 = mux(T_1138, T_1193, T_1185) @[Arbiter.scala 49:22] - node T_1195 = and(T_1194, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1195 @[Arbiter.scala 49:16] - node T_1197 = eq(T_1136, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1198 = mux(T_1138, T_1197, T_1187) @[Arbiter.scala 49:22] - node T_1199 = and(T_1198, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1199 @[Arbiter.scala 49:16] - node T_1201 = eq(T_1136, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1202 = mux(T_1138, T_1201, T_1189) @[Arbiter.scala 49:22] - node T_1203 = and(T_1202, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1203 @[Arbiter.scala 49:16] - node T_1205 = eq(T_1136, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1206 = mux(T_1138, T_1205, T_1191) @[Arbiter.scala 49:22] - node T_1207 = and(T_1206, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1207 @[Arbiter.scala 49:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module BasicBus : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1134 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1136 : UInt, clk with : + reset => (UInt<1>("h0"), T_1136) + node T_1138 = neq(T_1134, UInt<1>("h0")) + node T_1140 = and(UInt<1>("h1"), io.out.bits.payload.is_builtin_type) + wire T_1147 : UInt<3>[1] + T_1147 is invalid + T_1147[0] <= UInt<3>("h3") + node T_1149 = eq(io.out.bits.payload.a_type, T_1147[0]) + node T_1150 = and(T_1140, T_1149) + node T_1151 = and(io.out.ready, io.out.valid) + node T_1152 = and(T_1151, T_1150) + when T_1152 : + T_1136 <= io.chosen + node T_1154 = eq(T_1134, UInt<3>("h7")) + node T_1156 = add(T_1134, UInt<1>("h1")) + node T_1157 = tail(T_1156, 1) + T_1134 <= T_1157 + when T_1138 : + io.chosen <= T_1136 + node T_1159 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1159 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_1164 = or(validMask_0, validMask_1) + node T_1165 = or(T_1164, validMask_2) + node T_1166 = or(T_1165, validMask_3) + node T_1167 = or(T_1166, io.in[0].valid) + node T_1168 = or(T_1167, io.in[1].valid) + node T_1169 = or(T_1168, io.in[2].valid) + node T_1171 = eq(validMask_0, UInt<1>("h0")) + node T_1173 = eq(T_1164, UInt<1>("h0")) + node T_1175 = eq(T_1165, UInt<1>("h0")) + node T_1177 = eq(T_1166, UInt<1>("h0")) + node T_1179 = eq(T_1167, UInt<1>("h0")) + node T_1181 = eq(T_1168, UInt<1>("h0")) + node T_1183 = eq(T_1169, UInt<1>("h0")) + node T_1184 = and(UInt<1>("h1"), grantMask_0) + node T_1185 = or(T_1184, T_1177) + node T_1186 = and(T_1171, grantMask_1) + node T_1187 = or(T_1186, T_1179) + node T_1188 = and(T_1173, grantMask_2) + node T_1189 = or(T_1188, T_1181) + node T_1190 = and(T_1175, grantMask_3) + node T_1191 = or(T_1190, T_1183) + node T_1193 = eq(T_1136, UInt<1>("h0")) + node T_1194 = mux(T_1138, T_1193, T_1185) + node T_1195 = and(T_1194, io.out.ready) + io.in[0].ready <= T_1195 + node T_1197 = eq(T_1136, UInt<1>("h1")) + node T_1198 = mux(T_1138, T_1197, T_1187) + node T_1199 = and(T_1198, io.out.ready) + io.in[1].ready <= T_1199 + node T_1201 = eq(T_1136, UInt<2>("h2")) + node T_1202 = mux(T_1138, T_1201, T_1189) + node T_1203 = and(T_1202, io.out.ready) + io.in[2].ready <= T_1203 + node T_1205 = eq(T_1136, UInt<2>("h3")) + node T_1206 = mux(T_1138, T_1205, T_1191) + node T_1207 = and(T_1206, io.out.ready) + io.in[3].ready <= T_1207 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module BasicBus : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4]} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}}[4]} + io is invalid - inst arb of LockingRRArbiter @[Network.scala 37:19] + inst arb of LockingRRArbiter arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in <= io.in @[Network.scala 38:13] - arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready @[Network.scala 40:20] - node T_1529 = eq(arb.io.out.bits.header.dst, UInt<1>("h00")) @[Network.scala 42:65] - node T_1530 = and(arb.io.out.valid, T_1529) @[Network.scala 42:35] - io.out[0].valid <= T_1530 @[Network.scala 42:15] - io.out[0].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1532 = eq(arb.io.out.bits.header.dst, UInt<1>("h01")) @[Network.scala 42:65] - node T_1533 = and(arb.io.out.valid, T_1532) @[Network.scala 42:35] - io.out[1].valid <= T_1533 @[Network.scala 42:15] - io.out[1].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1535 = eq(arb.io.out.bits.header.dst, UInt<2>("h02")) @[Network.scala 42:65] - node T_1536 = and(arb.io.out.valid, T_1535) @[Network.scala 42:35] - io.out[2].valid <= T_1536 @[Network.scala 42:15] - io.out[2].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1538 = eq(arb.io.out.bits.header.dst, UInt<2>("h03")) @[Network.scala 42:65] - node T_1539 = and(arb.io.out.valid, T_1538) @[Network.scala 42:35] - io.out[3].valid <= T_1539 @[Network.scala 42:15] - io.out[3].bits <- arb.io.out.bits @[Network.scala 43:14] - - module LockingRRArbiter_1 : + arb.io.in <= io.in + arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready + node T_1529 = eq(arb.io.out.bits.header.dst, UInt<1>("h0")) + node T_1530 = and(arb.io.out.valid, T_1529) + io.out[0].valid <= T_1530 + io.out[0].bits <- arb.io.out.bits + node T_1532 = eq(arb.io.out.bits.header.dst, UInt<1>("h1")) + node T_1533 = and(arb.io.out.valid, T_1532) + io.out[1].valid <= T_1533 + io.out[1].bits <- arb.io.out.bits + node T_1535 = eq(arb.io.out.bits.header.dst, UInt<2>("h2")) + node T_1536 = and(arb.io.out.valid, T_1535) + io.out[2].valid <= T_1536 + io.out[2].bits <- arb.io.out.bits + node T_1538 = eq(arb.io.out.bits.header.dst, UInt<2>("h3")) + node T_1539 = and(arb.io.out.valid, T_1538) + io.out[3].valid <= T_1539 + io.out[3].bits <- arb.io.out.bits + + module LockingRRArbiter_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1100 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1102 : UInt, clk - node T_1104 = neq(T_1100, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_1106 = eq(io.out.bits.payload.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1107 = eq(io.out.bits.payload.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1108 = eq(io.out.bits.payload.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1109 = or(T_1106, T_1107) @[Package.scala 7:62] - node T_1110 = or(T_1109, T_1108) @[Package.scala 7:62] - node T_1111 = and(UInt<1>("h01"), T_1110) @[Definitions.scala 256:64] - node T_1112 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1113 = and(T_1112, T_1111) @[Arbiter.scala 42:25] - when T_1113 : @[Arbiter.scala 42:39] - T_1102 <= io.chosen @[Arbiter.scala 43:15] - node T_1115 = eq(T_1100, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1117 = add(T_1100, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1118 = tail(T_1117, 1) @[Counter.scala 21:22] - T_1100 <= T_1118 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1104 : @[Arbiter.scala 47:19] - io.chosen <= T_1102 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1120 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_1120 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_1125 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1126 = or(T_1125, validMask_2) @[Arbiter.scala 23:72] - node T_1127 = or(T_1126, validMask_3) @[Arbiter.scala 23:72] - node T_1128 = or(T_1127, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1129 = or(T_1128, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1130 = or(T_1129, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1132 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1134 = eq(T_1125, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1136 = eq(T_1126, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1138 = eq(T_1127, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1140 = eq(T_1128, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1142 = eq(T_1129, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1144 = eq(T_1130, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1145 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1146 = or(T_1145, T_1138) @[Arbiter.scala 64:50] - node T_1147 = and(T_1132, grantMask_1) @[Arbiter.scala 64:34] - node T_1148 = or(T_1147, T_1140) @[Arbiter.scala 64:50] - node T_1149 = and(T_1134, grantMask_2) @[Arbiter.scala 64:34] - node T_1150 = or(T_1149, T_1142) @[Arbiter.scala 64:50] - node T_1151 = and(T_1136, grantMask_3) @[Arbiter.scala 64:34] - node T_1152 = or(T_1151, T_1144) @[Arbiter.scala 64:50] - node T_1154 = eq(T_1102, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1155 = mux(T_1104, T_1154, T_1146) @[Arbiter.scala 49:22] - node T_1156 = and(T_1155, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1156 @[Arbiter.scala 49:16] - node T_1158 = eq(T_1102, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1159 = mux(T_1104, T_1158, T_1148) @[Arbiter.scala 49:22] - node T_1160 = and(T_1159, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1160 @[Arbiter.scala 49:16] - node T_1162 = eq(T_1102, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1163 = mux(T_1104, T_1162, T_1150) @[Arbiter.scala 49:22] - node T_1164 = and(T_1163, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1164 @[Arbiter.scala 49:16] - node T_1166 = eq(T_1102, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1167 = mux(T_1104, T_1166, T_1152) @[Arbiter.scala 49:22] - node T_1168 = and(T_1167, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1168 @[Arbiter.scala 49:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module BasicBus_1 : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1100 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1102 : UInt, clk with : + reset => (UInt<1>("h0"), T_1102) + node T_1104 = neq(T_1100, UInt<1>("h0")) + node T_1106 = eq(io.out.bits.payload.r_type, UInt<3>("h0")) + node T_1107 = eq(io.out.bits.payload.r_type, UInt<3>("h1")) + node T_1108 = eq(io.out.bits.payload.r_type, UInt<3>("h2")) + node T_1109 = or(T_1106, T_1107) + node T_1110 = or(T_1109, T_1108) + node T_1111 = and(UInt<1>("h1"), T_1110) + node T_1112 = and(io.out.ready, io.out.valid) + node T_1113 = and(T_1112, T_1111) + when T_1113 : + T_1102 <= io.chosen + node T_1115 = eq(T_1100, UInt<3>("h7")) + node T_1117 = add(T_1100, UInt<1>("h1")) + node T_1118 = tail(T_1117, 1) + T_1100 <= T_1118 + when T_1104 : + io.chosen <= T_1102 + node T_1120 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1120 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_1125 = or(validMask_0, validMask_1) + node T_1126 = or(T_1125, validMask_2) + node T_1127 = or(T_1126, validMask_3) + node T_1128 = or(T_1127, io.in[0].valid) + node T_1129 = or(T_1128, io.in[1].valid) + node T_1130 = or(T_1129, io.in[2].valid) + node T_1132 = eq(validMask_0, UInt<1>("h0")) + node T_1134 = eq(T_1125, UInt<1>("h0")) + node T_1136 = eq(T_1126, UInt<1>("h0")) + node T_1138 = eq(T_1127, UInt<1>("h0")) + node T_1140 = eq(T_1128, UInt<1>("h0")) + node T_1142 = eq(T_1129, UInt<1>("h0")) + node T_1144 = eq(T_1130, UInt<1>("h0")) + node T_1145 = and(UInt<1>("h1"), grantMask_0) + node T_1146 = or(T_1145, T_1138) + node T_1147 = and(T_1132, grantMask_1) + node T_1148 = or(T_1147, T_1140) + node T_1149 = and(T_1134, grantMask_2) + node T_1150 = or(T_1149, T_1142) + node T_1151 = and(T_1136, grantMask_3) + node T_1152 = or(T_1151, T_1144) + node T_1154 = eq(T_1102, UInt<1>("h0")) + node T_1155 = mux(T_1104, T_1154, T_1146) + node T_1156 = and(T_1155, io.out.ready) + io.in[0].ready <= T_1156 + node T_1158 = eq(T_1102, UInt<1>("h1")) + node T_1159 = mux(T_1104, T_1158, T_1148) + node T_1160 = and(T_1159, io.out.ready) + io.in[1].ready <= T_1160 + node T_1162 = eq(T_1102, UInt<2>("h2")) + node T_1163 = mux(T_1104, T_1162, T_1150) + node T_1164 = and(T_1163, io.out.ready) + io.in[2].ready <= T_1164 + node T_1166 = eq(T_1102, UInt<2>("h3")) + node T_1167 = mux(T_1104, T_1166, T_1152) + node T_1168 = and(T_1167, io.out.ready) + io.in[3].ready <= T_1168 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module BasicBus_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4]} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}}[4]} + io is invalid - inst arb of LockingRRArbiter_1 @[Network.scala 37:19] + inst arb of LockingRRArbiter_1 arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in <= io.in @[Network.scala 38:13] - arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready @[Network.scala 40:20] - node T_1483 = eq(arb.io.out.bits.header.dst, UInt<1>("h00")) @[Network.scala 42:65] - node T_1484 = and(arb.io.out.valid, T_1483) @[Network.scala 42:35] - io.out[0].valid <= T_1484 @[Network.scala 42:15] - io.out[0].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1486 = eq(arb.io.out.bits.header.dst, UInt<1>("h01")) @[Network.scala 42:65] - node T_1487 = and(arb.io.out.valid, T_1486) @[Network.scala 42:35] - io.out[1].valid <= T_1487 @[Network.scala 42:15] - io.out[1].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1489 = eq(arb.io.out.bits.header.dst, UInt<2>("h02")) @[Network.scala 42:65] - node T_1490 = and(arb.io.out.valid, T_1489) @[Network.scala 42:35] - io.out[2].valid <= T_1490 @[Network.scala 42:15] - io.out[2].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1492 = eq(arb.io.out.bits.header.dst, UInt<2>("h03")) @[Network.scala 42:65] - node T_1493 = and(arb.io.out.valid, T_1492) @[Network.scala 42:35] - io.out[3].valid <= T_1493 @[Network.scala 42:15] - io.out[3].bits <- arb.io.out.bits @[Network.scala 43:14] - - module LockingRRArbiter_2 : + arb.io.in <= io.in + arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready + node T_1483 = eq(arb.io.out.bits.header.dst, UInt<1>("h0")) + node T_1484 = and(arb.io.out.valid, T_1483) + io.out[0].valid <= T_1484 + io.out[0].bits <- arb.io.out.bits + node T_1486 = eq(arb.io.out.bits.header.dst, UInt<1>("h1")) + node T_1487 = and(arb.io.out.valid, T_1486) + io.out[1].valid <= T_1487 + io.out[1].bits <- arb.io.out.bits + node T_1489 = eq(arb.io.out.bits.header.dst, UInt<2>("h2")) + node T_1490 = and(arb.io.out.valid, T_1489) + io.out[2].valid <= T_1490 + io.out[2].bits <- arb.io.out.bits + node T_1492 = eq(arb.io.out.bits.header.dst, UInt<2>("h3")) + node T_1493 = and(arb.io.out.valid, T_1492) + io.out[3].valid <= T_1493 + io.out[3].bits <- arb.io.out.bits + + module LockingRRArbiter_2 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - node T_964 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_964 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_969 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_970 = or(T_969, validMask_2) @[Arbiter.scala 23:72] - node T_971 = or(T_970, validMask_3) @[Arbiter.scala 23:72] - node T_972 = or(T_971, io.in[0].valid) @[Arbiter.scala 23:72] - node T_973 = or(T_972, io.in[1].valid) @[Arbiter.scala 23:72] - node T_974 = or(T_973, io.in[2].valid) @[Arbiter.scala 23:72] - node T_976 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_978 = eq(T_969, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_980 = eq(T_970, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_982 = eq(T_971, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_984 = eq(T_972, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_986 = eq(T_973, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_988 = eq(T_974, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_989 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_990 = or(T_989, T_982) @[Arbiter.scala 64:50] - node T_991 = and(T_976, grantMask_1) @[Arbiter.scala 64:34] - node T_992 = or(T_991, T_984) @[Arbiter.scala 64:50] - node T_993 = and(T_978, grantMask_2) @[Arbiter.scala 64:34] - node T_994 = or(T_993, T_986) @[Arbiter.scala 64:50] - node T_995 = and(T_980, grantMask_3) @[Arbiter.scala 64:34] - node T_996 = or(T_995, T_988) @[Arbiter.scala 64:50] - node T_997 = and(T_990, io.out.ready) @[Arbiter.scala 52:21] - io.in[0].ready <= T_997 @[Arbiter.scala 52:16] - node T_998 = and(T_992, io.out.ready) @[Arbiter.scala 52:21] - io.in[1].ready <= T_998 @[Arbiter.scala 52:16] - node T_999 = and(T_994, io.out.ready) @[Arbiter.scala 52:21] - io.in[2].ready <= T_999 @[Arbiter.scala 52:16] - node T_1000 = and(T_996, io.out.ready) @[Arbiter.scala 52:21] - io.in[3].ready <= T_1000 @[Arbiter.scala 52:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module BasicBus_2 : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + node T_964 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_964 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_969 = or(validMask_0, validMask_1) + node T_970 = or(T_969, validMask_2) + node T_971 = or(T_970, validMask_3) + node T_972 = or(T_971, io.in[0].valid) + node T_973 = or(T_972, io.in[1].valid) + node T_974 = or(T_973, io.in[2].valid) + node T_976 = eq(validMask_0, UInt<1>("h0")) + node T_978 = eq(T_969, UInt<1>("h0")) + node T_980 = eq(T_970, UInt<1>("h0")) + node T_982 = eq(T_971, UInt<1>("h0")) + node T_984 = eq(T_972, UInt<1>("h0")) + node T_986 = eq(T_973, UInt<1>("h0")) + node T_988 = eq(T_974, UInt<1>("h0")) + node T_989 = and(UInt<1>("h1"), grantMask_0) + node T_990 = or(T_989, T_982) + node T_991 = and(T_976, grantMask_1) + node T_992 = or(T_991, T_984) + node T_993 = and(T_978, grantMask_2) + node T_994 = or(T_993, T_986) + node T_995 = and(T_980, grantMask_3) + node T_996 = or(T_995, T_988) + node T_997 = and(T_990, io.out.ready) + io.in[0].ready <= T_997 + node T_998 = and(T_992, io.out.ready) + io.in[1].ready <= T_998 + node T_999 = and(T_994, io.out.ready) + io.in[2].ready <= T_999 + node T_1000 = and(T_996, io.out.ready) + io.in[3].ready <= T_1000 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module BasicBus_2 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}[4]} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}}[4]} + io is invalid - inst arb of LockingRRArbiter_2 @[Network.scala 37:19] + inst arb of LockingRRArbiter_2 arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in <= io.in @[Network.scala 38:13] - arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready @[Network.scala 40:20] - node T_1299 = eq(arb.io.out.bits.header.dst, UInt<1>("h00")) @[Network.scala 42:65] - node T_1300 = and(arb.io.out.valid, T_1299) @[Network.scala 42:35] - io.out[0].valid <= T_1300 @[Network.scala 42:15] - io.out[0].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1302 = eq(arb.io.out.bits.header.dst, UInt<1>("h01")) @[Network.scala 42:65] - node T_1303 = and(arb.io.out.valid, T_1302) @[Network.scala 42:35] - io.out[1].valid <= T_1303 @[Network.scala 42:15] - io.out[1].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1305 = eq(arb.io.out.bits.header.dst, UInt<2>("h02")) @[Network.scala 42:65] - node T_1306 = and(arb.io.out.valid, T_1305) @[Network.scala 42:35] - io.out[2].valid <= T_1306 @[Network.scala 42:15] - io.out[2].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1308 = eq(arb.io.out.bits.header.dst, UInt<2>("h03")) @[Network.scala 42:65] - node T_1309 = and(arb.io.out.valid, T_1308) @[Network.scala 42:35] - io.out[3].valid <= T_1309 @[Network.scala 42:15] - io.out[3].bits <- arb.io.out.bits @[Network.scala 43:14] - - module LockingRRArbiter_3 : + arb.io.in <= io.in + arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready + node T_1299 = eq(arb.io.out.bits.header.dst, UInt<1>("h0")) + node T_1300 = and(arb.io.out.valid, T_1299) + io.out[0].valid <= T_1300 + io.out[0].bits <- arb.io.out.bits + node T_1302 = eq(arb.io.out.bits.header.dst, UInt<1>("h1")) + node T_1303 = and(arb.io.out.valid, T_1302) + io.out[1].valid <= T_1303 + io.out[1].bits <- arb.io.out.bits + node T_1305 = eq(arb.io.out.bits.header.dst, UInt<2>("h2")) + node T_1306 = and(arb.io.out.valid, T_1305) + io.out[2].valid <= T_1306 + io.out[2].bits <- arb.io.out.bits + node T_1308 = eq(arb.io.out.bits.header.dst, UInt<2>("h3")) + node T_1309 = and(arb.io.out.valid, T_1308) + io.out[3].valid <= T_1309 + io.out[3].bits <- arb.io.out.bits + + module LockingRRArbiter_3 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1100 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1102 : UInt, clk - node T_1104 = neq(T_1100, UInt<1>("h00")) @[Arbiter.scala 39:34] - wire T_1112 : UInt<3>[1] @[Definitions.scala 853:34] - T_1112 is invalid @[Definitions.scala 853:34] - T_1112[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1114 = eq(io.out.bits.payload.g_type, T_1112[0]) @[Package.scala 7:47] - node T_1115 = eq(io.out.bits.payload.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1116 = mux(io.out.bits.payload.is_builtin_type, T_1114, T_1115) @[Definitions.scala 274:33] - node T_1117 = and(UInt<1>("h01"), T_1116) @[Definitions.scala 274:27] - node T_1118 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1119 = and(T_1118, T_1117) @[Arbiter.scala 42:25] - when T_1119 : @[Arbiter.scala 42:39] - T_1102 <= io.chosen @[Arbiter.scala 43:15] - node T_1121 = eq(T_1100, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1123 = add(T_1100, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1124 = tail(T_1123, 1) @[Counter.scala 21:22] - T_1100 <= T_1124 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1104 : @[Arbiter.scala 47:19] - io.chosen <= T_1102 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1126 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_1126 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_1131 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1132 = or(T_1131, validMask_2) @[Arbiter.scala 23:72] - node T_1133 = or(T_1132, validMask_3) @[Arbiter.scala 23:72] - node T_1134 = or(T_1133, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1135 = or(T_1134, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1136 = or(T_1135, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1138 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1140 = eq(T_1131, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1142 = eq(T_1132, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1144 = eq(T_1133, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1146 = eq(T_1134, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1148 = eq(T_1135, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1150 = eq(T_1136, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1151 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1152 = or(T_1151, T_1144) @[Arbiter.scala 64:50] - node T_1153 = and(T_1138, grantMask_1) @[Arbiter.scala 64:34] - node T_1154 = or(T_1153, T_1146) @[Arbiter.scala 64:50] - node T_1155 = and(T_1140, grantMask_2) @[Arbiter.scala 64:34] - node T_1156 = or(T_1155, T_1148) @[Arbiter.scala 64:50] - node T_1157 = and(T_1142, grantMask_3) @[Arbiter.scala 64:34] - node T_1158 = or(T_1157, T_1150) @[Arbiter.scala 64:50] - node T_1160 = eq(T_1102, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1161 = mux(T_1104, T_1160, T_1152) @[Arbiter.scala 49:22] - node T_1162 = and(T_1161, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1162 @[Arbiter.scala 49:16] - node T_1164 = eq(T_1102, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1165 = mux(T_1104, T_1164, T_1154) @[Arbiter.scala 49:22] - node T_1166 = and(T_1165, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1166 @[Arbiter.scala 49:16] - node T_1168 = eq(T_1102, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1169 = mux(T_1104, T_1168, T_1156) @[Arbiter.scala 49:22] - node T_1170 = and(T_1169, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1170 @[Arbiter.scala 49:16] - node T_1172 = eq(T_1102, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1173 = mux(T_1104, T_1172, T_1158) @[Arbiter.scala 49:22] - node T_1174 = and(T_1173, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1174 @[Arbiter.scala 49:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module BasicBus_3 : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1100 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1102 : UInt, clk with : + reset => (UInt<1>("h0"), T_1102) + node T_1104 = neq(T_1100, UInt<1>("h0")) + wire T_1112 : UInt<3>[1] + T_1112 is invalid + T_1112[0] <= UInt<3>("h5") + node T_1114 = eq(io.out.bits.payload.g_type, T_1112[0]) + node T_1115 = eq(io.out.bits.payload.g_type, UInt<1>("h0")) + node T_1116 = mux(io.out.bits.payload.is_builtin_type, T_1114, T_1115) + node T_1117 = and(UInt<1>("h1"), T_1116) + node T_1118 = and(io.out.ready, io.out.valid) + node T_1119 = and(T_1118, T_1117) + when T_1119 : + T_1102 <= io.chosen + node T_1121 = eq(T_1100, UInt<3>("h7")) + node T_1123 = add(T_1100, UInt<1>("h1")) + node T_1124 = tail(T_1123, 1) + T_1100 <= T_1124 + when T_1104 : + io.chosen <= T_1102 + node T_1126 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1126 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_1131 = or(validMask_0, validMask_1) + node T_1132 = or(T_1131, validMask_2) + node T_1133 = or(T_1132, validMask_3) + node T_1134 = or(T_1133, io.in[0].valid) + node T_1135 = or(T_1134, io.in[1].valid) + node T_1136 = or(T_1135, io.in[2].valid) + node T_1138 = eq(validMask_0, UInt<1>("h0")) + node T_1140 = eq(T_1131, UInt<1>("h0")) + node T_1142 = eq(T_1132, UInt<1>("h0")) + node T_1144 = eq(T_1133, UInt<1>("h0")) + node T_1146 = eq(T_1134, UInt<1>("h0")) + node T_1148 = eq(T_1135, UInt<1>("h0")) + node T_1150 = eq(T_1136, UInt<1>("h0")) + node T_1151 = and(UInt<1>("h1"), grantMask_0) + node T_1152 = or(T_1151, T_1144) + node T_1153 = and(T_1138, grantMask_1) + node T_1154 = or(T_1153, T_1146) + node T_1155 = and(T_1140, grantMask_2) + node T_1156 = or(T_1155, T_1148) + node T_1157 = and(T_1142, grantMask_3) + node T_1158 = or(T_1157, T_1150) + node T_1160 = eq(T_1102, UInt<1>("h0")) + node T_1161 = mux(T_1104, T_1160, T_1152) + node T_1162 = and(T_1161, io.out.ready) + io.in[0].ready <= T_1162 + node T_1164 = eq(T_1102, UInt<1>("h1")) + node T_1165 = mux(T_1104, T_1164, T_1154) + node T_1166 = and(T_1165, io.out.ready) + io.in[1].ready <= T_1166 + node T_1168 = eq(T_1102, UInt<2>("h2")) + node T_1169 = mux(T_1104, T_1168, T_1156) + node T_1170 = and(T_1169, io.out.ready) + io.in[2].ready <= T_1170 + node T_1172 = eq(T_1102, UInt<2>("h3")) + node T_1173 = mux(T_1104, T_1172, T_1158) + node T_1174 = and(T_1173, io.out.ready) + io.in[3].ready <= T_1174 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module BasicBus_3 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} + io is invalid - inst arb of LockingRRArbiter_3 @[Network.scala 37:19] + inst arb of LockingRRArbiter_3 arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in <= io.in @[Network.scala 38:13] - arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready @[Network.scala 40:20] - node T_1483 = eq(arb.io.out.bits.header.dst, UInt<1>("h00")) @[Network.scala 42:65] - node T_1484 = and(arb.io.out.valid, T_1483) @[Network.scala 42:35] - io.out[0].valid <= T_1484 @[Network.scala 42:15] - io.out[0].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1486 = eq(arb.io.out.bits.header.dst, UInt<1>("h01")) @[Network.scala 42:65] - node T_1487 = and(arb.io.out.valid, T_1486) @[Network.scala 42:35] - io.out[1].valid <= T_1487 @[Network.scala 42:15] - io.out[1].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1489 = eq(arb.io.out.bits.header.dst, UInt<2>("h02")) @[Network.scala 42:65] - node T_1490 = and(arb.io.out.valid, T_1489) @[Network.scala 42:35] - io.out[2].valid <= T_1490 @[Network.scala 42:15] - io.out[2].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1492 = eq(arb.io.out.bits.header.dst, UInt<2>("h03")) @[Network.scala 42:65] - node T_1493 = and(arb.io.out.valid, T_1492) @[Network.scala 42:35] - io.out[3].valid <= T_1493 @[Network.scala 42:15] - io.out[3].bits <- arb.io.out.bits @[Network.scala 43:14] - - module LockingRRArbiter_4 : + arb.io.in <= io.in + arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready + node T_1483 = eq(arb.io.out.bits.header.dst, UInt<1>("h0")) + node T_1484 = and(arb.io.out.valid, T_1483) + io.out[0].valid <= T_1484 + io.out[0].bits <- arb.io.out.bits + node T_1486 = eq(arb.io.out.bits.header.dst, UInt<1>("h1")) + node T_1487 = and(arb.io.out.valid, T_1486) + io.out[1].valid <= T_1487 + io.out[1].bits <- arb.io.out.bits + node T_1489 = eq(arb.io.out.bits.header.dst, UInt<2>("h2")) + node T_1490 = and(arb.io.out.valid, T_1489) + io.out[2].valid <= T_1490 + io.out[2].bits <- arb.io.out.bits + node T_1492 = eq(arb.io.out.bits.header.dst, UInt<2>("h3")) + node T_1493 = and(arb.io.out.valid, T_1492) + io.out[3].valid <= T_1493 + io.out[3].bits <- arb.io.out.bits + + module LockingRRArbiter_4 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - node T_930 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_930 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_935 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_936 = or(T_935, validMask_2) @[Arbiter.scala 23:72] - node T_937 = or(T_936, validMask_3) @[Arbiter.scala 23:72] - node T_938 = or(T_937, io.in[0].valid) @[Arbiter.scala 23:72] - node T_939 = or(T_938, io.in[1].valid) @[Arbiter.scala 23:72] - node T_940 = or(T_939, io.in[2].valid) @[Arbiter.scala 23:72] - node T_942 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_944 = eq(T_935, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_946 = eq(T_936, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_948 = eq(T_937, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_950 = eq(T_938, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_952 = eq(T_939, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_954 = eq(T_940, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_955 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_956 = or(T_955, T_948) @[Arbiter.scala 64:50] - node T_957 = and(T_942, grantMask_1) @[Arbiter.scala 64:34] - node T_958 = or(T_957, T_950) @[Arbiter.scala 64:50] - node T_959 = and(T_944, grantMask_2) @[Arbiter.scala 64:34] - node T_960 = or(T_959, T_952) @[Arbiter.scala 64:50] - node T_961 = and(T_946, grantMask_3) @[Arbiter.scala 64:34] - node T_962 = or(T_961, T_954) @[Arbiter.scala 64:50] - node T_963 = and(T_956, io.out.ready) @[Arbiter.scala 52:21] - io.in[0].ready <= T_963 @[Arbiter.scala 52:16] - node T_964 = and(T_958, io.out.ready) @[Arbiter.scala 52:21] - io.in[1].ready <= T_964 @[Arbiter.scala 52:16] - node T_965 = and(T_960, io.out.ready) @[Arbiter.scala 52:21] - io.in[2].ready <= T_965 @[Arbiter.scala 52:16] - node T_966 = and(T_962, io.out.ready) @[Arbiter.scala 52:21] - io.in[3].ready <= T_966 @[Arbiter.scala 52:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module BasicBus_4 : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + node T_930 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_930 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_935 = or(validMask_0, validMask_1) + node T_936 = or(T_935, validMask_2) + node T_937 = or(T_936, validMask_3) + node T_938 = or(T_937, io.in[0].valid) + node T_939 = or(T_938, io.in[1].valid) + node T_940 = or(T_939, io.in[2].valid) + node T_942 = eq(validMask_0, UInt<1>("h0")) + node T_944 = eq(T_935, UInt<1>("h0")) + node T_946 = eq(T_936, UInt<1>("h0")) + node T_948 = eq(T_937, UInt<1>("h0")) + node T_950 = eq(T_938, UInt<1>("h0")) + node T_952 = eq(T_939, UInt<1>("h0")) + node T_954 = eq(T_940, UInt<1>("h0")) + node T_955 = and(UInt<1>("h1"), grantMask_0) + node T_956 = or(T_955, T_948) + node T_957 = and(T_942, grantMask_1) + node T_958 = or(T_957, T_950) + node T_959 = and(T_944, grantMask_2) + node T_960 = or(T_959, T_952) + node T_961 = and(T_946, grantMask_3) + node T_962 = or(T_961, T_954) + node T_963 = and(T_956, io.out.ready) + io.in[0].ready <= T_963 + node T_964 = and(T_958, io.out.ready) + io.in[1].ready <= T_964 + node T_965 = and(T_960, io.out.ready) + io.in[2].ready <= T_965 + node T_966 = and(T_962, io.out.ready) + io.in[3].ready <= T_966 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module BasicBus_4 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[4]} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}}[4]} + io is invalid - inst arb of LockingRRArbiter_4 @[Network.scala 37:19] + inst arb of LockingRRArbiter_4 arb.io is invalid arb.clk <= clk arb.reset <= reset - arb.io.in <= io.in @[Network.scala 38:13] - arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready @[Network.scala 40:20] - node T_1253 = eq(arb.io.out.bits.header.dst, UInt<1>("h00")) @[Network.scala 42:65] - node T_1254 = and(arb.io.out.valid, T_1253) @[Network.scala 42:35] - io.out[0].valid <= T_1254 @[Network.scala 42:15] - io.out[0].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1256 = eq(arb.io.out.bits.header.dst, UInt<1>("h01")) @[Network.scala 42:65] - node T_1257 = and(arb.io.out.valid, T_1256) @[Network.scala 42:35] - io.out[1].valid <= T_1257 @[Network.scala 42:15] - io.out[1].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1259 = eq(arb.io.out.bits.header.dst, UInt<2>("h02")) @[Network.scala 42:65] - node T_1260 = and(arb.io.out.valid, T_1259) @[Network.scala 42:35] - io.out[2].valid <= T_1260 @[Network.scala 42:15] - io.out[2].bits <- arb.io.out.bits @[Network.scala 43:14] - node T_1262 = eq(arb.io.out.bits.header.dst, UInt<2>("h03")) @[Network.scala 42:65] - node T_1263 = and(arb.io.out.valid, T_1262) @[Network.scala 42:35] - io.out[3].valid <= T_1263 @[Network.scala 42:15] - io.out[3].bits <- arb.io.out.bits @[Network.scala 43:14] - - module PortedTileLinkCrossbar : + arb.io.in <= io.in + arb.io.out.ready <= io.out[arb.io.out.bits.header.dst].ready + node T_1253 = eq(arb.io.out.bits.header.dst, UInt<1>("h0")) + node T_1254 = and(arb.io.out.valid, T_1253) + io.out[0].valid <= T_1254 + io.out[0].bits <- arb.io.out.bits + node T_1256 = eq(arb.io.out.bits.header.dst, UInt<1>("h1")) + node T_1257 = and(arb.io.out.valid, T_1256) + io.out[1].valid <= T_1257 + io.out[1].bits <- arb.io.out.bits + node T_1259 = eq(arb.io.out.bits.header.dst, UInt<2>("h2")) + node T_1260 = and(arb.io.out.valid, T_1259) + io.out[2].valid <= T_1260 + io.out[2].bits <- arb.io.out.bits + node T_1262 = eq(arb.io.out.bits.header.dst, UInt<2>("h3")) + node T_1263 = and(arb.io.out.valid, T_1262) + io.out[3].valid <= T_1263 + io.out[3].bits <- arb.io.out.bits + + module PortedTileLinkCrossbar : input clk : Clock input reset : UInt<1> - output io : {flip clients_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>, manager_id : UInt<1>}}}[1], flip clients_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}[2]} - + output io : { flip clients_cached : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>, manager_id : UInt<1>}}}[1], flip clients_uncached : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], flip managers : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}[2]} + io is invalid - inst TileLinkEnqueuer_4 of TileLinkEnqueuer @[Interconnect.scala 46:22] + inst TileLinkEnqueuer_4 of TileLinkEnqueuer TileLinkEnqueuer_4.io is invalid TileLinkEnqueuer_4.clk <= clk TileLinkEnqueuer_4.reset <= reset - inst ClientTileLinkNetworkPort_1 of ClientTileLinkNetworkPort @[Interconnect.scala 49:28] + inst ClientTileLinkNetworkPort_1 of ClientTileLinkNetworkPort ClientTileLinkNetworkPort_1.io is invalid ClientTileLinkNetworkPort_1.clk <= clk ClientTileLinkNetworkPort_1.reset <= reset - ClientTileLinkNetworkPort_1.io.client <- io.clients_cached[0] @[Interconnect.scala 50:26] - TileLinkEnqueuer_4.io.client <- ClientTileLinkNetworkPort_1.io.network @[Interconnect.scala 51:24] - inst TileLinkEnqueuer_1_1 of TileLinkEnqueuer_1 @[Interconnect.scala 46:22] + ClientTileLinkNetworkPort_1.io.client <- io.clients_cached[0] + TileLinkEnqueuer_4.io.client <- ClientTileLinkNetworkPort_1.io.network + inst TileLinkEnqueuer_1_1 of TileLinkEnqueuer_1 TileLinkEnqueuer_1_1.io is invalid TileLinkEnqueuer_1_1.clk <= clk TileLinkEnqueuer_1_1.reset <= reset - inst ClientUncachedTileLinkNetworkPort_1 of ClientUncachedTileLinkNetworkPort @[Interconnect.scala 55:28] + inst ClientUncachedTileLinkNetworkPort_1 of ClientUncachedTileLinkNetworkPort ClientUncachedTileLinkNetworkPort_1.io is invalid ClientUncachedTileLinkNetworkPort_1.clk <= clk ClientUncachedTileLinkNetworkPort_1.reset <= reset - ClientUncachedTileLinkNetworkPort_1.io.client <- io.clients_uncached[0] @[Interconnect.scala 56:26] - TileLinkEnqueuer_1_1.io.client <- ClientUncachedTileLinkNetworkPort_1.io.network @[Interconnect.scala 57:24] - inst ManagerTileLinkNetworkPort_2 of ManagerTileLinkNetworkPort @[Interconnect.scala 66:24] + ClientUncachedTileLinkNetworkPort_1.io.client <- io.clients_uncached[0] + TileLinkEnqueuer_1_1.io.client <- ClientUncachedTileLinkNetworkPort_1.io.network + inst ManagerTileLinkNetworkPort_2 of ManagerTileLinkNetworkPort ManagerTileLinkNetworkPort_2.io is invalid ManagerTileLinkNetworkPort_2.clk <= clk ManagerTileLinkNetworkPort_2.reset <= reset - inst TileLinkEnqueuer_2_1 of TileLinkEnqueuer_2 @[Interconnect.scala 67:22] + inst TileLinkEnqueuer_2_1 of TileLinkEnqueuer_2 TileLinkEnqueuer_2_1.io is invalid TileLinkEnqueuer_2_1.clk <= clk TileLinkEnqueuer_2_1.reset <= reset - ManagerTileLinkNetworkPort_2.io.manager <- io.managers[0] @[Interconnect.scala 68:23] - ManagerTileLinkNetworkPort_2.io.network <- TileLinkEnqueuer_2_1.io.manager @[Interconnect.scala 69:23] - inst ManagerTileLinkNetworkPort_1_1 of ManagerTileLinkNetworkPort_1 @[Interconnect.scala 66:24] + ManagerTileLinkNetworkPort_2.io.manager <- io.managers[0] + ManagerTileLinkNetworkPort_2.io.network <- TileLinkEnqueuer_2_1.io.manager + inst ManagerTileLinkNetworkPort_1_1 of ManagerTileLinkNetworkPort_1 ManagerTileLinkNetworkPort_1_1.io is invalid ManagerTileLinkNetworkPort_1_1.clk <= clk ManagerTileLinkNetworkPort_1_1.reset <= reset - inst TileLinkEnqueuer_3_1 of TileLinkEnqueuer_2 @[Interconnect.scala 67:22] + inst TileLinkEnqueuer_3_1 of TileLinkEnqueuer_2 TileLinkEnqueuer_3_1.io is invalid TileLinkEnqueuer_3_1.clk <= clk TileLinkEnqueuer_3_1.reset <= reset - ManagerTileLinkNetworkPort_1_1.io.manager <- io.managers[1] @[Interconnect.scala 68:23] - ManagerTileLinkNetworkPort_1_1.io.network <- TileLinkEnqueuer_3_1.io.manager @[Interconnect.scala 69:23] - inst acqNet of BasicBus @[Interconnect.scala 114:22] + ManagerTileLinkNetworkPort_1_1.io.manager <- io.managers[1] + ManagerTileLinkNetworkPort_1_1.io.network <- TileLinkEnqueuer_3_1.io.manager + inst acqNet of BasicBus acqNet.io is invalid acqNet.clk <= clk acqNet.reset <= reset - inst relNet of BasicBus_1 @[Interconnect.scala 115:22] + inst relNet of BasicBus_1 relNet.io is invalid relNet.clk <= clk relNet.reset <= reset - inst prbNet of BasicBus_2 @[Interconnect.scala 116:22] + inst prbNet of BasicBus_2 prbNet.io is invalid prbNet.clk <= clk prbNet.reset <= reset - inst gntNet of BasicBus_3 @[Interconnect.scala 117:22] + inst gntNet of BasicBus_3 gntNet.io is invalid gntNet.clk <= clk gntNet.reset <= reset - inst ackNet of BasicBus_4 @[Interconnect.scala 118:22] + inst ackNet of BasicBus_4 ackNet.io is invalid ackNet.clk <= clk ackNet.reset <= reset - wire T_12724 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 105:19] - T_12724 is invalid @[Network.scala 105:19] - T_12724.bits.header <- acqNet.io.out[0].bits.header @[Network.scala 106:21] - T_12724.bits.payload <- acqNet.io.out[0].bits.payload @[Network.scala 107:22] - T_12724.valid <= acqNet.io.out[0].valid @[Network.scala 108:15] - acqNet.io.out[0].ready <= T_12724.ready @[Network.scala 109:14] - node T_12952 = sub(acqNet.io.out[0].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_12953 = tail(T_12952, 1) @[Interconnect.scala 129:47] - T_12724.bits.header.src <= T_12953 @[Interconnect.scala 129:25] - TileLinkEnqueuer_2_1.io.client.acquire.valid <= T_12724.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_2_1.io.client.acquire.bits <- T_12724.bits @[Interconnect.scala 161:17] - T_12724.ready <= TileLinkEnqueuer_2_1.io.client.acquire.ready @[Interconnect.scala 162:13] - acqNet.io.in[0].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_13294 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 105:19] - T_13294 is invalid @[Network.scala 105:19] - T_13294.bits.header <- acqNet.io.out[1].bits.header @[Network.scala 106:21] - T_13294.bits.payload <- acqNet.io.out[1].bits.payload @[Network.scala 107:22] - T_13294.valid <= acqNet.io.out[1].valid @[Network.scala 108:15] - acqNet.io.out[1].ready <= T_13294.ready @[Network.scala 109:14] - node T_13522 = sub(acqNet.io.out[1].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_13523 = tail(T_13522, 1) @[Interconnect.scala 129:47] - T_13294.bits.header.src <= T_13523 @[Interconnect.scala 129:25] - TileLinkEnqueuer_3_1.io.client.acquire.valid <= T_13294.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_3_1.io.client.acquire.bits <- T_13294.bits @[Interconnect.scala 161:17] - T_13294.ready <= TileLinkEnqueuer_3_1.io.client.acquire.ready @[Interconnect.scala 162:13] - acqNet.io.in[1].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_13624 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 117:19] - T_13624 is invalid @[Network.scala 117:19] - T_13624.bits.header <- TileLinkEnqueuer_4.io.manager.acquire.bits.header @[Network.scala 118:21] - T_13624.bits.payload <- TileLinkEnqueuer_4.io.manager.acquire.bits.payload @[Network.scala 119:22] - T_13624.valid <= TileLinkEnqueuer_4.io.manager.acquire.valid @[Network.scala 120:15] - TileLinkEnqueuer_4.io.manager.acquire.ready <= T_13624.ready @[Network.scala 121:14] - node T_13692 = add(TileLinkEnqueuer_4.io.manager.acquire.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_13693 = tail(T_13692, 1) @[Interconnect.scala 144:47] - T_13624.bits.header.src <= T_13693 @[Interconnect.scala 144:25] - acqNet.io.in[2].valid <= T_13624.valid @[Interconnect.scala 152:19] - acqNet.io.in[2].bits <- T_13624.bits @[Interconnect.scala 153:18] - T_13624.ready <= acqNet.io.in[2].ready @[Interconnect.scala 154:13] - acqNet.io.out[2].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_13794 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} @[Network.scala 117:19] - T_13794 is invalid @[Network.scala 117:19] - T_13794.bits.header <- TileLinkEnqueuer_1_1.io.manager.acquire.bits.header @[Network.scala 118:21] - T_13794.bits.payload <- TileLinkEnqueuer_1_1.io.manager.acquire.bits.payload @[Network.scala 119:22] - T_13794.valid <= TileLinkEnqueuer_1_1.io.manager.acquire.valid @[Network.scala 120:15] - TileLinkEnqueuer_1_1.io.manager.acquire.ready <= T_13794.ready @[Network.scala 121:14] - node T_13862 = add(TileLinkEnqueuer_1_1.io.manager.acquire.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_13863 = tail(T_13862, 1) @[Interconnect.scala 144:47] - T_13794.bits.header.src <= T_13863 @[Interconnect.scala 144:25] - acqNet.io.in[3].valid <= T_13794.valid @[Interconnect.scala 152:19] - acqNet.io.in[3].bits <- T_13794.bits @[Interconnect.scala 153:18] - T_13794.ready <= acqNet.io.in[3].ready @[Interconnect.scala 154:13] - acqNet.io.out[3].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_14201 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} @[Network.scala 105:19] - T_14201 is invalid @[Network.scala 105:19] - T_14201.bits.header <- relNet.io.out[0].bits.header @[Network.scala 106:21] - T_14201.bits.payload <- relNet.io.out[0].bits.payload @[Network.scala 107:22] - T_14201.valid <= relNet.io.out[0].valid @[Network.scala 108:15] - relNet.io.out[0].ready <= T_14201.ready @[Network.scala 109:14] - node T_14427 = sub(relNet.io.out[0].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_14428 = tail(T_14427, 1) @[Interconnect.scala 129:47] - T_14201.bits.header.src <= T_14428 @[Interconnect.scala 129:25] - TileLinkEnqueuer_2_1.io.client.release.valid <= T_14201.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_2_1.io.client.release.bits <- T_14201.bits @[Interconnect.scala 161:17] - T_14201.ready <= TileLinkEnqueuer_2_1.io.client.release.ready @[Interconnect.scala 162:13] - relNet.io.in[0].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_14766 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} @[Network.scala 105:19] - T_14766 is invalid @[Network.scala 105:19] - T_14766.bits.header <- relNet.io.out[1].bits.header @[Network.scala 106:21] - T_14766.bits.payload <- relNet.io.out[1].bits.payload @[Network.scala 107:22] - T_14766.valid <= relNet.io.out[1].valid @[Network.scala 108:15] - relNet.io.out[1].ready <= T_14766.ready @[Network.scala 109:14] - node T_14992 = sub(relNet.io.out[1].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_14993 = tail(T_14992, 1) @[Interconnect.scala 129:47] - T_14766.bits.header.src <= T_14993 @[Interconnect.scala 129:25] - TileLinkEnqueuer_3_1.io.client.release.valid <= T_14766.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_3_1.io.client.release.bits <- T_14766.bits @[Interconnect.scala 161:17] - T_14766.ready <= TileLinkEnqueuer_3_1.io.client.release.ready @[Interconnect.scala 162:13] - relNet.io.in[1].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_15091 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} @[Network.scala 117:19] - T_15091 is invalid @[Network.scala 117:19] - T_15091.bits.header <- TileLinkEnqueuer_4.io.manager.release.bits.header @[Network.scala 118:21] - T_15091.bits.payload <- TileLinkEnqueuer_4.io.manager.release.bits.payload @[Network.scala 119:22] - T_15091.valid <= TileLinkEnqueuer_4.io.manager.release.valid @[Network.scala 120:15] - TileLinkEnqueuer_4.io.manager.release.ready <= T_15091.ready @[Network.scala 121:14] - node T_15157 = add(TileLinkEnqueuer_4.io.manager.release.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_15158 = tail(T_15157, 1) @[Interconnect.scala 144:47] - T_15091.bits.header.src <= T_15158 @[Interconnect.scala 144:25] - relNet.io.in[2].valid <= T_15091.valid @[Interconnect.scala 152:19] - relNet.io.in[2].bits <- T_15091.bits @[Interconnect.scala 153:18] - T_15091.ready <= relNet.io.in[2].ready @[Interconnect.scala 154:13] - relNet.io.out[2].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_15256 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} @[Network.scala 117:19] - T_15256 is invalid @[Network.scala 117:19] - T_15256.bits.header <- TileLinkEnqueuer_1_1.io.manager.release.bits.header @[Network.scala 118:21] - T_15256.bits.payload <- TileLinkEnqueuer_1_1.io.manager.release.bits.payload @[Network.scala 119:22] - T_15256.valid <= TileLinkEnqueuer_1_1.io.manager.release.valid @[Network.scala 120:15] - TileLinkEnqueuer_1_1.io.manager.release.ready <= T_15256.ready @[Network.scala 121:14] - node T_15322 = add(TileLinkEnqueuer_1_1.io.manager.release.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_15323 = tail(T_15322, 1) @[Interconnect.scala 144:47] - T_15256.bits.header.src <= T_15323 @[Interconnect.scala 144:25] - relNet.io.in[3].valid <= T_15256.valid @[Interconnect.scala 152:19] - relNet.io.in[3].bits <- T_15256.bits @[Interconnect.scala 153:18] - T_15256.ready <= relNet.io.in[3].ready @[Interconnect.scala 154:13] - relNet.io.out[3].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_15409 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} @[Network.scala 117:19] - T_15409 is invalid @[Network.scala 117:19] - T_15409.bits.header <- TileLinkEnqueuer_2_1.io.client.probe.bits.header @[Network.scala 118:21] - T_15409.bits.payload <- TileLinkEnqueuer_2_1.io.client.probe.bits.payload @[Network.scala 119:22] - T_15409.valid <= TileLinkEnqueuer_2_1.io.client.probe.valid @[Network.scala 120:15] - TileLinkEnqueuer_2_1.io.client.probe.ready <= T_15409.ready @[Network.scala 121:14] - node T_15467 = add(TileLinkEnqueuer_2_1.io.client.probe.bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 139:47] - node T_15468 = tail(T_15467, 1) @[Interconnect.scala 139:47] - T_15409.bits.header.dst <= T_15468 @[Interconnect.scala 139:25] - prbNet.io.in[0].valid <= T_15409.valid @[Interconnect.scala 152:19] - prbNet.io.in[0].bits <- T_15409.bits @[Interconnect.scala 153:18] - T_15409.ready <= prbNet.io.in[0].ready @[Interconnect.scala 154:13] - prbNet.io.out[0].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_15554 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} @[Network.scala 117:19] - T_15554 is invalid @[Network.scala 117:19] - T_15554.bits.header <- TileLinkEnqueuer_3_1.io.client.probe.bits.header @[Network.scala 118:21] - T_15554.bits.payload <- TileLinkEnqueuer_3_1.io.client.probe.bits.payload @[Network.scala 119:22] - T_15554.valid <= TileLinkEnqueuer_3_1.io.client.probe.valid @[Network.scala 120:15] - TileLinkEnqueuer_3_1.io.client.probe.ready <= T_15554.ready @[Network.scala 121:14] - node T_15612 = add(TileLinkEnqueuer_3_1.io.client.probe.bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 139:47] - node T_15613 = tail(T_15612, 1) @[Interconnect.scala 139:47] - T_15554.bits.header.dst <= T_15613 @[Interconnect.scala 139:25] - prbNet.io.in[1].valid <= T_15554.valid @[Interconnect.scala 152:19] - prbNet.io.in[1].bits <- T_15554.bits @[Interconnect.scala 153:18] - T_15554.ready <= prbNet.io.in[1].ready @[Interconnect.scala 154:13] - prbNet.io.out[1].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_15939 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} @[Network.scala 105:19] - T_15939 is invalid @[Network.scala 105:19] - T_15939.bits.header <- prbNet.io.out[2].bits.header @[Network.scala 106:21] - T_15939.bits.payload <- prbNet.io.out[2].bits.payload @[Network.scala 107:22] - T_15939.valid <= prbNet.io.out[2].valid @[Network.scala 108:15] - prbNet.io.out[2].ready <= T_15939.ready @[Network.scala 109:14] - node T_16157 = sub(prbNet.io.out[2].bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 134:47] - node T_16158 = tail(T_16157, 1) @[Interconnect.scala 134:47] - T_15939.bits.header.dst <= T_16158 @[Interconnect.scala 134:25] - TileLinkEnqueuer_4.io.manager.probe.valid <= T_15939.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_4.io.manager.probe.bits <- T_15939.bits @[Interconnect.scala 161:17] - T_15939.ready <= TileLinkEnqueuer_4.io.manager.probe.ready @[Interconnect.scala 162:13] - prbNet.io.in[2].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_16484 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} @[Network.scala 105:19] - T_16484 is invalid @[Network.scala 105:19] - T_16484.bits.header <- prbNet.io.out[3].bits.header @[Network.scala 106:21] - T_16484.bits.payload <- prbNet.io.out[3].bits.payload @[Network.scala 107:22] - T_16484.valid <= prbNet.io.out[3].valid @[Network.scala 108:15] - prbNet.io.out[3].ready <= T_16484.ready @[Network.scala 109:14] - node T_16702 = sub(prbNet.io.out[3].bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 134:47] - node T_16703 = tail(T_16702, 1) @[Interconnect.scala 134:47] - T_16484.bits.header.dst <= T_16703 @[Interconnect.scala 134:25] - TileLinkEnqueuer_1_1.io.manager.probe.valid <= T_16484.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_1_1.io.manager.probe.bits <- T_16484.bits @[Interconnect.scala 161:17] - T_16484.ready <= TileLinkEnqueuer_1_1.io.manager.probe.ready @[Interconnect.scala 162:13] - prbNet.io.in[3].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_16801 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} @[Network.scala 117:19] - T_16801 is invalid @[Network.scala 117:19] - T_16801.bits.header <- TileLinkEnqueuer_2_1.io.client.grant.bits.header @[Network.scala 118:21] - T_16801.bits.payload <- TileLinkEnqueuer_2_1.io.client.grant.bits.payload @[Network.scala 119:22] - T_16801.valid <= TileLinkEnqueuer_2_1.io.client.grant.valid @[Network.scala 120:15] - TileLinkEnqueuer_2_1.io.client.grant.ready <= T_16801.ready @[Network.scala 121:14] - node T_16867 = add(TileLinkEnqueuer_2_1.io.client.grant.bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 139:47] - node T_16868 = tail(T_16867, 1) @[Interconnect.scala 139:47] - T_16801.bits.header.dst <= T_16868 @[Interconnect.scala 139:25] - gntNet.io.in[0].valid <= T_16801.valid @[Interconnect.scala 152:19] - gntNet.io.in[0].bits <- T_16801.bits @[Interconnect.scala 153:18] - T_16801.ready <= gntNet.io.in[0].ready @[Interconnect.scala 154:13] - gntNet.io.out[0].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_16966 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} @[Network.scala 117:19] - T_16966 is invalid @[Network.scala 117:19] - T_16966.bits.header <- TileLinkEnqueuer_3_1.io.client.grant.bits.header @[Network.scala 118:21] - T_16966.bits.payload <- TileLinkEnqueuer_3_1.io.client.grant.bits.payload @[Network.scala 119:22] - T_16966.valid <= TileLinkEnqueuer_3_1.io.client.grant.valid @[Network.scala 120:15] - TileLinkEnqueuer_3_1.io.client.grant.ready <= T_16966.ready @[Network.scala 121:14] - node T_17032 = add(TileLinkEnqueuer_3_1.io.client.grant.bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 139:47] - node T_17033 = tail(T_17032, 1) @[Interconnect.scala 139:47] - T_16966.bits.header.dst <= T_17033 @[Interconnect.scala 139:25] - gntNet.io.in[1].valid <= T_16966.valid @[Interconnect.scala 152:19] - gntNet.io.in[1].bits <- T_16966.bits @[Interconnect.scala 153:18] - T_16966.ready <= gntNet.io.in[1].ready @[Interconnect.scala 154:13] - gntNet.io.out[1].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_17371 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} @[Network.scala 105:19] - T_17371 is invalid @[Network.scala 105:19] - T_17371.bits.header <- gntNet.io.out[2].bits.header @[Network.scala 106:21] - T_17371.bits.payload <- gntNet.io.out[2].bits.payload @[Network.scala 107:22] - T_17371.valid <= gntNet.io.out[2].valid @[Network.scala 108:15] - gntNet.io.out[2].ready <= T_17371.ready @[Network.scala 109:14] - node T_17597 = sub(gntNet.io.out[2].bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 134:47] - node T_17598 = tail(T_17597, 1) @[Interconnect.scala 134:47] - T_17371.bits.header.dst <= T_17598 @[Interconnect.scala 134:25] - TileLinkEnqueuer_4.io.manager.grant.valid <= T_17371.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_4.io.manager.grant.bits <- T_17371.bits @[Interconnect.scala 161:17] - T_17371.ready <= TileLinkEnqueuer_4.io.manager.grant.ready @[Interconnect.scala 162:13] - gntNet.io.in[2].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_17936 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} @[Network.scala 105:19] - T_17936 is invalid @[Network.scala 105:19] - T_17936.bits.header <- gntNet.io.out[3].bits.header @[Network.scala 106:21] - T_17936.bits.payload <- gntNet.io.out[3].bits.payload @[Network.scala 107:22] - T_17936.valid <= gntNet.io.out[3].valid @[Network.scala 108:15] - gntNet.io.out[3].ready <= T_17936.ready @[Network.scala 109:14] - node T_18162 = sub(gntNet.io.out[3].bits.header.dst, UInt<2>("h02")) @[Interconnect.scala 134:47] - node T_18163 = tail(T_18162, 1) @[Interconnect.scala 134:47] - T_17936.bits.header.dst <= T_18163 @[Interconnect.scala 134:25] - TileLinkEnqueuer_1_1.io.manager.grant.valid <= T_17936.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_1_1.io.manager.grant.bits <- T_17936.bits @[Interconnect.scala 161:17] - T_17936.ready <= TileLinkEnqueuer_1_1.io.manager.grant.ready @[Interconnect.scala 162:13] - gntNet.io.in[3].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_18486 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} @[Network.scala 105:19] - T_18486 is invalid @[Network.scala 105:19] - T_18486.bits.header <- ackNet.io.out[0].bits.header @[Network.scala 106:21] - T_18486.bits.payload <- ackNet.io.out[0].bits.payload @[Network.scala 107:22] - T_18486.valid <= ackNet.io.out[0].valid @[Network.scala 108:15] - ackNet.io.out[0].ready <= T_18486.ready @[Network.scala 109:14] - node T_18702 = sub(ackNet.io.out[0].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_18703 = tail(T_18702, 1) @[Interconnect.scala 129:47] - T_18486.bits.header.src <= T_18703 @[Interconnect.scala 129:25] - TileLinkEnqueuer_2_1.io.client.finish.valid <= T_18486.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_2_1.io.client.finish.bits <- T_18486.bits @[Interconnect.scala 161:17] - T_18486.ready <= TileLinkEnqueuer_2_1.io.client.finish.ready @[Interconnect.scala 162:13] - ackNet.io.in[0].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_19026 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} @[Network.scala 105:19] - T_19026 is invalid @[Network.scala 105:19] - T_19026.bits.header <- ackNet.io.out[1].bits.header @[Network.scala 106:21] - T_19026.bits.payload <- ackNet.io.out[1].bits.payload @[Network.scala 107:22] - T_19026.valid <= ackNet.io.out[1].valid @[Network.scala 108:15] - ackNet.io.out[1].ready <= T_19026.ready @[Network.scala 109:14] - node T_19242 = sub(ackNet.io.out[1].bits.header.src, UInt<2>("h02")) @[Interconnect.scala 129:47] - node T_19243 = tail(T_19242, 1) @[Interconnect.scala 129:47] - T_19026.bits.header.src <= T_19243 @[Interconnect.scala 129:25] - TileLinkEnqueuer_3_1.io.client.finish.valid <= T_19026.valid @[Interconnect.scala 160:18] - TileLinkEnqueuer_3_1.io.client.finish.bits <- T_19026.bits @[Interconnect.scala 161:17] - T_19026.ready <= TileLinkEnqueuer_3_1.io.client.finish.ready @[Interconnect.scala 162:13] - ackNet.io.in[1].valid <= UInt<1>("h00") @[Interconnect.scala 163:19] - wire T_19326 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} @[Network.scala 117:19] - T_19326 is invalid @[Network.scala 117:19] - T_19326.bits.header <- TileLinkEnqueuer_4.io.manager.finish.bits.header @[Network.scala 118:21] - T_19326.bits.payload <- TileLinkEnqueuer_4.io.manager.finish.bits.payload @[Network.scala 119:22] - T_19326.valid <= TileLinkEnqueuer_4.io.manager.finish.valid @[Network.scala 120:15] - TileLinkEnqueuer_4.io.manager.finish.ready <= T_19326.ready @[Network.scala 121:14] - node T_19382 = add(TileLinkEnqueuer_4.io.manager.finish.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_19383 = tail(T_19382, 1) @[Interconnect.scala 144:47] - T_19326.bits.header.src <= T_19383 @[Interconnect.scala 144:25] - ackNet.io.in[2].valid <= T_19326.valid @[Interconnect.scala 152:19] - ackNet.io.in[2].bits <- T_19326.bits @[Interconnect.scala 153:18] - T_19326.ready <= ackNet.io.in[2].ready @[Interconnect.scala 154:13] - ackNet.io.out[2].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - wire T_19466 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} @[Network.scala 117:19] - T_19466 is invalid @[Network.scala 117:19] - T_19466.bits.header <- TileLinkEnqueuer_1_1.io.manager.finish.bits.header @[Network.scala 118:21] - T_19466.bits.payload <- TileLinkEnqueuer_1_1.io.manager.finish.bits.payload @[Network.scala 119:22] - T_19466.valid <= TileLinkEnqueuer_1_1.io.manager.finish.valid @[Network.scala 120:15] - TileLinkEnqueuer_1_1.io.manager.finish.ready <= T_19466.ready @[Network.scala 121:14] - node T_19522 = add(TileLinkEnqueuer_1_1.io.manager.finish.bits.header.src, UInt<2>("h02")) @[Interconnect.scala 144:47] - node T_19523 = tail(T_19522, 1) @[Interconnect.scala 144:47] - T_19466.bits.header.src <= T_19523 @[Interconnect.scala 144:25] - ackNet.io.in[3].valid <= T_19466.valid @[Interconnect.scala 152:19] - ackNet.io.in[3].bits <- T_19466.bits @[Interconnect.scala 153:18] - T_19466.ready <= ackNet.io.in[3].ready @[Interconnect.scala 154:13] - ackNet.io.out[3].ready <= UInt<1>("h00") @[Interconnect.scala 155:20] - - module BufferedBroadcastVoluntaryReleaseTracker : + wire T_12724 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + T_12724 is invalid + T_12724.bits.header <- acqNet.io.out[0].bits.header + T_12724.bits.payload <- acqNet.io.out[0].bits.payload + T_12724.valid <= acqNet.io.out[0].valid + acqNet.io.out[0].ready <= T_12724.ready + node T_12952 = sub(acqNet.io.out[0].bits.header.src, UInt<2>("h2")) + node T_12953 = tail(T_12952, 1) + T_12724.bits.header.src <= T_12953 + TileLinkEnqueuer_2_1.io.client.acquire.valid <= T_12724.valid + TileLinkEnqueuer_2_1.io.client.acquire.bits <- T_12724.bits + T_12724.ready <= TileLinkEnqueuer_2_1.io.client.acquire.ready + acqNet.io.in[0].valid <= UInt<1>("h0") + wire T_13294 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + T_13294 is invalid + T_13294.bits.header <- acqNet.io.out[1].bits.header + T_13294.bits.payload <- acqNet.io.out[1].bits.payload + T_13294.valid <= acqNet.io.out[1].valid + acqNet.io.out[1].ready <= T_13294.ready + node T_13522 = sub(acqNet.io.out[1].bits.header.src, UInt<2>("h2")) + node T_13523 = tail(T_13522, 1) + T_13294.bits.header.src <= T_13523 + TileLinkEnqueuer_3_1.io.client.acquire.valid <= T_13294.valid + TileLinkEnqueuer_3_1.io.client.acquire.bits <- T_13294.bits + T_13294.ready <= TileLinkEnqueuer_3_1.io.client.acquire.ready + acqNet.io.in[1].valid <= UInt<1>("h0") + wire T_13624 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + T_13624 is invalid + T_13624.bits.header <- TileLinkEnqueuer_4.io.manager.acquire.bits.header + T_13624.bits.payload <- TileLinkEnqueuer_4.io.manager.acquire.bits.payload + T_13624.valid <= TileLinkEnqueuer_4.io.manager.acquire.valid + TileLinkEnqueuer_4.io.manager.acquire.ready <= T_13624.ready + node T_13692 = add(TileLinkEnqueuer_4.io.manager.acquire.bits.header.src, UInt<2>("h2")) + node T_13693 = tail(T_13692, 1) + T_13624.bits.header.src <= T_13693 + acqNet.io.in[2].valid <= T_13624.valid + acqNet.io.in[2].bits <- T_13624.bits + T_13624.ready <= acqNet.io.in[2].ready + acqNet.io.out[2].ready <= UInt<1>("h0") + wire T_13794 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}} + T_13794 is invalid + T_13794.bits.header <- TileLinkEnqueuer_1_1.io.manager.acquire.bits.header + T_13794.bits.payload <- TileLinkEnqueuer_1_1.io.manager.acquire.bits.payload + T_13794.valid <= TileLinkEnqueuer_1_1.io.manager.acquire.valid + TileLinkEnqueuer_1_1.io.manager.acquire.ready <= T_13794.ready + node T_13862 = add(TileLinkEnqueuer_1_1.io.manager.acquire.bits.header.src, UInt<2>("h2")) + node T_13863 = tail(T_13862, 1) + T_13794.bits.header.src <= T_13863 + acqNet.io.in[3].valid <= T_13794.valid + acqNet.io.in[3].bits <- T_13794.bits + T_13794.ready <= acqNet.io.in[3].ready + acqNet.io.out[3].ready <= UInt<1>("h0") + wire T_14201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} + T_14201 is invalid + T_14201.bits.header <- relNet.io.out[0].bits.header + T_14201.bits.payload <- relNet.io.out[0].bits.payload + T_14201.valid <= relNet.io.out[0].valid + relNet.io.out[0].ready <= T_14201.ready + node T_14427 = sub(relNet.io.out[0].bits.header.src, UInt<2>("h2")) + node T_14428 = tail(T_14427, 1) + T_14201.bits.header.src <= T_14428 + TileLinkEnqueuer_2_1.io.client.release.valid <= T_14201.valid + TileLinkEnqueuer_2_1.io.client.release.bits <- T_14201.bits + T_14201.ready <= TileLinkEnqueuer_2_1.io.client.release.ready + relNet.io.in[0].valid <= UInt<1>("h0") + wire T_14766 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} + T_14766 is invalid + T_14766.bits.header <- relNet.io.out[1].bits.header + T_14766.bits.payload <- relNet.io.out[1].bits.payload + T_14766.valid <= relNet.io.out[1].valid + relNet.io.out[1].ready <= T_14766.ready + node T_14992 = sub(relNet.io.out[1].bits.header.src, UInt<2>("h2")) + node T_14993 = tail(T_14992, 1) + T_14766.bits.header.src <= T_14993 + TileLinkEnqueuer_3_1.io.client.release.valid <= T_14766.valid + TileLinkEnqueuer_3_1.io.client.release.bits <- T_14766.bits + T_14766.ready <= TileLinkEnqueuer_3_1.io.client.release.ready + relNet.io.in[1].valid <= UInt<1>("h0") + wire T_15091 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} + T_15091 is invalid + T_15091.bits.header <- TileLinkEnqueuer_4.io.manager.release.bits.header + T_15091.bits.payload <- TileLinkEnqueuer_4.io.manager.release.bits.payload + T_15091.valid <= TileLinkEnqueuer_4.io.manager.release.valid + TileLinkEnqueuer_4.io.manager.release.ready <= T_15091.ready + node T_15157 = add(TileLinkEnqueuer_4.io.manager.release.bits.header.src, UInt<2>("h2")) + node T_15158 = tail(T_15157, 1) + T_15091.bits.header.src <= T_15158 + relNet.io.in[2].valid <= T_15091.valid + relNet.io.in[2].bits <- T_15091.bits + T_15091.ready <= relNet.io.in[2].ready + relNet.io.out[2].ready <= UInt<1>("h0") + wire T_15256 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}} + T_15256 is invalid + T_15256.bits.header <- TileLinkEnqueuer_1_1.io.manager.release.bits.header + T_15256.bits.payload <- TileLinkEnqueuer_1_1.io.manager.release.bits.payload + T_15256.valid <= TileLinkEnqueuer_1_1.io.manager.release.valid + TileLinkEnqueuer_1_1.io.manager.release.ready <= T_15256.ready + node T_15322 = add(TileLinkEnqueuer_1_1.io.manager.release.bits.header.src, UInt<2>("h2")) + node T_15323 = tail(T_15322, 1) + T_15256.bits.header.src <= T_15323 + relNet.io.in[3].valid <= T_15256.valid + relNet.io.in[3].bits <- T_15256.bits + T_15256.ready <= relNet.io.in[3].ready + relNet.io.out[3].ready <= UInt<1>("h0") + wire T_15409 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}} + T_15409 is invalid + T_15409.bits.header <- TileLinkEnqueuer_2_1.io.client.probe.bits.header + T_15409.bits.payload <- TileLinkEnqueuer_2_1.io.client.probe.bits.payload + T_15409.valid <= TileLinkEnqueuer_2_1.io.client.probe.valid + TileLinkEnqueuer_2_1.io.client.probe.ready <= T_15409.ready + node T_15467 = add(TileLinkEnqueuer_2_1.io.client.probe.bits.header.dst, UInt<2>("h2")) + node T_15468 = tail(T_15467, 1) + T_15409.bits.header.dst <= T_15468 + prbNet.io.in[0].valid <= T_15409.valid + prbNet.io.in[0].bits <- T_15409.bits + T_15409.ready <= prbNet.io.in[0].ready + prbNet.io.out[0].ready <= UInt<1>("h0") + wire T_15554 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}} + T_15554 is invalid + T_15554.bits.header <- TileLinkEnqueuer_3_1.io.client.probe.bits.header + T_15554.bits.payload <- TileLinkEnqueuer_3_1.io.client.probe.bits.payload + T_15554.valid <= TileLinkEnqueuer_3_1.io.client.probe.valid + TileLinkEnqueuer_3_1.io.client.probe.ready <= T_15554.ready + node T_15612 = add(TileLinkEnqueuer_3_1.io.client.probe.bits.header.dst, UInt<2>("h2")) + node T_15613 = tail(T_15612, 1) + T_15554.bits.header.dst <= T_15613 + prbNet.io.in[1].valid <= T_15554.valid + prbNet.io.in[1].bits <- T_15554.bits + T_15554.ready <= prbNet.io.in[1].ready + prbNet.io.out[1].ready <= UInt<1>("h0") + wire T_15939 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}} + T_15939 is invalid + T_15939.bits.header <- prbNet.io.out[2].bits.header + T_15939.bits.payload <- prbNet.io.out[2].bits.payload + T_15939.valid <= prbNet.io.out[2].valid + prbNet.io.out[2].ready <= T_15939.ready + node T_16157 = sub(prbNet.io.out[2].bits.header.dst, UInt<2>("h2")) + node T_16158 = tail(T_16157, 1) + T_15939.bits.header.dst <= T_16158 + TileLinkEnqueuer_4.io.manager.probe.valid <= T_15939.valid + TileLinkEnqueuer_4.io.manager.probe.bits <- T_15939.bits + T_15939.ready <= TileLinkEnqueuer_4.io.manager.probe.ready + prbNet.io.in[2].valid <= UInt<1>("h0") + wire T_16484 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_block : UInt<26>, p_type : UInt<2>}}} + T_16484 is invalid + T_16484.bits.header <- prbNet.io.out[3].bits.header + T_16484.bits.payload <- prbNet.io.out[3].bits.payload + T_16484.valid <= prbNet.io.out[3].valid + prbNet.io.out[3].ready <= T_16484.ready + node T_16702 = sub(prbNet.io.out[3].bits.header.dst, UInt<2>("h2")) + node T_16703 = tail(T_16702, 1) + T_16484.bits.header.dst <= T_16703 + TileLinkEnqueuer_1_1.io.manager.probe.valid <= T_16484.valid + TileLinkEnqueuer_1_1.io.manager.probe.bits <- T_16484.bits + T_16484.ready <= TileLinkEnqueuer_1_1.io.manager.probe.ready + prbNet.io.in[3].valid <= UInt<1>("h0") + wire T_16801 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} + T_16801 is invalid + T_16801.bits.header <- TileLinkEnqueuer_2_1.io.client.grant.bits.header + T_16801.bits.payload <- TileLinkEnqueuer_2_1.io.client.grant.bits.payload + T_16801.valid <= TileLinkEnqueuer_2_1.io.client.grant.valid + TileLinkEnqueuer_2_1.io.client.grant.ready <= T_16801.ready + node T_16867 = add(TileLinkEnqueuer_2_1.io.client.grant.bits.header.dst, UInt<2>("h2")) + node T_16868 = tail(T_16867, 1) + T_16801.bits.header.dst <= T_16868 + gntNet.io.in[0].valid <= T_16801.valid + gntNet.io.in[0].bits <- T_16801.bits + T_16801.ready <= gntNet.io.in[0].ready + gntNet.io.out[0].ready <= UInt<1>("h0") + wire T_16966 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} + T_16966 is invalid + T_16966.bits.header <- TileLinkEnqueuer_3_1.io.client.grant.bits.header + T_16966.bits.payload <- TileLinkEnqueuer_3_1.io.client.grant.bits.payload + T_16966.valid <= TileLinkEnqueuer_3_1.io.client.grant.valid + TileLinkEnqueuer_3_1.io.client.grant.ready <= T_16966.ready + node T_17032 = add(TileLinkEnqueuer_3_1.io.client.grant.bits.header.dst, UInt<2>("h2")) + node T_17033 = tail(T_17032, 1) + T_16966.bits.header.dst <= T_17033 + gntNet.io.in[1].valid <= T_16966.valid + gntNet.io.in[1].bits <- T_16966.bits + T_16966.ready <= gntNet.io.in[1].ready + gntNet.io.out[1].ready <= UInt<1>("h0") + wire T_17371 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} + T_17371 is invalid + T_17371.bits.header <- gntNet.io.out[2].bits.header + T_17371.bits.payload <- gntNet.io.out[2].bits.payload + T_17371.valid <= gntNet.io.out[2].valid + gntNet.io.out[2].ready <= T_17371.ready + node T_17597 = sub(gntNet.io.out[2].bits.header.dst, UInt<2>("h2")) + node T_17598 = tail(T_17597, 1) + T_17371.bits.header.dst <= T_17598 + TileLinkEnqueuer_4.io.manager.grant.valid <= T_17371.valid + TileLinkEnqueuer_4.io.manager.grant.bits <- T_17371.bits + T_17371.ready <= TileLinkEnqueuer_4.io.manager.grant.ready + gntNet.io.in[2].valid <= UInt<1>("h0") + wire T_17936 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} + T_17936 is invalid + T_17936.bits.header <- gntNet.io.out[3].bits.header + T_17936.bits.payload <- gntNet.io.out[3].bits.payload + T_17936.valid <= gntNet.io.out[3].valid + gntNet.io.out[3].ready <= T_17936.ready + node T_18162 = sub(gntNet.io.out[3].bits.header.dst, UInt<2>("h2")) + node T_18163 = tail(T_18162, 1) + T_17936.bits.header.dst <= T_18163 + TileLinkEnqueuer_1_1.io.manager.grant.valid <= T_17936.valid + TileLinkEnqueuer_1_1.io.manager.grant.bits <- T_17936.bits + T_17936.ready <= TileLinkEnqueuer_1_1.io.manager.grant.ready + gntNet.io.in[3].valid <= UInt<1>("h0") + wire T_18486 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}} + T_18486 is invalid + T_18486.bits.header <- ackNet.io.out[0].bits.header + T_18486.bits.payload <- ackNet.io.out[0].bits.payload + T_18486.valid <= ackNet.io.out[0].valid + ackNet.io.out[0].ready <= T_18486.ready + node T_18702 = sub(ackNet.io.out[0].bits.header.src, UInt<2>("h2")) + node T_18703 = tail(T_18702, 1) + T_18486.bits.header.src <= T_18703 + TileLinkEnqueuer_2_1.io.client.finish.valid <= T_18486.valid + TileLinkEnqueuer_2_1.io.client.finish.bits <- T_18486.bits + T_18486.ready <= TileLinkEnqueuer_2_1.io.client.finish.ready + ackNet.io.in[0].valid <= UInt<1>("h0") + wire T_19026 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}} + T_19026 is invalid + T_19026.bits.header <- ackNet.io.out[1].bits.header + T_19026.bits.payload <- ackNet.io.out[1].bits.payload + T_19026.valid <= ackNet.io.out[1].valid + ackNet.io.out[1].ready <= T_19026.ready + node T_19242 = sub(ackNet.io.out[1].bits.header.src, UInt<2>("h2")) + node T_19243 = tail(T_19242, 1) + T_19026.bits.header.src <= T_19243 + TileLinkEnqueuer_3_1.io.client.finish.valid <= T_19026.valid + TileLinkEnqueuer_3_1.io.client.finish.bits <- T_19026.bits + T_19026.ready <= TileLinkEnqueuer_3_1.io.client.finish.ready + ackNet.io.in[1].valid <= UInt<1>("h0") + wire T_19326 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}} + T_19326 is invalid + T_19326.bits.header <- TileLinkEnqueuer_4.io.manager.finish.bits.header + T_19326.bits.payload <- TileLinkEnqueuer_4.io.manager.finish.bits.payload + T_19326.valid <= TileLinkEnqueuer_4.io.manager.finish.valid + TileLinkEnqueuer_4.io.manager.finish.ready <= T_19326.ready + node T_19382 = add(TileLinkEnqueuer_4.io.manager.finish.bits.header.src, UInt<2>("h2")) + node T_19383 = tail(T_19382, 1) + T_19326.bits.header.src <= T_19383 + ackNet.io.in[2].valid <= T_19326.valid + ackNet.io.in[2].bits <- T_19326.bits + T_19326.ready <= ackNet.io.in[2].ready + ackNet.io.out[2].ready <= UInt<1>("h0") + wire T_19466 : { flip ready : UInt<1>, valid : UInt<1>, bits : { header : { src : UInt<2>, dst : UInt<2>}, payload : { manager_xact_id : UInt<4>}}} + T_19466 is invalid + T_19466.bits.header <- TileLinkEnqueuer_1_1.io.manager.finish.bits.header + T_19466.bits.payload <- TileLinkEnqueuer_1_1.io.manager.finish.bits.payload + T_19466.valid <= TileLinkEnqueuer_1_1.io.manager.finish.valid + TileLinkEnqueuer_1_1.io.manager.finish.ready <= T_19466.ready + node T_19522 = add(TileLinkEnqueuer_1_1.io.manager.finish.bits.header.src, UInt<2>("h2")) + node T_19523 = tail(T_19522, 1) + T_19466.bits.header.src <= T_19523 + ackNet.io.in[3].valid <= T_19466.valid + ackNet.io.in[3].bits <- T_19466.bits + T_19466.ready <= ackNet.io.in[3].ready + ackNet.io.out[3].ready <= UInt<1>("h0") + + module BufferedBroadcastVoluntaryReleaseTracker : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2005 : UInt<1> + T_2005 is invalid + wire T_1621 : UInt<1> + T_1621 is invalid + wire T_2034 : UInt<1> + T_2034 is invalid + wire T_1590 : UInt<1> + T_1590 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_78 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_79 = or(pending_orel_send, T_78) @[Trackers.scala 307:40] - node scoreboard_2 = or(T_79, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_103 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_103 is invalid @[Metadata.scala 309:20] - T_103.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_149 : {state : UInt<2>} @[Metadata.scala 158:20] - T_149 is invalid @[Metadata.scala 158:20] - T_149.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_103 @[Metadata.scala 338:13] - coh.outer <- T_149 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1519 = eq(state, UInt<4>("h00")) @[Broadcast.scala 81:18] - node T_1520 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_1521 = and(T_1519, T_1520) @[Broadcast.scala 81:29] - node T_1522 = and(T_1521, io.alloc.irel.should) @[Broadcast.scala 81:56] - node T_1524 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Broadcast.scala 81:83] - node T_1525 = and(T_1522, T_1524) @[Broadcast.scala 81:80] - node T_1527 = eq(T_1525, UInt<1>("h00")) @[Broadcast.scala 81:10] - node T_1528 = or(T_1527, reset) @[Broadcast.scala 81:9] - node T_1530 = eq(T_1528, UInt<1>("h00")) @[Broadcast.scala 81:9] - when T_1530 : @[Broadcast.scala 81:9] - printf(clk, UInt<1>(1), "Assertion failed: VoluntaryReleaseTracker accepted Release that wasn't voluntary!\n at Broadcast.scala:81 assert(!(state === s_idle && io.inner.release.fire() && io.alloc.irel.should && !io.irel().isVoluntary()),\n") @[Broadcast.scala 81:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 81:9] - skip @[Broadcast.scala 81:9] - wire T_1544 : UInt<64>[8] @[Trackers.scala 150:54] - T_1544 is invalid @[Trackers.scala 150:54] - T_1544[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1544[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1544)) - node T_1552 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1553 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1554 = and(T_1552, T_1553) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1554 @[Trackers.scala 428:27] - node T_1555 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1556 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1557 = and(T_1555, T_1556) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1557 @[Trackers.scala 429:27] - node T_1558 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1559 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1560 = and(T_1558, T_1559) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1560 @[Trackers.scala 430:27] - node T_1561 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1562 = and(T_1561, UInt<1>("h00")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1562 @[Trackers.scala 431:23] - node T_1563 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1564 = and(T_1563, UInt<1>("h01")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1564 @[Trackers.scala 432:23] - node T_1565 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1566 = and(T_1565, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1566 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1567 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1567 @[Trackers.scala 435:19] - node T_1568 = or(scoreboard_2, vol_ognt_counter.pending) @[Broadcast.scala 117:46] - node T_1570 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_1571 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_1572 = mux(T_1571, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_1573 = and(T_1572, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_1576 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_1577 = and(T_1573, T_1576) @[Trackers.scala 254:95] - node T_1578 = and(T_1570, T_1577) @[Counters.scala 123:62] - node T_1580 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1581 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1582 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1583 = or(T_1580, T_1581) @[Package.scala 7:62] - node T_1584 = or(T_1583, T_1582) @[Package.scala 7:62] - node T_1585 = and(UInt<1>("h01"), T_1584) @[Definitions.scala 256:64] - node T_1586 = and(T_1578, T_1585) @[Counters.scala 67:47] - reg T_1588 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_1586 : @[Counter.scala 43:17] - node T_1590 = eq(T_1588, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1592 = add(T_1588, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1593 = tail(T_1592, 1) @[Counter.scala 21:22] - T_1588 <= T_1593 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_1594 = and(T_1586, T_1590) @[Counter.scala 44:20] - node T_1595 = mux(T_1585, T_1588, UInt<1>("h00")) @[Counters.scala 68:18] - node T_1596 = mux(T_1585, T_1594, T_1578) @[Counters.scala 69:19] - node T_1597 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_1598 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_1600 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_1601 = and(io.inner.grant.bits.is_builtin_type, T_1600) @[Definitions.scala 277:59] - node T_1602 = and(T_1598, T_1601) @[Trackers.scala 256:52] - node T_1603 = and(T_1597, T_1602) @[Counters.scala 124:64] - wire T_1611 : UInt<3>[1] @[Definitions.scala 853:34] - T_1611 is invalid @[Definitions.scala 853:34] - T_1611[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1613 = eq(io.inner.grant.bits.g_type, T_1611[0]) @[Package.scala 7:47] - node T_1614 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1615 = mux(io.inner.grant.bits.is_builtin_type, T_1613, T_1614) @[Definitions.scala 274:33] - node T_1616 = and(UInt<1>("h01"), T_1615) @[Definitions.scala 274:27] - node T_1617 = and(T_1603, T_1616) @[Counters.scala 67:47] - reg T_1619 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_1617 : @[Counter.scala 43:17] - node T_1621 = eq(T_1619, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1623 = add(T_1619, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1624 = tail(T_1623, 1) @[Counter.scala 21:22] - T_1619 <= T_1624 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_1625 = and(T_1617, T_1621) @[Counter.scala 44:20] - node T_1626 = mux(T_1616, T_1619, UInt<1>("h00")) @[Counters.scala 68:18] - node T_1627 = mux(T_1616, T_1625, T_1603) @[Counters.scala 69:19] - reg T_1629 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1631 = eq(T_1627, UInt<1>("h00")) @[Counters.scala 33:17] - node T_1632 = and(T_1596, T_1631) @[Counters.scala 33:14] - when T_1632 : @[Counters.scala 33:24] - node T_1634 = add(T_1629, UInt<1>("h01")) @[Counters.scala 33:37] - node T_1635 = tail(T_1634, 1) @[Counters.scala 33:37] - T_1629 <= T_1635 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_1637 = eq(T_1596, UInt<1>("h00")) @[Counters.scala 34:19] - node T_1638 = and(T_1627, T_1637) @[Counters.scala 34:16] - when T_1638 : @[Counters.scala 34:24] - node T_1640 = sub(T_1629, UInt<1>("h01")) @[Counters.scala 34:37] - node T_1641 = tail(T_1640, 1) @[Counters.scala 34:37] - T_1629 <= T_1641 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_1643 = gt(T_1629, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_1643 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_1595 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_1596 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_1626 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_1627 @[Counters.scala 130:22] - node T_1644 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_1645 = and(T_1644, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_1646 = and(T_1645, io.inner.release.valid) @[Trackers.scala 245:75] - when T_1646 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_1648 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_1648 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_1649 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_1650 = and(T_1649, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_1651 = and(T_1650, io.inner.release.valid) @[Trackers.scala 245:75] - node T_1653 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1654 = and(T_1653, io.inner.release.bits.voluntary) @[Trackers.scala 644:61] - node T_1656 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 646:45] - node T_1657 = and(T_1654, T_1656) @[Trackers.scala 645:51] - node T_1658 = or(UInt<1>("h00"), T_1657) @[Trackers.scala 246:47] - node T_1659 = and(T_1658, io.inner.release.valid) @[Trackers.scala 246:66] - node T_1660 = or(T_1651, T_1659) @[Trackers.scala 268:41] - node T_1661 = and(T_1660, io.inner.release.ready) @[Trackers.scala 268:61] - when T_1661 : @[Trackers.scala 269:22] - node T_1663 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1664 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1665 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1666 = or(T_1663, T_1664) @[Package.scala 7:62] - node T_1667 = or(T_1666, T_1665) @[Package.scala 7:62] - node T_1668 = and(UInt<1>("h01"), T_1667) @[Definitions.scala 256:64] - node T_1670 = eq(T_1668, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1672 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1673 = or(T_1670, T_1672) @[Definitions.scala 141:57] - when T_1673 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_1675 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1676 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1677 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1678 = or(T_1675, T_1676) @[Package.scala 7:62] - node T_1679 = or(T_1678, T_1677) @[Package.scala 7:62] - node T_1680 = and(UInt<1>("h01"), T_1679) @[Definitions.scala 256:64] - node T_1681 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_1682 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1683 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1684 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1685 = or(T_1682, T_1683) @[Package.scala 7:62] - node T_1686 = or(T_1685, T_1684) @[Package.scala 7:62] - node T_1687 = and(T_1681, T_1686) @[Trackers.scala 122:38] - node T_1688 = bits(T_1687, 0, 0) @[Bitwise.scala 33:15] - node T_1691 = mux(T_1688, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1692 = not(T_1691) @[Trackers.scala 92:5] - node T_1694 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_1695 = not(T_1694) @[Trackers.scala 92:34] - node T_1696 = or(T_1692, T_1695) @[Trackers.scala 92:32] - node T_1698 = mux(T_1680, T_1696, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_1698 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_1700 = eq(T_1673, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_1700 : @[Trackers.scala 281:20] - node T_1701 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_1702 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1703 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1704 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1705 = or(T_1702, T_1703) @[Package.scala 7:62] - node T_1706 = or(T_1705, T_1704) @[Package.scala 7:62] - node T_1707 = and(T_1701, T_1706) @[Trackers.scala 122:38] - node T_1708 = bits(T_1707, 0, 0) @[Bitwise.scala 33:15] - node T_1711 = mux(T_1708, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1712 = not(T_1711) @[Trackers.scala 92:5] - node T_1714 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_1715 = not(T_1714) @[Trackers.scala 92:34] - node T_1716 = or(T_1712, T_1715) @[Trackers.scala 92:32] - node T_1717 = and(pending_irel_data, T_1716) @[Trackers.scala 282:49] - pending_irel_data <= T_1717 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_1718 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_1719 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_1720 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_1721 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_1722 = or(T_1718, T_1719) @[Package.scala 7:62] - node T_1723 = or(T_1722, T_1720) @[Package.scala 7:62] - node T_1724 = or(T_1723, T_1721) @[Package.scala 7:62] - node T_1725 = and(T_1724, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_1727 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_1728 = or(T_1727, T_1568) @[Trackers.scala 294:55] - node T_1730 = eq(T_1728, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_1731 = and(T_1725, T_1730) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_1731 @[Trackers.scala 292:26] - wire T_1763 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_1763 is invalid @[Definitions.scala 773:19] - T_1763.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_1763.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_1763.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_1763.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_1763.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_1763.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_1763.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_1824 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_1824 is invalid @[Definitions.scala 882:19] - T_1824.client_id <= T_1763.client_id @[Definitions.scala 883:19] - T_1824.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_1824.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_1824.client_xact_id <= T_1763.client_xact_id @[Definitions.scala 886:24] - T_1824.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_1824.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_1824.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_1824 @[Trackers.scala 296:25] - node scoreboard_0 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_1853 = eq(state, UInt<4>("h00")) @[Broadcast.scala 120:35] - node T_1855 = or(T_1853, UInt<1>("h00")) @[Broadcast.scala 120:46] - node T_1856 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1857 = and(T_1856, io.inner.release.bits.voluntary) @[Trackers.scala 644:61] - node T_1859 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 646:45] - node T_1860 = and(T_1857, T_1859) @[Trackers.scala 645:51] - node T_1861 = or(T_1855, T_1860) @[Broadcast.scala 120:64] - io.inner.release.ready <= T_1861 @[Broadcast.scala 120:26] - node T_1862 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - when T_1862 : @[Broadcast.scala 122:33] - data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data @[Broadcast.scala 122:68] - skip @[Broadcast.scala 122:33] - node T_1863 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_1864 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_1865 = or(T_1863, T_1864) @[Consts.scala 36:42] - node T_1867 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_1868 = or(UInt<1>("h00"), T_1867) @[Consts.scala 33:33] - node T_1869 = or(T_1865, T_1868) @[Consts.scala 36:59] - node T_1870 = mux(T_1869, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_1893 : {state : UInt<2>} @[Metadata.scala 158:20] - T_1893 is invalid @[Metadata.scala 158:20] - T_1893.state <= T_1870 @[Metadata.scala 159:16] - node T_1915 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_1916 = and(T_1915, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_1917 = and(T_1916, io.inner.release.valid) @[Trackers.scala 245:75] - node T_1921 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_1922 = or(T_1921, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_1922 : @[Trackers.scala 331:53] - node T_1924 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_1925 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1926 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1927 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1928 = or(T_1925, T_1926) @[Package.scala 7:62] - node T_1929 = or(T_1928, T_1927) @[Package.scala 7:62] - node T_1930 = and(T_1924, T_1929) @[Trackers.scala 101:37] - node T_1931 = and(T_1930, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_1932 = bits(T_1931, 0, 0) @[Bitwise.scala 33:15] - node T_1935 = mux(T_1932, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1937 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_1938 = and(T_1935, T_1937) @[Trackers.scala 89:31] - node T_1939 = or(pending_orel_data, T_1938) @[Trackers.scala 332:47] - node T_1940 = or(T_1939, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_1941 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_1942 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1943 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1944 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1945 = or(T_1942, T_1943) @[Package.scala 7:62] - node T_1946 = or(T_1945, T_1944) @[Package.scala 7:62] - node T_1947 = and(T_1941, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1957 = and(T_1940, T_1956) @[Trackers.scala 334:34] - pending_orel_data <= T_1957 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when T_1917 : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_1959 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_1959 : @[Trackers.scala 338:36] - node T_1961 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1962 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1963 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1964 = or(T_1961, T_1962) @[Package.scala 7:62] - node T_1965 = or(T_1964, T_1963) @[Package.scala 7:62] - node T_1966 = and(UInt<1>("h01"), T_1965) @[Definitions.scala 256:64] - node T_1968 = eq(T_1966, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1970 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1971 = or(T_1968, T_1970) @[Definitions.scala 141:57] - when T_1971 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_1974 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1975 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1976 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1977 = or(T_1974, T_1975) @[Package.scala 7:62] - node T_1978 = or(T_1977, T_1976) @[Package.scala 7:62] - node T_1979 = and(UInt<1>("h01"), T_1978) @[Definitions.scala 256:64] - node T_1981 = eq(T_1979, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_1983 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_1984 = or(T_1981, T_1983) @[Definitions.scala 142:56] - when T_1984 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_1988 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_1991 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_1992 = and(io.outer.release.bits.voluntary, T_1991) @[Trackers.scala 348:51] - node T_1993 = and(T_1988, T_1992) @[Counters.scala 123:62] - node T_1995 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1996 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1997 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1998 = or(T_1995, T_1996) @[Package.scala 7:62] - node T_1999 = or(T_1998, T_1997) @[Package.scala 7:62] - node T_2000 = and(UInt<1>("h01"), T_1999) @[Definitions.scala 256:64] - node T_2001 = and(T_1993, T_2000) @[Counters.scala 67:47] - reg T_2003 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2001 : @[Counter.scala 43:17] - node T_2005 = eq(T_2003, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2007 = add(T_2003, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2008 = tail(T_2007, 1) @[Counter.scala 21:22] - T_2003 <= T_2008 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2009 = and(T_2001, T_2005) @[Counter.scala 44:20] - node T_2010 = mux(T_2000, T_2003, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2011 = mux(T_2000, T_2009, T_1993) @[Counters.scala 69:19] - node T_2012 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2014 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2015 = and(io.outer.grant.bits.is_builtin_type, T_2014) @[Definitions.scala 277:59] - node T_2016 = and(T_2012, T_2015) @[Counters.scala 124:64] - wire T_2024 : UInt<3>[1] @[Definitions.scala 853:34] - T_2024 is invalid @[Definitions.scala 853:34] - T_2024[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2026 = eq(io.outer.grant.bits.g_type, T_2024[0]) @[Package.scala 7:47] - node T_2027 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2028 = mux(io.outer.grant.bits.is_builtin_type, T_2026, T_2027) @[Definitions.scala 274:33] - node T_2029 = and(UInt<1>("h01"), T_2028) @[Definitions.scala 274:27] - node T_2030 = and(T_2016, T_2029) @[Counters.scala 67:47] - reg T_2032 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2030 : @[Counter.scala 43:17] - node T_2034 = eq(T_2032, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2036 = add(T_2032, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2037 = tail(T_2036, 1) @[Counter.scala 21:22] - T_2032 <= T_2037 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2038 = and(T_2030, T_2034) @[Counter.scala 44:20] - node T_2039 = mux(T_2029, T_2032, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2040 = mux(T_2029, T_2038, T_2016) @[Counters.scala 69:19] - reg T_2042 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2044 = eq(T_2040, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2045 = and(T_2011, T_2044) @[Counters.scala 33:14] - when T_2045 : @[Counters.scala 33:24] - node T_2047 = add(T_2042, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2048 = tail(T_2047, 1) @[Counters.scala 33:37] - T_2042 <= T_2048 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2050 = eq(T_2011, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2051 = and(T_2040, T_2050) @[Counters.scala 34:16] - when T_2051 : @[Counters.scala 34:24] - node T_2053 = sub(T_2042, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2054 = tail(T_2053, 1) @[Counters.scala 34:37] - T_2042 <= T_2054 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2056 = gt(T_2042, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2056 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2010 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2011 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2039 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2040 @[Counters.scala 130:22] - node T_2058 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2059 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2060 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2061 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2062 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2063 = or(T_2060, T_2061) @[Package.scala 7:62] - node T_2064 = or(T_2063, T_2062) @[Package.scala 7:62] - node T_2065 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2066 = bits(T_2065, 0, 0) @[Trackers.scala 353:26] - node T_2067 = mux(T_2064, T_2066, pending_orel_send) @[Trackers.scala 352:32] - node T_2068 = and(T_2059, T_2067) @[Trackers.scala 352:26] - node T_2069 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2070 = and(T_2069, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2071 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2072 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2073 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2074 = or(T_2071, T_2072) @[Package.scala 7:62] - node T_2075 = or(T_2074, T_2073) @[Package.scala 7:62] - node T_2076 = and(T_2070, T_2075) @[Trackers.scala 356:49] - node T_2077 = and(T_2076, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2078 = mux(UInt<1>("h01"), T_2068, T_2077) @[Trackers.scala 351:49] - node T_2079 = and(T_2058, T_2078) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2079 @[Trackers.scala 351:28] - node T_2082 = eq(T_1893.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2083 = mux(T_2082, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2084 = mux(T_2082, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2085 = mux(T_2082, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2086 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2087 = mux(T_2086, T_2085, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2088 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2089 = mux(T_2088, T_2084, T_2087) @[Mux.scala 46:16] - node T_2090 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2091 = mux(T_2090, T_2083, T_2089) @[Mux.scala 46:16] - wire T_2119 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2119 is invalid @[Definitions.scala 754:19] - T_2119.r_type <= T_2091 @[Definitions.scala 755:16] - T_2119.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2119.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2119.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2119.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2119.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2119 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2148 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_2149 = or(T_2148, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_2150 = or(T_2149, scoreboard_2) @[Trackers.scala 50:60] - node T_2151 = or(T_2150, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_2153 = eq(T_2151, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_2153 @[Trackers.scala 50:22] - node T_2154 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_2155 = and(T_2154, all_pending_done) @[Trackers.scala 51:27] - when T_2155 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - skip @[Trackers.scala 51:48] - - module Queue_8 : + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_78 = neq(pending_orel_data, UInt<1>("h0")) + node T_79 = or(pending_orel_send, T_78) + node scoreboard_2 = or(T_79, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_103 : { sharers : UInt<1>} + T_103 is invalid + T_103.sharers <= UInt<1>("h0") + wire T_149 : { state : UInt<2>} + T_149 is invalid + T_149.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_103 + coh.outer <- T_149 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1519 = eq(state, UInt<4>("h0")) + node T_1520 = and(io.inner.release.ready, io.inner.release.valid) + node T_1521 = and(T_1519, T_1520) + node T_1522 = and(T_1521, io.alloc.irel.should) + node T_1524 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_1525 = and(T_1522, T_1524) + node T_1527 = eq(T_1525, UInt<1>("h0")) + node T_1528 = or(T_1527, reset) + node T_1530 = eq(T_1528, UInt<1>("h0")) + when T_1530 : + printf(clk, UInt<1>("h1"), "Assertion failed: VoluntaryReleaseTracker accepted Release that wasn't voluntary!\n at Broadcast.scala:81 assert(!(state === s_idle && io.inner.release.fire() && io.alloc.irel.should && !io.irel().isVoluntary()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1544 : UInt<64>[8] + T_1544 is invalid + T_1544[0] <= UInt<64>("h0") + T_1544[1] <= UInt<64>("h0") + T_1544[2] <= UInt<64>("h0") + T_1544[3] <= UInt<64>("h0") + T_1544[4] <= UInt<64>("h0") + T_1544[5] <= UInt<64>("h0") + T_1544[6] <= UInt<64>("h0") + T_1544[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1544) + node T_1552 = neq(state, UInt<4>("h0")) + node T_1553 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1554 = and(T_1552, T_1553) + io.alloc.iacq.matches <= T_1554 + node T_1555 = neq(state, UInt<4>("h0")) + node T_1556 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1557 = and(T_1555, T_1556) + io.alloc.irel.matches <= T_1557 + node T_1558 = neq(state, UInt<4>("h0")) + node T_1559 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1560 = and(T_1558, T_1559) + io.alloc.oprb.matches <= T_1560 + node T_1561 = eq(state, UInt<4>("h0")) + node T_1562 = and(T_1561, UInt<1>("h0")) + io.alloc.iacq.can <= T_1562 + node T_1563 = eq(state, UInt<4>("h0")) + node T_1564 = and(T_1563, UInt<1>("h1")) + io.alloc.irel.can <= T_1564 + node T_1565 = eq(state, UInt<4>("h0")) + node T_1566 = and(T_1565, UInt<1>("h0")) + io.alloc.oprb.can <= T_1566 + io.alloc.addr_block <= xact_addr_block + node T_1567 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1567 + node T_1568 = or(scoreboard_2, vol_ognt_counter.pending) + node T_1570 = and(io.inner.release.ready, io.inner.release.valid) + node T_1571 = eq(state, UInt<4>("h0")) + node T_1572 = mux(T_1571, io.alloc.irel.should, io.alloc.irel.matches) + node T_1573 = and(T_1572, io.inner.release.bits.voluntary) + node T_1576 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1577 = and(T_1573, T_1576) + node T_1578 = and(T_1570, T_1577) + node T_1580 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1581 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1582 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1583 = or(T_1580, T_1581) + node T_1584 = or(T_1583, T_1582) + node T_1585 = and(UInt<1>("h1"), T_1584) + node T_1586 = and(T_1578, T_1585) + reg T_1588 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_1586 : + T_1590 <= eq(T_1588, UInt<3>("h7")) + node T_1592 = add(T_1588, UInt<1>("h1")) + node T_1593 = tail(T_1592, 1) + T_1588 <= T_1593 + node T_1594 = and(T_1586, T_1590) + node T_1595 = mux(T_1585, T_1588, UInt<1>("h0")) + node T_1596 = mux(T_1585, T_1594, T_1578) + node T_1597 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_1598 = neq(state, UInt<4>("h0")) + node T_1600 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_1601 = and(io.inner.grant.bits.is_builtin_type, T_1600) + node T_1602 = and(T_1598, T_1601) + node T_1603 = and(T_1597, T_1602) + wire T_1611 : UInt<3>[1] + T_1611 is invalid + T_1611[0] <= UInt<3>("h5") + node T_1613 = eq(io.inner.grant.bits.g_type, T_1611[0]) + node T_1614 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_1615 = mux(io.inner.grant.bits.is_builtin_type, T_1613, T_1614) + node T_1616 = and(UInt<1>("h1"), T_1615) + node T_1617 = and(T_1603, T_1616) + reg T_1619 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_1617 : + T_1621 <= eq(T_1619, UInt<3>("h7")) + node T_1623 = add(T_1619, UInt<1>("h1")) + node T_1624 = tail(T_1623, 1) + T_1619 <= T_1624 + node T_1625 = and(T_1617, T_1621) + node T_1626 = mux(T_1616, T_1619, UInt<1>("h0")) + node T_1627 = mux(T_1616, T_1625, T_1603) + reg T_1629 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_1631 = eq(T_1627, UInt<1>("h0")) + node T_1632 = and(T_1596, T_1631) + when T_1632 : + node T_1634 = add(T_1629, UInt<1>("h1")) + node T_1635 = tail(T_1634, 1) + T_1629 <= T_1635 + node T_1637 = eq(T_1596, UInt<1>("h0")) + node T_1638 = and(T_1627, T_1637) + when T_1638 : + node T_1640 = sub(T_1629, UInt<1>("h1")) + node T_1641 = tail(T_1640, 1) + T_1629 <= T_1641 + node T_1643 = gt(T_1629, UInt<1>("h0")) + vol_ignt_counter.pending <= T_1643 + vol_ignt_counter.up.idx <= T_1595 + vol_ignt_counter.up.done <= T_1596 + vol_ignt_counter.down.idx <= T_1626 + vol_ignt_counter.down.done <= T_1627 + node T_1644 = eq(state, UInt<4>("h0")) + node T_1645 = and(T_1644, io.alloc.irel.should) + node T_1646 = and(T_1645, io.inner.release.valid) + when T_1646 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_1648 = not(UInt<8>("h0")) + pending_irel_data <= T_1648 + state <= UInt<4>("h7") + node T_1649 = eq(state, UInt<4>("h0")) + node T_1650 = and(T_1649, io.alloc.irel.should) + node T_1651 = and(T_1650, io.inner.release.valid) + node T_1653 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1654 = and(T_1653, io.inner.release.bits.voluntary) + node T_1656 = neq(pending_irel_data, UInt<1>("h0")) + node T_1657 = and(T_1654, T_1656) + node T_1658 = or(UInt<1>("h0"), T_1657) + node T_1659 = and(T_1658, io.inner.release.valid) + node T_1660 = or(T_1651, T_1659) + node T_1661 = and(T_1660, io.inner.release.ready) + when T_1661 : + node T_1663 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1664 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1665 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1666 = or(T_1663, T_1664) + node T_1667 = or(T_1666, T_1665) + node T_1668 = and(UInt<1>("h1"), T_1667) + node T_1670 = eq(T_1668, UInt<1>("h0")) + node T_1672 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_1673 = or(T_1670, T_1672) + when T_1673 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_1675 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1676 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1677 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1678 = or(T_1675, T_1676) + node T_1679 = or(T_1678, T_1677) + node T_1680 = and(UInt<1>("h1"), T_1679) + node T_1681 = and(io.inner.release.ready, io.inner.release.valid) + node T_1682 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1683 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1684 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1685 = or(T_1682, T_1683) + node T_1686 = or(T_1685, T_1684) + node T_1687 = and(T_1681, T_1686) + node T_1688 = bits(T_1687, 0, 0) + node T_1691 = mux(T_1688, UInt<8>("hff"), UInt<8>("h0")) + node T_1692 = not(T_1691) + node T_1694 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_1695 = not(T_1694) + node T_1696 = or(T_1692, T_1695) + node T_1698 = mux(T_1680, T_1696, UInt<1>("h0")) + pending_irel_data <= T_1698 + node T_1700 = eq(T_1673, UInt<1>("h0")) + when T_1700 : + node T_1701 = and(io.inner.release.ready, io.inner.release.valid) + node T_1702 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1703 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1704 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1705 = or(T_1702, T_1703) + node T_1706 = or(T_1705, T_1704) + node T_1707 = and(T_1701, T_1706) + node T_1708 = bits(T_1707, 0, 0) + node T_1711 = mux(T_1708, UInt<8>("hff"), UInt<8>("h0")) + node T_1712 = not(T_1711) + node T_1714 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_1715 = not(T_1714) + node T_1716 = or(T_1712, T_1715) + node T_1717 = and(pending_irel_data, T_1716) + pending_irel_data <= T_1717 + node T_1718 = eq(state, UInt<4>("h3")) + node T_1719 = eq(state, UInt<4>("h4")) + node T_1720 = eq(state, UInt<4>("h5")) + node T_1721 = eq(state, UInt<4>("h7")) + node T_1722 = or(T_1718, T_1719) + node T_1723 = or(T_1722, T_1720) + node T_1724 = or(T_1723, T_1721) + node T_1725 = and(T_1724, vol_ignt_counter.pending) + node T_1727 = neq(pending_irel_data, UInt<1>("h0")) + node T_1728 = or(T_1727, T_1568) + node T_1730 = eq(T_1728, UInt<1>("h0")) + node T_1731 = and(T_1725, T_1730) + io.inner.grant.valid <= T_1731 + wire T_1763 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_1763 is invalid + T_1763.client_id <= xact_vol_ir_src + T_1763.voluntary <= UInt<1>("h1") + T_1763.r_type <= xact_vol_ir_r_type + T_1763.client_xact_id <= xact_vol_ir_client_xact_id + T_1763.addr_block <= xact_addr_block + T_1763.addr_beat <= UInt<1>("h0") + T_1763.data <= UInt<1>("h0") + wire T_1824 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_1824 is invalid + T_1824.client_id <= T_1763.client_id + T_1824.is_builtin_type <= UInt<1>("h1") + T_1824.g_type <= UInt<3>("h0") + T_1824.client_xact_id <= T_1763.client_xact_id + T_1824.manager_xact_id <= UInt<1>("h0") + T_1824.addr_beat <= UInt<1>("h0") + T_1824.data <= UInt<1>("h0") + io.inner.grant.bits <- T_1824 + node scoreboard_0 = neq(pending_irel_data, UInt<1>("h0")) + node T_1853 = eq(state, UInt<4>("h0")) + node T_1855 = or(T_1853, UInt<1>("h0")) + node T_1856 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1857 = and(T_1856, io.inner.release.bits.voluntary) + node T_1859 = neq(pending_irel_data, UInt<1>("h0")) + node T_1860 = and(T_1857, T_1859) + node T_1861 = or(T_1855, T_1860) + io.inner.release.ready <= T_1861 + node T_1862 = and(io.inner.release.ready, io.inner.release.valid) + when T_1862 : + data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data + node T_1863 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_1864 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_1865 = or(T_1863, T_1864) + node T_1867 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_1868 = or(UInt<1>("h0"), T_1867) + node T_1869 = or(T_1865, T_1868) + node T_1870 = mux(T_1869, UInt<2>("h2"), coh.outer.state) + wire T_1893 : { state : UInt<2>} + T_1893 is invalid + T_1893.state <= T_1870 + node T_1915 = eq(state, UInt<4>("h0")) + node T_1916 = and(T_1915, io.alloc.irel.should) + node T_1917 = and(T_1916, io.inner.release.valid) + node T_1921 = neq(state, UInt<4>("h0")) + node T_1922 = or(T_1921, io.alloc.irel.should) + when T_1922 : + node T_1924 = and(io.inner.release.ready, io.inner.release.valid) + node T_1925 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_1926 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_1927 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_1928 = or(T_1925, T_1926) + node T_1929 = or(T_1928, T_1927) + node T_1930 = and(T_1924, T_1929) + node T_1931 = and(T_1930, UInt<1>("h1")) + node T_1932 = bits(T_1931, 0, 0) + node T_1935 = mux(T_1932, UInt<8>("hff"), UInt<8>("h0")) + node T_1937 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_1938 = and(T_1935, T_1937) + node T_1939 = or(pending_orel_data, T_1938) + node T_1940 = or(T_1939, UInt<1>("h0")) + node T_1941 = and(io.outer.release.ready, io.outer.release.valid) + node T_1942 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_1943 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_1944 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_1945 = or(T_1942, T_1943) + node T_1946 = or(T_1945, T_1944) + node T_1947 = and(T_1941, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1957 = and(T_1940, T_1956) + pending_orel_data <= T_1957 + when T_1917 : + pending_orel_send <= UInt<1>("h1") + node T_1959 = and(io.outer.release.ready, io.outer.release.valid) + when T_1959 : + node T_1961 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_1962 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_1963 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_1964 = or(T_1961, T_1962) + node T_1965 = or(T_1964, T_1963) + node T_1966 = and(UInt<1>("h1"), T_1965) + node T_1968 = eq(T_1966, UInt<1>("h0")) + node T_1970 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_1971 = or(T_1968, T_1970) + when T_1971 : + sending_orel <= UInt<1>("h1") + node T_1974 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_1975 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_1976 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_1977 = or(T_1974, T_1975) + node T_1978 = or(T_1977, T_1976) + node T_1979 = and(UInt<1>("h1"), T_1978) + node T_1981 = eq(T_1979, UInt<1>("h0")) + node T_1983 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_1984 = or(T_1981, T_1983) + when T_1984 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_1988 = and(io.outer.release.ready, io.outer.release.valid) + node T_1991 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1992 = and(io.outer.release.bits.voluntary, T_1991) + node T_1993 = and(T_1988, T_1992) + node T_1995 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_1996 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_1997 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_1998 = or(T_1995, T_1996) + node T_1999 = or(T_1998, T_1997) + node T_2000 = and(UInt<1>("h1"), T_1999) + node T_2001 = and(T_1993, T_2000) + reg T_2003 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2001 : + T_2005 <= eq(T_2003, UInt<3>("h7")) + node T_2007 = add(T_2003, UInt<1>("h1")) + node T_2008 = tail(T_2007, 1) + T_2003 <= T_2008 + node T_2009 = and(T_2001, T_2005) + node T_2010 = mux(T_2000, T_2003, UInt<1>("h0")) + node T_2011 = mux(T_2000, T_2009, T_1993) + node T_2012 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2014 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2015 = and(io.outer.grant.bits.is_builtin_type, T_2014) + node T_2016 = and(T_2012, T_2015) + wire T_2024 : UInt<3>[1] + T_2024 is invalid + T_2024[0] <= UInt<3>("h5") + node T_2026 = eq(io.outer.grant.bits.g_type, T_2024[0]) + node T_2027 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2028 = mux(io.outer.grant.bits.is_builtin_type, T_2026, T_2027) + node T_2029 = and(UInt<1>("h1"), T_2028) + node T_2030 = and(T_2016, T_2029) + reg T_2032 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2030 : + T_2034 <= eq(T_2032, UInt<3>("h7")) + node T_2036 = add(T_2032, UInt<1>("h1")) + node T_2037 = tail(T_2036, 1) + T_2032 <= T_2037 + node T_2038 = and(T_2030, T_2034) + node T_2039 = mux(T_2029, T_2032, UInt<1>("h0")) + node T_2040 = mux(T_2029, T_2038, T_2016) + reg T_2042 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2044 = eq(T_2040, UInt<1>("h0")) + node T_2045 = and(T_2011, T_2044) + when T_2045 : + node T_2047 = add(T_2042, UInt<1>("h1")) + node T_2048 = tail(T_2047, 1) + T_2042 <= T_2048 + node T_2050 = eq(T_2011, UInt<1>("h0")) + node T_2051 = and(T_2040, T_2050) + when T_2051 : + node T_2053 = sub(T_2042, UInt<1>("h1")) + node T_2054 = tail(T_2053, 1) + T_2042 <= T_2054 + node T_2056 = gt(T_2042, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2056 + vol_ognt_counter.up.idx <= T_2010 + vol_ognt_counter.up.done <= T_2011 + vol_ognt_counter.down.idx <= T_2039 + vol_ognt_counter.down.done <= T_2040 + node T_2058 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2059 = eq(state, UInt<4>("h7")) + node T_2060 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2061 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2062 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2063 = or(T_2060, T_2061) + node T_2064 = or(T_2063, T_2062) + node T_2065 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2066 = bits(T_2065, 0, 0) + node T_2067 = mux(T_2064, T_2066, pending_orel_send) + node T_2068 = and(T_2059, T_2067) + node T_2069 = neq(state, UInt<4>("h0")) + node T_2070 = and(T_2069, io.alloc.irel.matches) + node T_2071 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2072 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2073 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2074 = or(T_2071, T_2072) + node T_2075 = or(T_2074, T_2073) + node T_2076 = and(T_2070, T_2075) + node T_2077 = and(T_2076, io.inner.release.valid) + node T_2078 = mux(UInt<1>("h1"), T_2068, T_2077) + node T_2079 = and(T_2058, T_2078) + io.outer.release.valid <= T_2079 + node T_2082 = eq(T_1893.state, UInt<2>("h2")) + node T_2083 = mux(T_2082, UInt<3>("h0"), UInt<3>("h3")) + node T_2084 = mux(T_2082, UInt<3>("h1"), UInt<3>("h4")) + node T_2085 = mux(T_2082, UInt<3>("h2"), UInt<3>("h5")) + node T_2086 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2087 = mux(T_2086, T_2085, UInt<3>("h5")) + node T_2088 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2089 = mux(T_2088, T_2084, T_2087) + node T_2090 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2091 = mux(T_2090, T_2083, T_2089) + wire T_2119 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2119 is invalid + T_2119.r_type <= T_2091 + T_2119.client_xact_id <= UInt<1>("h0") + T_2119.addr_block <= xact_addr_block + T_2119.addr_beat <= vol_ognt_counter.up.idx + T_2119.data <= data_buffer[vol_ognt_counter.up.idx] + T_2119.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2119 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2148 = or(UInt<1>("h0"), scoreboard_0) + node T_2149 = or(T_2148, vol_ignt_counter.pending) + node T_2150 = or(T_2149, scoreboard_2) + node T_2151 = or(T_2150, vol_ognt_counter.pending) + node T_2153 = eq(T_2151, UInt<1>("h0")) + all_pending_done <= T_2153 + node T_2154 = eq(state, UInt<4>("h7")) + node T_2155 = and(T_2154, all_pending_done) + when T_2155 : + state <= UInt<4>("h0") + + module Queue_8 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>}}, count : UInt<2>} + io is invalid - cmem ram : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>}[2] @[Decoupled.scala 162:16] - reg T_245 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_247 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_245, T_247) @[Decoupled.scala 167:33] - node T_250 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_250) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_251 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} [2] + reg T_245 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_247 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_245, T_247) + node T_250 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_250) + node full = and(ptr_match, maybe_full) + node T_251 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_251 - node T_252 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_252 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_252 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_253 = ram[T_245], clk - T_253 <- io.enq.bits @[Decoupled.scala 174:24] - node T_280 = eq(T_245, UInt<1>("h01")) @[Counter.scala 20:24] - node T_282 = add(T_245, UInt<1>("h01")) @[Counter.scala 21:22] - node T_283 = tail(T_282, 1) @[Counter.scala 21:22] - T_245 <= T_283 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_285 = eq(T_247, UInt<1>("h01")) @[Counter.scala 20:24] - node T_287 = add(T_247, UInt<1>("h01")) @[Counter.scala 21:22] - node T_288 = tail(T_287, 1) @[Counter.scala 21:22] - T_247 <= T_288 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_289 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_289 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_291 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_291 @[Decoupled.scala 184:16] - node T_293 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_293 @[Decoupled.scala 185:16] + T_253 <- io.enq.bits + node T_280 = eq(T_245, UInt<1>("h1")) + node T_282 = add(T_245, UInt<1>("h1")) + node T_283 = tail(T_282, 1) + T_245 <= T_283 + when do_deq : + node T_285 = eq(T_247, UInt<1>("h1")) + node T_287 = add(T_247, UInt<1>("h1")) + node T_288 = tail(T_287, 1) + T_247 <= T_288 + node T_289 = neq(do_enq, do_deq) + when T_289 : + maybe_full <= do_enq + node T_291 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_291 + node T_293 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_293 infer mport T_294 = ram[T_247], clk - io.deq.bits <- T_294 @[Decoupled.scala 186:15] - node T_320 = sub(T_245, T_247) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_320, 1) @[Decoupled.scala 201:32] - node T_321 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_322 = cat(T_321, ptr_diff) @[Cat.scala 20:58] - io.count <= T_322 @[Decoupled.scala 203:14] - - module BufferedBroadcastAcquireTracker : + io.deq.bits <- T_294 + node T_320 = sub(T_245, T_247) + node ptr_diff = tail(T_320, 1) + node T_321 = and(maybe_full, ptr_match) + node T_322 = cat(T_321, ptr_diff) + io.count <= T_322 + + module BufferedBroadcastAcquireTracker : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<1>("h01") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_1 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<1>("h1") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_1 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<2>("h02") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_2 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<2>("h2") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_2 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<2>("h03") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_3 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<2>("h3") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_3 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<3>("h04") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_4 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<3>("h4") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_4 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<3>("h05") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_5 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<3>("h5") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_5 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<3>("h06") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module BufferedBroadcastAcquireTracker_6 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<3>("h6") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module BufferedBroadcastAcquireTracker_6 : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : {iacq : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : {matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, alloc : { iacq : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, irel : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, oprb : { matches : UInt<1>, can : UInt<1>, flip should : UInt<1>}, idle : UInt<1>, addr_block : UInt<26>}} + + wire T_2910 : UInt<1> + T_2910 is invalid + wire T_3301 : UInt<1> + T_3301 is invalid + wire T_2714 : UInt<1> + T_2714 is invalid + wire T_2117 : UInt<1> + T_2117 is invalid + wire T_2168 : UInt<1> + T_2168 is invalid + wire T_2879 : UInt<1> + T_2879 is invalid + wire T_3501 : UInt<1> + T_3501 is invalid + wire T_2199 : UInt<1> + T_2199 is invalid + wire T_2093 : UInt<1> + T_2093 is invalid + wire T_3316 : UInt<1> + T_3316 is invalid + wire T_2743 : UInt<1> + T_2743 is invalid io is invalid - wire all_pending_done : UInt<1> @[Trackers.scala 86:30] - all_pending_done is invalid @[Trackers.scala 86:30] - reg state : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) - reg xact_addr_block : UInt<26>, clk with : (reset => (reset, UInt<26>("h00"))) - reg xact_allocate : UInt<1>, clk - reg xact_amo_shift_bytes : UInt, clk - reg xact_op_code : UInt, clk - reg xact_addr_byte : UInt, clk - reg xact_op_size : UInt, clk - wire xact_addr_beat : UInt @[Trackers.scala 215:28] - xact_addr_beat is invalid @[Trackers.scala 215:28] - wire xact_iacq : {client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} @[Trackers.scala 216:23] - xact_iacq is invalid @[Trackers.scala 216:23] - reg xact_vol_ir_r_type : UInt, clk - reg xact_vol_ir_src : UInt, clk - reg xact_vol_ir_client_xact_id : UInt, clk - reg pending_irel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ignt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 241:30] - vol_ignt_counter is invalid @[Trackers.scala 241:30] - wire scoreboard_6 : UInt<1> @[Trackers.scala 454:26] - scoreboard_6 is invalid @[Trackers.scala 454:26] - wire ignt_data_idx : UInt @[Trackers.scala 455:27] - ignt_data_idx is invalid @[Trackers.scala 455:27] - wire ignt_data_done : UInt<1> @[Trackers.scala 456:28] - ignt_data_done is invalid @[Trackers.scala 456:28] - wire ifin_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 457:26] - ifin_counter is invalid @[Trackers.scala 457:26] - reg pending_put_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - reg pending_ignt_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 577:26] - ognt_counter is invalid @[Trackers.scala 577:26] - reg pending_iprbs : UInt<1>, clk - node T_152 = bits(pending_iprbs, 0, 0) @[OneHot.scala 35:40] - reg pending_orel_send : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg pending_orel_data : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) - wire vol_ognt_counter : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 306:30] - vol_ognt_counter is invalid @[Trackers.scala 306:30] - node T_170 = neq(pending_orel_data, UInt<1>("h00")) @[Trackers.scala 307:61] - node T_171 = or(pending_orel_send, T_170) @[Trackers.scala 307:40] - node scoreboard_3 = or(T_171, vol_ognt_counter.pending) @[Trackers.scala 307:65] - reg sending_orel : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire T_195 : {sharers : UInt<1>} @[Metadata.scala 309:20] - T_195 is invalid @[Metadata.scala 309:20] - T_195.sharers <= UInt<1>("h00") @[Metadata.scala 311:18] - wire T_241 : {state : UInt<2>} @[Metadata.scala 158:20] - T_241 is invalid @[Metadata.scala 158:20] - T_241.state <= UInt<1>("h00") @[Metadata.scala 159:16] - wire coh : {inner : {sharers : UInt<1>}, outer : {state : UInt<2>}} @[Metadata.scala 337:17] - coh is invalid @[Metadata.scala 337:17] - coh.inner <- T_195 @[Metadata.scala 338:13] - coh.outer <- T_241 @[Metadata.scala 339:13] - io.outer.finish.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.grant.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.release.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.outer.probe.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.outer.acquire.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.release.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.probe.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.finish.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - io.inner.grant.valid <= UInt<1>("h00") @[Trackers.scala 62:50] - io.inner.acquire.ready <= UInt<1>("h00") @[Trackers.scala 61:45] - node T_1611 = eq(state, UInt<4>("h00")) @[Broadcast.scala 98:18] - node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1613 = and(T_1611, T_1612) @[Broadcast.scala 98:29] - node T_1614 = and(T_1613, io.alloc.iacq.should) @[Broadcast.scala 98:56] - node T_1616 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1623 : UInt<3>[1] @[Definitions.scala 355:35] - T_1623 is invalid @[Definitions.scala 355:35] - T_1623[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) @[Package.scala 7:47] - node T_1626 = and(T_1616, T_1625) @[Definitions.scala 231:89] - node T_1627 = and(T_1614, T_1626) @[Broadcast.scala 98:80] - node T_1629 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1636 : UInt<3>[1] @[Definitions.scala 355:35] - T_1636 is invalid @[Definitions.scala 355:35] - T_1636[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) @[Package.scala 7:47] - node T_1639 = and(T_1629, T_1638) @[Definitions.scala 231:89] - node T_1641 = eq(T_1639, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1644 = or(T_1641, T_1643) @[Definitions.scala 141:57] - node T_1646 = eq(T_1644, UInt<1>("h00")) @[Broadcast.scala 99:37] - node T_1647 = and(T_1627, T_1646) @[Broadcast.scala 99:34] - node T_1649 = eq(T_1647, UInt<1>("h00")) @[Broadcast.scala 98:10] - node T_1650 = or(T_1649, reset) @[Broadcast.scala 98:9] - node T_1652 = eq(T_1650, UInt<1>("h00")) @[Broadcast.scala 98:9] - when T_1652 : @[Broadcast.scala 98:9] - printf(clk, UInt<1>(1), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") @[Broadcast.scala 98:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 98:9] - skip @[Broadcast.scala 98:9] - node T_1653 = neq(state, UInt<4>("h00")) @[Broadcast.scala 102:18] - node T_1654 = and(T_1653, scoreboard_6) @[Broadcast.scala 102:29] - node T_1656 = eq(xact_iacq.a_type, UInt<3>("h05")) @[Definitions.scala 207:28] - node T_1658 = eq(xact_iacq.a_type, UInt<3>("h06")) @[Definitions.scala 207:28] - node T_1659 = or(T_1656, T_1658) @[Definitions.scala 219:73] - node T_1660 = and(xact_iacq.is_builtin_type, T_1659) @[Definitions.scala 218:58] - node T_1661 = and(T_1654, T_1660) @[Broadcast.scala 102:45] - node T_1663 = eq(T_1661, UInt<1>("h00")) @[Broadcast.scala 102:10] - node T_1664 = or(T_1663, reset) @[Broadcast.scala 102:9] - node T_1666 = eq(T_1664, UInt<1>("h00")) @[Broadcast.scala 102:9] - when T_1666 : @[Broadcast.scala 102:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") @[Broadcast.scala 102:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 102:9] - skip @[Broadcast.scala 102:9] - node T_1667 = neq(state, UInt<4>("h00")) @[Broadcast.scala 105:18] - node T_1668 = and(T_1667, scoreboard_6) @[Broadcast.scala 105:29] - node T_1670 = eq(xact_iacq.a_type, UInt<3>("h04")) @[Definitions.scala 207:28] - node T_1671 = and(xact_iacq.is_builtin_type, T_1670) @[Definitions.scala 222:56] - node T_1672 = and(T_1668, T_1671) @[Broadcast.scala 105:45] - node T_1674 = eq(T_1672, UInt<1>("h00")) @[Broadcast.scala 105:10] - node T_1675 = or(T_1674, reset) @[Broadcast.scala 105:9] - node T_1677 = eq(T_1675, UInt<1>("h00")) @[Broadcast.scala 105:9] - when T_1677 : @[Broadcast.scala 105:9] - printf(clk, UInt<1>(1), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") @[Broadcast.scala 105:9] - stop(clk, UInt<1>(1), 1) @[Broadcast.scala 105:9] - skip @[Broadcast.scala 105:9] - wire T_1691 : UInt<64>[8] @[Trackers.scala 150:54] - T_1691 is invalid @[Trackers.scala 150:54] - T_1691[0] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[1] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[2] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[3] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[4] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[5] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[6] <= UInt<64>("h00") @[Trackers.scala 150:54] - T_1691[7] <= UInt<64>("h00") @[Trackers.scala 150:54] - reg data_buffer : UInt<64>[8], clk with : (reset => (reset, T_1691)) - wire T_1709 : UInt<8>[8] @[Trackers.scala 179:55] - T_1709 is invalid @[Trackers.scala 179:55] - T_1709[0] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[1] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[2] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[3] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[4] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[5] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[6] <= UInt<8>("h00") @[Trackers.scala 179:55] - T_1709[7] <= UInt<8>("h00") @[Trackers.scala 179:55] - reg wmask_buffer : UInt<8>[8], clk with : (reset => (reset, T_1709)) - node T_1714 = not(wmask_buffer[0]) @[Trackers.scala 180:56] - node T_1716 = eq(T_1714, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1717 = not(wmask_buffer[1]) @[Trackers.scala 180:56] - node T_1719 = eq(T_1717, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1720 = not(wmask_buffer[2]) @[Trackers.scala 180:56] - node T_1722 = eq(T_1720, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1723 = not(wmask_buffer[3]) @[Trackers.scala 180:56] - node T_1725 = eq(T_1723, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1726 = not(wmask_buffer[4]) @[Trackers.scala 180:56] - node T_1728 = eq(T_1726, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1729 = not(wmask_buffer[5]) @[Trackers.scala 180:56] - node T_1731 = eq(T_1729, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1732 = not(wmask_buffer[6]) @[Trackers.scala 180:56] - node T_1734 = eq(T_1732, UInt<1>("h00")) @[Trackers.scala 180:56] - node T_1735 = not(wmask_buffer[7]) @[Trackers.scala 180:56] - node T_1737 = eq(T_1735, UInt<1>("h00")) @[Trackers.scala 180:56] - wire data_valid : UInt<1>[8] @[Trackers.scala 180:23] - data_valid is invalid @[Trackers.scala 180:23] - data_valid[0] <= T_1716 @[Trackers.scala 180:23] - data_valid[1] <= T_1719 @[Trackers.scala 180:23] - data_valid[2] <= T_1722 @[Trackers.scala 180:23] - data_valid[3] <= T_1725 @[Trackers.scala 180:23] - data_valid[4] <= T_1728 @[Trackers.scala 180:23] - data_valid[5] <= T_1731 @[Trackers.scala 180:23] - data_valid[6] <= T_1734 @[Trackers.scala 180:23] - data_valid[7] <= T_1737 @[Trackers.scala 180:23] - node T_1747 = neq(state, UInt<4>("h00")) @[Trackers.scala 428:37] - node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1749 = and(T_1747, T_1748) @[Trackers.scala 428:49] - io.alloc.iacq.matches <= T_1749 @[Trackers.scala 428:27] - node T_1750 = neq(state, UInt<4>("h00")) @[Trackers.scala 429:37] - node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1752 = and(T_1750, T_1751) @[Trackers.scala 429:49] - io.alloc.irel.matches <= T_1752 @[Trackers.scala 429:27] - node T_1753 = neq(state, UInt<4>("h00")) @[Trackers.scala 430:37] - node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_1755 = and(T_1753, T_1754) @[Trackers.scala 430:49] - io.alloc.oprb.matches <= T_1755 @[Trackers.scala 430:27] - node T_1756 = eq(state, UInt<4>("h00")) @[Trackers.scala 431:32] - node T_1757 = and(T_1756, UInt<1>("h01")) @[Trackers.scala 431:43] - io.alloc.iacq.can <= T_1757 @[Trackers.scala 431:23] - node T_1758 = eq(state, UInt<4>("h00")) @[Trackers.scala 432:32] - node T_1759 = and(T_1758, UInt<1>("h00")) @[Trackers.scala 432:43] - io.alloc.irel.can <= T_1759 @[Trackers.scala 432:23] - node T_1760 = eq(state, UInt<4>("h00")) @[Trackers.scala 433:32] - node T_1761 = and(T_1760, UInt<1>("h00")) @[Trackers.scala 433:43] - io.alloc.oprb.can <= T_1761 @[Trackers.scala 433:23] - io.alloc.addr_block <= xact_addr_block @[Trackers.scala 434:25] - node T_1762 = eq(state, UInt<4>("h00")) @[Trackers.scala 435:28] - io.alloc.idle <= T_1762 @[Trackers.scala 435:19] - node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1766 = and(T_1764, T_1765) @[Trackers.scala 462:61] - node T_1767 = and(T_1766, scoreboard_6) @[Trackers.scala 463:53] - node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) @[Trackers.scala 471:67] - node T_1769 = and(T_1767, T_1768) @[Trackers.scala 471:44] - inst ignt_q of Queue_8 @[Trackers.scala 450:27] + wire all_pending_done : UInt<1> + all_pending_done is invalid + reg state : UInt<4>, clk with : + reset => (reset, UInt<4>("h0")) + reg xact_addr_block : UInt<26>, clk with : + reset => (reset, UInt<26>("h0")) + reg xact_allocate : UInt<1>, clk with : + reset => (UInt<1>("h0"), xact_allocate) + reg xact_amo_shift_bytes : UInt, clk with : + reset => (UInt<1>("h0"), xact_amo_shift_bytes) + reg xact_op_code : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_code) + reg xact_addr_byte : UInt, clk with : + reset => (UInt<1>("h0"), xact_addr_byte) + reg xact_op_size : UInt, clk with : + reset => (UInt<1>("h0"), xact_op_size) + wire xact_addr_beat : UInt + xact_addr_beat is invalid + wire xact_iacq : { client_xact_id : UInt<1>, addr_beat : UInt<3>, client_id : UInt<1>, is_builtin_type : UInt<1>, a_type : UInt<3>} + xact_iacq is invalid + reg xact_vol_ir_r_type : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_r_type) + reg xact_vol_ir_src : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_src) + reg xact_vol_ir_client_xact_id : UInt, clk with : + reset => (UInt<1>("h0"), xact_vol_ir_client_xact_id) + reg pending_irel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ignt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ignt_counter is invalid + wire scoreboard_6 : UInt<1> + scoreboard_6 is invalid + wire ignt_data_idx : UInt + ignt_data_idx is invalid + wire ignt_data_done : UInt<1> + ignt_data_done is invalid + wire ifin_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ifin_counter is invalid + reg pending_put_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + reg pending_ignt_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + ognt_counter is invalid + reg pending_iprbs : UInt<1>, clk with : + reset => (UInt<1>("h0"), pending_iprbs) + node T_152 = bits(pending_iprbs, 0, 0) + reg pending_orel_send : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg pending_orel_data : UInt<8>, clk with : + reset => (reset, UInt<8>("h0")) + wire vol_ognt_counter : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + vol_ognt_counter is invalid + node T_170 = neq(pending_orel_data, UInt<1>("h0")) + node T_171 = or(pending_orel_send, T_170) + node scoreboard_3 = or(T_171, vol_ognt_counter.pending) + reg sending_orel : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire T_195 : { sharers : UInt<1>} + T_195 is invalid + T_195.sharers <= UInt<1>("h0") + wire T_241 : { state : UInt<2>} + T_241 is invalid + T_241.state <= UInt<1>("h0") + wire coh : { inner : { sharers : UInt<1>}, outer : { state : UInt<2>}} + coh is invalid + coh.inner <- T_195 + coh.outer <- T_241 + io.outer.finish.valid <= UInt<1>("h0") + io.outer.grant.ready <= UInt<1>("h0") + io.outer.release.valid <= UInt<1>("h0") + io.outer.probe.ready <= UInt<1>("h0") + io.outer.acquire.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + io.inner.probe.valid <= UInt<1>("h0") + io.inner.finish.ready <= UInt<1>("h0") + io.inner.grant.valid <= UInt<1>("h0") + io.inner.acquire.ready <= UInt<1>("h0") + node T_1611 = eq(state, UInt<4>("h0")) + node T_1612 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1613 = and(T_1611, T_1612) + node T_1614 = and(T_1613, io.alloc.iacq.should) + node T_1616 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1623 : UInt<3>[1] + T_1623 is invalid + T_1623[0] <= UInt<3>("h3") + node T_1625 = eq(io.inner.acquire.bits.a_type, T_1623[0]) + node T_1626 = and(T_1616, T_1625) + node T_1627 = and(T_1614, T_1626) + node T_1629 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1636 : UInt<3>[1] + T_1636 is invalid + T_1636[0] <= UInt<3>("h3") + node T_1638 = eq(io.inner.acquire.bits.a_type, T_1636[0]) + node T_1639 = and(T_1629, T_1638) + node T_1641 = eq(T_1639, UInt<1>("h0")) + node T_1643 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1644 = or(T_1641, T_1643) + node T_1646 = eq(T_1644, UInt<1>("h0")) + node T_1647 = and(T_1627, T_1646) + node T_1649 = eq(T_1647, UInt<1>("h0")) + node T_1650 = or(T_1649, reset) + node T_1652 = eq(T_1650, UInt<1>("h0")) + when T_1652 : + printf(clk, UInt<1>("h1"), "Assertion failed: AcquireTracker initialized with a tail data beat.\n at Broadcast.scala:98 assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&\n") + stop(clk, UInt<1>("h1"), 1) + node T_1653 = neq(state, UInt<4>("h0")) + node T_1654 = and(T_1653, scoreboard_6) + node T_1656 = eq(xact_iacq.a_type, UInt<3>("h5")) + node T_1658 = eq(xact_iacq.a_type, UInt<3>("h6")) + node T_1659 = or(T_1656, T_1658) + node T_1660 = and(xact_iacq.is_builtin_type, T_1659) + node T_1661 = and(T_1654, T_1660) + node T_1663 = eq(T_1661, UInt<1>("h0")) + node T_1664 = or(T_1663, reset) + node T_1666 = eq(T_1664, UInt<1>("h0")) + when T_1666 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support Prefetches.\n at Broadcast.scala:102 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),\n") + stop(clk, UInt<1>("h1"), 1) + node T_1667 = neq(state, UInt<4>("h0")) + node T_1668 = and(T_1667, scoreboard_6) + node T_1670 = eq(xact_iacq.a_type, UInt<3>("h4")) + node T_1671 = and(xact_iacq.is_builtin_type, T_1670) + node T_1672 = and(T_1668, T_1671) + node T_1674 = eq(T_1672, UInt<1>("h0")) + node T_1675 = or(T_1674, reset) + node T_1677 = eq(T_1675, UInt<1>("h0")) + when T_1677 : + printf(clk, UInt<1>("h1"), "Assertion failed: Broadcast Hub does not support PutAtomics.\n at Broadcast.scala:105 assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),\n") + stop(clk, UInt<1>("h1"), 1) + wire T_1691 : UInt<64>[8] + T_1691 is invalid + T_1691[0] <= UInt<64>("h0") + T_1691[1] <= UInt<64>("h0") + T_1691[2] <= UInt<64>("h0") + T_1691[3] <= UInt<64>("h0") + T_1691[4] <= UInt<64>("h0") + T_1691[5] <= UInt<64>("h0") + T_1691[6] <= UInt<64>("h0") + T_1691[7] <= UInt<64>("h0") + reg data_buffer : UInt<64>[8], clk with : + reset => (reset, T_1691) + wire T_1709 : UInt<8>[8] + T_1709 is invalid + T_1709[0] <= UInt<8>("h0") + T_1709[1] <= UInt<8>("h0") + T_1709[2] <= UInt<8>("h0") + T_1709[3] <= UInt<8>("h0") + T_1709[4] <= UInt<8>("h0") + T_1709[5] <= UInt<8>("h0") + T_1709[6] <= UInt<8>("h0") + T_1709[7] <= UInt<8>("h0") + reg wmask_buffer : UInt<8>[8], clk with : + reset => (reset, T_1709) + node T_1714 = not(wmask_buffer[0]) + node T_1716 = eq(T_1714, UInt<1>("h0")) + node T_1717 = not(wmask_buffer[1]) + node T_1719 = eq(T_1717, UInt<1>("h0")) + node T_1720 = not(wmask_buffer[2]) + node T_1722 = eq(T_1720, UInt<1>("h0")) + node T_1723 = not(wmask_buffer[3]) + node T_1725 = eq(T_1723, UInt<1>("h0")) + node T_1726 = not(wmask_buffer[4]) + node T_1728 = eq(T_1726, UInt<1>("h0")) + node T_1729 = not(wmask_buffer[5]) + node T_1731 = eq(T_1729, UInt<1>("h0")) + node T_1732 = not(wmask_buffer[6]) + node T_1734 = eq(T_1732, UInt<1>("h0")) + node T_1735 = not(wmask_buffer[7]) + node T_1737 = eq(T_1735, UInt<1>("h0")) + wire data_valid : UInt<1>[8] + data_valid is invalid + data_valid[0] <= T_1716 + data_valid[1] <= T_1719 + data_valid[2] <= T_1722 + data_valid[3] <= T_1725 + data_valid[4] <= T_1728 + data_valid[5] <= T_1731 + data_valid[6] <= T_1734 + data_valid[7] <= T_1737 + node T_1747 = neq(state, UInt<4>("h0")) + node T_1748 = eq(io.inner.acquire.bits.addr_block, xact_addr_block) + node T_1749 = and(T_1747, T_1748) + io.alloc.iacq.matches <= T_1749 + node T_1750 = neq(state, UInt<4>("h0")) + node T_1751 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_1752 = and(T_1750, T_1751) + io.alloc.irel.matches <= T_1752 + node T_1753 = neq(state, UInt<4>("h0")) + node T_1754 = eq(io.outer.probe.bits.addr_block, xact_addr_block) + node T_1755 = and(T_1753, T_1754) + io.alloc.oprb.matches <= T_1755 + node T_1756 = eq(state, UInt<4>("h0")) + node T_1757 = and(T_1756, UInt<1>("h1")) + io.alloc.iacq.can <= T_1757 + node T_1758 = eq(state, UInt<4>("h0")) + node T_1759 = and(T_1758, UInt<1>("h0")) + io.alloc.irel.can <= T_1759 + node T_1760 = eq(state, UInt<4>("h0")) + node T_1761 = and(T_1760, UInt<1>("h0")) + io.alloc.oprb.can <= T_1761 + io.alloc.addr_block <= xact_addr_block + node T_1762 = eq(state, UInt<4>("h0")) + io.alloc.idle <= T_1762 + node T_1764 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1765 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1766 = and(T_1764, T_1765) + node T_1767 = and(T_1766, scoreboard_6) + node T_1768 = eq(xact_iacq.addr_beat, io.inner.acquire.bits.addr_beat) + node T_1769 = and(T_1767, T_1768) + inst ignt_q of Queue_8 ignt_q.io is invalid ignt_q.clk <= clk ignt_q.reset <= reset - node T_1796 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1797 = and(T_1796, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1798 = and(T_1797, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_1800 = eq(T_1769, UInt<1>("h00")) @[Trackers.scala 475:29] - node T_1801 = and(T_1800, scoreboard_6) @[Trackers.scala 475:48] - node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1803 = and(T_1801, T_1802) @[Trackers.scala 475:64] - node T_1805 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1812 : UInt<3>[1] @[Definitions.scala 355:35] - T_1812 is invalid @[Definitions.scala 355:35] - T_1812[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) @[Package.scala 7:47] - node T_1815 = and(T_1805, T_1814) @[Definitions.scala 231:89] - node T_1817 = eq(T_1815, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_1820 = or(T_1817, T_1819) @[Definitions.scala 141:57] - node T_1821 = and(T_1803, T_1820) @[Trackers.scala 476:54] - node T_1822 = or(T_1798, T_1821) @[Trackers.scala 474:47] - ignt_q.io.enq.valid <= T_1822 @[Trackers.scala 474:25] - ignt_q.io.enq.bits <- io.inner.acquire.bits @[Trackers.scala 477:24] - node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) @[Trackers.scala 480:21] - xact_iacq <- T_1823 @[Trackers.scala 480:15] - xact_addr_beat <= xact_iacq.addr_beat @[Trackers.scala 481:20] - node T_1850 = gt(ignt_q.io.count, UInt<1>("h00")) @[Trackers.scala 482:37] - scoreboard_6 <= T_1850 @[Trackers.scala 482:18] - node T_1851 = neq(state, UInt<4>("h00")) @[Trackers.scala 485:17] - node T_1852 = or(T_1851, io.alloc.iacq.should) @[Trackers.scala 485:28] - when T_1852 : @[Trackers.scala 485:53] - node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1862 : UInt<3>[3] @[Definitions.scala 354:26] - T_1862 is invalid @[Definitions.scala 354:26] - T_1862[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1862[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1862[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) @[Package.scala 7:47] - node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) @[Package.scala 7:47] - node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) @[Package.scala 7:47] - node T_1867 = or(T_1864, T_1865) @[Package.scala 7:62] - node T_1868 = or(T_1867, T_1866) @[Package.scala 7:62] - node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) @[Definitions.scala 228:55] - node T_1870 = and(T_1853, T_1869) @[Trackers.scala 122:38] - node T_1871 = bits(T_1870, 0, 0) @[Bitwise.scala 33:15] - node T_1874 = mux(T_1871, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1875 = not(T_1874) @[Trackers.scala 92:5] - node T_1877 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1878 = not(T_1877) @[Trackers.scala 92:34] - node T_1879 = or(T_1875, T_1878) @[Trackers.scala 92:32] - node T_1880 = and(pending_put_data, T_1879) @[Trackers.scala 486:45] - node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - node T_1883 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1890 : UInt<3>[1] @[Definitions.scala 355:35] - T_1890 is invalid @[Definitions.scala 355:35] - T_1890[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) @[Package.scala 7:47] - node T_1893 = and(T_1883, T_1892) @[Definitions.scala 231:89] - node T_1894 = and(T_1881, T_1893) @[Trackers.scala 140:28] - node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) @[Trackers.scala 142:36] - node T_1897 = and(T_1894, T_1896) @[Trackers.scala 141:45] - node T_1902 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 33:12] - node T_1904 = cat(T_1902, UInt<1>("h00")) @[Cat.scala 20:58] - node T_1906 = mux(T_1897, T_1904, UInt<8>("h00")) @[Trackers.scala 137:8] - node T_1907 = or(T_1880, T_1906) @[Trackers.scala 487:60] - pending_put_data <= T_1907 @[Trackers.scala 486:24] - skip @[Trackers.scala 485:53] - node T_1908 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_1909 = and(T_1908, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_1910 = and(T_1909, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_1910 : @[Trackers.scala 492:30] - xact_addr_block <= io.inner.acquire.bits.addr_block @[Trackers.scala 493:23] - node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) @[Definitions.scala 170:39] - node T_1912 = and(T_1911, UInt<1>("h00")) @[Trackers.scala 494:45] - xact_allocate <= T_1912 @[Trackers.scala 494:21] - node T_1915 = mul(UInt<4>("h08"), UInt<1>("h00")) @[Definitions.scala 183:65] - xact_amo_shift_bytes <= T_1915 @[Trackers.scala 495:28] - node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) @[Definitions.scala 212:54] - node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) @[Definitions.scala 212:54] - node T_1922 = or(T_1918, T_1921) @[Definitions.scala 173:36] - node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) @[Definitions.scala 174:17] - node T_1924 = mux(T_1922, UInt<5>("h01"), T_1923) @[Definitions.scala 172:36] - xact_op_code <= T_1924 @[Trackers.scala 496:20] - node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - xact_addr_byte <= T_1925 @[Trackers.scala 497:22] - node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - xact_op_size <= T_1926 @[Trackers.scala 498:20] - node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) @[Definitions.scala 212:54] - node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_1939 : UInt<3>[3] @[Definitions.scala 354:26] - T_1939 is invalid @[Definitions.scala 354:26] - T_1939[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_1939[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_1939[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) @[Package.scala 7:47] - node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) @[Package.scala 7:47] - node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) @[Package.scala 7:47] - node T_1944 = or(T_1941, T_1942) @[Package.scala 7:62] - node T_1945 = or(T_1944, T_1943) @[Package.scala 7:62] - node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) @[Definitions.scala 228:55] - node T_1947 = and(T_1930, T_1946) @[Trackers.scala 122:38] - node T_1948 = bits(T_1947, 0, 0) @[Bitwise.scala 33:15] - node T_1951 = mux(T_1948, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1952 = not(T_1951) @[Trackers.scala 92:5] - node T_1954 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) @[OneHot.scala 44:15] - node T_1955 = not(T_1954) @[Trackers.scala 92:34] - node T_1956 = or(T_1952, T_1955) @[Trackers.scala 92:32] - node T_1958 = mux(T_1929, T_1956, UInt<1>("h00")) @[Trackers.scala 500:30] - pending_put_data <= T_1958 @[Trackers.scala 500:24] - pending_ignt_data <= UInt<1>("h00") @[Trackers.scala 504:25] - state <= UInt<4>("h05") @[Trackers.scala 505:13] - skip @[Trackers.scala 492:30] - node scoreboard_0 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 508:37] - node T_1961 = eq(state, UInt<4>("h00")) @[Broadcast.scala 146:35] - node T_1963 = or(T_1961, UInt<1>("h00")) @[Broadcast.scala 146:46] - node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_1966 = and(T_1964, T_1965) @[Trackers.scala 462:61] - node T_1967 = and(T_1966, scoreboard_6) @[Trackers.scala 463:53] - node T_1969 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1976 : UInt<3>[1] @[Definitions.scala 355:35] - T_1976 is invalid @[Definitions.scala 355:35] - T_1976[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) @[Package.scala 7:47] - node T_1979 = and(T_1969, T_1978) @[Definitions.scala 231:89] - node T_1980 = and(T_1967, T_1979) @[Trackers.scala 465:49] - node T_1981 = or(T_1963, T_1980) @[Broadcast.scala 146:64] - io.inner.acquire.ready <= T_1981 @[Broadcast.scala 146:26] - node T_1982 = not(pending_ignt_data) @[Broadcast.scala 151:46] - node skip_outer_acquire = eq(T_1982, UInt<1>("h00")) @[Broadcast.scala 151:46] - node T_1991 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1992 = mux(T_1991, UInt<2>("h00"), UInt<2>("h02")) @[Mux.scala 46:16] - node T_1993 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1994 = mux(T_1993, UInt<2>("h00"), T_1992) @[Mux.scala 46:16] - node T_1995 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1996 = mux(T_1995, UInt<2>("h02"), T_1994) @[Mux.scala 46:16] - node T_1997 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_1998 = mux(T_1997, UInt<2>("h00"), T_1996) @[Mux.scala 46:16] - node T_1999 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2000 = mux(T_1999, UInt<2>("h02"), T_1998) @[Mux.scala 46:16] - node T_2001 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2002 = mux(T_2001, UInt<2>("h00"), T_2000) @[Mux.scala 46:16] - node T_2003 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_2004 = mux(T_2003, UInt<2>("h02"), T_2002) @[Mux.scala 46:16] - node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h00")) @[Policies.scala 289:8] - wire T_2030 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} @[Definitions.scala 694:19] - T_2030 is invalid @[Definitions.scala 694:19] - T_2030.client_id <= UInt<1>("h00") @[Definitions.scala 695:19] - T_2030.p_type <= T_2005 @[Definitions.scala 696:16] - T_2030.addr_block <= xact_addr_block @[Definitions.scala 697:20] - node T_2055 = eq(skip_outer_acquire, UInt<1>("h00")) @[Broadcast.scala 155:9] - node T_2056 = mux(T_2055, UInt<4>("h06"), UInt<4>("h07")) @[Broadcast.scala 155:8] - wire T_2065 : {pending : UInt<1>, up : {idx : UInt, done : UInt<1>}, down : {idx : UInt, done : UInt<1>}} @[Trackers.scala 393:30] - T_2065 is invalid @[Trackers.scala 393:30] - node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2074 = not(T_2073) @[Trackers.scala 98:5] - node T_2076 = dshl(UInt<1>("h01"), io.inner.probe.bits.client_id) @[OneHot.scala 44:15] - node T_2077 = not(T_2076) @[Trackers.scala 98:40] - node T_2078 = or(T_2074, T_2077) @[Trackers.scala 98:38] - node T_2079 = and(pending_iprbs, T_2078) @[Trackers.scala 395:38] - pending_iprbs <= T_2079 @[Trackers.scala 395:21] - node T_2080 = eq(state, UInt<4>("h05")) @[Trackers.scala 396:37] - node T_2082 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 396:72] - node T_2083 = and(T_2080, T_2082) @[Trackers.scala 396:55] - io.inner.probe.valid <= T_2083 @[Trackers.scala 396:28] - io.inner.probe.bits <- T_2030 @[Trackers.scala 397:27] - node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) @[Decoupled.scala 21:42] - node T_2087 = and(T_2085, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2089 = and(T_2087, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_2091 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2089 : @[Counter.scala 43:17] - node T_2093 = eq(T_2091, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2095 = add(T_2091, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2096 = tail(T_2095, 1) @[Counter.scala 21:22] - T_2091 <= T_2096 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2097 = and(T_2089, T_2093) @[Counter.scala 44:20] - node T_2098 = mux(UInt<1>("h00"), T_2091, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2099 = mux(UInt<1>("h00"), T_2097, T_2087) @[Counters.scala 69:19] - node T_2100 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2101 = neq(state, UInt<4>("h00")) @[Trackers.scala 404:44] - node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 404:59] - node T_2104 = and(T_2101, T_2103) @[Trackers.scala 404:56] - node T_2105 = and(T_2100, T_2104) @[Counters.scala 124:64] - node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2110 = or(T_2107, T_2108) @[Package.scala 7:62] - node T_2111 = or(T_2110, T_2109) @[Package.scala 7:62] - node T_2112 = and(UInt<1>("h01"), T_2111) @[Definitions.scala 256:64] - node T_2113 = and(T_2105, T_2112) @[Counters.scala 67:47] - reg T_2115 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2113 : @[Counter.scala 43:17] - node T_2117 = eq(T_2115, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2119 = add(T_2115, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2120 = tail(T_2119, 1) @[Counter.scala 21:22] - T_2115 <= T_2120 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2121 = and(T_2113, T_2117) @[Counter.scala 44:20] - node T_2122 = mux(T_2112, T_2115, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2123 = mux(T_2112, T_2121, T_2105) @[Counters.scala 69:19] - reg T_2125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2127 = eq(T_2123, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2128 = and(T_2099, T_2127) @[Counters.scala 33:14] - when T_2128 : @[Counters.scala 33:24] - node T_2130 = add(T_2125, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2131 = tail(T_2130, 1) @[Counters.scala 33:37] - T_2125 <= T_2131 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2133 = eq(T_2099, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2134 = and(T_2123, T_2133) @[Counters.scala 34:16] - when T_2134 : @[Counters.scala 34:24] - node T_2136 = sub(T_2125, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2137 = tail(T_2136, 1) @[Counters.scala 34:37] - T_2125 <= T_2137 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2139 = gt(T_2125, UInt<1>("h00")) @[Counters.scala 126:27] - T_2065.pending <= T_2139 @[Counters.scala 126:20] - T_2065.up.idx <= T_2098 @[Counters.scala 127:19] - T_2065.up.done <= T_2099 @[Counters.scala 128:20] - T_2065.down.idx <= T_2122 @[Counters.scala 129:21] - T_2065.down.done <= T_2123 @[Counters.scala 130:22] - node T_2140 = eq(state, UInt<4>("h05")) @[Trackers.scala 406:18] - node T_2142 = neq(pending_iprbs, UInt<1>("h00")) @[Trackers.scala 406:55] - node T_2143 = or(T_2142, T_2065.pending) @[Trackers.scala 406:59] - node T_2145 = eq(T_2143, UInt<1>("h00")) @[Trackers.scala 406:39] - node T_2146 = and(T_2140, T_2145) @[Trackers.scala 406:36] - when T_2146 : @[Trackers.scala 406:85] - state <= T_2056 @[Trackers.scala 407:15] - skip @[Trackers.scala 406:85] - node T_2148 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2149 = eq(state, UInt<4>("h00")) @[Trackers.scala 254:19] - node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) @[Trackers.scala 254:12] - node T_2151 = and(T_2150, io.inner.release.bits.voluntary) @[Trackers.scala 254:76] - node T_2154 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2155 = and(T_2151, T_2154) @[Trackers.scala 254:95] - node T_2156 = and(T_2148, T_2155) @[Counters.scala 123:62] - node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2161 = or(T_2158, T_2159) @[Package.scala 7:62] - node T_2162 = or(T_2161, T_2160) @[Package.scala 7:62] - node T_2163 = and(UInt<1>("h01"), T_2162) @[Definitions.scala 256:64] - node T_2164 = and(T_2156, T_2163) @[Counters.scala 67:47] - reg T_2166 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2164 : @[Counter.scala 43:17] - node T_2168 = eq(T_2166, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2170 = add(T_2166, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2171 = tail(T_2170, 1) @[Counter.scala 21:22] - T_2166 <= T_2171 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2172 = and(T_2164, T_2168) @[Counter.scala 44:20] - node T_2173 = mux(T_2163, T_2166, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2174 = mux(T_2163, T_2172, T_2156) @[Counters.scala 69:19] - node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2176 = neq(state, UInt<4>("h00")) @[Trackers.scala 256:40] - node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) @[Definitions.scala 277:59] - node T_2180 = and(T_2176, T_2179) @[Trackers.scala 256:52] - node T_2181 = and(T_2175, T_2180) @[Counters.scala 124:64] - wire T_2189 : UInt<3>[1] @[Definitions.scala 853:34] - T_2189 is invalid @[Definitions.scala 853:34] - T_2189[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) @[Package.scala 7:47] - node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) @[Definitions.scala 274:33] - node T_2194 = and(UInt<1>("h01"), T_2193) @[Definitions.scala 274:27] - node T_2195 = and(T_2181, T_2194) @[Counters.scala 67:47] - reg T_2197 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2195 : @[Counter.scala 43:17] - node T_2199 = eq(T_2197, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2201 = add(T_2197, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2202 = tail(T_2201, 1) @[Counter.scala 21:22] - T_2197 <= T_2202 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2203 = and(T_2195, T_2199) @[Counter.scala 44:20] - node T_2204 = mux(T_2194, T_2197, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2205 = mux(T_2194, T_2203, T_2181) @[Counters.scala 69:19] - reg T_2207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2209 = eq(T_2205, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2210 = and(T_2174, T_2209) @[Counters.scala 33:14] - when T_2210 : @[Counters.scala 33:24] - node T_2212 = add(T_2207, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2213 = tail(T_2212, 1) @[Counters.scala 33:37] - T_2207 <= T_2213 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2215 = eq(T_2174, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2216 = and(T_2205, T_2215) @[Counters.scala 34:16] - when T_2216 : @[Counters.scala 34:24] - node T_2218 = sub(T_2207, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2219 = tail(T_2218, 1) @[Counters.scala 34:37] - T_2207 <= T_2219 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2221 = gt(T_2207, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ignt_counter.pending <= T_2221 @[Counters.scala 126:20] - vol_ignt_counter.up.idx <= T_2173 @[Counters.scala 127:19] - vol_ignt_counter.up.done <= T_2174 @[Counters.scala 128:20] - vol_ignt_counter.down.idx <= T_2204 @[Counters.scala 129:21] - vol_ignt_counter.down.done <= T_2205 @[Counters.scala 130:22] - node T_2222 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2223 = and(T_2222, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2224 = and(T_2223, io.inner.release.valid) @[Trackers.scala 245:75] - when T_2224 : @[Trackers.scala 259:30] - xact_addr_block <= io.inner.release.bits.addr_block @[Trackers.scala 260:23] - node T_2226 = not(UInt<8>("h00")) @[Trackers.scala 264:28] - pending_irel_data <= T_2226 @[Trackers.scala 264:25] - state <= UInt<4>("h07") @[Trackers.scala 265:13] - skip @[Trackers.scala 259:30] - node T_2227 = eq(state, UInt<4>("h00")) @[Trackers.scala 245:40] - node T_2228 = and(T_2227, io.alloc.irel.should) @[Trackers.scala 245:51] - node T_2229 = and(T_2228, io.inner.release.valid) @[Trackers.scala 245:75] - node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2231 = and(T_2230, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2232 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2233 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2234 = or(T_2232, T_2233) @[Package.scala 7:62] - node T_2236 = eq(T_2234, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2237 = and(T_2231, T_2236) @[Broadcast.scala 160:50] - node T_2239 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2240 = and(T_2237, T_2239) @[Broadcast.scala 161:63] - node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2243 = eq(T_2241, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2244 = and(T_2240, T_2243) @[Broadcast.scala 162:44] - node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2247 = eq(T_2245, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2248 = and(T_2244, T_2247) @[Broadcast.scala 163:49] - node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2251 = and(T_2248, T_2250) @[Broadcast.scala 164:49] - node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2253 = bits(T_2252, 0, 0) @[Trackers.scala 318:60] - node T_2254 = and(sending_orel, T_2253) @[Trackers.scala 318:40] - node T_2255 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2257 = and(T_2255, T_2256) @[Trackers.scala 319:47] - node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2261 = or(T_2258, T_2259) @[Package.scala 7:62] - node T_2262 = or(T_2261, T_2260) @[Package.scala 7:62] - node T_2263 = or(T_2254, T_2257) @[Trackers.scala 320:39] - node T_2264 = and(T_2262, T_2263) @[Trackers.scala 320:19] - node T_2266 = eq(T_2264, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2267 = and(T_2251, T_2266) @[Broadcast.scala 165:52] - node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2271 = and(T_2268, T_2270) @[Trackers.scala 387:61] - node T_2272 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2273 = and(T_2271, T_2272) @[Trackers.scala 388:51] - node T_2274 = or(T_2267, T_2273) @[Trackers.scala 246:47] - node T_2275 = and(T_2274, io.inner.release.valid) @[Trackers.scala 246:66] - node T_2276 = or(T_2229, T_2275) @[Trackers.scala 268:41] - node T_2277 = and(T_2276, io.inner.release.ready) @[Trackers.scala 268:61] - when T_2277 : @[Trackers.scala 269:22] - node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2282 = or(T_2279, T_2280) @[Package.scala 7:62] - node T_2283 = or(T_2282, T_2281) @[Package.scala 7:62] - node T_2284 = and(UInt<1>("h01"), T_2283) @[Definitions.scala 256:64] - node T_2286 = eq(T_2284, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2289 = or(T_2286, T_2288) @[Definitions.scala 141:57] - when T_2289 : @[Trackers.scala 270:32] - when io.inner.release.bits.voluntary : @[Trackers.scala 271:40] - xact_vol_ir_r_type <= io.inner.release.bits.r_type @[Trackers.scala 272:30] - xact_vol_ir_src <= io.inner.release.bits.client_id @[Trackers.scala 273:27] - xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id @[Trackers.scala 274:38] - skip @[Trackers.scala 271:40] - node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2294 = or(T_2291, T_2292) @[Package.scala 7:62] - node T_2295 = or(T_2294, T_2293) @[Package.scala 7:62] - node T_2296 = and(UInt<1>("h01"), T_2295) @[Definitions.scala 256:64] - node T_2297 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2301 = or(T_2298, T_2299) @[Package.scala 7:62] - node T_2302 = or(T_2301, T_2300) @[Package.scala 7:62] - node T_2303 = and(T_2297, T_2302) @[Trackers.scala 122:38] - node T_2304 = bits(T_2303, 0, 0) @[Bitwise.scala 33:15] - node T_2307 = mux(T_2304, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2308 = not(T_2307) @[Trackers.scala 92:5] - node T_2310 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2311 = not(T_2310) @[Trackers.scala 92:34] - node T_2312 = or(T_2308, T_2311) @[Trackers.scala 92:32] - node T_2314 = mux(T_2296, T_2312, UInt<1>("h00")) @[Trackers.scala 278:33] - pending_irel_data <= T_2314 @[Trackers.scala 278:27] - skip @[Trackers.scala 270:32] - node T_2316 = eq(T_2289, UInt<1>("h00")) @[Trackers.scala 270:32] - when T_2316 : @[Trackers.scala 281:20] - node T_2317 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2321 = or(T_2318, T_2319) @[Package.scala 7:62] - node T_2322 = or(T_2321, T_2320) @[Package.scala 7:62] - node T_2323 = and(T_2317, T_2322) @[Trackers.scala 122:38] - node T_2324 = bits(T_2323, 0, 0) @[Bitwise.scala 33:15] - node T_2327 = mux(T_2324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2328 = not(T_2327) @[Trackers.scala 92:5] - node T_2330 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2331 = not(T_2330) @[Trackers.scala 92:34] - node T_2332 = or(T_2328, T_2331) @[Trackers.scala 92:32] - node T_2333 = and(pending_irel_data, T_2332) @[Trackers.scala 282:49] - pending_irel_data <= T_2333 @[Trackers.scala 282:27] - skip @[Trackers.scala 281:20] - skip @[Trackers.scala 269:22] - node T_2334 = eq(state, UInt<4>("h03")) @[Package.scala 7:47] - node T_2335 = eq(state, UInt<4>("h04")) @[Package.scala 7:47] - node T_2336 = eq(state, UInt<4>("h05")) @[Package.scala 7:47] - node T_2337 = eq(state, UInt<4>("h07")) @[Package.scala 7:47] - node T_2338 = or(T_2334, T_2335) @[Package.scala 7:62] - node T_2339 = or(T_2338, T_2336) @[Package.scala 7:62] - node T_2340 = or(T_2339, T_2337) @[Package.scala 7:62] - node T_2341 = and(T_2340, vol_ignt_counter.pending) @[Trackers.scala 292:87] - node T_2343 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 294:51] - node T_2344 = or(T_2343, vol_ognt_counter.pending) @[Trackers.scala 294:55] - node T_2346 = eq(T_2344, UInt<1>("h00")) @[Trackers.scala 294:31] - node T_2347 = and(T_2341, T_2346) @[Trackers.scala 293:56] - io.inner.grant.valid <= T_2347 @[Trackers.scala 292:26] - wire T_2379 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 773:19] - T_2379 is invalid @[Definitions.scala 773:19] - T_2379.client_id <= xact_vol_ir_src @[Definitions.scala 774:19] - T_2379.voluntary <= UInt<1>("h01") @[Definitions.scala 775:19] - T_2379.r_type <= xact_vol_ir_r_type @[Definitions.scala 776:16] - T_2379.client_xact_id <= xact_vol_ir_client_xact_id @[Definitions.scala 777:24] - T_2379.addr_block <= xact_addr_block @[Definitions.scala 778:20] - T_2379.addr_beat <= UInt<1>("h00") @[Definitions.scala 779:19] - T_2379.data <= UInt<1>("h00") @[Definitions.scala 780:14] - wire T_2440 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_2440 is invalid @[Definitions.scala 882:19] - T_2440.client_id <= T_2379.client_id @[Definitions.scala 883:19] - T_2440.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 884:25] - T_2440.g_type <= UInt<3>("h00") @[Definitions.scala 885:16] - T_2440.client_xact_id <= T_2379.client_xact_id @[Definitions.scala 886:24] - T_2440.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 887:25] - T_2440.addr_beat <= UInt<1>("h00") @[Definitions.scala 888:19] - T_2440.data <= UInt<1>("h00") @[Definitions.scala 889:14] - io.inner.grant.bits <- T_2440 @[Trackers.scala 296:25] - node scoreboard_1 = neq(pending_irel_data, UInt<1>("h00")) @[Trackers.scala 298:38] - node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2470 = and(T_2469, io.inner.release.bits.voluntary) @[Broadcast.scala 159:61] - node T_2471 = eq(state, UInt<4>("h00")) @[Package.scala 7:47] - node T_2472 = eq(state, UInt<4>("h08")) @[Package.scala 7:47] - node T_2473 = or(T_2471, T_2472) @[Package.scala 7:62] - node T_2475 = eq(T_2473, UInt<1>("h00")) @[Broadcast.scala 161:26] - node T_2476 = and(T_2470, T_2475) @[Broadcast.scala 160:50] - node T_2478 = eq(all_pending_done, UInt<1>("h00")) @[Broadcast.scala 162:26] - node T_2479 = and(T_2476, T_2478) @[Broadcast.scala 161:63] - node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2482 = eq(T_2480, UInt<1>("h00")) @[Broadcast.scala 163:26] - node T_2483 = and(T_2479, T_2482) @[Broadcast.scala 162:44] - node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_2486 = eq(T_2484, UInt<1>("h00")) @[Broadcast.scala 164:26] - node T_2487 = and(T_2483, T_2486) @[Broadcast.scala 163:49] - node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Broadcast.scala 165:26] - node T_2490 = and(T_2487, T_2489) @[Broadcast.scala 164:49] - node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) @[Trackers.scala 318:60] - node T_2492 = bits(T_2491, 0, 0) @[Trackers.scala 318:60] - node T_2493 = and(sending_orel, T_2492) @[Trackers.scala 318:40] - node T_2494 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) @[Trackers.scala 319:64] - node T_2496 = and(T_2494, T_2495) @[Trackers.scala 319:47] - node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2500 = or(T_2497, T_2498) @[Package.scala 7:62] - node T_2501 = or(T_2500, T_2499) @[Package.scala 7:62] - node T_2502 = or(T_2493, T_2496) @[Trackers.scala 320:39] - node T_2503 = and(T_2501, T_2502) @[Trackers.scala 320:19] - node T_2505 = eq(T_2503, UInt<1>("h00")) @[Broadcast.scala 166:26] - node T_2506 = and(T_2490, T_2505) @[Broadcast.scala 165:52] - node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) @[Definitions.scala 117:47] - node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) @[Trackers.scala 388:26] - node T_2510 = and(T_2507, T_2509) @[Trackers.scala 387:61] - node T_2511 = eq(state, UInt<4>("h05")) @[Trackers.scala 389:32] - node T_2512 = and(T_2510, T_2511) @[Trackers.scala 388:51] - node T_2513 = or(T_2506, T_2512) @[Broadcast.scala 171:44] - io.inner.release.ready <= T_2513 @[Broadcast.scala 171:26] - node T_2514 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2518 = or(T_2515, T_2516) @[Package.scala 7:62] - node T_2519 = or(T_2518, T_2517) @[Package.scala 7:62] - node T_2520 = and(T_2514, T_2519) @[Trackers.scala 166:20] - when T_2520 : @[Trackers.scala 166:42] - node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_2529 = bits(T_2521, 0, 0) @[Bitwise.scala 33:15] - node T_2532 = mux(T_2529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2533 = bits(T_2522, 0, 0) @[Bitwise.scala 33:15] - node T_2536 = mux(T_2533, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2537 = bits(T_2523, 0, 0) @[Bitwise.scala 33:15] - node T_2540 = mux(T_2537, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2541 = bits(T_2524, 0, 0) @[Bitwise.scala 33:15] - node T_2544 = mux(T_2541, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2545 = bits(T_2525, 0, 0) @[Bitwise.scala 33:15] - node T_2548 = mux(T_2545, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2549 = bits(T_2526, 0, 0) @[Bitwise.scala 33:15] - node T_2552 = mux(T_2549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2553 = bits(T_2527, 0, 0) @[Bitwise.scala 33:15] - node T_2556 = mux(T_2553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2557 = bits(T_2528, 0, 0) @[Bitwise.scala 33:15] - node T_2560 = mux(T_2557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2561 = cat(T_2536, T_2532) @[Cat.scala 20:58] - node T_2562 = cat(T_2544, T_2540) @[Cat.scala 20:58] - node T_2563 = cat(T_2562, T_2561) @[Cat.scala 20:58] - node T_2564 = cat(T_2552, T_2548) @[Cat.scala 20:58] - node T_2565 = cat(T_2560, T_2556) @[Cat.scala 20:58] - node T_2566 = cat(T_2565, T_2564) @[Cat.scala 20:58] - node T_2567 = cat(T_2566, T_2563) @[Cat.scala 20:58] - node T_2568 = not(T_2567) @[Trackers.scala 195:27] - node T_2569 = and(T_2568, io.inner.release.bits.data) @[Trackers.scala 195:34] - node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) @[Trackers.scala 195:55] - node T_2571 = or(T_2569, T_2570) @[Trackers.scala 195:46] - data_buffer[io.inner.release.bits.addr_beat] <= T_2571 @[Trackers.scala 195:23] - node T_2573 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 @[Trackers.scala 196:24] - skip @[Trackers.scala 166:42] - node T_2574 = eq(UInt<5>("h01"), UInt<5>("h01")) @[Consts.scala 36:32] - node T_2575 = eq(UInt<5>("h01"), UInt<5>("h07")) @[Consts.scala 36:49] - node T_2576 = or(T_2574, T_2575) @[Consts.scala 36:42] - node T_2578 = eq(UInt<5>("h01"), UInt<5>("h04")) @[Consts.scala 33:40] - node T_2579 = or(UInt<1>("h00"), T_2578) @[Consts.scala 33:33] - node T_2580 = or(T_2576, T_2579) @[Consts.scala 36:59] - node T_2581 = mux(T_2580, UInt<2>("h02"), coh.outer.state) @[Policies.scala 257:23] - wire T_2604 : {state : UInt<2>} @[Metadata.scala 158:20] - T_2604 is invalid @[Metadata.scala 158:20] - T_2604.state <= T_2581 @[Metadata.scala 159:16] - node T_2630 = neq(state, UInt<4>("h00")) @[Trackers.scala 331:17] - node T_2631 = or(T_2630, io.alloc.irel.should) @[Trackers.scala 331:28] - when T_2631 : @[Trackers.scala 331:53] - node T_2633 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2637 = or(T_2634, T_2635) @[Package.scala 7:62] - node T_2638 = or(T_2637, T_2636) @[Package.scala 7:62] - node T_2639 = and(T_2633, T_2638) @[Trackers.scala 101:37] - node T_2640 = and(T_2639, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_2641 = bits(T_2640, 0, 0) @[Bitwise.scala 33:15] - node T_2644 = mux(T_2641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2646 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2647 = and(T_2644, T_2646) @[Trackers.scala 89:31] - node T_2648 = or(pending_orel_data, T_2647) @[Trackers.scala 332:47] - node T_2649 = or(T_2648, UInt<1>("h00")) @[Trackers.scala 333:58] - node T_2650 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2654 = or(T_2651, T_2652) @[Package.scala 7:62] - node T_2655 = or(T_2654, T_2653) @[Package.scala 7:62] - node T_2656 = and(T_2650, T_2655) @[Trackers.scala 122:38] - node T_2657 = bits(T_2656, 0, 0) @[Bitwise.scala 33:15] - node T_2660 = mux(T_2657, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_2661 = not(T_2660) @[Trackers.scala 92:5] - node T_2663 = dshl(UInt<1>("h01"), io.outer.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_2664 = not(T_2663) @[Trackers.scala 92:34] - node T_2665 = or(T_2661, T_2664) @[Trackers.scala 92:32] - node T_2666 = and(T_2649, T_2665) @[Trackers.scala 334:34] - pending_orel_data <= T_2666 @[Trackers.scala 332:25] - skip @[Trackers.scala 331:53] - when UInt<1>("h00") : @[Trackers.scala 337:33] - pending_orel_send <= UInt<1>("h01") @[Trackers.scala 337:53] - skip @[Trackers.scala 337:33] - node T_2668 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - when T_2668 : @[Trackers.scala 338:36] - node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2673 = or(T_2670, T_2671) @[Package.scala 7:62] - node T_2674 = or(T_2673, T_2672) @[Package.scala 7:62] - node T_2675 = and(UInt<1>("h01"), T_2674) @[Definitions.scala 256:64] - node T_2677 = eq(T_2675, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node T_2680 = or(T_2677, T_2679) @[Definitions.scala 141:57] - when T_2680 : @[Trackers.scala 339:44] - sending_orel <= UInt<1>("h01") @[Trackers.scala 339:59] - skip @[Trackers.scala 339:44] - node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2686 = or(T_2683, T_2684) @[Package.scala 7:62] - node T_2687 = or(T_2686, T_2685) @[Package.scala 7:62] - node T_2688 = and(UInt<1>("h01"), T_2687) @[Definitions.scala 256:64] - node T_2690 = eq(T_2688, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_2693 = or(T_2690, T_2692) @[Definitions.scala 142:56] - when T_2693 : @[Trackers.scala 340:44] - sending_orel <= UInt<1>("h00") @[Trackers.scala 340:59] - skip @[Trackers.scala 340:44] - pending_orel_send <= UInt<1>("h00") @[Trackers.scala 341:25] - skip @[Trackers.scala 338:36] - node T_2697 = and(io.outer.release.ready, io.outer.release.valid) @[Decoupled.scala 21:42] - node T_2700 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 259:37] - node T_2701 = and(io.outer.release.bits.voluntary, T_2700) @[Trackers.scala 348:51] - node T_2702 = and(T_2697, T_2701) @[Counters.scala 123:62] - node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2707 = or(T_2704, T_2705) @[Package.scala 7:62] - node T_2708 = or(T_2707, T_2706) @[Package.scala 7:62] - node T_2709 = and(UInt<1>("h01"), T_2708) @[Definitions.scala 256:64] - node T_2710 = and(T_2702, T_2709) @[Counters.scala 67:47] - reg T_2712 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2710 : @[Counter.scala 43:17] - node T_2714 = eq(T_2712, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2716 = add(T_2712, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2717 = tail(T_2716, 1) @[Counter.scala 21:22] - T_2712 <= T_2717 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2718 = and(T_2710, T_2714) @[Counter.scala 44:20] - node T_2719 = mux(T_2709, T_2712, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2720 = mux(T_2709, T_2718, T_2702) @[Counters.scala 69:19] - node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) @[Definitions.scala 277:59] - node T_2725 = and(T_2721, T_2724) @[Counters.scala 124:64] - wire T_2733 : UInt<3>[1] @[Definitions.scala 853:34] - T_2733 is invalid @[Definitions.scala 853:34] - T_2733[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) @[Package.scala 7:47] - node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) @[Definitions.scala 274:33] - node T_2738 = and(UInt<1>("h01"), T_2737) @[Definitions.scala 274:27] - node T_2739 = and(T_2725, T_2738) @[Counters.scala 67:47] - reg T_2741 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2739 : @[Counter.scala 43:17] - node T_2743 = eq(T_2741, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2745 = add(T_2741, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2746 = tail(T_2745, 1) @[Counter.scala 21:22] - T_2741 <= T_2746 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2747 = and(T_2739, T_2743) @[Counter.scala 44:20] - node T_2748 = mux(T_2738, T_2741, UInt<1>("h00")) @[Counters.scala 68:18] - node T_2749 = mux(T_2738, T_2747, T_2725) @[Counters.scala 69:19] - reg T_2751 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2753 = eq(T_2749, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2754 = and(T_2720, T_2753) @[Counters.scala 33:14] - when T_2754 : @[Counters.scala 33:24] - node T_2756 = add(T_2751, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2757 = tail(T_2756, 1) @[Counters.scala 33:37] - T_2751 <= T_2757 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2759 = eq(T_2720, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2760 = and(T_2749, T_2759) @[Counters.scala 34:16] - when T_2760 : @[Counters.scala 34:24] - node T_2762 = sub(T_2751, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2763 = tail(T_2762, 1) @[Counters.scala 34:37] - T_2751 <= T_2763 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2765 = gt(T_2751, UInt<1>("h00")) @[Counters.scala 126:27] - vol_ognt_counter.pending <= T_2765 @[Counters.scala 126:20] - vol_ognt_counter.up.idx <= T_2719 @[Counters.scala 127:19] - vol_ognt_counter.up.done <= T_2720 @[Counters.scala 128:20] - vol_ognt_counter.down.idx <= T_2748 @[Counters.scala 129:21] - vol_ognt_counter.down.done <= T_2749 @[Counters.scala 130:22] - node T_2767 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 351:31] - node T_2768 = eq(state, UInt<4>("h07")) @[Trackers.scala 352:14] - node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2772 = or(T_2769, T_2770) @[Package.scala 7:62] - node T_2773 = or(T_2772, T_2771) @[Package.scala 7:62] - node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) @[Trackers.scala 353:26] - node T_2775 = bits(T_2774, 0, 0) @[Trackers.scala 353:26] - node T_2776 = mux(T_2773, T_2775, pending_orel_send) @[Trackers.scala 352:32] - node T_2777 = and(T_2768, T_2776) @[Trackers.scala 352:26] - node T_2778 = neq(state, UInt<4>("h00")) @[Trackers.scala 356:13] - node T_2779 = and(T_2778, io.alloc.irel.matches) @[Trackers.scala 356:24] - node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_2783 = or(T_2780, T_2781) @[Package.scala 7:62] - node T_2784 = or(T_2783, T_2782) @[Package.scala 7:62] - node T_2785 = and(T_2779, T_2784) @[Trackers.scala 356:49] - node T_2786 = and(T_2785, io.inner.release.valid) @[Trackers.scala 357:29] - node T_2787 = mux(UInt<1>("h01"), T_2777, T_2786) @[Trackers.scala 351:49] - node T_2788 = and(T_2767, T_2787) @[Trackers.scala 351:43] - io.outer.release.valid <= T_2788 @[Trackers.scala 351:28] - node T_2791 = eq(T_2604.state, UInt<2>("h02")) @[Package.scala 7:47] - node T_2792 = mux(T_2791, UInt<3>("h00"), UInt<3>("h03")) @[Policies.scala 245:23] - node T_2793 = mux(T_2791, UInt<3>("h01"), UInt<3>("h04")) @[Policies.scala 246:23] - node T_2794 = mux(T_2791, UInt<3>("h02"), UInt<3>("h05")) @[Policies.scala 247:23] - node T_2795 = eq(UInt<5>("h013"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2796 = mux(T_2795, T_2794, UInt<3>("h05")) @[Mux.scala 46:16] - node T_2797 = eq(UInt<5>("h011"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2798 = mux(T_2797, T_2793, T_2796) @[Mux.scala 46:16] - node T_2799 = eq(UInt<5>("h010"), UInt<5>("h010")) @[Mux.scala 46:19] - node T_2800 = mux(T_2799, T_2792, T_2798) @[Mux.scala 46:16] - wire T_2828 : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} @[Definitions.scala 754:19] - T_2828 is invalid @[Definitions.scala 754:19] - T_2828.r_type <= T_2800 @[Definitions.scala 755:16] - T_2828.client_xact_id <= UInt<1>("h00") @[Definitions.scala 756:24] - T_2828.addr_block <= xact_addr_block @[Definitions.scala 757:20] - T_2828.addr_beat <= vol_ognt_counter.up.idx @[Definitions.scala 758:19] - T_2828.data <= data_buffer[vol_ognt_counter.up.idx] @[Definitions.scala 759:14] - T_2828.voluntary <= UInt<1>("h01") @[Definitions.scala 760:19] - io.outer.release.bits <- T_2828 @[Trackers.scala 359:27] - when vol_ognt_counter.pending : @[Trackers.scala 365:37] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 365:60] - skip @[Trackers.scala 365:37] - node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h00")) @[Broadcast.scala 182:15] - node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_2862 = and(T_2860, UInt<1>("h01")) @[Counters.scala 123:62] - node T_2864 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_2871 : UInt<3>[1] @[Definitions.scala 355:35] - T_2871 is invalid @[Definitions.scala 355:35] - T_2871[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) @[Package.scala 7:47] - node T_2874 = and(T_2864, T_2873) @[Definitions.scala 231:89] - node T_2875 = and(T_2862, T_2874) @[Counters.scala 67:47] - reg T_2877 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2875 : @[Counter.scala 43:17] - node T_2879 = eq(T_2877, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2881 = add(T_2877, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2882 = tail(T_2881, 1) @[Counter.scala 21:22] - T_2877 <= T_2882 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2883 = and(T_2875, T_2879) @[Counter.scala 44:20] - node T_2884 = mux(T_2874, T_2877, xact_addr_beat) @[Counters.scala 68:18] - node T_2885 = mux(T_2874, T_2883, T_2862) @[Counters.scala 69:19] - node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) @[Definitions.scala 277:59] - node T_2891 = eq(T_2889, UInt<1>("h00")) @[Trackers.scala 599:33] - node T_2892 = and(T_2886, T_2891) @[Counters.scala 124:64] - wire T_2900 : UInt<3>[1] @[Definitions.scala 853:34] - T_2900 is invalid @[Definitions.scala 853:34] - T_2900[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) @[Package.scala 7:47] - node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) @[Definitions.scala 274:33] - node T_2905 = and(UInt<1>("h01"), T_2904) @[Definitions.scala 274:27] - node T_2906 = and(T_2892, T_2905) @[Counters.scala 67:47] - reg T_2908 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_2906 : @[Counter.scala 43:17] - node T_2910 = eq(T_2908, UInt<3>("h07")) @[Counter.scala 20:24] - node T_2912 = add(T_2908, UInt<1>("h01")) @[Counter.scala 21:22] - node T_2913 = tail(T_2912, 1) @[Counter.scala 21:22] - T_2908 <= T_2913 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_2914 = and(T_2906, T_2910) @[Counter.scala 44:20] - node T_2915 = mux(T_2905, T_2908, xact_addr_beat) @[Counters.scala 68:18] - node T_2916 = mux(T_2905, T_2914, T_2892) @[Counters.scala 69:19] - reg T_2918 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_2920 = eq(T_2916, UInt<1>("h00")) @[Counters.scala 33:17] - node T_2921 = and(T_2885, T_2920) @[Counters.scala 33:14] - when T_2921 : @[Counters.scala 33:24] - node T_2923 = add(T_2918, UInt<1>("h01")) @[Counters.scala 33:37] - node T_2924 = tail(T_2923, 1) @[Counters.scala 33:37] - T_2918 <= T_2924 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_2926 = eq(T_2885, UInt<1>("h00")) @[Counters.scala 34:19] - node T_2927 = and(T_2916, T_2926) @[Counters.scala 34:16] - when T_2927 : @[Counters.scala 34:24] - node T_2929 = sub(T_2918, UInt<1>("h01")) @[Counters.scala 34:37] - node T_2930 = tail(T_2929, 1) @[Counters.scala 34:37] - T_2918 <= T_2930 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_2932 = gt(T_2918, UInt<1>("h00")) @[Counters.scala 126:27] - ognt_counter.pending <= T_2932 @[Counters.scala 126:20] - ognt_counter.up.idx <= T_2884 @[Counters.scala 127:19] - ognt_counter.up.done <= T_2885 @[Counters.scala 128:20] - ognt_counter.down.idx <= T_2915 @[Counters.scala 129:21] - ognt_counter.down.done <= T_2916 @[Counters.scala 130:22] - node T_2933 = eq(state, UInt<4>("h06")) @[Trackers.scala 602:13] - node T_2935 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Trackers.scala 602:36] - node T_2936 = and(T_2933, T_2935) @[Trackers.scala 602:33] - node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) @[Trackers.scala 605:30] - node T_2938 = bits(T_2937, 0, 0) @[Trackers.scala 605:30] - node T_2940 = eq(T_2938, UInt<1>("h00")) @[Trackers.scala 605:13] - wire T_2949 : UInt<3>[3] @[Definitions.scala 354:26] - T_2949 is invalid @[Definitions.scala 354:26] - T_2949[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_2949[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_2949[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_2951 = eq(xact_iacq.a_type, T_2949[0]) @[Package.scala 7:47] - node T_2952 = eq(xact_iacq.a_type, T_2949[1]) @[Package.scala 7:47] - node T_2953 = eq(xact_iacq.a_type, T_2949[2]) @[Package.scala 7:47] - node T_2954 = or(T_2951, T_2952) @[Package.scala 7:62] - node T_2955 = or(T_2954, T_2953) @[Package.scala 7:62] - node T_2956 = and(xact_iacq.is_builtin_type, T_2955) @[Definitions.scala 228:55] - node T_2958 = eq(T_2956, UInt<1>("h00")) @[Trackers.scala 610:30] - node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_2961 = and(T_2959, T_2960) @[Trackers.scala 462:61] - node T_2962 = and(T_2961, scoreboard_6) @[Trackers.scala 463:53] - node T_2963 = and(io.inner.acquire.valid, T_2962) @[Trackers.scala 611:39] - node T_2964 = or(T_2958, T_2963) @[Trackers.scala 610:51] - node T_2965 = and(scoreboard_6, T_2964) @[Trackers.scala 610:26] - node T_2966 = mux(UInt<1>("h01"), T_2940, T_2965) @[Trackers.scala 604:14] - node T_2967 = or(xact_allocate, T_2966) @[Trackers.scala 603:24] - node T_2968 = and(T_2936, T_2967) @[Trackers.scala 602:57] - io.outer.acquire.valid <= T_2968 @[Trackers.scala 601:28] - node T_2971 = eq(xact_op_code, UInt<5>("h01")) @[Consts.scala 36:32] - node T_2972 = eq(xact_op_code, UInt<5>("h07")) @[Consts.scala 36:49] - node T_2973 = or(T_2971, T_2972) @[Consts.scala 36:42] - node T_2974 = bits(xact_op_code, 3, 3) @[Consts.scala 33:29] - node T_2975 = eq(xact_op_code, UInt<5>("h04")) @[Consts.scala 33:40] - node T_2976 = or(T_2974, T_2975) @[Consts.scala 33:33] - node T_2977 = or(T_2973, T_2976) @[Consts.scala 36:59] - node T_2978 = eq(xact_op_code, UInt<5>("h03")) @[Consts.scala 37:54] - node T_2979 = or(T_2977, T_2978) @[Consts.scala 37:47] - node T_2980 = eq(xact_op_code, UInt<5>("h06")) @[Consts.scala 37:71] - node T_2981 = or(T_2979, T_2980) @[Consts.scala 37:64] - node T_2982 = mux(T_2981, UInt<1>("h01"), UInt<1>("h00")) @[Policies.scala 240:8] - node T_2984 = cat(xact_op_code, UInt<1>("h01")) @[Cat.scala 20:58] - wire T_3015 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3015 is invalid @[Definitions.scala 417:19] - T_3015.is_builtin_type <= UInt<1>("h00") @[Definitions.scala 418:25] - T_3015.a_type <= T_2982 @[Definitions.scala 419:16] - T_3015.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3015.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3015.addr_beat <= UInt<1>("h00") @[Definitions.scala 422:19] - T_3015.data <= UInt<1>("h00") @[Definitions.scala 423:14] - T_3015.union <= T_2984 @[Definitions.scala 424:15] - node T_3067 = or(UInt<3>("h00"), xact_addr_byte) @[Definitions.scala 386:49] - node T_3068 = bits(T_3067, 2, 0) @[Definitions.scala 386:61] - node T_3070 = or(UInt<2>("h00"), xact_op_size) @[Definitions.scala 387:61] - node T_3071 = bits(T_3070, 1, 0) @[Definitions.scala 387:76] - node T_3073 = or(UInt<5>("h00"), xact_op_code) @[Definitions.scala 388:36] - node T_3074 = bits(T_3073, 4, 0) @[Definitions.scala 388:45] - node T_3076 = or(UInt<8>("h00"), wmask_buffer[ognt_counter.up.idx]) @[Definitions.scala 389:46] - node T_3077 = bits(T_3076, 7, 0) @[Definitions.scala 389:54] - node T_3080 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3081 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3082 = cat(T_3081, T_3080) @[Cat.scala 20:58] - node T_3084 = cat(T_3071, T_3074) @[Cat.scala 20:58] - node T_3085 = cat(T_3084, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3087 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3089 = cat(T_3077, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3091 = cat(T_3074, UInt<1>("h00")) @[Cat.scala 20:58] - node T_3092 = cat(T_3068, T_3071) @[Cat.scala 20:58] - node T_3093 = cat(T_3092, T_3091) @[Cat.scala 20:58] - node T_3095 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3097 = cat(UInt<5>("h01"), UInt<1>("h00")) @[Cat.scala 20:58] - node T_3098 = eq(UInt<3>("h06"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3099 = mux(T_3098, T_3097, UInt<1>("h00")) @[Mux.scala 46:16] - node T_3100 = eq(UInt<3>("h05"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3101 = mux(T_3100, T_3095, T_3099) @[Mux.scala 46:16] - node T_3102 = eq(UInt<3>("h04"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3103 = mux(T_3102, T_3093, T_3101) @[Mux.scala 46:16] - node T_3104 = eq(UInt<3>("h03"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3105 = mux(T_3104, T_3089, T_3103) @[Mux.scala 46:16] - node T_3106 = eq(UInt<3>("h02"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3107 = mux(T_3106, T_3087, T_3105) @[Mux.scala 46:16] - node T_3108 = eq(UInt<3>("h01"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3109 = mux(T_3108, T_3085, T_3107) @[Mux.scala 46:16] - node T_3110 = eq(UInt<3>("h00"), xact_iacq.a_type) @[Mux.scala 46:19] - node T_3111 = mux(T_3110, T_3082, T_3109) @[Mux.scala 46:16] - wire T_3140 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_3140 is invalid @[Definitions.scala 417:19] - T_3140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_3140.a_type <= xact_iacq.a_type @[Definitions.scala 419:16] - T_3140.client_xact_id <= UInt<1>("h00") @[Definitions.scala 420:24] - T_3140.addr_block <= xact_addr_block @[Definitions.scala 421:20] - T_3140.addr_beat <= ognt_counter.up.idx @[Definitions.scala 422:19] - T_3140.data <= data_buffer[ognt_counter.up.idx] @[Definitions.scala 423:14] - T_3140.union <= T_3111 @[Definitions.scala 424:15] - node T_3168 = mux(T_2857, T_3015, T_3140) @[Trackers.scala 614:10] - io.outer.acquire.bits <- T_3168 @[Trackers.scala 613:27] - node T_3196 = eq(state, UInt<4>("h06")) @[Trackers.scala 632:16] - node T_3197 = and(T_3196, ognt_counter.up.done) @[Trackers.scala 632:36] - when T_3197 : @[Trackers.scala 632:61] - state <= UInt<4>("h07") @[Trackers.scala 632:69] - skip @[Trackers.scala 632:61] - when ognt_counter.pending : @[Trackers.scala 634:33] - io.outer.grant.ready <= UInt<1>("h01") @[Trackers.scala 634:56] - skip @[Trackers.scala 634:33] - node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3207 : UInt<3>[2] @[Definitions.scala 852:26] - T_3207 is invalid @[Definitions.scala 852:26] - T_3207[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3207[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) @[Package.scala 7:47] - node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) @[Package.scala 7:47] - node T_3211 = or(T_3209, T_3210) @[Package.scala 7:62] - node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) @[Definitions.scala 270:42] - node T_3214 = and(T_3199, T_3213) @[Trackers.scala 172:20] - when T_3214 : @[Trackers.scala 172:42] - node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) @[Bitwise.scala 13:51] - node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) @[Bitwise.scala 13:51] - node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) @[Bitwise.scala 13:51] - node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) @[Bitwise.scala 13:51] - node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) @[Bitwise.scala 13:51] - node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) @[Bitwise.scala 13:51] - node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) @[Bitwise.scala 13:51] - node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) @[Bitwise.scala 13:51] - node T_3223 = bits(T_3215, 0, 0) @[Bitwise.scala 33:15] - node T_3226 = mux(T_3223, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3227 = bits(T_3216, 0, 0) @[Bitwise.scala 33:15] - node T_3230 = mux(T_3227, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3231 = bits(T_3217, 0, 0) @[Bitwise.scala 33:15] - node T_3234 = mux(T_3231, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3235 = bits(T_3218, 0, 0) @[Bitwise.scala 33:15] - node T_3238 = mux(T_3235, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3239 = bits(T_3219, 0, 0) @[Bitwise.scala 33:15] - node T_3242 = mux(T_3239, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3243 = bits(T_3220, 0, 0) @[Bitwise.scala 33:15] - node T_3246 = mux(T_3243, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3247 = bits(T_3221, 0, 0) @[Bitwise.scala 33:15] - node T_3250 = mux(T_3247, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3251 = bits(T_3222, 0, 0) @[Bitwise.scala 33:15] - node T_3254 = mux(T_3251, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3255 = cat(T_3230, T_3226) @[Cat.scala 20:58] - node T_3256 = cat(T_3238, T_3234) @[Cat.scala 20:58] - node T_3257 = cat(T_3256, T_3255) @[Cat.scala 20:58] - node T_3258 = cat(T_3246, T_3242) @[Cat.scala 20:58] - node T_3259 = cat(T_3254, T_3250) @[Cat.scala 20:58] - node T_3260 = cat(T_3259, T_3258) @[Cat.scala 20:58] - node T_3261 = cat(T_3260, T_3257) @[Cat.scala 20:58] - node T_3262 = not(T_3261) @[Trackers.scala 195:27] - node T_3263 = and(T_3262, io.outer.grant.bits.data) @[Trackers.scala 195:34] - node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) @[Trackers.scala 195:55] - node T_3265 = or(T_3263, T_3264) @[Trackers.scala 195:46] - data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 @[Trackers.scala 195:23] - node T_3267 = not(UInt<8>("h00")) @[Trackers.scala 196:27] - wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 @[Trackers.scala 196:24] - skip @[Trackers.scala 172:42] - node T_3268 = or(scoreboard_3, ognt_counter.pending) @[Broadcast.scala 194:37] - node T_3269 = or(T_3268, vol_ognt_counter.pending) @[Broadcast.scala 194:61] - node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - node T_3276 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) @[Definitions.scala 277:59] - node T_3281 = eq(T_3279, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_3282 = and(T_3276, T_3281) @[Definitions.scala 278:89] - node T_3283 = and(T_3273, T_3282) @[Counters.scala 123:62] - wire T_3291 : UInt<3>[1] @[Definitions.scala 853:34] - T_3291 is invalid @[Definitions.scala 853:34] - T_3291[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) @[Package.scala 7:47] - node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) @[Definitions.scala 274:33] - node T_3296 = and(UInt<1>("h01"), T_3295) @[Definitions.scala 274:27] - node T_3297 = and(T_3283, T_3296) @[Counters.scala 67:47] - reg T_3299 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3297 : @[Counter.scala 43:17] - node T_3301 = eq(T_3299, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3303 = add(T_3299, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3304 = tail(T_3303, 1) @[Counter.scala 21:22] - T_3299 <= T_3304 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3305 = and(T_3297, T_3301) @[Counter.scala 44:20] - node T_3306 = mux(T_3296, T_3299, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3307 = mux(T_3296, T_3305, T_3283) @[Counters.scala 69:19] - node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_3310 = and(T_3308, UInt<1>("h01")) @[Counters.scala 124:64] - node T_3312 = and(T_3310, UInt<1>("h00")) @[Counters.scala 67:47] - reg T_3314 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3312 : @[Counter.scala 43:17] - node T_3316 = eq(T_3314, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3318 = add(T_3314, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3319 = tail(T_3318, 1) @[Counter.scala 21:22] - T_3314 <= T_3319 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3320 = and(T_3312, T_3316) @[Counter.scala 44:20] - node T_3321 = mux(UInt<1>("h00"), T_3314, UInt<1>("h00")) @[Counters.scala 68:18] - node T_3322 = mux(UInt<1>("h00"), T_3320, T_3310) @[Counters.scala 69:19] - reg T_3324 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_3326 = eq(T_3322, UInt<1>("h00")) @[Counters.scala 33:17] - node T_3327 = and(T_3307, T_3326) @[Counters.scala 33:14] - when T_3327 : @[Counters.scala 33:24] - node T_3329 = add(T_3324, UInt<1>("h01")) @[Counters.scala 33:37] - node T_3330 = tail(T_3329, 1) @[Counters.scala 33:37] - T_3324 <= T_3330 @[Counters.scala 33:30] - skip @[Counters.scala 33:24] - node T_3332 = eq(T_3307, UInt<1>("h00")) @[Counters.scala 34:19] - node T_3333 = and(T_3322, T_3332) @[Counters.scala 34:16] - when T_3333 : @[Counters.scala 34:24] - node T_3335 = sub(T_3324, UInt<1>("h01")) @[Counters.scala 34:37] - node T_3336 = tail(T_3335, 1) @[Counters.scala 34:37] - T_3324 <= T_3336 @[Counters.scala 34:30] - skip @[Counters.scala 34:24] - node T_3338 = gt(T_3324, UInt<1>("h00")) @[Counters.scala 126:27] - ifin_counter.pending <= T_3338 @[Counters.scala 126:20] - ifin_counter.up.idx <= T_3306 @[Counters.scala 127:19] - ifin_counter.up.done <= T_3307 @[Counters.scala 128:20] - ifin_counter.down.idx <= T_3321 @[Counters.scala 129:21] - ifin_counter.down.done <= T_3322 @[Counters.scala 130:22] - node T_3339 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3340 = and(T_3339, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3341 = and(T_3340, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3343 = eq(T_3341, UInt<1>("h00")) @[Trackers.scala 525:10] - when T_3343 : @[Trackers.scala 525:31] - node T_3345 = and(io.inner.release.ready, io.inner.release.valid) @[Decoupled.scala 21:42] - node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_3349 = or(T_3346, T_3347) @[Package.scala 7:62] - node T_3350 = or(T_3349, T_3348) @[Package.scala 7:62] - node T_3351 = and(T_3345, T_3350) @[Trackers.scala 101:37] - node T_3352 = and(T_3351, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3353 = bits(T_3352, 0, 0) @[Bitwise.scala 33:15] - node T_3356 = mux(T_3353, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3358 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) @[OneHot.scala 44:15] - node T_3359 = and(T_3356, T_3358) @[Trackers.scala 89:31] - node T_3360 = or(pending_ignt_data, T_3359) @[Trackers.scala 526:46] - node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) @[Decoupled.scala 21:42] - wire T_3370 : UInt<3>[2] @[Definitions.scala 852:26] - T_3370 is invalid @[Definitions.scala 852:26] - T_3370[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3370[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) @[Package.scala 7:47] - node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) @[Package.scala 7:47] - node T_3374 = or(T_3372, T_3373) @[Package.scala 7:62] - node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) @[Definitions.scala 270:42] - node T_3377 = and(T_3362, T_3376) @[Trackers.scala 101:37] - node T_3378 = and(T_3377, UInt<1>("h01")) @[Trackers.scala 101:58] - node T_3379 = bits(T_3378, 0, 0) @[Bitwise.scala 33:15] - node T_3382 = mux(T_3379, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3384 = dshl(UInt<1>("h01"), io.outer.grant.bits.addr_beat) @[OneHot.scala 44:15] - node T_3385 = and(T_3382, T_3384) @[Trackers.scala 89:31] - node T_3386 = or(T_3360, T_3385) @[Trackers.scala 527:77] - node T_3387 = or(T_3386, UInt<1>("h00")) @[Trackers.scala 528:75] - pending_ignt_data <= T_3387 @[Trackers.scala 526:25] - skip @[Trackers.scala 525:31] - node T_3388 = eq(state, UInt<4>("h00")) @[Trackers.scala 540:33] - node T_3389 = eq(state, UInt<4>("h01")) @[Trackers.scala 541:33] - node T_3390 = or(T_3388, T_3389) @[Trackers.scala 540:44] - node T_3392 = neq(pending_put_data, UInt<1>("h00")) @[Trackers.scala 542:44] - node T_3393 = or(T_3390, T_3392) @[Trackers.scala 541:49] - node T_3395 = eq(T_3393, UInt<1>("h00")) @[Trackers.scala 540:25] - node T_3412 = eq(UInt<3>("h06"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3413 = mux(T_3412, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_3414 = eq(UInt<3>("h05"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3415 = mux(T_3414, UInt<3>("h01"), T_3413) @[Mux.scala 46:16] - node T_3416 = eq(UInt<3>("h04"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3417 = mux(T_3416, UInt<3>("h04"), T_3415) @[Mux.scala 46:16] - node T_3418 = eq(UInt<3>("h03"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3419 = mux(T_3418, UInt<3>("h03"), T_3417) @[Mux.scala 46:16] - node T_3420 = eq(UInt<3>("h02"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3421 = mux(T_3420, UInt<3>("h03"), T_3419) @[Mux.scala 46:16] - node T_3422 = eq(UInt<3>("h01"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3423 = mux(T_3422, UInt<3>("h05"), T_3421) @[Mux.scala 46:16] - node T_3424 = eq(UInt<3>("h00"), ignt_q.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_3425 = mux(T_3424, UInt<3>("h04"), T_3423) @[Mux.scala 46:16] - node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h00")) @[Policies.scala 301:8] - wire T_3455 : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} @[Definitions.scala 882:19] - T_3455 is invalid @[Definitions.scala 882:19] - T_3455.client_id <= ignt_q.io.deq.bits.client_id @[Definitions.scala 883:19] - T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type @[Definitions.scala 884:25] - T_3455.g_type <= T_3426 @[Definitions.scala 885:16] - T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id @[Definitions.scala 886:24] - T_3455.manager_xact_id <= UInt<3>("h07") @[Definitions.scala 887:25] - T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat @[Definitions.scala 888:19] - T_3455.data <= data_buffer[ignt_data_idx] @[Definitions.scala 889:14] - node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_3491 : UInt<3>[1] @[Definitions.scala 853:34] - T_3491 is invalid @[Definitions.scala 853:34] - T_3491[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) @[Package.scala 7:47] - node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) @[Definitions.scala 274:33] - node T_3496 = and(UInt<1>("h01"), T_3495) @[Definitions.scala 274:27] - node T_3497 = and(T_3483, T_3496) @[Counters.scala 67:47] - reg T_3499 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_3497 : @[Counter.scala 43:17] - node T_3501 = eq(T_3499, UInt<3>("h07")) @[Counter.scala 20:24] - node T_3503 = add(T_3499, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3504 = tail(T_3503, 1) @[Counter.scala 21:22] - T_3499 <= T_3504 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node T_3505 = and(T_3497, T_3501) @[Counter.scala 44:20] - node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) @[Counters.scala 68:18] - node T_3507 = mux(T_3496, T_3505, T_3483) @[Counters.scala 69:19] - ignt_data_idx <= T_3506 @[Trackers.scala 551:19] - ignt_data_done <= T_3507 @[Trackers.scala 552:20] - ignt_q.io.deq.ready <= UInt<1>("h00") @[Trackers.scala 553:25] - node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h00")) @[Trackers.scala 554:10] - when T_3510 : @[Trackers.scala 554:37] - ignt_q.io.deq.ready <= ignt_data_done @[Trackers.scala 555:27] - io.inner.grant.bits <- T_3455 @[Trackers.scala 556:27] - io.inner.grant.bits.addr_beat <= ignt_data_idx @[Trackers.scala 557:37] - node T_3511 = eq(state, UInt<4>("h07")) @[Trackers.scala 558:19] - node T_3512 = and(T_3511, scoreboard_6) @[Trackers.scala 558:30] - when T_3512 : @[Trackers.scala 558:47] - node T_3514 = eq(T_3269, UInt<1>("h00")) @[Trackers.scala 559:33] - wire T_3522 : UInt<3>[2] @[Definitions.scala 852:26] - T_3522 is invalid @[Definitions.scala 852:26] - T_3522[0] <= UInt<3>("h05") @[Definitions.scala 852:26] - T_3522[1] <= UInt<3>("h04") @[Definitions.scala 852:26] - node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) @[Package.scala 7:47] - node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) @[Package.scala 7:47] - node T_3526 = or(T_3524, T_3525) @[Package.scala 7:62] - node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) @[Definitions.scala 270:42] - node T_3529 = dshr(pending_ignt_data, ignt_data_idx) @[Trackers.scala 562:32] - node T_3530 = bits(T_3529, 0, 0) @[Trackers.scala 562:32] - node T_3531 = mux(UInt<1>("h01"), T_3530, io.outer.grant.valid) @[Trackers.scala 561:16] - node T_3532 = mux(T_3528, T_3531, T_3395) @[Trackers.scala 560:14] - node T_3533 = and(T_3514, T_3532) @[Trackers.scala 559:51] - io.inner.grant.valid <= T_3533 @[Trackers.scala 559:30] - skip @[Trackers.scala 558:47] - skip @[Trackers.scala 554:37] - node T_3534 = eq(state, UInt<4>("h07")) @[Trackers.scala 569:36] - io.inner.finish.ready <= T_3534 @[Trackers.scala 569:27] - node T_3535 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3536 = and(T_3535, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3537 = and(T_3536, io.inner.acquire.valid) @[Trackers.scala 467:75] - when T_3537 : @[Broadcast.scala 196:28] - node T_3539 = not(UInt<1>("h00")) @[Broadcast.scala 70:29] - node T_3540 = not(io.incoherent[0]) @[Trackers.scala 383:46] - node T_3541 = and(T_3539, T_3540) @[Trackers.scala 383:44] - pending_iprbs <= T_3541 @[Trackers.scala 383:21] - skip @[Broadcast.scala 196:28] - node T_3542 = eq(state, UInt<4>("h00")) @[Trackers.scala 467:40] - node T_3543 = and(T_3542, io.alloc.iacq.should) @[Trackers.scala 467:51] - node T_3544 = and(T_3543, io.inner.acquire.valid) @[Trackers.scala 467:75] - node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) @[Trackers.scala 462:31] - node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) @[Trackers.scala 463:28] - node T_3548 = and(T_3546, T_3547) @[Trackers.scala 462:61] - node T_3549 = and(T_3548, scoreboard_6) @[Trackers.scala 463:53] - node T_3550 = or(UInt<1>("h00"), T_3549) @[Trackers.scala 468:47] - node T_3551 = and(T_3550, io.inner.acquire.valid) @[Trackers.scala 468:66] - node T_3552 = or(T_3544, T_3551) @[Broadcast.scala 200:54] - node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) @[Decoupled.scala 21:42] - wire T_3562 : UInt<3>[3] @[Definitions.scala 354:26] - T_3562 is invalid @[Definitions.scala 354:26] - T_3562[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_3562[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_3562[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) @[Package.scala 7:47] - node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) @[Package.scala 7:47] - node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) @[Package.scala 7:47] - node T_3567 = or(T_3564, T_3565) @[Package.scala 7:62] - node T_3568 = or(T_3567, T_3566) @[Package.scala 7:62] - node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) @[Definitions.scala 228:55] - node T_3570 = and(T_3553, T_3569) @[Trackers.scala 183:20] - node T_3571 = and(T_3570, T_3552) @[Trackers.scala 183:41] - when T_3571 : @[Trackers.scala 183:51] - node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) @[Definitions.scala 212:54] - node T_3596 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) @[Definitions.scala 212:54] - node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) @[Definitions.scala 212:54] - node T_3603 = or(T_3599, T_3602) @[Definitions.scala 190:56] - node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3606 = mux(T_3603, T_3604, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3607 = mux(T_3574, T_3596, T_3606) @[Definitions.scala 192:8] - node T_3608 = bits(T_3607, 0, 0) @[Bitwise.scala 13:51] - node T_3609 = bits(T_3607, 1, 1) @[Bitwise.scala 13:51] - node T_3610 = bits(T_3607, 2, 2) @[Bitwise.scala 13:51] - node T_3611 = bits(T_3607, 3, 3) @[Bitwise.scala 13:51] - node T_3612 = bits(T_3607, 4, 4) @[Bitwise.scala 13:51] - node T_3613 = bits(T_3607, 5, 5) @[Bitwise.scala 13:51] - node T_3614 = bits(T_3607, 6, 6) @[Bitwise.scala 13:51] - node T_3615 = bits(T_3607, 7, 7) @[Bitwise.scala 13:51] - node T_3616 = bits(T_3608, 0, 0) @[Bitwise.scala 33:15] - node T_3619 = mux(T_3616, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3620 = bits(T_3609, 0, 0) @[Bitwise.scala 33:15] - node T_3623 = mux(T_3620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3624 = bits(T_3610, 0, 0) @[Bitwise.scala 33:15] - node T_3627 = mux(T_3624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3628 = bits(T_3611, 0, 0) @[Bitwise.scala 33:15] - node T_3631 = mux(T_3628, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3632 = bits(T_3612, 0, 0) @[Bitwise.scala 33:15] - node T_3635 = mux(T_3632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3636 = bits(T_3613, 0, 0) @[Bitwise.scala 33:15] - node T_3639 = mux(T_3636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3640 = bits(T_3614, 0, 0) @[Bitwise.scala 33:15] - node T_3643 = mux(T_3640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3644 = bits(T_3615, 0, 0) @[Bitwise.scala 33:15] - node T_3647 = mux(T_3644, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_3648 = cat(T_3623, T_3619) @[Cat.scala 20:58] - node T_3649 = cat(T_3631, T_3627) @[Cat.scala 20:58] - node T_3650 = cat(T_3649, T_3648) @[Cat.scala 20:58] - node T_3651 = cat(T_3639, T_3635) @[Cat.scala 20:58] - node T_3652 = cat(T_3647, T_3643) @[Cat.scala 20:58] - node T_3653 = cat(T_3652, T_3651) @[Cat.scala 20:58] - node T_3654 = cat(T_3653, T_3650) @[Cat.scala 20:58] - node T_3655 = not(T_3654) @[Trackers.scala 186:29] - node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 186:35] - node T_3657 = and(T_3654, io.inner.acquire.bits.data) @[Trackers.scala 186:64] - node T_3658 = or(T_3656, T_3657) @[Trackers.scala 186:56] - data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 @[Trackers.scala 186:25] - node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) @[Definitions.scala 212:54] - node T_3683 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) @[Definitions.scala 212:54] - node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) @[Definitions.scala 212:54] - node T_3690 = or(T_3686, T_3689) @[Definitions.scala 190:56] - node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_3693 = mux(T_3690, T_3691, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_3694 = mux(T_3661, T_3683, T_3693) @[Definitions.scala 192:8] - node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) @[Trackers.scala 187:45] - wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 @[Trackers.scala 187:26] - skip @[Trackers.scala 183:51] - node T_3697 = or(UInt<1>("h00"), scoreboard_0) @[Trackers.scala 50:60] - node T_3698 = or(T_3697, scoreboard_1) @[Trackers.scala 50:60] - node T_3699 = or(T_3698, vol_ignt_counter.pending) @[Trackers.scala 50:60] - node T_3700 = or(T_3699, scoreboard_3) @[Trackers.scala 50:60] - node T_3701 = or(T_3700, vol_ognt_counter.pending) @[Trackers.scala 50:60] - node T_3702 = or(T_3701, ognt_counter.pending) @[Trackers.scala 50:60] - node T_3703 = or(T_3702, scoreboard_6) @[Trackers.scala 50:60] - node T_3704 = or(T_3703, ifin_counter.pending) @[Trackers.scala 50:60] - node T_3706 = eq(T_3704, UInt<1>("h00")) @[Trackers.scala 50:25] - all_pending_done <= T_3706 @[Trackers.scala 50:22] - node T_3707 = eq(state, UInt<4>("h07")) @[Trackers.scala 51:16] - node T_3708 = and(T_3707, all_pending_done) @[Trackers.scala 51:27] - when T_3708 : @[Trackers.scala 51:48] - state <= UInt<4>("h00") @[Trackers.scala 52:13] - wmask_buffer[0] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[1] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[2] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[3] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[4] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[5] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[6] <= UInt<1>("h00") @[Trackers.scala 200:35] - wmask_buffer[7] <= UInt<1>("h00") @[Trackers.scala 200:35] - skip @[Trackers.scala 51:48] - - module LockingRRArbiter_5 : + node T_1796 = eq(state, UInt<4>("h0")) + node T_1797 = and(T_1796, io.alloc.iacq.should) + node T_1798 = and(T_1797, io.inner.acquire.valid) + node T_1800 = eq(T_1769, UInt<1>("h0")) + node T_1801 = and(T_1800, scoreboard_6) + node T_1802 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1803 = and(T_1801, T_1802) + node T_1805 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1812 : UInt<3>[1] + T_1812 is invalid + T_1812[0] <= UInt<3>("h3") + node T_1814 = eq(io.inner.acquire.bits.a_type, T_1812[0]) + node T_1815 = and(T_1805, T_1814) + node T_1817 = eq(T_1815, UInt<1>("h0")) + node T_1819 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1820 = or(T_1817, T_1819) + node T_1821 = and(T_1803, T_1820) + node T_1822 = or(T_1798, T_1821) + ignt_q.io.enq.valid <= T_1822 + ignt_q.io.enq.bits <- io.inner.acquire.bits + node T_1823 = mux(ignt_q.io.deq.valid, ignt_q.io.deq.bits, ignt_q.io.enq.bits) + xact_iacq <- T_1823 + xact_addr_beat <= xact_iacq.addr_beat + node T_1850 = gt(ignt_q.io.count, UInt<1>("h0")) + scoreboard_6 <= T_1850 + node T_1851 = neq(state, UInt<4>("h0")) + node T_1852 = or(T_1851, io.alloc.iacq.should) + when T_1852 : + node T_1853 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1862 : UInt<3>[3] + T_1862 is invalid + T_1862[0] <= UInt<3>("h2") + T_1862[1] <= UInt<3>("h3") + T_1862[2] <= UInt<3>("h4") + node T_1864 = eq(io.inner.acquire.bits.a_type, T_1862[0]) + node T_1865 = eq(io.inner.acquire.bits.a_type, T_1862[1]) + node T_1866 = eq(io.inner.acquire.bits.a_type, T_1862[2]) + node T_1867 = or(T_1864, T_1865) + node T_1868 = or(T_1867, T_1866) + node T_1869 = and(io.inner.acquire.bits.is_builtin_type, T_1868) + node T_1870 = and(T_1853, T_1869) + node T_1871 = bits(T_1870, 0, 0) + node T_1874 = mux(T_1871, UInt<8>("hff"), UInt<8>("h0")) + node T_1875 = not(T_1874) + node T_1877 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1878 = not(T_1877) + node T_1879 = or(T_1875, T_1878) + node T_1880 = and(pending_put_data, T_1879) + node T_1881 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1883 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1890 : UInt<3>[1] + T_1890 is invalid + T_1890[0] <= UInt<3>("h3") + node T_1892 = eq(io.inner.acquire.bits.a_type, T_1890[0]) + node T_1893 = and(T_1883, T_1892) + node T_1894 = and(T_1881, T_1893) + node T_1896 = eq(io.inner.acquire.bits.addr_beat, UInt<1>("h0")) + node T_1897 = and(T_1894, T_1896) + node T_1902 = mux(UInt<1>("h1"), UInt<7>("h7f"), UInt<7>("h0")) + node T_1904 = cat(T_1902, UInt<1>("h0")) + node T_1906 = mux(T_1897, T_1904, UInt<8>("h0")) + node T_1907 = or(T_1880, T_1906) + pending_put_data <= T_1907 + node T_1908 = eq(state, UInt<4>("h0")) + node T_1909 = and(T_1908, io.alloc.iacq.should) + node T_1910 = and(T_1909, io.inner.acquire.valid) + when T_1910 : + xact_addr_block <= io.inner.acquire.bits.addr_block + node T_1911 = bits(io.inner.acquire.bits.union, 0, 0) + node T_1912 = and(T_1911, UInt<1>("h0")) + xact_allocate <= T_1912 + node T_1915 = mul(UInt<4>("h8"), UInt<1>("h0")) + xact_amo_shift_bytes <= T_1915 + node T_1917 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_1918 = and(io.inner.acquire.bits.is_builtin_type, T_1917) + node T_1920 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1921 = and(io.inner.acquire.bits.is_builtin_type, T_1920) + node T_1922 = or(T_1918, T_1921) + node T_1923 = bits(io.inner.acquire.bits.union, 5, 1) + node T_1924 = mux(T_1922, UInt<5>("h1"), T_1923) + xact_op_code <= T_1924 + node T_1925 = bits(io.inner.acquire.bits.union, 10, 8) + xact_addr_byte <= T_1925 + node T_1926 = bits(io.inner.acquire.bits.union, 7, 6) + xact_op_size <= T_1926 + node T_1928 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_1929 = and(io.inner.acquire.bits.is_builtin_type, T_1928) + node T_1930 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1939 : UInt<3>[3] + T_1939 is invalid + T_1939[0] <= UInt<3>("h2") + T_1939[1] <= UInt<3>("h3") + T_1939[2] <= UInt<3>("h4") + node T_1941 = eq(io.inner.acquire.bits.a_type, T_1939[0]) + node T_1942 = eq(io.inner.acquire.bits.a_type, T_1939[1]) + node T_1943 = eq(io.inner.acquire.bits.a_type, T_1939[2]) + node T_1944 = or(T_1941, T_1942) + node T_1945 = or(T_1944, T_1943) + node T_1946 = and(io.inner.acquire.bits.is_builtin_type, T_1945) + node T_1947 = and(T_1930, T_1946) + node T_1948 = bits(T_1947, 0, 0) + node T_1951 = mux(T_1948, UInt<8>("hff"), UInt<8>("h0")) + node T_1952 = not(T_1951) + node T_1954 = dshl(UInt<1>("h1"), io.inner.acquire.bits.addr_beat) + node T_1955 = not(T_1954) + node T_1956 = or(T_1952, T_1955) + node T_1958 = mux(T_1929, T_1956, UInt<1>("h0")) + pending_put_data <= T_1958 + pending_ignt_data <= UInt<1>("h0") + state <= UInt<4>("h5") + node scoreboard_0 = neq(pending_put_data, UInt<1>("h0")) + node T_1961 = eq(state, UInt<4>("h0")) + node T_1963 = or(T_1961, UInt<1>("h0")) + node T_1964 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_1965 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_1966 = and(T_1964, T_1965) + node T_1967 = and(T_1966, scoreboard_6) + node T_1969 = and(UInt<1>("h1"), io.inner.acquire.bits.is_builtin_type) + wire T_1976 : UInt<3>[1] + T_1976 is invalid + T_1976[0] <= UInt<3>("h3") + node T_1978 = eq(io.inner.acquire.bits.a_type, T_1976[0]) + node T_1979 = and(T_1969, T_1978) + node T_1980 = and(T_1967, T_1979) + node T_1981 = or(T_1963, T_1980) + io.inner.acquire.ready <= T_1981 + node T_1982 = not(pending_ignt_data) + node skip_outer_acquire = eq(T_1982, UInt<1>("h0")) + node T_1991 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_1992 = mux(T_1991, UInt<2>("h0"), UInt<2>("h2")) + node T_1993 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_1994 = mux(T_1993, UInt<2>("h0"), T_1992) + node T_1995 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_1996 = mux(T_1995, UInt<2>("h2"), T_1994) + node T_1997 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_1998 = mux(T_1997, UInt<2>("h0"), T_1996) + node T_1999 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_2000 = mux(T_1999, UInt<2>("h2"), T_1998) + node T_2001 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_2002 = mux(T_2001, UInt<2>("h0"), T_2000) + node T_2003 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_2004 = mux(T_2003, UInt<2>("h2"), T_2002) + node T_2005 = mux(xact_iacq.is_builtin_type, T_2004, UInt<2>("h0")) + wire T_2030 : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>} + T_2030 is invalid + T_2030.client_id <= UInt<1>("h0") + T_2030.p_type <= T_2005 + T_2030.addr_block <= xact_addr_block + node T_2055 = eq(skip_outer_acquire, UInt<1>("h0")) + node T_2056 = mux(T_2055, UInt<4>("h6"), UInt<4>("h7")) + wire T_2065 : { pending : UInt<1>, up : { idx : UInt, done : UInt<1>}, down : { idx : UInt, done : UInt<1>}} + T_2065 is invalid + node T_2073 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2074 = not(T_2073) + node T_2076 = dshl(UInt<1>("h1"), io.inner.probe.bits.client_id) + node T_2077 = not(T_2076) + node T_2078 = or(T_2074, T_2077) + node T_2079 = and(pending_iprbs, T_2078) + pending_iprbs <= T_2079 + node T_2080 = eq(state, UInt<4>("h5")) + node T_2082 = neq(pending_iprbs, UInt<1>("h0")) + node T_2083 = and(T_2080, T_2082) + io.inner.probe.valid <= T_2083 + io.inner.probe.bits <- T_2030 + node T_2085 = and(io.inner.probe.ready, io.inner.probe.valid) + node T_2087 = and(T_2085, UInt<1>("h1")) + node T_2089 = and(T_2087, UInt<1>("h0")) + reg T_2091 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2089 : + T_2093 <= eq(T_2091, UInt<3>("h7")) + node T_2095 = add(T_2091, UInt<1>("h1")) + node T_2096 = tail(T_2095, 1) + T_2091 <= T_2096 + node T_2097 = and(T_2089, T_2093) + node T_2098 = mux(UInt<1>("h0"), T_2091, UInt<1>("h0")) + node T_2099 = mux(UInt<1>("h0"), T_2097, T_2087) + node T_2100 = and(io.inner.release.ready, io.inner.release.valid) + node T_2101 = neq(state, UInt<4>("h0")) + node T_2103 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2104 = and(T_2101, T_2103) + node T_2105 = and(T_2100, T_2104) + node T_2107 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2108 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2109 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2110 = or(T_2107, T_2108) + node T_2111 = or(T_2110, T_2109) + node T_2112 = and(UInt<1>("h1"), T_2111) + node T_2113 = and(T_2105, T_2112) + reg T_2115 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2113 : + T_2117 <= eq(T_2115, UInt<3>("h7")) + node T_2119 = add(T_2115, UInt<1>("h1")) + node T_2120 = tail(T_2119, 1) + T_2115 <= T_2120 + node T_2121 = and(T_2113, T_2117) + node T_2122 = mux(T_2112, T_2115, UInt<1>("h0")) + node T_2123 = mux(T_2112, T_2121, T_2105) + reg T_2125 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2127 = eq(T_2123, UInt<1>("h0")) + node T_2128 = and(T_2099, T_2127) + when T_2128 : + node T_2130 = add(T_2125, UInt<1>("h1")) + node T_2131 = tail(T_2130, 1) + T_2125 <= T_2131 + node T_2133 = eq(T_2099, UInt<1>("h0")) + node T_2134 = and(T_2123, T_2133) + when T_2134 : + node T_2136 = sub(T_2125, UInt<1>("h1")) + node T_2137 = tail(T_2136, 1) + T_2125 <= T_2137 + node T_2139 = gt(T_2125, UInt<1>("h0")) + T_2065.pending <= T_2139 + T_2065.up.idx <= T_2098 + T_2065.up.done <= T_2099 + T_2065.down.idx <= T_2122 + T_2065.down.done <= T_2123 + node T_2140 = eq(state, UInt<4>("h5")) + node T_2142 = neq(pending_iprbs, UInt<1>("h0")) + node T_2143 = or(T_2142, T_2065.pending) + node T_2145 = eq(T_2143, UInt<1>("h0")) + node T_2146 = and(T_2140, T_2145) + when T_2146 : + state <= T_2056 + node T_2148 = and(io.inner.release.ready, io.inner.release.valid) + node T_2149 = eq(state, UInt<4>("h0")) + node T_2150 = mux(T_2149, io.alloc.irel.should, io.alloc.irel.matches) + node T_2151 = and(T_2150, io.inner.release.bits.voluntary) + node T_2154 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2155 = and(T_2151, T_2154) + node T_2156 = and(T_2148, T_2155) + node T_2158 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2159 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2160 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2161 = or(T_2158, T_2159) + node T_2162 = or(T_2161, T_2160) + node T_2163 = and(UInt<1>("h1"), T_2162) + node T_2164 = and(T_2156, T_2163) + reg T_2166 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2164 : + T_2168 <= eq(T_2166, UInt<3>("h7")) + node T_2170 = add(T_2166, UInt<1>("h1")) + node T_2171 = tail(T_2170, 1) + T_2166 <= T_2171 + node T_2172 = and(T_2164, T_2168) + node T_2173 = mux(T_2163, T_2166, UInt<1>("h0")) + node T_2174 = mux(T_2163, T_2172, T_2156) + node T_2175 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2176 = neq(state, UInt<4>("h0")) + node T_2178 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_2179 = and(io.inner.grant.bits.is_builtin_type, T_2178) + node T_2180 = and(T_2176, T_2179) + node T_2181 = and(T_2175, T_2180) + wire T_2189 : UInt<3>[1] + T_2189 is invalid + T_2189[0] <= UInt<3>("h5") + node T_2191 = eq(io.inner.grant.bits.g_type, T_2189[0]) + node T_2192 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_2193 = mux(io.inner.grant.bits.is_builtin_type, T_2191, T_2192) + node T_2194 = and(UInt<1>("h1"), T_2193) + node T_2195 = and(T_2181, T_2194) + reg T_2197 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2195 : + T_2199 <= eq(T_2197, UInt<3>("h7")) + node T_2201 = add(T_2197, UInt<1>("h1")) + node T_2202 = tail(T_2201, 1) + T_2197 <= T_2202 + node T_2203 = and(T_2195, T_2199) + node T_2204 = mux(T_2194, T_2197, UInt<1>("h0")) + node T_2205 = mux(T_2194, T_2203, T_2181) + reg T_2207 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2209 = eq(T_2205, UInt<1>("h0")) + node T_2210 = and(T_2174, T_2209) + when T_2210 : + node T_2212 = add(T_2207, UInt<1>("h1")) + node T_2213 = tail(T_2212, 1) + T_2207 <= T_2213 + node T_2215 = eq(T_2174, UInt<1>("h0")) + node T_2216 = and(T_2205, T_2215) + when T_2216 : + node T_2218 = sub(T_2207, UInt<1>("h1")) + node T_2219 = tail(T_2218, 1) + T_2207 <= T_2219 + node T_2221 = gt(T_2207, UInt<1>("h0")) + vol_ignt_counter.pending <= T_2221 + vol_ignt_counter.up.idx <= T_2173 + vol_ignt_counter.up.done <= T_2174 + vol_ignt_counter.down.idx <= T_2204 + vol_ignt_counter.down.done <= T_2205 + node T_2222 = eq(state, UInt<4>("h0")) + node T_2223 = and(T_2222, io.alloc.irel.should) + node T_2224 = and(T_2223, io.inner.release.valid) + when T_2224 : + xact_addr_block <= io.inner.release.bits.addr_block + node T_2226 = not(UInt<8>("h0")) + pending_irel_data <= T_2226 + state <= UInt<4>("h7") + node T_2227 = eq(state, UInt<4>("h0")) + node T_2228 = and(T_2227, io.alloc.irel.should) + node T_2229 = and(T_2228, io.inner.release.valid) + node T_2230 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2231 = and(T_2230, io.inner.release.bits.voluntary) + node T_2232 = eq(state, UInt<4>("h0")) + node T_2233 = eq(state, UInt<4>("h8")) + node T_2234 = or(T_2232, T_2233) + node T_2236 = eq(T_2234, UInt<1>("h0")) + node T_2237 = and(T_2231, T_2236) + node T_2239 = eq(all_pending_done, UInt<1>("h0")) + node T_2240 = and(T_2237, T_2239) + node T_2241 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2243 = eq(T_2241, UInt<1>("h0")) + node T_2244 = and(T_2240, T_2243) + node T_2245 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2247 = eq(T_2245, UInt<1>("h0")) + node T_2248 = and(T_2244, T_2247) + node T_2250 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2251 = and(T_2248, T_2250) + node T_2252 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2253 = bits(T_2252, 0, 0) + node T_2254 = and(sending_orel, T_2253) + node T_2255 = and(io.outer.release.ready, io.outer.release.valid) + node T_2256 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2257 = and(T_2255, T_2256) + node T_2258 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2259 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2260 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2261 = or(T_2258, T_2259) + node T_2262 = or(T_2261, T_2260) + node T_2263 = or(T_2254, T_2257) + node T_2264 = and(T_2262, T_2263) + node T_2266 = eq(T_2264, UInt<1>("h0")) + node T_2267 = and(T_2251, T_2266) + node T_2268 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2270 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2271 = and(T_2268, T_2270) + node T_2272 = eq(state, UInt<4>("h5")) + node T_2273 = and(T_2271, T_2272) + node T_2274 = or(T_2267, T_2273) + node T_2275 = and(T_2274, io.inner.release.valid) + node T_2276 = or(T_2229, T_2275) + node T_2277 = and(T_2276, io.inner.release.ready) + when T_2277 : + node T_2279 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2280 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2281 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2282 = or(T_2279, T_2280) + node T_2283 = or(T_2282, T_2281) + node T_2284 = and(UInt<1>("h1"), T_2283) + node T_2286 = eq(T_2284, UInt<1>("h0")) + node T_2288 = eq(io.inner.release.bits.addr_beat, UInt<1>("h0")) + node T_2289 = or(T_2286, T_2288) + when T_2289 : + when io.inner.release.bits.voluntary : + xact_vol_ir_r_type <= io.inner.release.bits.r_type + xact_vol_ir_src <= io.inner.release.bits.client_id + xact_vol_ir_client_xact_id <= io.inner.release.bits.client_xact_id + node T_2291 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2292 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2293 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2294 = or(T_2291, T_2292) + node T_2295 = or(T_2294, T_2293) + node T_2296 = and(UInt<1>("h1"), T_2295) + node T_2297 = and(io.inner.release.ready, io.inner.release.valid) + node T_2298 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2299 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2300 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2301 = or(T_2298, T_2299) + node T_2302 = or(T_2301, T_2300) + node T_2303 = and(T_2297, T_2302) + node T_2304 = bits(T_2303, 0, 0) + node T_2307 = mux(T_2304, UInt<8>("hff"), UInt<8>("h0")) + node T_2308 = not(T_2307) + node T_2310 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2311 = not(T_2310) + node T_2312 = or(T_2308, T_2311) + node T_2314 = mux(T_2296, T_2312, UInt<1>("h0")) + pending_irel_data <= T_2314 + node T_2316 = eq(T_2289, UInt<1>("h0")) + when T_2316 : + node T_2317 = and(io.inner.release.ready, io.inner.release.valid) + node T_2318 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2319 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2320 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2321 = or(T_2318, T_2319) + node T_2322 = or(T_2321, T_2320) + node T_2323 = and(T_2317, T_2322) + node T_2324 = bits(T_2323, 0, 0) + node T_2327 = mux(T_2324, UInt<8>("hff"), UInt<8>("h0")) + node T_2328 = not(T_2327) + node T_2330 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2331 = not(T_2330) + node T_2332 = or(T_2328, T_2331) + node T_2333 = and(pending_irel_data, T_2332) + pending_irel_data <= T_2333 + node T_2334 = eq(state, UInt<4>("h3")) + node T_2335 = eq(state, UInt<4>("h4")) + node T_2336 = eq(state, UInt<4>("h5")) + node T_2337 = eq(state, UInt<4>("h7")) + node T_2338 = or(T_2334, T_2335) + node T_2339 = or(T_2338, T_2336) + node T_2340 = or(T_2339, T_2337) + node T_2341 = and(T_2340, vol_ignt_counter.pending) + node T_2343 = neq(pending_irel_data, UInt<1>("h0")) + node T_2344 = or(T_2343, vol_ognt_counter.pending) + node T_2346 = eq(T_2344, UInt<1>("h0")) + node T_2347 = and(T_2341, T_2346) + io.inner.grant.valid <= T_2347 + wire T_2379 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>} + T_2379 is invalid + T_2379.client_id <= xact_vol_ir_src + T_2379.voluntary <= UInt<1>("h1") + T_2379.r_type <= xact_vol_ir_r_type + T_2379.client_xact_id <= xact_vol_ir_client_xact_id + T_2379.addr_block <= xact_addr_block + T_2379.addr_beat <= UInt<1>("h0") + T_2379.data <= UInt<1>("h0") + wire T_2440 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_2440 is invalid + T_2440.client_id <= T_2379.client_id + T_2440.is_builtin_type <= UInt<1>("h1") + T_2440.g_type <= UInt<3>("h0") + T_2440.client_xact_id <= T_2379.client_xact_id + T_2440.manager_xact_id <= UInt<1>("h0") + T_2440.addr_beat <= UInt<1>("h0") + T_2440.data <= UInt<1>("h0") + io.inner.grant.bits <- T_2440 + node scoreboard_1 = neq(pending_irel_data, UInt<1>("h0")) + node T_2469 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2470 = and(T_2469, io.inner.release.bits.voluntary) + node T_2471 = eq(state, UInt<4>("h0")) + node T_2472 = eq(state, UInt<4>("h8")) + node T_2473 = or(T_2471, T_2472) + node T_2475 = eq(T_2473, UInt<1>("h0")) + node T_2476 = and(T_2470, T_2475) + node T_2478 = eq(all_pending_done, UInt<1>("h0")) + node T_2479 = and(T_2476, T_2478) + node T_2480 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2482 = eq(T_2480, UInt<1>("h0")) + node T_2483 = and(T_2479, T_2482) + node T_2484 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_2486 = eq(T_2484, UInt<1>("h0")) + node T_2487 = and(T_2483, T_2486) + node T_2489 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + node T_2490 = and(T_2487, T_2489) + node T_2491 = dshr(pending_orel_data, io.inner.release.bits.addr_beat) + node T_2492 = bits(T_2491, 0, 0) + node T_2493 = and(sending_orel, T_2492) + node T_2494 = and(io.outer.release.ready, io.outer.release.valid) + node T_2495 = eq(io.inner.release.bits.addr_beat, io.outer.release.bits.addr_beat) + node T_2496 = and(T_2494, T_2495) + node T_2497 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2498 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2499 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2500 = or(T_2497, T_2498) + node T_2501 = or(T_2500, T_2499) + node T_2502 = or(T_2493, T_2496) + node T_2503 = and(T_2501, T_2502) + node T_2505 = eq(T_2503, UInt<1>("h0")) + node T_2506 = and(T_2490, T_2505) + node T_2507 = eq(io.inner.release.bits.addr_block, xact_addr_block) + node T_2509 = eq(io.inner.release.bits.voluntary, UInt<1>("h0")) + node T_2510 = and(T_2507, T_2509) + node T_2511 = eq(state, UInt<4>("h5")) + node T_2512 = and(T_2510, T_2511) + node T_2513 = or(T_2506, T_2512) + io.inner.release.ready <= T_2513 + node T_2514 = and(io.inner.release.ready, io.inner.release.valid) + node T_2515 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2516 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2517 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2518 = or(T_2515, T_2516) + node T_2519 = or(T_2518, T_2517) + node T_2520 = and(T_2514, T_2519) + when T_2520 : + node T_2521 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 0, 0) + node T_2522 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 1, 1) + node T_2523 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 2, 2) + node T_2524 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 3, 3) + node T_2525 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 4, 4) + node T_2526 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 5, 5) + node T_2527 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 6, 6) + node T_2528 = bits(wmask_buffer[io.inner.release.bits.addr_beat], 7, 7) + node T_2529 = bits(T_2521, 0, 0) + node T_2532 = mux(T_2529, UInt<8>("hff"), UInt<8>("h0")) + node T_2533 = bits(T_2522, 0, 0) + node T_2536 = mux(T_2533, UInt<8>("hff"), UInt<8>("h0")) + node T_2537 = bits(T_2523, 0, 0) + node T_2540 = mux(T_2537, UInt<8>("hff"), UInt<8>("h0")) + node T_2541 = bits(T_2524, 0, 0) + node T_2544 = mux(T_2541, UInt<8>("hff"), UInt<8>("h0")) + node T_2545 = bits(T_2525, 0, 0) + node T_2548 = mux(T_2545, UInt<8>("hff"), UInt<8>("h0")) + node T_2549 = bits(T_2526, 0, 0) + node T_2552 = mux(T_2549, UInt<8>("hff"), UInt<8>("h0")) + node T_2553 = bits(T_2527, 0, 0) + node T_2556 = mux(T_2553, UInt<8>("hff"), UInt<8>("h0")) + node T_2557 = bits(T_2528, 0, 0) + node T_2560 = mux(T_2557, UInt<8>("hff"), UInt<8>("h0")) + node T_2561 = cat(T_2536, T_2532) + node T_2562 = cat(T_2544, T_2540) + node T_2563 = cat(T_2562, T_2561) + node T_2564 = cat(T_2552, T_2548) + node T_2565 = cat(T_2560, T_2556) + node T_2566 = cat(T_2565, T_2564) + node T_2567 = cat(T_2566, T_2563) + node T_2568 = not(T_2567) + node T_2569 = and(T_2568, io.inner.release.bits.data) + node T_2570 = and(T_2567, data_buffer[io.inner.release.bits.addr_beat]) + node T_2571 = or(T_2569, T_2570) + data_buffer[io.inner.release.bits.addr_beat] <= T_2571 + node T_2573 = not(UInt<8>("h0")) + wmask_buffer[io.inner.release.bits.addr_beat] <= T_2573 + node T_2574 = eq(UInt<5>("h1"), UInt<5>("h1")) + node T_2575 = eq(UInt<5>("h1"), UInt<5>("h7")) + node T_2576 = or(T_2574, T_2575) + node T_2578 = eq(UInt<5>("h1"), UInt<5>("h4")) + node T_2579 = or(UInt<1>("h0"), T_2578) + node T_2580 = or(T_2576, T_2579) + node T_2581 = mux(T_2580, UInt<2>("h2"), coh.outer.state) + wire T_2604 : { state : UInt<2>} + T_2604 is invalid + T_2604.state <= T_2581 + node T_2630 = neq(state, UInt<4>("h0")) + node T_2631 = or(T_2630, io.alloc.irel.should) + when T_2631 : + node T_2633 = and(io.inner.release.ready, io.inner.release.valid) + node T_2634 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2635 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2636 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2637 = or(T_2634, T_2635) + node T_2638 = or(T_2637, T_2636) + node T_2639 = and(T_2633, T_2638) + node T_2640 = and(T_2639, UInt<1>("h1")) + node T_2641 = bits(T_2640, 0, 0) + node T_2644 = mux(T_2641, UInt<8>("hff"), UInt<8>("h0")) + node T_2646 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_2647 = and(T_2644, T_2646) + node T_2648 = or(pending_orel_data, T_2647) + node T_2649 = or(T_2648, UInt<1>("h0")) + node T_2650 = and(io.outer.release.ready, io.outer.release.valid) + node T_2651 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2652 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2653 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2654 = or(T_2651, T_2652) + node T_2655 = or(T_2654, T_2653) + node T_2656 = and(T_2650, T_2655) + node T_2657 = bits(T_2656, 0, 0) + node T_2660 = mux(T_2657, UInt<8>("hff"), UInt<8>("h0")) + node T_2661 = not(T_2660) + node T_2663 = dshl(UInt<1>("h1"), io.outer.release.bits.addr_beat) + node T_2664 = not(T_2663) + node T_2665 = or(T_2661, T_2664) + node T_2666 = and(T_2649, T_2665) + pending_orel_data <= T_2666 + when UInt<1>("h0") : + pending_orel_send <= UInt<1>("h1") + node T_2668 = and(io.outer.release.ready, io.outer.release.valid) + when T_2668 : + node T_2670 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2671 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2672 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2673 = or(T_2670, T_2671) + node T_2674 = or(T_2673, T_2672) + node T_2675 = and(UInt<1>("h1"), T_2674) + node T_2677 = eq(T_2675, UInt<1>("h0")) + node T_2679 = eq(io.outer.release.bits.addr_beat, UInt<1>("h0")) + node T_2680 = or(T_2677, T_2679) + when T_2680 : + sending_orel <= UInt<1>("h1") + node T_2683 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2684 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2685 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2686 = or(T_2683, T_2684) + node T_2687 = or(T_2686, T_2685) + node T_2688 = and(UInt<1>("h1"), T_2687) + node T_2690 = eq(T_2688, UInt<1>("h0")) + node T_2692 = eq(io.outer.release.bits.addr_beat, UInt<3>("h7")) + node T_2693 = or(T_2690, T_2692) + when T_2693 : + sending_orel <= UInt<1>("h0") + pending_orel_send <= UInt<1>("h0") + node T_2697 = and(io.outer.release.ready, io.outer.release.valid) + node T_2700 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2701 = and(io.outer.release.bits.voluntary, T_2700) + node T_2702 = and(T_2697, T_2701) + node T_2704 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2705 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2706 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2707 = or(T_2704, T_2705) + node T_2708 = or(T_2707, T_2706) + node T_2709 = and(UInt<1>("h1"), T_2708) + node T_2710 = and(T_2702, T_2709) + reg T_2712 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2710 : + T_2714 <= eq(T_2712, UInt<3>("h7")) + node T_2716 = add(T_2712, UInt<1>("h1")) + node T_2717 = tail(T_2716, 1) + T_2712 <= T_2717 + node T_2718 = and(T_2710, T_2714) + node T_2719 = mux(T_2709, T_2712, UInt<1>("h0")) + node T_2720 = mux(T_2709, T_2718, T_2702) + node T_2721 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2723 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2724 = and(io.outer.grant.bits.is_builtin_type, T_2723) + node T_2725 = and(T_2721, T_2724) + wire T_2733 : UInt<3>[1] + T_2733 is invalid + T_2733[0] <= UInt<3>("h5") + node T_2735 = eq(io.outer.grant.bits.g_type, T_2733[0]) + node T_2736 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2737 = mux(io.outer.grant.bits.is_builtin_type, T_2735, T_2736) + node T_2738 = and(UInt<1>("h1"), T_2737) + node T_2739 = and(T_2725, T_2738) + reg T_2741 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2739 : + T_2743 <= eq(T_2741, UInt<3>("h7")) + node T_2745 = add(T_2741, UInt<1>("h1")) + node T_2746 = tail(T_2745, 1) + T_2741 <= T_2746 + node T_2747 = and(T_2739, T_2743) + node T_2748 = mux(T_2738, T_2741, UInt<1>("h0")) + node T_2749 = mux(T_2738, T_2747, T_2725) + reg T_2751 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2753 = eq(T_2749, UInt<1>("h0")) + node T_2754 = and(T_2720, T_2753) + when T_2754 : + node T_2756 = add(T_2751, UInt<1>("h1")) + node T_2757 = tail(T_2756, 1) + T_2751 <= T_2757 + node T_2759 = eq(T_2720, UInt<1>("h0")) + node T_2760 = and(T_2749, T_2759) + when T_2760 : + node T_2762 = sub(T_2751, UInt<1>("h1")) + node T_2763 = tail(T_2762, 1) + T_2751 <= T_2763 + node T_2765 = gt(T_2751, UInt<1>("h0")) + vol_ognt_counter.pending <= T_2765 + vol_ognt_counter.up.idx <= T_2719 + vol_ognt_counter.up.done <= T_2720 + vol_ognt_counter.down.idx <= T_2748 + vol_ognt_counter.down.done <= T_2749 + node T_2767 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2768 = eq(state, UInt<4>("h7")) + node T_2769 = eq(io.outer.release.bits.r_type, UInt<3>("h0")) + node T_2770 = eq(io.outer.release.bits.r_type, UInt<3>("h1")) + node T_2771 = eq(io.outer.release.bits.r_type, UInt<3>("h2")) + node T_2772 = or(T_2769, T_2770) + node T_2773 = or(T_2772, T_2771) + node T_2774 = dshr(pending_orel_data, vol_ognt_counter.up.idx) + node T_2775 = bits(T_2774, 0, 0) + node T_2776 = mux(T_2773, T_2775, pending_orel_send) + node T_2777 = and(T_2768, T_2776) + node T_2778 = neq(state, UInt<4>("h0")) + node T_2779 = and(T_2778, io.alloc.irel.matches) + node T_2780 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_2781 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_2782 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_2783 = or(T_2780, T_2781) + node T_2784 = or(T_2783, T_2782) + node T_2785 = and(T_2779, T_2784) + node T_2786 = and(T_2785, io.inner.release.valid) + node T_2787 = mux(UInt<1>("h1"), T_2777, T_2786) + node T_2788 = and(T_2767, T_2787) + io.outer.release.valid <= T_2788 + node T_2791 = eq(T_2604.state, UInt<2>("h2")) + node T_2792 = mux(T_2791, UInt<3>("h0"), UInt<3>("h3")) + node T_2793 = mux(T_2791, UInt<3>("h1"), UInt<3>("h4")) + node T_2794 = mux(T_2791, UInt<3>("h2"), UInt<3>("h5")) + node T_2795 = eq(UInt<5>("h13"), UInt<5>("h10")) + node T_2796 = mux(T_2795, T_2794, UInt<3>("h5")) + node T_2797 = eq(UInt<5>("h11"), UInt<5>("h10")) + node T_2798 = mux(T_2797, T_2793, T_2796) + node T_2799 = eq(UInt<5>("h10"), UInt<5>("h10")) + node T_2800 = mux(T_2799, T_2792, T_2798) + wire T_2828 : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>} + T_2828 is invalid + T_2828.r_type <= T_2800 + T_2828.client_xact_id <= UInt<1>("h0") + T_2828.addr_block <= xact_addr_block + T_2828.addr_beat <= vol_ognt_counter.up.idx + T_2828.data <= data_buffer[vol_ognt_counter.up.idx] + T_2828.voluntary <= UInt<1>("h1") + io.outer.release.bits <- T_2828 + when vol_ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_2857 = eq(xact_iacq.is_builtin_type, UInt<1>("h0")) + node T_2860 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_2862 = and(T_2860, UInt<1>("h1")) + node T_2864 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_2871 : UInt<3>[1] + T_2871 is invalid + T_2871[0] <= UInt<3>("h3") + node T_2873 = eq(io.outer.acquire.bits.a_type, T_2871[0]) + node T_2874 = and(T_2864, T_2873) + node T_2875 = and(T_2862, T_2874) + reg T_2877 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2875 : + T_2879 <= eq(T_2877, UInt<3>("h7")) + node T_2881 = add(T_2877, UInt<1>("h1")) + node T_2882 = tail(T_2881, 1) + T_2877 <= T_2882 + node T_2883 = and(T_2875, T_2879) + node T_2884 = mux(T_2874, T_2877, xact_addr_beat) + node T_2885 = mux(T_2874, T_2883, T_2862) + node T_2886 = and(io.outer.grant.ready, io.outer.grant.valid) + node T_2888 = eq(io.outer.grant.bits.g_type, UInt<3>("h0")) + node T_2889 = and(io.outer.grant.bits.is_builtin_type, T_2888) + node T_2891 = eq(T_2889, UInt<1>("h0")) + node T_2892 = and(T_2886, T_2891) + wire T_2900 : UInt<3>[1] + T_2900 is invalid + T_2900[0] <= UInt<3>("h5") + node T_2902 = eq(io.outer.grant.bits.g_type, T_2900[0]) + node T_2903 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_2904 = mux(io.outer.grant.bits.is_builtin_type, T_2902, T_2903) + node T_2905 = and(UInt<1>("h1"), T_2904) + node T_2906 = and(T_2892, T_2905) + reg T_2908 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_2906 : + T_2910 <= eq(T_2908, UInt<3>("h7")) + node T_2912 = add(T_2908, UInt<1>("h1")) + node T_2913 = tail(T_2912, 1) + T_2908 <= T_2913 + node T_2914 = and(T_2906, T_2910) + node T_2915 = mux(T_2905, T_2908, xact_addr_beat) + node T_2916 = mux(T_2905, T_2914, T_2892) + reg T_2918 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_2920 = eq(T_2916, UInt<1>("h0")) + node T_2921 = and(T_2885, T_2920) + when T_2921 : + node T_2923 = add(T_2918, UInt<1>("h1")) + node T_2924 = tail(T_2923, 1) + T_2918 <= T_2924 + node T_2926 = eq(T_2885, UInt<1>("h0")) + node T_2927 = and(T_2916, T_2926) + when T_2927 : + node T_2929 = sub(T_2918, UInt<1>("h1")) + node T_2930 = tail(T_2929, 1) + T_2918 <= T_2930 + node T_2932 = gt(T_2918, UInt<1>("h0")) + ognt_counter.pending <= T_2932 + ognt_counter.up.idx <= T_2884 + ognt_counter.up.done <= T_2885 + ognt_counter.down.idx <= T_2915 + ognt_counter.down.done <= T_2916 + node T_2933 = eq(state, UInt<4>("h6")) + node T_2935 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_2936 = and(T_2933, T_2935) + node T_2937 = dshr(pending_put_data, ognt_counter.up.idx) + node T_2938 = bits(T_2937, 0, 0) + node T_2940 = eq(T_2938, UInt<1>("h0")) + wire T_2949 : UInt<3>[3] + T_2949 is invalid + T_2949[0] <= UInt<3>("h2") + T_2949[1] <= UInt<3>("h3") + T_2949[2] <= UInt<3>("h4") + node T_2951 = eq(xact_iacq.a_type, T_2949[0]) + node T_2952 = eq(xact_iacq.a_type, T_2949[1]) + node T_2953 = eq(xact_iacq.a_type, T_2949[2]) + node T_2954 = or(T_2951, T_2952) + node T_2955 = or(T_2954, T_2953) + node T_2956 = and(xact_iacq.is_builtin_type, T_2955) + node T_2958 = eq(T_2956, UInt<1>("h0")) + node T_2959 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_2960 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_2961 = and(T_2959, T_2960) + node T_2962 = and(T_2961, scoreboard_6) + node T_2963 = and(io.inner.acquire.valid, T_2962) + node T_2964 = or(T_2958, T_2963) + node T_2965 = and(scoreboard_6, T_2964) + node T_2966 = mux(UInt<1>("h1"), T_2940, T_2965) + node T_2967 = or(xact_allocate, T_2966) + node T_2968 = and(T_2936, T_2967) + io.outer.acquire.valid <= T_2968 + node T_2971 = eq(xact_op_code, UInt<5>("h1")) + node T_2972 = eq(xact_op_code, UInt<5>("h7")) + node T_2973 = or(T_2971, T_2972) + node T_2974 = bits(xact_op_code, 3, 3) + node T_2975 = eq(xact_op_code, UInt<5>("h4")) + node T_2976 = or(T_2974, T_2975) + node T_2977 = or(T_2973, T_2976) + node T_2978 = eq(xact_op_code, UInt<5>("h3")) + node T_2979 = or(T_2977, T_2978) + node T_2980 = eq(xact_op_code, UInt<5>("h6")) + node T_2981 = or(T_2979, T_2980) + node T_2982 = mux(T_2981, UInt<1>("h1"), UInt<1>("h0")) + node T_2984 = cat(xact_op_code, UInt<1>("h1")) + wire T_3015 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3015 is invalid + T_3015.is_builtin_type <= UInt<1>("h0") + T_3015.a_type <= T_2982 + T_3015.client_xact_id <= UInt<1>("h0") + T_3015.addr_block <= xact_addr_block + T_3015.addr_beat <= UInt<1>("h0") + T_3015.data <= UInt<1>("h0") + T_3015.union <= T_2984 + node T_3067 = or(UInt<3>("h0"), xact_addr_byte) + node T_3068 = bits(T_3067, 2, 0) + node T_3070 = or(UInt<2>("h0"), xact_op_size) + node T_3071 = bits(T_3070, 1, 0) + node T_3073 = or(UInt<5>("h0"), xact_op_code) + node T_3074 = bits(T_3073, 4, 0) + node T_3076 = or(UInt<8>("h0"), wmask_buffer[ognt_counter.up.idx]) + node T_3077 = bits(T_3076, 7, 0) + node T_3080 = cat(T_3074, UInt<1>("h0")) + node T_3081 = cat(T_3068, T_3071) + node T_3082 = cat(T_3081, T_3080) + node T_3084 = cat(T_3071, T_3074) + node T_3085 = cat(T_3084, UInt<1>("h0")) + node T_3087 = cat(T_3077, UInt<1>("h0")) + node T_3089 = cat(T_3077, UInt<1>("h0")) + node T_3091 = cat(T_3074, UInt<1>("h0")) + node T_3092 = cat(T_3068, T_3071) + node T_3093 = cat(T_3092, T_3091) + node T_3095 = cat(UInt<5>("h0"), UInt<1>("h0")) + node T_3097 = cat(UInt<5>("h1"), UInt<1>("h0")) + node T_3098 = eq(UInt<3>("h6"), xact_iacq.a_type) + node T_3099 = mux(T_3098, T_3097, UInt<1>("h0")) + node T_3100 = eq(UInt<3>("h5"), xact_iacq.a_type) + node T_3101 = mux(T_3100, T_3095, T_3099) + node T_3102 = eq(UInt<3>("h4"), xact_iacq.a_type) + node T_3103 = mux(T_3102, T_3093, T_3101) + node T_3104 = eq(UInt<3>("h3"), xact_iacq.a_type) + node T_3105 = mux(T_3104, T_3089, T_3103) + node T_3106 = eq(UInt<3>("h2"), xact_iacq.a_type) + node T_3107 = mux(T_3106, T_3087, T_3105) + node T_3108 = eq(UInt<3>("h1"), xact_iacq.a_type) + node T_3109 = mux(T_3108, T_3085, T_3107) + node T_3110 = eq(UInt<3>("h0"), xact_iacq.a_type) + node T_3111 = mux(T_3110, T_3082, T_3109) + wire T_3140 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_3140 is invalid + T_3140.is_builtin_type <= UInt<1>("h1") + T_3140.a_type <= xact_iacq.a_type + T_3140.client_xact_id <= UInt<1>("h0") + T_3140.addr_block <= xact_addr_block + T_3140.addr_beat <= ognt_counter.up.idx + T_3140.data <= data_buffer[ognt_counter.up.idx] + T_3140.union <= T_3111 + node T_3168 = mux(T_2857, T_3015, T_3140) + io.outer.acquire.bits <- T_3168 + node T_3196 = eq(state, UInt<4>("h6")) + node T_3197 = and(T_3196, ognt_counter.up.done) + when T_3197 : + state <= UInt<4>("h7") + when ognt_counter.pending : + io.outer.grant.ready <= UInt<1>("h1") + node T_3199 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3207 : UInt<3>[2] + T_3207 is invalid + T_3207[0] <= UInt<3>("h5") + T_3207[1] <= UInt<3>("h4") + node T_3209 = eq(io.outer.grant.bits.g_type, T_3207[0]) + node T_3210 = eq(io.outer.grant.bits.g_type, T_3207[1]) + node T_3211 = or(T_3209, T_3210) + node T_3212 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3213 = mux(io.outer.grant.bits.is_builtin_type, T_3211, T_3212) + node T_3214 = and(T_3199, T_3213) + when T_3214 : + node T_3215 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 0, 0) + node T_3216 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 1, 1) + node T_3217 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 2, 2) + node T_3218 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 3, 3) + node T_3219 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 4, 4) + node T_3220 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 5, 5) + node T_3221 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 6, 6) + node T_3222 = bits(wmask_buffer[io.outer.grant.bits.addr_beat], 7, 7) + node T_3223 = bits(T_3215, 0, 0) + node T_3226 = mux(T_3223, UInt<8>("hff"), UInt<8>("h0")) + node T_3227 = bits(T_3216, 0, 0) + node T_3230 = mux(T_3227, UInt<8>("hff"), UInt<8>("h0")) + node T_3231 = bits(T_3217, 0, 0) + node T_3234 = mux(T_3231, UInt<8>("hff"), UInt<8>("h0")) + node T_3235 = bits(T_3218, 0, 0) + node T_3238 = mux(T_3235, UInt<8>("hff"), UInt<8>("h0")) + node T_3239 = bits(T_3219, 0, 0) + node T_3242 = mux(T_3239, UInt<8>("hff"), UInt<8>("h0")) + node T_3243 = bits(T_3220, 0, 0) + node T_3246 = mux(T_3243, UInt<8>("hff"), UInt<8>("h0")) + node T_3247 = bits(T_3221, 0, 0) + node T_3250 = mux(T_3247, UInt<8>("hff"), UInt<8>("h0")) + node T_3251 = bits(T_3222, 0, 0) + node T_3254 = mux(T_3251, UInt<8>("hff"), UInt<8>("h0")) + node T_3255 = cat(T_3230, T_3226) + node T_3256 = cat(T_3238, T_3234) + node T_3257 = cat(T_3256, T_3255) + node T_3258 = cat(T_3246, T_3242) + node T_3259 = cat(T_3254, T_3250) + node T_3260 = cat(T_3259, T_3258) + node T_3261 = cat(T_3260, T_3257) + node T_3262 = not(T_3261) + node T_3263 = and(T_3262, io.outer.grant.bits.data) + node T_3264 = and(T_3261, data_buffer[io.outer.grant.bits.addr_beat]) + node T_3265 = or(T_3263, T_3264) + data_buffer[io.outer.grant.bits.addr_beat] <= T_3265 + node T_3267 = not(UInt<8>("h0")) + wmask_buffer[io.outer.grant.bits.addr_beat] <= T_3267 + node T_3268 = or(scoreboard_3, ognt_counter.pending) + node T_3269 = or(T_3268, vol_ognt_counter.pending) + node T_3273 = and(io.inner.grant.ready, io.inner.grant.valid) + node T_3276 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_3278 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_3279 = and(io.inner.grant.bits.is_builtin_type, T_3278) + node T_3281 = eq(T_3279, UInt<1>("h0")) + node T_3282 = and(T_3276, T_3281) + node T_3283 = and(T_3273, T_3282) + wire T_3291 : UInt<3>[1] + T_3291 is invalid + T_3291[0] <= UInt<3>("h5") + node T_3293 = eq(io.inner.grant.bits.g_type, T_3291[0]) + node T_3294 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3295 = mux(io.inner.grant.bits.is_builtin_type, T_3293, T_3294) + node T_3296 = and(UInt<1>("h1"), T_3295) + node T_3297 = and(T_3283, T_3296) + reg T_3299 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3297 : + T_3301 <= eq(T_3299, UInt<3>("h7")) + node T_3303 = add(T_3299, UInt<1>("h1")) + node T_3304 = tail(T_3303, 1) + T_3299 <= T_3304 + node T_3305 = and(T_3297, T_3301) + node T_3306 = mux(T_3296, T_3299, UInt<1>("h0")) + node T_3307 = mux(T_3296, T_3305, T_3283) + node T_3308 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_3310 = and(T_3308, UInt<1>("h1")) + node T_3312 = and(T_3310, UInt<1>("h0")) + reg T_3314 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3312 : + T_3316 <= eq(T_3314, UInt<3>("h7")) + node T_3318 = add(T_3314, UInt<1>("h1")) + node T_3319 = tail(T_3318, 1) + T_3314 <= T_3319 + node T_3320 = and(T_3312, T_3316) + node T_3321 = mux(UInt<1>("h0"), T_3314, UInt<1>("h0")) + node T_3322 = mux(UInt<1>("h0"), T_3320, T_3310) + reg T_3324 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_3326 = eq(T_3322, UInt<1>("h0")) + node T_3327 = and(T_3307, T_3326) + when T_3327 : + node T_3329 = add(T_3324, UInt<1>("h1")) + node T_3330 = tail(T_3329, 1) + T_3324 <= T_3330 + node T_3332 = eq(T_3307, UInt<1>("h0")) + node T_3333 = and(T_3322, T_3332) + when T_3333 : + node T_3335 = sub(T_3324, UInt<1>("h1")) + node T_3336 = tail(T_3335, 1) + T_3324 <= T_3336 + node T_3338 = gt(T_3324, UInt<1>("h0")) + ifin_counter.pending <= T_3338 + ifin_counter.up.idx <= T_3306 + ifin_counter.up.done <= T_3307 + ifin_counter.down.idx <= T_3321 + ifin_counter.down.done <= T_3322 + node T_3339 = eq(state, UInt<4>("h0")) + node T_3340 = and(T_3339, io.alloc.iacq.should) + node T_3341 = and(T_3340, io.inner.acquire.valid) + node T_3343 = eq(T_3341, UInt<1>("h0")) + when T_3343 : + node T_3345 = and(io.inner.release.ready, io.inner.release.valid) + node T_3346 = eq(io.inner.release.bits.r_type, UInt<3>("h0")) + node T_3347 = eq(io.inner.release.bits.r_type, UInt<3>("h1")) + node T_3348 = eq(io.inner.release.bits.r_type, UInt<3>("h2")) + node T_3349 = or(T_3346, T_3347) + node T_3350 = or(T_3349, T_3348) + node T_3351 = and(T_3345, T_3350) + node T_3352 = and(T_3351, UInt<1>("h1")) + node T_3353 = bits(T_3352, 0, 0) + node T_3356 = mux(T_3353, UInt<8>("hff"), UInt<8>("h0")) + node T_3358 = dshl(UInt<1>("h1"), io.inner.release.bits.addr_beat) + node T_3359 = and(T_3356, T_3358) + node T_3360 = or(pending_ignt_data, T_3359) + node T_3362 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_3370 : UInt<3>[2] + T_3370 is invalid + T_3370[0] <= UInt<3>("h5") + T_3370[1] <= UInt<3>("h4") + node T_3372 = eq(io.outer.grant.bits.g_type, T_3370[0]) + node T_3373 = eq(io.outer.grant.bits.g_type, T_3370[1]) + node T_3374 = or(T_3372, T_3373) + node T_3375 = eq(io.outer.grant.bits.g_type, UInt<1>("h0")) + node T_3376 = mux(io.outer.grant.bits.is_builtin_type, T_3374, T_3375) + node T_3377 = and(T_3362, T_3376) + node T_3378 = and(T_3377, UInt<1>("h1")) + node T_3379 = bits(T_3378, 0, 0) + node T_3382 = mux(T_3379, UInt<8>("hff"), UInt<8>("h0")) + node T_3384 = dshl(UInt<1>("h1"), io.outer.grant.bits.addr_beat) + node T_3385 = and(T_3382, T_3384) + node T_3386 = or(T_3360, T_3385) + node T_3387 = or(T_3386, UInt<1>("h0")) + pending_ignt_data <= T_3387 + node T_3388 = eq(state, UInt<4>("h0")) + node T_3389 = eq(state, UInt<4>("h1")) + node T_3390 = or(T_3388, T_3389) + node T_3392 = neq(pending_put_data, UInt<1>("h0")) + node T_3393 = or(T_3390, T_3392) + node T_3395 = eq(T_3393, UInt<1>("h0")) + node T_3412 = eq(UInt<3>("h6"), ignt_q.io.deq.bits.a_type) + node T_3413 = mux(T_3412, UInt<3>("h1"), UInt<3>("h3")) + node T_3414 = eq(UInt<3>("h5"), ignt_q.io.deq.bits.a_type) + node T_3415 = mux(T_3414, UInt<3>("h1"), T_3413) + node T_3416 = eq(UInt<3>("h4"), ignt_q.io.deq.bits.a_type) + node T_3417 = mux(T_3416, UInt<3>("h4"), T_3415) + node T_3418 = eq(UInt<3>("h3"), ignt_q.io.deq.bits.a_type) + node T_3419 = mux(T_3418, UInt<3>("h3"), T_3417) + node T_3420 = eq(UInt<3>("h2"), ignt_q.io.deq.bits.a_type) + node T_3421 = mux(T_3420, UInt<3>("h3"), T_3419) + node T_3422 = eq(UInt<3>("h1"), ignt_q.io.deq.bits.a_type) + node T_3423 = mux(T_3422, UInt<3>("h5"), T_3421) + node T_3424 = eq(UInt<3>("h0"), ignt_q.io.deq.bits.a_type) + node T_3425 = mux(T_3424, UInt<3>("h4"), T_3423) + node T_3426 = mux(ignt_q.io.deq.bits.is_builtin_type, T_3425, UInt<1>("h0")) + wire T_3455 : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>} + T_3455 is invalid + T_3455.client_id <= ignt_q.io.deq.bits.client_id + T_3455.is_builtin_type <= ignt_q.io.deq.bits.is_builtin_type + T_3455.g_type <= T_3426 + T_3455.client_xact_id <= ignt_q.io.deq.bits.client_xact_id + T_3455.manager_xact_id <= UInt<3>("h7") + T_3455.addr_beat <= ignt_q.io.deq.bits.addr_beat + T_3455.data <= data_buffer[ignt_data_idx] + node T_3483 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_3491 : UInt<3>[1] + T_3491 is invalid + T_3491[0] <= UInt<3>("h5") + node T_3493 = eq(io.inner.grant.bits.g_type, T_3491[0]) + node T_3494 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3495 = mux(io.inner.grant.bits.is_builtin_type, T_3493, T_3494) + node T_3496 = and(UInt<1>("h1"), T_3495) + node T_3497 = and(T_3483, T_3496) + reg T_3499 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_3497 : + T_3501 <= eq(T_3499, UInt<3>("h7")) + node T_3503 = add(T_3499, UInt<1>("h1")) + node T_3504 = tail(T_3503, 1) + T_3499 <= T_3504 + node T_3505 = and(T_3497, T_3501) + node T_3506 = mux(T_3496, T_3499, ignt_q.io.deq.bits.addr_beat) + node T_3507 = mux(T_3496, T_3505, T_3483) + ignt_data_idx <= T_3506 + ignt_data_done <= T_3507 + ignt_q.io.deq.ready <= UInt<1>("h0") + node T_3510 = eq(vol_ignt_counter.pending, UInt<1>("h0")) + when T_3510 : + ignt_q.io.deq.ready <= ignt_data_done + io.inner.grant.bits <- T_3455 + io.inner.grant.bits.addr_beat <= ignt_data_idx + node T_3511 = eq(state, UInt<4>("h7")) + node T_3512 = and(T_3511, scoreboard_6) + when T_3512 : + node T_3514 = eq(T_3269, UInt<1>("h0")) + wire T_3522 : UInt<3>[2] + T_3522 is invalid + T_3522[0] <= UInt<3>("h5") + T_3522[1] <= UInt<3>("h4") + node T_3524 = eq(io.inner.grant.bits.g_type, T_3522[0]) + node T_3525 = eq(io.inner.grant.bits.g_type, T_3522[1]) + node T_3526 = or(T_3524, T_3525) + node T_3527 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_3528 = mux(io.inner.grant.bits.is_builtin_type, T_3526, T_3527) + node T_3529 = dshr(pending_ignt_data, ignt_data_idx) + node T_3530 = bits(T_3529, 0, 0) + node T_3531 = mux(UInt<1>("h1"), T_3530, io.outer.grant.valid) + node T_3532 = mux(T_3528, T_3531, T_3395) + node T_3533 = and(T_3514, T_3532) + io.inner.grant.valid <= T_3533 + node T_3534 = eq(state, UInt<4>("h7")) + io.inner.finish.ready <= T_3534 + node T_3535 = eq(state, UInt<4>("h0")) + node T_3536 = and(T_3535, io.alloc.iacq.should) + node T_3537 = and(T_3536, io.inner.acquire.valid) + when T_3537 : + node T_3539 = not(UInt<1>("h0")) + node T_3540 = not(io.incoherent[0]) + node T_3541 = and(T_3539, T_3540) + pending_iprbs <= T_3541 + node T_3542 = eq(state, UInt<4>("h0")) + node T_3543 = and(T_3542, io.alloc.iacq.should) + node T_3544 = and(T_3543, io.inner.acquire.valid) + node T_3546 = eq(xact_iacq.client_xact_id, io.inner.acquire.bits.client_xact_id) + node T_3547 = eq(xact_iacq.client_id, io.inner.acquire.bits.client_id) + node T_3548 = and(T_3546, T_3547) + node T_3549 = and(T_3548, scoreboard_6) + node T_3550 = or(UInt<1>("h0"), T_3549) + node T_3551 = and(T_3550, io.inner.acquire.valid) + node T_3552 = or(T_3544, T_3551) + node T_3553 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_3562 : UInt<3>[3] + T_3562 is invalid + T_3562[0] <= UInt<3>("h2") + T_3562[1] <= UInt<3>("h3") + T_3562[2] <= UInt<3>("h4") + node T_3564 = eq(io.inner.acquire.bits.a_type, T_3562[0]) + node T_3565 = eq(io.inner.acquire.bits.a_type, T_3562[1]) + node T_3566 = eq(io.inner.acquire.bits.a_type, T_3562[2]) + node T_3567 = or(T_3564, T_3565) + node T_3568 = or(T_3567, T_3566) + node T_3569 = and(io.inner.acquire.bits.is_builtin_type, T_3568) + node T_3570 = and(T_3553, T_3569) + node T_3571 = and(T_3570, T_3552) + when T_3571 : + node T_3573 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3574 = and(io.inner.acquire.bits.is_builtin_type, T_3573) + node T_3596 = asUInt(asSInt(UInt<8>("hff"))) + node T_3598 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3599 = and(io.inner.acquire.bits.is_builtin_type, T_3598) + node T_3601 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3602 = and(io.inner.acquire.bits.is_builtin_type, T_3601) + node T_3603 = or(T_3599, T_3602) + node T_3604 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3606 = mux(T_3603, T_3604, UInt<1>("h0")) + node T_3607 = mux(T_3574, T_3596, T_3606) + node T_3608 = bits(T_3607, 0, 0) + node T_3609 = bits(T_3607, 1, 1) + node T_3610 = bits(T_3607, 2, 2) + node T_3611 = bits(T_3607, 3, 3) + node T_3612 = bits(T_3607, 4, 4) + node T_3613 = bits(T_3607, 5, 5) + node T_3614 = bits(T_3607, 6, 6) + node T_3615 = bits(T_3607, 7, 7) + node T_3616 = bits(T_3608, 0, 0) + node T_3619 = mux(T_3616, UInt<8>("hff"), UInt<8>("h0")) + node T_3620 = bits(T_3609, 0, 0) + node T_3623 = mux(T_3620, UInt<8>("hff"), UInt<8>("h0")) + node T_3624 = bits(T_3610, 0, 0) + node T_3627 = mux(T_3624, UInt<8>("hff"), UInt<8>("h0")) + node T_3628 = bits(T_3611, 0, 0) + node T_3631 = mux(T_3628, UInt<8>("hff"), UInt<8>("h0")) + node T_3632 = bits(T_3612, 0, 0) + node T_3635 = mux(T_3632, UInt<8>("hff"), UInt<8>("h0")) + node T_3636 = bits(T_3613, 0, 0) + node T_3639 = mux(T_3636, UInt<8>("hff"), UInt<8>("h0")) + node T_3640 = bits(T_3614, 0, 0) + node T_3643 = mux(T_3640, UInt<8>("hff"), UInt<8>("h0")) + node T_3644 = bits(T_3615, 0, 0) + node T_3647 = mux(T_3644, UInt<8>("hff"), UInt<8>("h0")) + node T_3648 = cat(T_3623, T_3619) + node T_3649 = cat(T_3631, T_3627) + node T_3650 = cat(T_3649, T_3648) + node T_3651 = cat(T_3639, T_3635) + node T_3652 = cat(T_3647, T_3643) + node T_3653 = cat(T_3652, T_3651) + node T_3654 = cat(T_3653, T_3650) + node T_3655 = not(T_3654) + node T_3656 = and(T_3655, data_buffer[io.inner.acquire.bits.addr_beat]) + node T_3657 = and(T_3654, io.inner.acquire.bits.data) + node T_3658 = or(T_3656, T_3657) + data_buffer[io.inner.acquire.bits.addr_beat] <= T_3658 + node T_3660 = eq(io.inner.acquire.bits.a_type, UInt<3>("h4")) + node T_3661 = and(io.inner.acquire.bits.is_builtin_type, T_3660) + node T_3683 = asUInt(asSInt(UInt<8>("hff"))) + node T_3685 = eq(io.inner.acquire.bits.a_type, UInt<3>("h3")) + node T_3686 = and(io.inner.acquire.bits.is_builtin_type, T_3685) + node T_3688 = eq(io.inner.acquire.bits.a_type, UInt<3>("h2")) + node T_3689 = and(io.inner.acquire.bits.is_builtin_type, T_3688) + node T_3690 = or(T_3686, T_3689) + node T_3691 = bits(io.inner.acquire.bits.union, 8, 1) + node T_3693 = mux(T_3690, T_3691, UInt<1>("h0")) + node T_3694 = mux(T_3661, T_3683, T_3693) + node T_3695 = or(T_3694, wmask_buffer[io.inner.acquire.bits.addr_beat]) + wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_3695 + node T_3697 = or(UInt<1>("h0"), scoreboard_0) + node T_3698 = or(T_3697, scoreboard_1) + node T_3699 = or(T_3698, vol_ignt_counter.pending) + node T_3700 = or(T_3699, scoreboard_3) + node T_3701 = or(T_3700, vol_ognt_counter.pending) + node T_3702 = or(T_3701, ognt_counter.pending) + node T_3703 = or(T_3702, scoreboard_6) + node T_3704 = or(T_3703, ifin_counter.pending) + node T_3706 = eq(T_3704, UInt<1>("h0")) + all_pending_done <= T_3706 + node T_3707 = eq(state, UInt<4>("h7")) + node T_3708 = and(T_3707, all_pending_done) + when T_3708 : + state <= UInt<4>("h0") + wmask_buffer[0] <= UInt<1>("h0") + wmask_buffer[1] <= UInt<1>("h0") + wmask_buffer[2] <= UInt<1>("h0") + wmask_buffer[3] <= UInt<1>("h0") + wmask_buffer[4] <= UInt<1>("h0") + wmask_buffer[5] <= UInt<1>("h0") + wmask_buffer[6] <= UInt<1>("h0") + wmask_buffer[7] <= UInt<1>("h0") + + module LockingRRArbiter_5 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, chosen : UInt<3>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, chosen : UInt<3>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<3>("h07") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1462 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1464 : UInt, clk - node T_1466 = neq(T_1462, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_1468 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1475 : UInt<3>[1] @[Definitions.scala 355:35] - T_1475 is invalid @[Definitions.scala 355:35] - T_1475[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1477 = eq(io.out.bits.a_type, T_1475[0]) @[Package.scala 7:47] - node T_1478 = and(T_1468, T_1477) @[Definitions.scala 231:89] - node T_1479 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1480 = and(T_1479, T_1478) @[Arbiter.scala 42:25] - when T_1480 : @[Arbiter.scala 42:39] - T_1464 <= io.chosen @[Arbiter.scala 43:15] - node T_1482 = eq(T_1462, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1484 = add(T_1462, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1485 = tail(T_1484, 1) @[Counter.scala 21:22] - T_1462 <= T_1485 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1466 : @[Arbiter.scala 47:19] - io.chosen <= T_1464 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1487 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<3>, clk - when T_1487 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_4 = gt(UInt<3>("h04"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_5 = gt(UInt<3>("h05"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_6 = gt(UInt<3>("h06"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_7 = gt(UInt<3>("h07"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node validMask_4 = and(io.in[4].valid, grantMask_4) @[Arbiter.scala 60:75] - node validMask_5 = and(io.in[5].valid, grantMask_5) @[Arbiter.scala 60:75] - node validMask_6 = and(io.in[6].valid, grantMask_6) @[Arbiter.scala 60:75] - node validMask_7 = and(io.in[7].valid, grantMask_7) @[Arbiter.scala 60:75] - node T_1496 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1497 = or(T_1496, validMask_2) @[Arbiter.scala 23:72] - node T_1498 = or(T_1497, validMask_3) @[Arbiter.scala 23:72] - node T_1499 = or(T_1498, validMask_4) @[Arbiter.scala 23:72] - node T_1500 = or(T_1499, validMask_5) @[Arbiter.scala 23:72] - node T_1501 = or(T_1500, validMask_6) @[Arbiter.scala 23:72] - node T_1502 = or(T_1501, validMask_7) @[Arbiter.scala 23:72] - node T_1503 = or(T_1502, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1504 = or(T_1503, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1505 = or(T_1504, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1506 = or(T_1505, io.in[3].valid) @[Arbiter.scala 23:72] - node T_1507 = or(T_1506, io.in[4].valid) @[Arbiter.scala 23:72] - node T_1508 = or(T_1507, io.in[5].valid) @[Arbiter.scala 23:72] - node T_1509 = or(T_1508, io.in[6].valid) @[Arbiter.scala 23:72] - node T_1511 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1513 = eq(T_1496, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1515 = eq(T_1497, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1517 = eq(T_1498, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1519 = eq(T_1499, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1521 = eq(T_1500, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1523 = eq(T_1501, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1525 = eq(T_1502, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1527 = eq(T_1503, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1529 = eq(T_1504, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1531 = eq(T_1505, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1533 = eq(T_1506, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1535 = eq(T_1507, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1537 = eq(T_1508, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1539 = eq(T_1509, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1540 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1541 = or(T_1540, T_1525) @[Arbiter.scala 64:50] - node T_1542 = and(T_1511, grantMask_1) @[Arbiter.scala 64:34] - node T_1543 = or(T_1542, T_1527) @[Arbiter.scala 64:50] - node T_1544 = and(T_1513, grantMask_2) @[Arbiter.scala 64:34] - node T_1545 = or(T_1544, T_1529) @[Arbiter.scala 64:50] - node T_1546 = and(T_1515, grantMask_3) @[Arbiter.scala 64:34] - node T_1547 = or(T_1546, T_1531) @[Arbiter.scala 64:50] - node T_1548 = and(T_1517, grantMask_4) @[Arbiter.scala 64:34] - node T_1549 = or(T_1548, T_1533) @[Arbiter.scala 64:50] - node T_1550 = and(T_1519, grantMask_5) @[Arbiter.scala 64:34] - node T_1551 = or(T_1550, T_1535) @[Arbiter.scala 64:50] - node T_1552 = and(T_1521, grantMask_6) @[Arbiter.scala 64:34] - node T_1553 = or(T_1552, T_1537) @[Arbiter.scala 64:50] - node T_1554 = and(T_1523, grantMask_7) @[Arbiter.scala 64:34] - node T_1555 = or(T_1554, T_1539) @[Arbiter.scala 64:50] - node T_1557 = eq(T_1464, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1558 = mux(T_1466, T_1557, T_1541) @[Arbiter.scala 49:22] - node T_1559 = and(T_1558, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1559 @[Arbiter.scala 49:16] - node T_1561 = eq(T_1464, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1562 = mux(T_1466, T_1561, T_1543) @[Arbiter.scala 49:22] - node T_1563 = and(T_1562, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1563 @[Arbiter.scala 49:16] - node T_1565 = eq(T_1464, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1566 = mux(T_1466, T_1565, T_1545) @[Arbiter.scala 49:22] - node T_1567 = and(T_1566, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1567 @[Arbiter.scala 49:16] - node T_1569 = eq(T_1464, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1570 = mux(T_1466, T_1569, T_1547) @[Arbiter.scala 49:22] - node T_1571 = and(T_1570, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1571 @[Arbiter.scala 49:16] - node T_1573 = eq(T_1464, UInt<3>("h04")) @[Arbiter.scala 49:39] - node T_1574 = mux(T_1466, T_1573, T_1549) @[Arbiter.scala 49:22] - node T_1575 = and(T_1574, io.out.ready) @[Arbiter.scala 49:55] - io.in[4].ready <= T_1575 @[Arbiter.scala 49:16] - node T_1577 = eq(T_1464, UInt<3>("h05")) @[Arbiter.scala 49:39] - node T_1578 = mux(T_1466, T_1577, T_1551) @[Arbiter.scala 49:22] - node T_1579 = and(T_1578, io.out.ready) @[Arbiter.scala 49:55] - io.in[5].ready <= T_1579 @[Arbiter.scala 49:16] - node T_1581 = eq(T_1464, UInt<3>("h06")) @[Arbiter.scala 49:39] - node T_1582 = mux(T_1466, T_1581, T_1553) @[Arbiter.scala 49:22] - node T_1583 = and(T_1582, io.out.ready) @[Arbiter.scala 49:55] - io.in[6].ready <= T_1583 @[Arbiter.scala 49:16] - node T_1585 = eq(T_1464, UInt<3>("h07")) @[Arbiter.scala 49:39] - node T_1586 = mux(T_1466, T_1585, T_1555) @[Arbiter.scala 49:22] - node T_1587 = and(T_1586, io.out.ready) @[Arbiter.scala 49:55] - io.in[7].ready <= T_1587 @[Arbiter.scala 49:16] - when io.in[6].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h06") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[5].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h05") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[4].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h04") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[3].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h03") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_7 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h07") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_6 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h06") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_5 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h05") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_4 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h04") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module LockingRRArbiter_6 : + choice <= UInt<3>("h7") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1462 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1464 : UInt, clk with : + reset => (UInt<1>("h0"), T_1464) + node T_1466 = neq(T_1462, UInt<1>("h0")) + node T_1468 = and(UInt<1>("h1"), io.out.bits.is_builtin_type) + wire T_1475 : UInt<3>[1] + T_1475 is invalid + T_1475[0] <= UInt<3>("h3") + node T_1477 = eq(io.out.bits.a_type, T_1475[0]) + node T_1478 = and(T_1468, T_1477) + node T_1479 = and(io.out.ready, io.out.valid) + node T_1480 = and(T_1479, T_1478) + when T_1480 : + T_1464 <= io.chosen + node T_1482 = eq(T_1462, UInt<3>("h7")) + node T_1484 = add(T_1462, UInt<1>("h1")) + node T_1485 = tail(T_1484, 1) + T_1462 <= T_1485 + when T_1466 : + io.chosen <= T_1464 + node T_1487 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<3>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1487 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node grantMask_4 = gt(UInt<3>("h4"), lastGrant) + node grantMask_5 = gt(UInt<3>("h5"), lastGrant) + node grantMask_6 = gt(UInt<3>("h6"), lastGrant) + node grantMask_7 = gt(UInt<3>("h7"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node validMask_4 = and(io.in[4].valid, grantMask_4) + node validMask_5 = and(io.in[5].valid, grantMask_5) + node validMask_6 = and(io.in[6].valid, grantMask_6) + node validMask_7 = and(io.in[7].valid, grantMask_7) + node T_1496 = or(validMask_0, validMask_1) + node T_1497 = or(T_1496, validMask_2) + node T_1498 = or(T_1497, validMask_3) + node T_1499 = or(T_1498, validMask_4) + node T_1500 = or(T_1499, validMask_5) + node T_1501 = or(T_1500, validMask_6) + node T_1502 = or(T_1501, validMask_7) + node T_1503 = or(T_1502, io.in[0].valid) + node T_1504 = or(T_1503, io.in[1].valid) + node T_1505 = or(T_1504, io.in[2].valid) + node T_1506 = or(T_1505, io.in[3].valid) + node T_1507 = or(T_1506, io.in[4].valid) + node T_1508 = or(T_1507, io.in[5].valid) + node T_1509 = or(T_1508, io.in[6].valid) + node T_1511 = eq(validMask_0, UInt<1>("h0")) + node T_1513 = eq(T_1496, UInt<1>("h0")) + node T_1515 = eq(T_1497, UInt<1>("h0")) + node T_1517 = eq(T_1498, UInt<1>("h0")) + node T_1519 = eq(T_1499, UInt<1>("h0")) + node T_1521 = eq(T_1500, UInt<1>("h0")) + node T_1523 = eq(T_1501, UInt<1>("h0")) + node T_1525 = eq(T_1502, UInt<1>("h0")) + node T_1527 = eq(T_1503, UInt<1>("h0")) + node T_1529 = eq(T_1504, UInt<1>("h0")) + node T_1531 = eq(T_1505, UInt<1>("h0")) + node T_1533 = eq(T_1506, UInt<1>("h0")) + node T_1535 = eq(T_1507, UInt<1>("h0")) + node T_1537 = eq(T_1508, UInt<1>("h0")) + node T_1539 = eq(T_1509, UInt<1>("h0")) + node T_1540 = and(UInt<1>("h1"), grantMask_0) + node T_1541 = or(T_1540, T_1525) + node T_1542 = and(T_1511, grantMask_1) + node T_1543 = or(T_1542, T_1527) + node T_1544 = and(T_1513, grantMask_2) + node T_1545 = or(T_1544, T_1529) + node T_1546 = and(T_1515, grantMask_3) + node T_1547 = or(T_1546, T_1531) + node T_1548 = and(T_1517, grantMask_4) + node T_1549 = or(T_1548, T_1533) + node T_1550 = and(T_1519, grantMask_5) + node T_1551 = or(T_1550, T_1535) + node T_1552 = and(T_1521, grantMask_6) + node T_1553 = or(T_1552, T_1537) + node T_1554 = and(T_1523, grantMask_7) + node T_1555 = or(T_1554, T_1539) + node T_1557 = eq(T_1464, UInt<1>("h0")) + node T_1558 = mux(T_1466, T_1557, T_1541) + node T_1559 = and(T_1558, io.out.ready) + io.in[0].ready <= T_1559 + node T_1561 = eq(T_1464, UInt<1>("h1")) + node T_1562 = mux(T_1466, T_1561, T_1543) + node T_1563 = and(T_1562, io.out.ready) + io.in[1].ready <= T_1563 + node T_1565 = eq(T_1464, UInt<2>("h2")) + node T_1566 = mux(T_1466, T_1565, T_1545) + node T_1567 = and(T_1566, io.out.ready) + io.in[2].ready <= T_1567 + node T_1569 = eq(T_1464, UInt<2>("h3")) + node T_1570 = mux(T_1466, T_1569, T_1547) + node T_1571 = and(T_1570, io.out.ready) + io.in[3].ready <= T_1571 + node T_1573 = eq(T_1464, UInt<3>("h4")) + node T_1574 = mux(T_1466, T_1573, T_1549) + node T_1575 = and(T_1574, io.out.ready) + io.in[4].ready <= T_1575 + node T_1577 = eq(T_1464, UInt<3>("h5")) + node T_1578 = mux(T_1466, T_1577, T_1551) + node T_1579 = and(T_1578, io.out.ready) + io.in[5].ready <= T_1579 + node T_1581 = eq(T_1464, UInt<3>("h6")) + node T_1582 = mux(T_1466, T_1581, T_1553) + node T_1583 = and(T_1582, io.out.ready) + io.in[6].ready <= T_1583 + node T_1585 = eq(T_1464, UInt<3>("h7")) + node T_1586 = mux(T_1466, T_1585, T_1555) + node T_1587 = and(T_1586, io.out.ready) + io.in[7].ready <= T_1587 + when io.in[6].valid : + choice <= UInt<3>("h6") + when io.in[5].valid : + choice <= UInt<3>("h5") + when io.in[4].valid : + choice <= UInt<3>("h4") + when io.in[3].valid : + choice <= UInt<2>("h3") + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_7 : + choice <= UInt<3>("h7") + when validMask_6 : + choice <= UInt<3>("h6") + when validMask_5 : + choice <= UInt<3>("h5") + when validMask_4 : + choice <= UInt<3>("h4") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module LockingRRArbiter_6 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, chosen : UInt<3>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, chosen : UInt<3>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<3>("h07") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1412 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1414 : UInt, clk - node T_1416 = neq(T_1412, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_1418 = eq(io.out.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1419 = eq(io.out.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1420 = eq(io.out.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1421 = or(T_1418, T_1419) @[Package.scala 7:62] - node T_1422 = or(T_1421, T_1420) @[Package.scala 7:62] - node T_1423 = and(UInt<1>("h01"), T_1422) @[Definitions.scala 256:64] - node T_1424 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1425 = and(T_1424, T_1423) @[Arbiter.scala 42:25] - when T_1425 : @[Arbiter.scala 42:39] - T_1414 <= io.chosen @[Arbiter.scala 43:15] - node T_1427 = eq(T_1412, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1429 = add(T_1412, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1430 = tail(T_1429, 1) @[Counter.scala 21:22] - T_1412 <= T_1430 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1416 : @[Arbiter.scala 47:19] - io.chosen <= T_1414 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1432 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<3>, clk - when T_1432 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_4 = gt(UInt<3>("h04"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_5 = gt(UInt<3>("h05"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_6 = gt(UInt<3>("h06"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_7 = gt(UInt<3>("h07"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node validMask_4 = and(io.in[4].valid, grantMask_4) @[Arbiter.scala 60:75] - node validMask_5 = and(io.in[5].valid, grantMask_5) @[Arbiter.scala 60:75] - node validMask_6 = and(io.in[6].valid, grantMask_6) @[Arbiter.scala 60:75] - node validMask_7 = and(io.in[7].valid, grantMask_7) @[Arbiter.scala 60:75] - node T_1441 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1442 = or(T_1441, validMask_2) @[Arbiter.scala 23:72] - node T_1443 = or(T_1442, validMask_3) @[Arbiter.scala 23:72] - node T_1444 = or(T_1443, validMask_4) @[Arbiter.scala 23:72] - node T_1445 = or(T_1444, validMask_5) @[Arbiter.scala 23:72] - node T_1446 = or(T_1445, validMask_6) @[Arbiter.scala 23:72] - node T_1447 = or(T_1446, validMask_7) @[Arbiter.scala 23:72] - node T_1448 = or(T_1447, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1449 = or(T_1448, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1450 = or(T_1449, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1451 = or(T_1450, io.in[3].valid) @[Arbiter.scala 23:72] - node T_1452 = or(T_1451, io.in[4].valid) @[Arbiter.scala 23:72] - node T_1453 = or(T_1452, io.in[5].valid) @[Arbiter.scala 23:72] - node T_1454 = or(T_1453, io.in[6].valid) @[Arbiter.scala 23:72] - node T_1456 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1458 = eq(T_1441, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1460 = eq(T_1442, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1462 = eq(T_1443, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1464 = eq(T_1444, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1466 = eq(T_1445, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1468 = eq(T_1446, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1470 = eq(T_1447, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1472 = eq(T_1448, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1474 = eq(T_1449, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1476 = eq(T_1450, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1478 = eq(T_1451, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1480 = eq(T_1452, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1482 = eq(T_1453, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1484 = eq(T_1454, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1485 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1486 = or(T_1485, T_1470) @[Arbiter.scala 64:50] - node T_1487 = and(T_1456, grantMask_1) @[Arbiter.scala 64:34] - node T_1488 = or(T_1487, T_1472) @[Arbiter.scala 64:50] - node T_1489 = and(T_1458, grantMask_2) @[Arbiter.scala 64:34] - node T_1490 = or(T_1489, T_1474) @[Arbiter.scala 64:50] - node T_1491 = and(T_1460, grantMask_3) @[Arbiter.scala 64:34] - node T_1492 = or(T_1491, T_1476) @[Arbiter.scala 64:50] - node T_1493 = and(T_1462, grantMask_4) @[Arbiter.scala 64:34] - node T_1494 = or(T_1493, T_1478) @[Arbiter.scala 64:50] - node T_1495 = and(T_1464, grantMask_5) @[Arbiter.scala 64:34] - node T_1496 = or(T_1495, T_1480) @[Arbiter.scala 64:50] - node T_1497 = and(T_1466, grantMask_6) @[Arbiter.scala 64:34] - node T_1498 = or(T_1497, T_1482) @[Arbiter.scala 64:50] - node T_1499 = and(T_1468, grantMask_7) @[Arbiter.scala 64:34] - node T_1500 = or(T_1499, T_1484) @[Arbiter.scala 64:50] - node T_1502 = eq(T_1414, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1503 = mux(T_1416, T_1502, T_1486) @[Arbiter.scala 49:22] - node T_1504 = and(T_1503, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1504 @[Arbiter.scala 49:16] - node T_1506 = eq(T_1414, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1507 = mux(T_1416, T_1506, T_1488) @[Arbiter.scala 49:22] - node T_1508 = and(T_1507, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1508 @[Arbiter.scala 49:16] - node T_1510 = eq(T_1414, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1511 = mux(T_1416, T_1510, T_1490) @[Arbiter.scala 49:22] - node T_1512 = and(T_1511, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1512 @[Arbiter.scala 49:16] - node T_1514 = eq(T_1414, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1515 = mux(T_1416, T_1514, T_1492) @[Arbiter.scala 49:22] - node T_1516 = and(T_1515, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1516 @[Arbiter.scala 49:16] - node T_1518 = eq(T_1414, UInt<3>("h04")) @[Arbiter.scala 49:39] - node T_1519 = mux(T_1416, T_1518, T_1494) @[Arbiter.scala 49:22] - node T_1520 = and(T_1519, io.out.ready) @[Arbiter.scala 49:55] - io.in[4].ready <= T_1520 @[Arbiter.scala 49:16] - node T_1522 = eq(T_1414, UInt<3>("h05")) @[Arbiter.scala 49:39] - node T_1523 = mux(T_1416, T_1522, T_1496) @[Arbiter.scala 49:22] - node T_1524 = and(T_1523, io.out.ready) @[Arbiter.scala 49:55] - io.in[5].ready <= T_1524 @[Arbiter.scala 49:16] - node T_1526 = eq(T_1414, UInt<3>("h06")) @[Arbiter.scala 49:39] - node T_1527 = mux(T_1416, T_1526, T_1498) @[Arbiter.scala 49:22] - node T_1528 = and(T_1527, io.out.ready) @[Arbiter.scala 49:55] - io.in[6].ready <= T_1528 @[Arbiter.scala 49:16] - node T_1530 = eq(T_1414, UInt<3>("h07")) @[Arbiter.scala 49:39] - node T_1531 = mux(T_1416, T_1530, T_1500) @[Arbiter.scala 49:22] - node T_1532 = and(T_1531, io.out.ready) @[Arbiter.scala 49:55] - io.in[7].ready <= T_1532 @[Arbiter.scala 49:16] - when io.in[6].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h06") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[5].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h05") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[4].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h04") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[3].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h03") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_7 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h07") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_6 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h06") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_5 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h05") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_4 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h04") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module ClientTileLinkIOArbiter : + choice <= UInt<3>("h7") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1412 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1414 : UInt, clk with : + reset => (UInt<1>("h0"), T_1414) + node T_1416 = neq(T_1412, UInt<1>("h0")) + node T_1418 = eq(io.out.bits.r_type, UInt<3>("h0")) + node T_1419 = eq(io.out.bits.r_type, UInt<3>("h1")) + node T_1420 = eq(io.out.bits.r_type, UInt<3>("h2")) + node T_1421 = or(T_1418, T_1419) + node T_1422 = or(T_1421, T_1420) + node T_1423 = and(UInt<1>("h1"), T_1422) + node T_1424 = and(io.out.ready, io.out.valid) + node T_1425 = and(T_1424, T_1423) + when T_1425 : + T_1414 <= io.chosen + node T_1427 = eq(T_1412, UInt<3>("h7")) + node T_1429 = add(T_1412, UInt<1>("h1")) + node T_1430 = tail(T_1429, 1) + T_1412 <= T_1430 + when T_1416 : + io.chosen <= T_1414 + node T_1432 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<3>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1432 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node grantMask_4 = gt(UInt<3>("h4"), lastGrant) + node grantMask_5 = gt(UInt<3>("h5"), lastGrant) + node grantMask_6 = gt(UInt<3>("h6"), lastGrant) + node grantMask_7 = gt(UInt<3>("h7"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node validMask_4 = and(io.in[4].valid, grantMask_4) + node validMask_5 = and(io.in[5].valid, grantMask_5) + node validMask_6 = and(io.in[6].valid, grantMask_6) + node validMask_7 = and(io.in[7].valid, grantMask_7) + node T_1441 = or(validMask_0, validMask_1) + node T_1442 = or(T_1441, validMask_2) + node T_1443 = or(T_1442, validMask_3) + node T_1444 = or(T_1443, validMask_4) + node T_1445 = or(T_1444, validMask_5) + node T_1446 = or(T_1445, validMask_6) + node T_1447 = or(T_1446, validMask_7) + node T_1448 = or(T_1447, io.in[0].valid) + node T_1449 = or(T_1448, io.in[1].valid) + node T_1450 = or(T_1449, io.in[2].valid) + node T_1451 = or(T_1450, io.in[3].valid) + node T_1452 = or(T_1451, io.in[4].valid) + node T_1453 = or(T_1452, io.in[5].valid) + node T_1454 = or(T_1453, io.in[6].valid) + node T_1456 = eq(validMask_0, UInt<1>("h0")) + node T_1458 = eq(T_1441, UInt<1>("h0")) + node T_1460 = eq(T_1442, UInt<1>("h0")) + node T_1462 = eq(T_1443, UInt<1>("h0")) + node T_1464 = eq(T_1444, UInt<1>("h0")) + node T_1466 = eq(T_1445, UInt<1>("h0")) + node T_1468 = eq(T_1446, UInt<1>("h0")) + node T_1470 = eq(T_1447, UInt<1>("h0")) + node T_1472 = eq(T_1448, UInt<1>("h0")) + node T_1474 = eq(T_1449, UInt<1>("h0")) + node T_1476 = eq(T_1450, UInt<1>("h0")) + node T_1478 = eq(T_1451, UInt<1>("h0")) + node T_1480 = eq(T_1452, UInt<1>("h0")) + node T_1482 = eq(T_1453, UInt<1>("h0")) + node T_1484 = eq(T_1454, UInt<1>("h0")) + node T_1485 = and(UInt<1>("h1"), grantMask_0) + node T_1486 = or(T_1485, T_1470) + node T_1487 = and(T_1456, grantMask_1) + node T_1488 = or(T_1487, T_1472) + node T_1489 = and(T_1458, grantMask_2) + node T_1490 = or(T_1489, T_1474) + node T_1491 = and(T_1460, grantMask_3) + node T_1492 = or(T_1491, T_1476) + node T_1493 = and(T_1462, grantMask_4) + node T_1494 = or(T_1493, T_1478) + node T_1495 = and(T_1464, grantMask_5) + node T_1496 = or(T_1495, T_1480) + node T_1497 = and(T_1466, grantMask_6) + node T_1498 = or(T_1497, T_1482) + node T_1499 = and(T_1468, grantMask_7) + node T_1500 = or(T_1499, T_1484) + node T_1502 = eq(T_1414, UInt<1>("h0")) + node T_1503 = mux(T_1416, T_1502, T_1486) + node T_1504 = and(T_1503, io.out.ready) + io.in[0].ready <= T_1504 + node T_1506 = eq(T_1414, UInt<1>("h1")) + node T_1507 = mux(T_1416, T_1506, T_1488) + node T_1508 = and(T_1507, io.out.ready) + io.in[1].ready <= T_1508 + node T_1510 = eq(T_1414, UInt<2>("h2")) + node T_1511 = mux(T_1416, T_1510, T_1490) + node T_1512 = and(T_1511, io.out.ready) + io.in[2].ready <= T_1512 + node T_1514 = eq(T_1414, UInt<2>("h3")) + node T_1515 = mux(T_1416, T_1514, T_1492) + node T_1516 = and(T_1515, io.out.ready) + io.in[3].ready <= T_1516 + node T_1518 = eq(T_1414, UInt<3>("h4")) + node T_1519 = mux(T_1416, T_1518, T_1494) + node T_1520 = and(T_1519, io.out.ready) + io.in[4].ready <= T_1520 + node T_1522 = eq(T_1414, UInt<3>("h5")) + node T_1523 = mux(T_1416, T_1522, T_1496) + node T_1524 = and(T_1523, io.out.ready) + io.in[5].ready <= T_1524 + node T_1526 = eq(T_1414, UInt<3>("h6")) + node T_1527 = mux(T_1416, T_1526, T_1498) + node T_1528 = and(T_1527, io.out.ready) + io.in[6].ready <= T_1528 + node T_1530 = eq(T_1414, UInt<3>("h7")) + node T_1531 = mux(T_1416, T_1530, T_1500) + node T_1532 = and(T_1531, io.out.ready) + io.in[7].ready <= T_1532 + when io.in[6].valid : + choice <= UInt<3>("h6") + when io.in[5].valid : + choice <= UInt<3>("h5") + when io.in[4].valid : + choice <= UInt<3>("h4") + when io.in[3].valid : + choice <= UInt<2>("h3") + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_7 : + choice <= UInt<3>("h7") + when validMask_6 : + choice <= UInt<3>("h6") + when validMask_5 : + choice <= UInt<3>("h5") + when validMask_4 : + choice <= UInt<3>("h4") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module ClientTileLinkIOArbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}[8], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} + io is invalid - inst LockingRRArbiter_5_1 of LockingRRArbiter_5 @[Arbiters.scala 41:21] + inst LockingRRArbiter_5_1 of LockingRRArbiter_5 LockingRRArbiter_5_1.io is invalid LockingRRArbiter_5_1.clk <= clk LockingRRArbiter_5_1.reset <= reset - LockingRRArbiter_5_1.io.in[0].valid <= io.in[0].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[0].bits <- io.in[0].acquire.bits @[Arbiters.scala 44:16] - node T_12220 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[0].bits.client_xact_id <= T_12220 @[Arbiters.scala 45:31] - io.in[0].acquire.ready <= LockingRRArbiter_5_1.io.in[0].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[1].valid <= io.in[1].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[1].bits <- io.in[1].acquire.bits @[Arbiters.scala 44:16] - node T_12222 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[1].bits.client_xact_id <= T_12222 @[Arbiters.scala 45:31] - io.in[1].acquire.ready <= LockingRRArbiter_5_1.io.in[1].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[2].valid <= io.in[2].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[2].bits <- io.in[2].acquire.bits @[Arbiters.scala 44:16] - node T_12224 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[2].bits.client_xact_id <= T_12224 @[Arbiters.scala 45:31] - io.in[2].acquire.ready <= LockingRRArbiter_5_1.io.in[2].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[3].valid <= io.in[3].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[3].bits <- io.in[3].acquire.bits @[Arbiters.scala 44:16] - node T_12226 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[3].bits.client_xact_id <= T_12226 @[Arbiters.scala 45:31] - io.in[3].acquire.ready <= LockingRRArbiter_5_1.io.in[3].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[4].valid <= io.in[4].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[4].bits <- io.in[4].acquire.bits @[Arbiters.scala 44:16] - node T_12228 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[4].bits.client_xact_id <= T_12228 @[Arbiters.scala 45:31] - io.in[4].acquire.ready <= LockingRRArbiter_5_1.io.in[4].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[5].valid <= io.in[5].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[5].bits <- io.in[5].acquire.bits @[Arbiters.scala 44:16] - node T_12230 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[5].bits.client_xact_id <= T_12230 @[Arbiters.scala 45:31] - io.in[5].acquire.ready <= LockingRRArbiter_5_1.io.in[5].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[6].valid <= io.in[6].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[6].bits <- io.in[6].acquire.bits @[Arbiters.scala 44:16] - node T_12232 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[6].bits.client_xact_id <= T_12232 @[Arbiters.scala 45:31] - io.in[6].acquire.ready <= LockingRRArbiter_5_1.io.in[6].ready @[Arbiters.scala 46:17] - LockingRRArbiter_5_1.io.in[7].valid <= io.in[7].acquire.valid @[Arbiters.scala 43:17] - LockingRRArbiter_5_1.io.in[7].bits <- io.in[7].acquire.bits @[Arbiters.scala 44:16] - node T_12234 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) @[Cat.scala 20:58] - LockingRRArbiter_5_1.io.in[7].bits.client_xact_id <= T_12234 @[Arbiters.scala 45:31] - io.in[7].acquire.ready <= LockingRRArbiter_5_1.io.in[7].ready @[Arbiters.scala 46:17] - io.out.acquire <- LockingRRArbiter_5_1.io.out @[Arbiters.scala 48:10] - inst LockingRRArbiter_6_1 of LockingRRArbiter_6 @[Arbiters.scala 41:21] + LockingRRArbiter_5_1.io.in[0].valid <= io.in[0].acquire.valid + LockingRRArbiter_5_1.io.in[0].bits <- io.in[0].acquire.bits + node T_12220 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h0")) + LockingRRArbiter_5_1.io.in[0].bits.client_xact_id <= T_12220 + io.in[0].acquire.ready <= LockingRRArbiter_5_1.io.in[0].ready + LockingRRArbiter_5_1.io.in[1].valid <= io.in[1].acquire.valid + LockingRRArbiter_5_1.io.in[1].bits <- io.in[1].acquire.bits + node T_12222 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h1")) + LockingRRArbiter_5_1.io.in[1].bits.client_xact_id <= T_12222 + io.in[1].acquire.ready <= LockingRRArbiter_5_1.io.in[1].ready + LockingRRArbiter_5_1.io.in[2].valid <= io.in[2].acquire.valid + LockingRRArbiter_5_1.io.in[2].bits <- io.in[2].acquire.bits + node T_12224 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h2")) + LockingRRArbiter_5_1.io.in[2].bits.client_xact_id <= T_12224 + io.in[2].acquire.ready <= LockingRRArbiter_5_1.io.in[2].ready + LockingRRArbiter_5_1.io.in[3].valid <= io.in[3].acquire.valid + LockingRRArbiter_5_1.io.in[3].bits <- io.in[3].acquire.bits + node T_12226 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h3")) + LockingRRArbiter_5_1.io.in[3].bits.client_xact_id <= T_12226 + io.in[3].acquire.ready <= LockingRRArbiter_5_1.io.in[3].ready + LockingRRArbiter_5_1.io.in[4].valid <= io.in[4].acquire.valid + LockingRRArbiter_5_1.io.in[4].bits <- io.in[4].acquire.bits + node T_12228 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h4")) + LockingRRArbiter_5_1.io.in[4].bits.client_xact_id <= T_12228 + io.in[4].acquire.ready <= LockingRRArbiter_5_1.io.in[4].ready + LockingRRArbiter_5_1.io.in[5].valid <= io.in[5].acquire.valid + LockingRRArbiter_5_1.io.in[5].bits <- io.in[5].acquire.bits + node T_12230 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h5")) + LockingRRArbiter_5_1.io.in[5].bits.client_xact_id <= T_12230 + io.in[5].acquire.ready <= LockingRRArbiter_5_1.io.in[5].ready + LockingRRArbiter_5_1.io.in[6].valid <= io.in[6].acquire.valid + LockingRRArbiter_5_1.io.in[6].bits <- io.in[6].acquire.bits + node T_12232 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h6")) + LockingRRArbiter_5_1.io.in[6].bits.client_xact_id <= T_12232 + io.in[6].acquire.ready <= LockingRRArbiter_5_1.io.in[6].ready + LockingRRArbiter_5_1.io.in[7].valid <= io.in[7].acquire.valid + LockingRRArbiter_5_1.io.in[7].bits <- io.in[7].acquire.bits + node T_12234 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h7")) + LockingRRArbiter_5_1.io.in[7].bits.client_xact_id <= T_12234 + io.in[7].acquire.ready <= LockingRRArbiter_5_1.io.in[7].ready + io.out.acquire <- LockingRRArbiter_5_1.io.out + inst LockingRRArbiter_6_1 of LockingRRArbiter_6 LockingRRArbiter_6_1.io is invalid LockingRRArbiter_6_1.clk <= clk LockingRRArbiter_6_1.reset <= reset - LockingRRArbiter_6_1.io.in[0].valid <= io.in[0].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[0].bits <- io.in[0].release.bits @[Arbiters.scala 44:16] - node T_12236 = cat(io.in[0].release.bits.client_xact_id, UInt<3>("h00")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[0].bits.client_xact_id <= T_12236 @[Arbiters.scala 45:31] - io.in[0].release.ready <= LockingRRArbiter_6_1.io.in[0].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[1].valid <= io.in[1].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[1].bits <- io.in[1].release.bits @[Arbiters.scala 44:16] - node T_12238 = cat(io.in[1].release.bits.client_xact_id, UInt<3>("h01")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[1].bits.client_xact_id <= T_12238 @[Arbiters.scala 45:31] - io.in[1].release.ready <= LockingRRArbiter_6_1.io.in[1].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[2].valid <= io.in[2].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[2].bits <- io.in[2].release.bits @[Arbiters.scala 44:16] - node T_12240 = cat(io.in[2].release.bits.client_xact_id, UInt<3>("h02")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[2].bits.client_xact_id <= T_12240 @[Arbiters.scala 45:31] - io.in[2].release.ready <= LockingRRArbiter_6_1.io.in[2].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[3].valid <= io.in[3].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[3].bits <- io.in[3].release.bits @[Arbiters.scala 44:16] - node T_12242 = cat(io.in[3].release.bits.client_xact_id, UInt<3>("h03")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[3].bits.client_xact_id <= T_12242 @[Arbiters.scala 45:31] - io.in[3].release.ready <= LockingRRArbiter_6_1.io.in[3].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[4].valid <= io.in[4].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[4].bits <- io.in[4].release.bits @[Arbiters.scala 44:16] - node T_12244 = cat(io.in[4].release.bits.client_xact_id, UInt<3>("h04")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[4].bits.client_xact_id <= T_12244 @[Arbiters.scala 45:31] - io.in[4].release.ready <= LockingRRArbiter_6_1.io.in[4].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[5].valid <= io.in[5].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[5].bits <- io.in[5].release.bits @[Arbiters.scala 44:16] - node T_12246 = cat(io.in[5].release.bits.client_xact_id, UInt<3>("h05")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[5].bits.client_xact_id <= T_12246 @[Arbiters.scala 45:31] - io.in[5].release.ready <= LockingRRArbiter_6_1.io.in[5].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[6].valid <= io.in[6].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[6].bits <- io.in[6].release.bits @[Arbiters.scala 44:16] - node T_12248 = cat(io.in[6].release.bits.client_xact_id, UInt<3>("h06")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[6].bits.client_xact_id <= T_12248 @[Arbiters.scala 45:31] - io.in[6].release.ready <= LockingRRArbiter_6_1.io.in[6].ready @[Arbiters.scala 46:17] - LockingRRArbiter_6_1.io.in[7].valid <= io.in[7].release.valid @[Arbiters.scala 43:17] - LockingRRArbiter_6_1.io.in[7].bits <- io.in[7].release.bits @[Arbiters.scala 44:16] - node T_12250 = cat(io.in[7].release.bits.client_xact_id, UInt<3>("h07")) @[Cat.scala 20:58] - LockingRRArbiter_6_1.io.in[7].bits.client_xact_id <= T_12250 @[Arbiters.scala 45:31] - io.in[7].release.ready <= LockingRRArbiter_6_1.io.in[7].ready @[Arbiters.scala 46:17] - io.out.release <- LockingRRArbiter_6_1.io.out @[Arbiters.scala 48:10] - io.in[0].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[1].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[2].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[3].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[4].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[5].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[6].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[7].probe.valid <= io.out.probe.valid @[Arbiters.scala 96:23] - io.in[0].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[1].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[2].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[3].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[4].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[5].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[6].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - io.in[7].probe.bits <- io.out.probe.bits @[Arbiters.scala 97:22] - node T_12251 = and(io.in[0].probe.ready, io.in[1].probe.ready) @[Arbiters.scala 98:45] - node T_12252 = and(T_12251, io.in[2].probe.ready) @[Arbiters.scala 98:45] - node T_12253 = and(T_12252, io.in[3].probe.ready) @[Arbiters.scala 98:45] - node T_12254 = and(T_12253, io.in[4].probe.ready) @[Arbiters.scala 98:45] - node T_12255 = and(T_12254, io.in[5].probe.ready) @[Arbiters.scala 98:45] - node T_12256 = and(T_12255, io.in[6].probe.ready) @[Arbiters.scala 98:45] - node T_12257 = and(T_12256, io.in[7].probe.ready) @[Arbiters.scala 98:45] - io.out.probe.ready <= T_12257 @[Arbiters.scala 98:16] - io.out.grant.ready <= UInt<1>("h00") @[Arbiters.scala 83:16] - io.in[0].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12260 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12262 = eq(T_12260, UInt<1>("h00")) @[Arbiters.scala 86:31] - when T_12262 : @[Arbiters.scala 86:44] - io.in[0].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[0].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[0].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12263 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[0].grant.bits.client_xact_id <= T_12263 @[Arbiters.scala 91:35] - io.in[1].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12265 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12267 = eq(T_12265, UInt<1>("h01")) @[Arbiters.scala 86:31] - when T_12267 : @[Arbiters.scala 86:44] - io.in[1].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[1].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[1].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12268 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[1].grant.bits.client_xact_id <= T_12268 @[Arbiters.scala 91:35] - io.in[2].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12270 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12272 = eq(T_12270, UInt<2>("h02")) @[Arbiters.scala 86:31] - when T_12272 : @[Arbiters.scala 86:44] - io.in[2].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[2].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[2].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12273 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[2].grant.bits.client_xact_id <= T_12273 @[Arbiters.scala 91:35] - io.in[3].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12275 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12277 = eq(T_12275, UInt<2>("h03")) @[Arbiters.scala 86:31] - when T_12277 : @[Arbiters.scala 86:44] - io.in[3].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[3].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[3].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12278 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[3].grant.bits.client_xact_id <= T_12278 @[Arbiters.scala 91:35] - io.in[4].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12280 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12282 = eq(T_12280, UInt<3>("h04")) @[Arbiters.scala 86:31] - when T_12282 : @[Arbiters.scala 86:44] - io.in[4].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[4].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[4].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12283 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[4].grant.bits.client_xact_id <= T_12283 @[Arbiters.scala 91:35] - io.in[5].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12285 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12287 = eq(T_12285, UInt<3>("h05")) @[Arbiters.scala 86:31] - when T_12287 : @[Arbiters.scala 86:44] - io.in[5].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[5].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[5].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12288 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[5].grant.bits.client_xact_id <= T_12288 @[Arbiters.scala 91:35] - io.in[6].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12290 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12292 = eq(T_12290, UInt<3>("h06")) @[Arbiters.scala 86:31] - when T_12292 : @[Arbiters.scala 86:44] - io.in[6].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[6].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[6].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12293 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[6].grant.bits.client_xact_id <= T_12293 @[Arbiters.scala 91:35] - io.in[7].grant.valid <= UInt<1>("h00") @[Arbiters.scala 85:21] - node T_12295 = bits(io.out.grant.bits.client_xact_id, 2, 0) @[Arbiters.scala 147:59] - node T_12297 = eq(T_12295, UInt<3>("h07")) @[Arbiters.scala 86:31] - when T_12297 : @[Arbiters.scala 86:44] - io.in[7].grant.valid <= io.out.grant.valid @[Arbiters.scala 87:23] - io.out.grant.ready <= io.in[7].grant.ready @[Arbiters.scala 88:20] - skip @[Arbiters.scala 86:44] - io.in[7].grant.bits <- io.out.grant.bits @[Arbiters.scala 90:20] - node T_12298 = shr(io.out.grant.bits.client_xact_id, 3) @[Arbiters.scala 143:25] - io.in[7].grant.bits.client_xact_id <= T_12298 @[Arbiters.scala 91:35] - - module LockingRRArbiter_7 : + LockingRRArbiter_6_1.io.in[0].valid <= io.in[0].release.valid + LockingRRArbiter_6_1.io.in[0].bits <- io.in[0].release.bits + node T_12236 = cat(io.in[0].release.bits.client_xact_id, UInt<3>("h0")) + LockingRRArbiter_6_1.io.in[0].bits.client_xact_id <= T_12236 + io.in[0].release.ready <= LockingRRArbiter_6_1.io.in[0].ready + LockingRRArbiter_6_1.io.in[1].valid <= io.in[1].release.valid + LockingRRArbiter_6_1.io.in[1].bits <- io.in[1].release.bits + node T_12238 = cat(io.in[1].release.bits.client_xact_id, UInt<3>("h1")) + LockingRRArbiter_6_1.io.in[1].bits.client_xact_id <= T_12238 + io.in[1].release.ready <= LockingRRArbiter_6_1.io.in[1].ready + LockingRRArbiter_6_1.io.in[2].valid <= io.in[2].release.valid + LockingRRArbiter_6_1.io.in[2].bits <- io.in[2].release.bits + node T_12240 = cat(io.in[2].release.bits.client_xact_id, UInt<3>("h2")) + LockingRRArbiter_6_1.io.in[2].bits.client_xact_id <= T_12240 + io.in[2].release.ready <= LockingRRArbiter_6_1.io.in[2].ready + LockingRRArbiter_6_1.io.in[3].valid <= io.in[3].release.valid + LockingRRArbiter_6_1.io.in[3].bits <- io.in[3].release.bits + node T_12242 = cat(io.in[3].release.bits.client_xact_id, UInt<3>("h3")) + LockingRRArbiter_6_1.io.in[3].bits.client_xact_id <= T_12242 + io.in[3].release.ready <= LockingRRArbiter_6_1.io.in[3].ready + LockingRRArbiter_6_1.io.in[4].valid <= io.in[4].release.valid + LockingRRArbiter_6_1.io.in[4].bits <- io.in[4].release.bits + node T_12244 = cat(io.in[4].release.bits.client_xact_id, UInt<3>("h4")) + LockingRRArbiter_6_1.io.in[4].bits.client_xact_id <= T_12244 + io.in[4].release.ready <= LockingRRArbiter_6_1.io.in[4].ready + LockingRRArbiter_6_1.io.in[5].valid <= io.in[5].release.valid + LockingRRArbiter_6_1.io.in[5].bits <- io.in[5].release.bits + node T_12246 = cat(io.in[5].release.bits.client_xact_id, UInt<3>("h5")) + LockingRRArbiter_6_1.io.in[5].bits.client_xact_id <= T_12246 + io.in[5].release.ready <= LockingRRArbiter_6_1.io.in[5].ready + LockingRRArbiter_6_1.io.in[6].valid <= io.in[6].release.valid + LockingRRArbiter_6_1.io.in[6].bits <- io.in[6].release.bits + node T_12248 = cat(io.in[6].release.bits.client_xact_id, UInt<3>("h6")) + LockingRRArbiter_6_1.io.in[6].bits.client_xact_id <= T_12248 + io.in[6].release.ready <= LockingRRArbiter_6_1.io.in[6].ready + LockingRRArbiter_6_1.io.in[7].valid <= io.in[7].release.valid + LockingRRArbiter_6_1.io.in[7].bits <- io.in[7].release.bits + node T_12250 = cat(io.in[7].release.bits.client_xact_id, UInt<3>("h7")) + LockingRRArbiter_6_1.io.in[7].bits.client_xact_id <= T_12250 + io.in[7].release.ready <= LockingRRArbiter_6_1.io.in[7].ready + io.out.release <- LockingRRArbiter_6_1.io.out + io.in[0].probe.valid <= io.out.probe.valid + io.in[1].probe.valid <= io.out.probe.valid + io.in[2].probe.valid <= io.out.probe.valid + io.in[3].probe.valid <= io.out.probe.valid + io.in[4].probe.valid <= io.out.probe.valid + io.in[5].probe.valid <= io.out.probe.valid + io.in[6].probe.valid <= io.out.probe.valid + io.in[7].probe.valid <= io.out.probe.valid + io.in[0].probe.bits <- io.out.probe.bits + io.in[1].probe.bits <- io.out.probe.bits + io.in[2].probe.bits <- io.out.probe.bits + io.in[3].probe.bits <- io.out.probe.bits + io.in[4].probe.bits <- io.out.probe.bits + io.in[5].probe.bits <- io.out.probe.bits + io.in[6].probe.bits <- io.out.probe.bits + io.in[7].probe.bits <- io.out.probe.bits + node T_12251 = and(io.in[0].probe.ready, io.in[1].probe.ready) + node T_12252 = and(T_12251, io.in[2].probe.ready) + node T_12253 = and(T_12252, io.in[3].probe.ready) + node T_12254 = and(T_12253, io.in[4].probe.ready) + node T_12255 = and(T_12254, io.in[5].probe.ready) + node T_12256 = and(T_12255, io.in[6].probe.ready) + node T_12257 = and(T_12256, io.in[7].probe.ready) + io.out.probe.ready <= T_12257 + io.out.grant.ready <= UInt<1>("h0") + io.in[0].grant.valid <= UInt<1>("h0") + node T_12260 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12262 = eq(T_12260, UInt<1>("h0")) + when T_12262 : + io.in[0].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[0].grant.ready + io.in[0].grant.bits <- io.out.grant.bits + node T_12263 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[0].grant.bits.client_xact_id <= T_12263 + io.in[1].grant.valid <= UInt<1>("h0") + node T_12265 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12267 = eq(T_12265, UInt<1>("h1")) + when T_12267 : + io.in[1].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[1].grant.ready + io.in[1].grant.bits <- io.out.grant.bits + node T_12268 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[1].grant.bits.client_xact_id <= T_12268 + io.in[2].grant.valid <= UInt<1>("h0") + node T_12270 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12272 = eq(T_12270, UInt<2>("h2")) + when T_12272 : + io.in[2].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[2].grant.ready + io.in[2].grant.bits <- io.out.grant.bits + node T_12273 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[2].grant.bits.client_xact_id <= T_12273 + io.in[3].grant.valid <= UInt<1>("h0") + node T_12275 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12277 = eq(T_12275, UInt<2>("h3")) + when T_12277 : + io.in[3].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[3].grant.ready + io.in[3].grant.bits <- io.out.grant.bits + node T_12278 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[3].grant.bits.client_xact_id <= T_12278 + io.in[4].grant.valid <= UInt<1>("h0") + node T_12280 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12282 = eq(T_12280, UInt<3>("h4")) + when T_12282 : + io.in[4].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[4].grant.ready + io.in[4].grant.bits <- io.out.grant.bits + node T_12283 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[4].grant.bits.client_xact_id <= T_12283 + io.in[5].grant.valid <= UInt<1>("h0") + node T_12285 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12287 = eq(T_12285, UInt<3>("h5")) + when T_12287 : + io.in[5].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[5].grant.ready + io.in[5].grant.bits <- io.out.grant.bits + node T_12288 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[5].grant.bits.client_xact_id <= T_12288 + io.in[6].grant.valid <= UInt<1>("h0") + node T_12290 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12292 = eq(T_12290, UInt<3>("h6")) + when T_12292 : + io.in[6].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[6].grant.ready + io.in[6].grant.bits <- io.out.grant.bits + node T_12293 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[6].grant.bits.client_xact_id <= T_12293 + io.in[7].grant.valid <= UInt<1>("h0") + node T_12295 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_12297 = eq(T_12295, UInt<3>("h7")) + when T_12297 : + io.in[7].grant.valid <= io.out.grant.valid + io.out.grant.ready <= io.in[7].grant.ready + io.in[7].grant.bits <- io.out.grant.bits + node T_12298 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[7].grant.bits.client_xact_id <= T_12298 + + module LockingRRArbiter_7 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, chosen : UInt<3>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, chosen : UInt<3>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<3>("h07") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1262 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1264 : UInt, clk - node T_1266 = neq(T_1262, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_1268 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1269 = and(T_1268, UInt<1>("h00")) @[Arbiter.scala 42:25] - when T_1269 : @[Arbiter.scala 42:39] - T_1264 <= io.chosen @[Arbiter.scala 43:15] - node T_1271 = eq(T_1262, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1273 = add(T_1262, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1274 = tail(T_1273, 1) @[Counter.scala 21:22] - T_1262 <= T_1274 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1266 : @[Arbiter.scala 47:19] - io.chosen <= T_1264 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1276 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<3>, clk - when T_1276 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_4 = gt(UInt<3>("h04"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_5 = gt(UInt<3>("h05"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_6 = gt(UInt<3>("h06"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_7 = gt(UInt<3>("h07"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node validMask_4 = and(io.in[4].valid, grantMask_4) @[Arbiter.scala 60:75] - node validMask_5 = and(io.in[5].valid, grantMask_5) @[Arbiter.scala 60:75] - node validMask_6 = and(io.in[6].valid, grantMask_6) @[Arbiter.scala 60:75] - node validMask_7 = and(io.in[7].valid, grantMask_7) @[Arbiter.scala 60:75] - node T_1285 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1286 = or(T_1285, validMask_2) @[Arbiter.scala 23:72] - node T_1287 = or(T_1286, validMask_3) @[Arbiter.scala 23:72] - node T_1288 = or(T_1287, validMask_4) @[Arbiter.scala 23:72] - node T_1289 = or(T_1288, validMask_5) @[Arbiter.scala 23:72] - node T_1290 = or(T_1289, validMask_6) @[Arbiter.scala 23:72] - node T_1291 = or(T_1290, validMask_7) @[Arbiter.scala 23:72] - node T_1292 = or(T_1291, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1293 = or(T_1292, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1294 = or(T_1293, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1295 = or(T_1294, io.in[3].valid) @[Arbiter.scala 23:72] - node T_1296 = or(T_1295, io.in[4].valid) @[Arbiter.scala 23:72] - node T_1297 = or(T_1296, io.in[5].valid) @[Arbiter.scala 23:72] - node T_1298 = or(T_1297, io.in[6].valid) @[Arbiter.scala 23:72] - node T_1300 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1302 = eq(T_1285, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1304 = eq(T_1286, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1306 = eq(T_1287, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1308 = eq(T_1288, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1310 = eq(T_1289, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1312 = eq(T_1290, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1314 = eq(T_1291, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1316 = eq(T_1292, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1318 = eq(T_1293, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1320 = eq(T_1294, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1322 = eq(T_1295, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1324 = eq(T_1296, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1326 = eq(T_1297, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1328 = eq(T_1298, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1329 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1330 = or(T_1329, T_1314) @[Arbiter.scala 64:50] - node T_1331 = and(T_1300, grantMask_1) @[Arbiter.scala 64:34] - node T_1332 = or(T_1331, T_1316) @[Arbiter.scala 64:50] - node T_1333 = and(T_1302, grantMask_2) @[Arbiter.scala 64:34] - node T_1334 = or(T_1333, T_1318) @[Arbiter.scala 64:50] - node T_1335 = and(T_1304, grantMask_3) @[Arbiter.scala 64:34] - node T_1336 = or(T_1335, T_1320) @[Arbiter.scala 64:50] - node T_1337 = and(T_1306, grantMask_4) @[Arbiter.scala 64:34] - node T_1338 = or(T_1337, T_1322) @[Arbiter.scala 64:50] - node T_1339 = and(T_1308, grantMask_5) @[Arbiter.scala 64:34] - node T_1340 = or(T_1339, T_1324) @[Arbiter.scala 64:50] - node T_1341 = and(T_1310, grantMask_6) @[Arbiter.scala 64:34] - node T_1342 = or(T_1341, T_1326) @[Arbiter.scala 64:50] - node T_1343 = and(T_1312, grantMask_7) @[Arbiter.scala 64:34] - node T_1344 = or(T_1343, T_1328) @[Arbiter.scala 64:50] - node T_1346 = eq(T_1264, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1347 = mux(T_1266, T_1346, T_1330) @[Arbiter.scala 49:22] - node T_1348 = and(T_1347, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1348 @[Arbiter.scala 49:16] - node T_1350 = eq(T_1264, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1351 = mux(T_1266, T_1350, T_1332) @[Arbiter.scala 49:22] - node T_1352 = and(T_1351, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1352 @[Arbiter.scala 49:16] - node T_1354 = eq(T_1264, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1355 = mux(T_1266, T_1354, T_1334) @[Arbiter.scala 49:22] - node T_1356 = and(T_1355, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1356 @[Arbiter.scala 49:16] - node T_1358 = eq(T_1264, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1359 = mux(T_1266, T_1358, T_1336) @[Arbiter.scala 49:22] - node T_1360 = and(T_1359, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1360 @[Arbiter.scala 49:16] - node T_1362 = eq(T_1264, UInt<3>("h04")) @[Arbiter.scala 49:39] - node T_1363 = mux(T_1266, T_1362, T_1338) @[Arbiter.scala 49:22] - node T_1364 = and(T_1363, io.out.ready) @[Arbiter.scala 49:55] - io.in[4].ready <= T_1364 @[Arbiter.scala 49:16] - node T_1366 = eq(T_1264, UInt<3>("h05")) @[Arbiter.scala 49:39] - node T_1367 = mux(T_1266, T_1366, T_1340) @[Arbiter.scala 49:22] - node T_1368 = and(T_1367, io.out.ready) @[Arbiter.scala 49:55] - io.in[5].ready <= T_1368 @[Arbiter.scala 49:16] - node T_1370 = eq(T_1264, UInt<3>("h06")) @[Arbiter.scala 49:39] - node T_1371 = mux(T_1266, T_1370, T_1342) @[Arbiter.scala 49:22] - node T_1372 = and(T_1371, io.out.ready) @[Arbiter.scala 49:55] - io.in[6].ready <= T_1372 @[Arbiter.scala 49:16] - node T_1374 = eq(T_1264, UInt<3>("h07")) @[Arbiter.scala 49:39] - node T_1375 = mux(T_1266, T_1374, T_1344) @[Arbiter.scala 49:22] - node T_1376 = and(T_1375, io.out.ready) @[Arbiter.scala 49:55] - io.in[7].ready <= T_1376 @[Arbiter.scala 49:16] - when io.in[6].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h06") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[5].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h05") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[4].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h04") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[3].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h03") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_7 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h07") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_6 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h06") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_5 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h05") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_4 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h04") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module LockingRRArbiter_8 : + choice <= UInt<3>("h7") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1262 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1264 : UInt, clk with : + reset => (UInt<1>("h0"), T_1264) + node T_1266 = neq(T_1262, UInt<1>("h0")) + node T_1268 = and(io.out.ready, io.out.valid) + node T_1269 = and(T_1268, UInt<1>("h0")) + when T_1269 : + T_1264 <= io.chosen + node T_1271 = eq(T_1262, UInt<3>("h7")) + node T_1273 = add(T_1262, UInt<1>("h1")) + node T_1274 = tail(T_1273, 1) + T_1262 <= T_1274 + when T_1266 : + io.chosen <= T_1264 + node T_1276 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<3>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1276 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node grantMask_4 = gt(UInt<3>("h4"), lastGrant) + node grantMask_5 = gt(UInt<3>("h5"), lastGrant) + node grantMask_6 = gt(UInt<3>("h6"), lastGrant) + node grantMask_7 = gt(UInt<3>("h7"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node validMask_4 = and(io.in[4].valid, grantMask_4) + node validMask_5 = and(io.in[5].valid, grantMask_5) + node validMask_6 = and(io.in[6].valid, grantMask_6) + node validMask_7 = and(io.in[7].valid, grantMask_7) + node T_1285 = or(validMask_0, validMask_1) + node T_1286 = or(T_1285, validMask_2) + node T_1287 = or(T_1286, validMask_3) + node T_1288 = or(T_1287, validMask_4) + node T_1289 = or(T_1288, validMask_5) + node T_1290 = or(T_1289, validMask_6) + node T_1291 = or(T_1290, validMask_7) + node T_1292 = or(T_1291, io.in[0].valid) + node T_1293 = or(T_1292, io.in[1].valid) + node T_1294 = or(T_1293, io.in[2].valid) + node T_1295 = or(T_1294, io.in[3].valid) + node T_1296 = or(T_1295, io.in[4].valid) + node T_1297 = or(T_1296, io.in[5].valid) + node T_1298 = or(T_1297, io.in[6].valid) + node T_1300 = eq(validMask_0, UInt<1>("h0")) + node T_1302 = eq(T_1285, UInt<1>("h0")) + node T_1304 = eq(T_1286, UInt<1>("h0")) + node T_1306 = eq(T_1287, UInt<1>("h0")) + node T_1308 = eq(T_1288, UInt<1>("h0")) + node T_1310 = eq(T_1289, UInt<1>("h0")) + node T_1312 = eq(T_1290, UInt<1>("h0")) + node T_1314 = eq(T_1291, UInt<1>("h0")) + node T_1316 = eq(T_1292, UInt<1>("h0")) + node T_1318 = eq(T_1293, UInt<1>("h0")) + node T_1320 = eq(T_1294, UInt<1>("h0")) + node T_1322 = eq(T_1295, UInt<1>("h0")) + node T_1324 = eq(T_1296, UInt<1>("h0")) + node T_1326 = eq(T_1297, UInt<1>("h0")) + node T_1328 = eq(T_1298, UInt<1>("h0")) + node T_1329 = and(UInt<1>("h1"), grantMask_0) + node T_1330 = or(T_1329, T_1314) + node T_1331 = and(T_1300, grantMask_1) + node T_1332 = or(T_1331, T_1316) + node T_1333 = and(T_1302, grantMask_2) + node T_1334 = or(T_1333, T_1318) + node T_1335 = and(T_1304, grantMask_3) + node T_1336 = or(T_1335, T_1320) + node T_1337 = and(T_1306, grantMask_4) + node T_1338 = or(T_1337, T_1322) + node T_1339 = and(T_1308, grantMask_5) + node T_1340 = or(T_1339, T_1324) + node T_1341 = and(T_1310, grantMask_6) + node T_1342 = or(T_1341, T_1326) + node T_1343 = and(T_1312, grantMask_7) + node T_1344 = or(T_1343, T_1328) + node T_1346 = eq(T_1264, UInt<1>("h0")) + node T_1347 = mux(T_1266, T_1346, T_1330) + node T_1348 = and(T_1347, io.out.ready) + io.in[0].ready <= T_1348 + node T_1350 = eq(T_1264, UInt<1>("h1")) + node T_1351 = mux(T_1266, T_1350, T_1332) + node T_1352 = and(T_1351, io.out.ready) + io.in[1].ready <= T_1352 + node T_1354 = eq(T_1264, UInt<2>("h2")) + node T_1355 = mux(T_1266, T_1354, T_1334) + node T_1356 = and(T_1355, io.out.ready) + io.in[2].ready <= T_1356 + node T_1358 = eq(T_1264, UInt<2>("h3")) + node T_1359 = mux(T_1266, T_1358, T_1336) + node T_1360 = and(T_1359, io.out.ready) + io.in[3].ready <= T_1360 + node T_1362 = eq(T_1264, UInt<3>("h4")) + node T_1363 = mux(T_1266, T_1362, T_1338) + node T_1364 = and(T_1363, io.out.ready) + io.in[4].ready <= T_1364 + node T_1366 = eq(T_1264, UInt<3>("h5")) + node T_1367 = mux(T_1266, T_1366, T_1340) + node T_1368 = and(T_1367, io.out.ready) + io.in[5].ready <= T_1368 + node T_1370 = eq(T_1264, UInt<3>("h6")) + node T_1371 = mux(T_1266, T_1370, T_1342) + node T_1372 = and(T_1371, io.out.ready) + io.in[6].ready <= T_1372 + node T_1374 = eq(T_1264, UInt<3>("h7")) + node T_1375 = mux(T_1266, T_1374, T_1344) + node T_1376 = and(T_1375, io.out.ready) + io.in[7].ready <= T_1376 + when io.in[6].valid : + choice <= UInt<3>("h6") + when io.in[5].valid : + choice <= UInt<3>("h5") + when io.in[4].valid : + choice <= UInt<3>("h4") + when io.in[3].valid : + choice <= UInt<2>("h3") + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_7 : + choice <= UInt<3>("h7") + when validMask_6 : + choice <= UInt<3>("h6") + when validMask_5 : + choice <= UInt<3>("h5") + when validMask_4 : + choice <= UInt<3>("h4") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module LockingRRArbiter_8 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<3>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<3>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<3>("h07") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_1462 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_1464 : UInt, clk - node T_1466 = neq(T_1462, UInt<1>("h00")) @[Arbiter.scala 39:34] - wire T_1474 : UInt<3>[1] @[Definitions.scala 853:34] - T_1474 is invalid @[Definitions.scala 853:34] - T_1474[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1476 = eq(io.out.bits.g_type, T_1474[0]) @[Package.scala 7:47] - node T_1477 = eq(io.out.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1478 = mux(io.out.bits.is_builtin_type, T_1476, T_1477) @[Definitions.scala 274:33] - node T_1479 = and(UInt<1>("h01"), T_1478) @[Definitions.scala 274:27] - node T_1480 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_1481 = and(T_1480, T_1479) @[Arbiter.scala 42:25] - when T_1481 : @[Arbiter.scala 42:39] - T_1464 <= io.chosen @[Arbiter.scala 43:15] - node T_1483 = eq(T_1462, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1485 = add(T_1462, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1486 = tail(T_1485, 1) @[Counter.scala 21:22] - T_1462 <= T_1486 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_1466 : @[Arbiter.scala 47:19] - io.chosen <= T_1464 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_1488 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<3>, clk - when T_1488 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_4 = gt(UInt<3>("h04"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_5 = gt(UInt<3>("h05"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_6 = gt(UInt<3>("h06"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_7 = gt(UInt<3>("h07"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node validMask_4 = and(io.in[4].valid, grantMask_4) @[Arbiter.scala 60:75] - node validMask_5 = and(io.in[5].valid, grantMask_5) @[Arbiter.scala 60:75] - node validMask_6 = and(io.in[6].valid, grantMask_6) @[Arbiter.scala 60:75] - node validMask_7 = and(io.in[7].valid, grantMask_7) @[Arbiter.scala 60:75] - node T_1497 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_1498 = or(T_1497, validMask_2) @[Arbiter.scala 23:72] - node T_1499 = or(T_1498, validMask_3) @[Arbiter.scala 23:72] - node T_1500 = or(T_1499, validMask_4) @[Arbiter.scala 23:72] - node T_1501 = or(T_1500, validMask_5) @[Arbiter.scala 23:72] - node T_1502 = or(T_1501, validMask_6) @[Arbiter.scala 23:72] - node T_1503 = or(T_1502, validMask_7) @[Arbiter.scala 23:72] - node T_1504 = or(T_1503, io.in[0].valid) @[Arbiter.scala 23:72] - node T_1505 = or(T_1504, io.in[1].valid) @[Arbiter.scala 23:72] - node T_1506 = or(T_1505, io.in[2].valid) @[Arbiter.scala 23:72] - node T_1507 = or(T_1506, io.in[3].valid) @[Arbiter.scala 23:72] - node T_1508 = or(T_1507, io.in[4].valid) @[Arbiter.scala 23:72] - node T_1509 = or(T_1508, io.in[5].valid) @[Arbiter.scala 23:72] - node T_1510 = or(T_1509, io.in[6].valid) @[Arbiter.scala 23:72] - node T_1512 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1514 = eq(T_1497, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1516 = eq(T_1498, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1518 = eq(T_1499, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1520 = eq(T_1500, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1522 = eq(T_1501, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1524 = eq(T_1502, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1526 = eq(T_1503, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1528 = eq(T_1504, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1530 = eq(T_1505, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1532 = eq(T_1506, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1534 = eq(T_1507, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1536 = eq(T_1508, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1538 = eq(T_1509, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1540 = eq(T_1510, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_1541 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_1542 = or(T_1541, T_1526) @[Arbiter.scala 64:50] - node T_1543 = and(T_1512, grantMask_1) @[Arbiter.scala 64:34] - node T_1544 = or(T_1543, T_1528) @[Arbiter.scala 64:50] - node T_1545 = and(T_1514, grantMask_2) @[Arbiter.scala 64:34] - node T_1546 = or(T_1545, T_1530) @[Arbiter.scala 64:50] - node T_1547 = and(T_1516, grantMask_3) @[Arbiter.scala 64:34] - node T_1548 = or(T_1547, T_1532) @[Arbiter.scala 64:50] - node T_1549 = and(T_1518, grantMask_4) @[Arbiter.scala 64:34] - node T_1550 = or(T_1549, T_1534) @[Arbiter.scala 64:50] - node T_1551 = and(T_1520, grantMask_5) @[Arbiter.scala 64:34] - node T_1552 = or(T_1551, T_1536) @[Arbiter.scala 64:50] - node T_1553 = and(T_1522, grantMask_6) @[Arbiter.scala 64:34] - node T_1554 = or(T_1553, T_1538) @[Arbiter.scala 64:50] - node T_1555 = and(T_1524, grantMask_7) @[Arbiter.scala 64:34] - node T_1556 = or(T_1555, T_1540) @[Arbiter.scala 64:50] - node T_1558 = eq(T_1464, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_1559 = mux(T_1466, T_1558, T_1542) @[Arbiter.scala 49:22] - node T_1560 = and(T_1559, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_1560 @[Arbiter.scala 49:16] - node T_1562 = eq(T_1464, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_1563 = mux(T_1466, T_1562, T_1544) @[Arbiter.scala 49:22] - node T_1564 = and(T_1563, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_1564 @[Arbiter.scala 49:16] - node T_1566 = eq(T_1464, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_1567 = mux(T_1466, T_1566, T_1546) @[Arbiter.scala 49:22] - node T_1568 = and(T_1567, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_1568 @[Arbiter.scala 49:16] - node T_1570 = eq(T_1464, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_1571 = mux(T_1466, T_1570, T_1548) @[Arbiter.scala 49:22] - node T_1572 = and(T_1571, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_1572 @[Arbiter.scala 49:16] - node T_1574 = eq(T_1464, UInt<3>("h04")) @[Arbiter.scala 49:39] - node T_1575 = mux(T_1466, T_1574, T_1550) @[Arbiter.scala 49:22] - node T_1576 = and(T_1575, io.out.ready) @[Arbiter.scala 49:55] - io.in[4].ready <= T_1576 @[Arbiter.scala 49:16] - node T_1578 = eq(T_1464, UInt<3>("h05")) @[Arbiter.scala 49:39] - node T_1579 = mux(T_1466, T_1578, T_1552) @[Arbiter.scala 49:22] - node T_1580 = and(T_1579, io.out.ready) @[Arbiter.scala 49:55] - io.in[5].ready <= T_1580 @[Arbiter.scala 49:16] - node T_1582 = eq(T_1464, UInt<3>("h06")) @[Arbiter.scala 49:39] - node T_1583 = mux(T_1466, T_1582, T_1554) @[Arbiter.scala 49:22] - node T_1584 = and(T_1583, io.out.ready) @[Arbiter.scala 49:55] - io.in[6].ready <= T_1584 @[Arbiter.scala 49:16] - node T_1586 = eq(T_1464, UInt<3>("h07")) @[Arbiter.scala 49:39] - node T_1587 = mux(T_1466, T_1586, T_1556) @[Arbiter.scala 49:22] - node T_1588 = and(T_1587, io.out.ready) @[Arbiter.scala 49:55] - io.in[7].ready <= T_1588 @[Arbiter.scala 49:16] - when io.in[6].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h06") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[5].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h05") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[4].valid : @[Arbiter.scala 69:27] - choice <= UInt<3>("h04") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[3].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h03") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_7 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h07") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_6 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h06") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_5 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h05") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_4 : @[Arbiter.scala 71:25] - choice <= UInt<3>("h04") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module L2BroadcastHub : + choice <= UInt<3>("h7") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_1462 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_1464 : UInt, clk with : + reset => (UInt<1>("h0"), T_1464) + node T_1466 = neq(T_1462, UInt<1>("h0")) + wire T_1474 : UInt<3>[1] + T_1474 is invalid + T_1474[0] <= UInt<3>("h5") + node T_1476 = eq(io.out.bits.g_type, T_1474[0]) + node T_1477 = eq(io.out.bits.g_type, UInt<1>("h0")) + node T_1478 = mux(io.out.bits.is_builtin_type, T_1476, T_1477) + node T_1479 = and(UInt<1>("h1"), T_1478) + node T_1480 = and(io.out.ready, io.out.valid) + node T_1481 = and(T_1480, T_1479) + when T_1481 : + T_1464 <= io.chosen + node T_1483 = eq(T_1462, UInt<3>("h7")) + node T_1485 = add(T_1462, UInt<1>("h1")) + node T_1486 = tail(T_1485, 1) + T_1462 <= T_1486 + when T_1466 : + io.chosen <= T_1464 + node T_1488 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<3>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_1488 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node grantMask_4 = gt(UInt<3>("h4"), lastGrant) + node grantMask_5 = gt(UInt<3>("h5"), lastGrant) + node grantMask_6 = gt(UInt<3>("h6"), lastGrant) + node grantMask_7 = gt(UInt<3>("h7"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node validMask_4 = and(io.in[4].valid, grantMask_4) + node validMask_5 = and(io.in[5].valid, grantMask_5) + node validMask_6 = and(io.in[6].valid, grantMask_6) + node validMask_7 = and(io.in[7].valid, grantMask_7) + node T_1497 = or(validMask_0, validMask_1) + node T_1498 = or(T_1497, validMask_2) + node T_1499 = or(T_1498, validMask_3) + node T_1500 = or(T_1499, validMask_4) + node T_1501 = or(T_1500, validMask_5) + node T_1502 = or(T_1501, validMask_6) + node T_1503 = or(T_1502, validMask_7) + node T_1504 = or(T_1503, io.in[0].valid) + node T_1505 = or(T_1504, io.in[1].valid) + node T_1506 = or(T_1505, io.in[2].valid) + node T_1507 = or(T_1506, io.in[3].valid) + node T_1508 = or(T_1507, io.in[4].valid) + node T_1509 = or(T_1508, io.in[5].valid) + node T_1510 = or(T_1509, io.in[6].valid) + node T_1512 = eq(validMask_0, UInt<1>("h0")) + node T_1514 = eq(T_1497, UInt<1>("h0")) + node T_1516 = eq(T_1498, UInt<1>("h0")) + node T_1518 = eq(T_1499, UInt<1>("h0")) + node T_1520 = eq(T_1500, UInt<1>("h0")) + node T_1522 = eq(T_1501, UInt<1>("h0")) + node T_1524 = eq(T_1502, UInt<1>("h0")) + node T_1526 = eq(T_1503, UInt<1>("h0")) + node T_1528 = eq(T_1504, UInt<1>("h0")) + node T_1530 = eq(T_1505, UInt<1>("h0")) + node T_1532 = eq(T_1506, UInt<1>("h0")) + node T_1534 = eq(T_1507, UInt<1>("h0")) + node T_1536 = eq(T_1508, UInt<1>("h0")) + node T_1538 = eq(T_1509, UInt<1>("h0")) + node T_1540 = eq(T_1510, UInt<1>("h0")) + node T_1541 = and(UInt<1>("h1"), grantMask_0) + node T_1542 = or(T_1541, T_1526) + node T_1543 = and(T_1512, grantMask_1) + node T_1544 = or(T_1543, T_1528) + node T_1545 = and(T_1514, grantMask_2) + node T_1546 = or(T_1545, T_1530) + node T_1547 = and(T_1516, grantMask_3) + node T_1548 = or(T_1547, T_1532) + node T_1549 = and(T_1518, grantMask_4) + node T_1550 = or(T_1549, T_1534) + node T_1551 = and(T_1520, grantMask_5) + node T_1552 = or(T_1551, T_1536) + node T_1553 = and(T_1522, grantMask_6) + node T_1554 = or(T_1553, T_1538) + node T_1555 = and(T_1524, grantMask_7) + node T_1556 = or(T_1555, T_1540) + node T_1558 = eq(T_1464, UInt<1>("h0")) + node T_1559 = mux(T_1466, T_1558, T_1542) + node T_1560 = and(T_1559, io.out.ready) + io.in[0].ready <= T_1560 + node T_1562 = eq(T_1464, UInt<1>("h1")) + node T_1563 = mux(T_1466, T_1562, T_1544) + node T_1564 = and(T_1563, io.out.ready) + io.in[1].ready <= T_1564 + node T_1566 = eq(T_1464, UInt<2>("h2")) + node T_1567 = mux(T_1466, T_1566, T_1546) + node T_1568 = and(T_1567, io.out.ready) + io.in[2].ready <= T_1568 + node T_1570 = eq(T_1464, UInt<2>("h3")) + node T_1571 = mux(T_1466, T_1570, T_1548) + node T_1572 = and(T_1571, io.out.ready) + io.in[3].ready <= T_1572 + node T_1574 = eq(T_1464, UInt<3>("h4")) + node T_1575 = mux(T_1466, T_1574, T_1550) + node T_1576 = and(T_1575, io.out.ready) + io.in[4].ready <= T_1576 + node T_1578 = eq(T_1464, UInt<3>("h5")) + node T_1579 = mux(T_1466, T_1578, T_1552) + node T_1580 = and(T_1579, io.out.ready) + io.in[5].ready <= T_1580 + node T_1582 = eq(T_1464, UInt<3>("h6")) + node T_1583 = mux(T_1466, T_1582, T_1554) + node T_1584 = and(T_1583, io.out.ready) + io.in[6].ready <= T_1584 + node T_1586 = eq(T_1464, UInt<3>("h7")) + node T_1587 = mux(T_1466, T_1586, T_1556) + node T_1588 = and(T_1587, io.out.ready) + io.in[7].ready <= T_1588 + when io.in[6].valid : + choice <= UInt<3>("h6") + when io.in[5].valid : + choice <= UInt<3>("h5") + when io.in[4].valid : + choice <= UInt<3>("h4") + when io.in[3].valid : + choice <= UInt<2>("h3") + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_7 : + choice <= UInt<3>("h7") + when validMask_6 : + choice <= UInt<3>("h6") + when validMask_5 : + choice <= UInt<3>("h5") + when validMask_4 : + choice <= UInt<3>("h4") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module L2BroadcastHub : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} + io is invalid - inst trackerList_0 of BufferedBroadcastVoluntaryReleaseTracker @[Broadcast.scala 17:13] + inst trackerList_0 of BufferedBroadcastVoluntaryReleaseTracker trackerList_0.io is invalid trackerList_0.clk <= clk trackerList_0.reset <= reset - inst trackerList_1 of BufferedBroadcastAcquireTracker @[Broadcast.scala 20:13] + inst trackerList_1 of BufferedBroadcastAcquireTracker trackerList_1.io is invalid trackerList_1.clk <= clk trackerList_1.reset <= reset - inst trackerList_2 of BufferedBroadcastAcquireTracker_1 @[Broadcast.scala 20:13] + inst trackerList_2 of BufferedBroadcastAcquireTracker_1 trackerList_2.io is invalid trackerList_2.clk <= clk trackerList_2.reset <= reset - inst trackerList_3 of BufferedBroadcastAcquireTracker_2 @[Broadcast.scala 20:13] + inst trackerList_3 of BufferedBroadcastAcquireTracker_2 trackerList_3.io is invalid trackerList_3.clk <= clk trackerList_3.reset <= reset - inst trackerList_4 of BufferedBroadcastAcquireTracker_3 @[Broadcast.scala 20:13] + inst trackerList_4 of BufferedBroadcastAcquireTracker_3 trackerList_4.io is invalid trackerList_4.clk <= clk trackerList_4.reset <= reset - inst trackerList_5 of BufferedBroadcastAcquireTracker_4 @[Broadcast.scala 20:13] + inst trackerList_5 of BufferedBroadcastAcquireTracker_4 trackerList_5.io is invalid trackerList_5.clk <= clk trackerList_5.reset <= reset - inst trackerList_6 of BufferedBroadcastAcquireTracker_5 @[Broadcast.scala 20:13] + inst trackerList_6 of BufferedBroadcastAcquireTracker_5 trackerList_6.io is invalid trackerList_6.clk <= clk trackerList_6.reset <= reset - inst trackerList_7 of BufferedBroadcastAcquireTracker_6 @[Broadcast.scala 20:13] + inst trackerList_7 of BufferedBroadcastAcquireTracker_6 trackerList_7.io is invalid trackerList_7.clk <= clk trackerList_7.reset <= reset - trackerList_0.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_1.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_2.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_3.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_4.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_5.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_6.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - trackerList_7.io.incoherent <= io.incoherent @[Broadcast.scala 24:48] - inst outer_arb of ClientTileLinkIOArbiter @[Broadcast.scala 28:25] + trackerList_0.io.incoherent <= io.incoherent + trackerList_1.io.incoherent <= io.incoherent + trackerList_2.io.incoherent <= io.incoherent + trackerList_3.io.incoherent <= io.incoherent + trackerList_4.io.incoherent <= io.incoherent + trackerList_5.io.incoherent <= io.incoherent + trackerList_6.io.incoherent <= io.incoherent + trackerList_7.io.incoherent <= io.incoherent + inst outer_arb of ClientTileLinkIOArbiter outer_arb.io is invalid outer_arb.clk <= clk outer_arb.reset <= reset - outer_arb.io.in[0] <- trackerList_0.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[1] <- trackerList_1.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[2] <- trackerList_2.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[3] <- trackerList_3.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[4] <- trackerList_4.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[5] <- trackerList_5.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[6] <- trackerList_6.io.outer @[Broadcast.scala 30:19] - outer_arb.io.in[7] <- trackerList_7.io.outer @[Broadcast.scala 30:19] - io.outer <- outer_arb.io.out @[Broadcast.scala 31:12] - node T_1215 = and(io.inner.acquire.valid, io.inner.release.valid) @[Broadcast.scala 35:28] - node T_1216 = eq(io.inner.release.bits.addr_block, io.inner.acquire.bits.addr_block) @[Definitions.scala 116:63] - node irel_vs_iacq_conflict = and(T_1215, T_1216) @[Broadcast.scala 36:28] - node T_1218 = eq(irel_vs_iacq_conflict, UInt<1>("h00")) @[Broadcast.scala 43:26] - node T_1219 = cat(trackerList_1.io.inner.acquire.ready, trackerList_0.io.inner.acquire.ready) @[Cat.scala 20:58] - node T_1220 = cat(trackerList_3.io.inner.acquire.ready, trackerList_2.io.inner.acquire.ready) @[Cat.scala 20:58] - node T_1221 = cat(T_1220, T_1219) @[Cat.scala 20:58] - node T_1222 = cat(trackerList_5.io.inner.acquire.ready, trackerList_4.io.inner.acquire.ready) @[Cat.scala 20:58] - node T_1223 = cat(trackerList_7.io.inner.acquire.ready, trackerList_6.io.inner.acquire.ready) @[Cat.scala 20:58] - node T_1224 = cat(T_1223, T_1222) @[Cat.scala 20:58] - node T_1225 = cat(T_1224, T_1221) @[Cat.scala 20:58] - node T_1226 = cat(trackerList_1.io.alloc.iacq.can, trackerList_0.io.alloc.iacq.can) @[Cat.scala 20:58] - node T_1227 = cat(trackerList_3.io.alloc.iacq.can, trackerList_2.io.alloc.iacq.can) @[Cat.scala 20:58] - node T_1228 = cat(T_1227, T_1226) @[Cat.scala 20:58] - node T_1229 = cat(trackerList_5.io.alloc.iacq.can, trackerList_4.io.alloc.iacq.can) @[Cat.scala 20:58] - node T_1230 = cat(trackerList_7.io.alloc.iacq.can, trackerList_6.io.alloc.iacq.can) @[Cat.scala 20:58] - node T_1231 = cat(T_1230, T_1229) @[Cat.scala 20:58] - node T_1232 = cat(T_1231, T_1228) @[Cat.scala 20:58] - node T_1233 = bits(T_1232, 0, 0) @[OneHot.scala 63:71] - node T_1234 = bits(T_1232, 1, 1) @[OneHot.scala 63:71] - node T_1235 = bits(T_1232, 2, 2) @[OneHot.scala 63:71] - node T_1236 = bits(T_1232, 3, 3) @[OneHot.scala 63:71] - node T_1237 = bits(T_1232, 4, 4) @[OneHot.scala 63:71] - node T_1238 = bits(T_1232, 5, 5) @[OneHot.scala 63:71] - node T_1239 = bits(T_1232, 6, 6) @[OneHot.scala 63:71] - node T_1240 = bits(T_1232, 7, 7) @[OneHot.scala 63:71] - node T_1251 = mux(T_1240, UInt<8>("h080"), UInt<8>("h00")) @[Mux.scala 31:69] - node T_1252 = mux(T_1239, UInt<8>("h040"), T_1251) @[Mux.scala 31:69] - node T_1253 = mux(T_1238, UInt<8>("h020"), T_1252) @[Mux.scala 31:69] - node T_1254 = mux(T_1237, UInt<8>("h010"), T_1253) @[Mux.scala 31:69] - node T_1255 = mux(T_1236, UInt<8>("h08"), T_1254) @[Mux.scala 31:69] - node T_1256 = mux(T_1235, UInt<8>("h04"), T_1255) @[Mux.scala 31:69] - node T_1257 = mux(T_1234, UInt<8>("h02"), T_1256) @[Mux.scala 31:69] - node T_1258 = mux(T_1233, UInt<8>("h01"), T_1257) @[Mux.scala 31:69] - node T_1259 = cat(trackerList_1.io.alloc.iacq.matches, trackerList_0.io.alloc.iacq.matches) @[Cat.scala 20:58] - node T_1260 = cat(trackerList_3.io.alloc.iacq.matches, trackerList_2.io.alloc.iacq.matches) @[Cat.scala 20:58] - node T_1261 = cat(T_1260, T_1259) @[Cat.scala 20:58] - node T_1262 = cat(trackerList_5.io.alloc.iacq.matches, trackerList_4.io.alloc.iacq.matches) @[Cat.scala 20:58] - node T_1263 = cat(trackerList_7.io.alloc.iacq.matches, trackerList_6.io.alloc.iacq.matches) @[Cat.scala 20:58] - node T_1264 = cat(T_1263, T_1262) @[Cat.scala 20:58] - node T_1265 = cat(T_1264, T_1261) @[Cat.scala 20:58] - node T_1267 = neq(T_1265, UInt<1>("h00")) @[Agents.scala 90:34] - node T_1269 = eq(T_1267, UInt<1>("h00")) @[Agents.scala 90:22] - node T_1271 = mux(T_1269, T_1232, T_1265) @[Agents.scala 93:21] - node T_1272 = and(T_1271, T_1225) @[Agents.scala 93:62] - node T_1274 = neq(T_1272, UInt<1>("h00")) @[Agents.scala 93:76] - node T_1275 = and(T_1274, T_1218) @[Agents.scala 93:80] - node T_1276 = and(T_1275, UInt<1>("h01")) @[Agents.scala 93:92] - io.inner.acquire.ready <= T_1276 @[Agents.scala 93:14] - node T_1277 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1278 = and(T_1277, T_1218) @[Agents.scala 95:41] - trackerList_0.io.inner.acquire.valid <= T_1278 @[Agents.scala 95:17] - trackerList_0.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1279 = bits(T_1258, 0, 0) @[Agents.scala 98:40] - node T_1280 = and(T_1279, T_1269) @[Agents.scala 98:44] - node T_1281 = and(T_1280, T_1218) @[Agents.scala 98:58] - trackerList_0.io.alloc.iacq.should <= T_1281 @[Agents.scala 98:20] - node T_1282 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1283 = and(T_1282, T_1218) @[Agents.scala 95:41] - trackerList_1.io.inner.acquire.valid <= T_1283 @[Agents.scala 95:17] - trackerList_1.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1284 = bits(T_1258, 1, 1) @[Agents.scala 98:40] - node T_1285 = and(T_1284, T_1269) @[Agents.scala 98:44] - node T_1286 = and(T_1285, T_1218) @[Agents.scala 98:58] - trackerList_1.io.alloc.iacq.should <= T_1286 @[Agents.scala 98:20] - node T_1287 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1288 = and(T_1287, T_1218) @[Agents.scala 95:41] - trackerList_2.io.inner.acquire.valid <= T_1288 @[Agents.scala 95:17] - trackerList_2.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1289 = bits(T_1258, 2, 2) @[Agents.scala 98:40] - node T_1290 = and(T_1289, T_1269) @[Agents.scala 98:44] - node T_1291 = and(T_1290, T_1218) @[Agents.scala 98:58] - trackerList_2.io.alloc.iacq.should <= T_1291 @[Agents.scala 98:20] - node T_1292 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1293 = and(T_1292, T_1218) @[Agents.scala 95:41] - trackerList_3.io.inner.acquire.valid <= T_1293 @[Agents.scala 95:17] - trackerList_3.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1294 = bits(T_1258, 3, 3) @[Agents.scala 98:40] - node T_1295 = and(T_1294, T_1269) @[Agents.scala 98:44] - node T_1296 = and(T_1295, T_1218) @[Agents.scala 98:58] - trackerList_3.io.alloc.iacq.should <= T_1296 @[Agents.scala 98:20] - node T_1297 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1298 = and(T_1297, T_1218) @[Agents.scala 95:41] - trackerList_4.io.inner.acquire.valid <= T_1298 @[Agents.scala 95:17] - trackerList_4.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1299 = bits(T_1258, 4, 4) @[Agents.scala 98:40] - node T_1300 = and(T_1299, T_1269) @[Agents.scala 98:44] - node T_1301 = and(T_1300, T_1218) @[Agents.scala 98:58] - trackerList_4.io.alloc.iacq.should <= T_1301 @[Agents.scala 98:20] - node T_1302 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1303 = and(T_1302, T_1218) @[Agents.scala 95:41] - trackerList_5.io.inner.acquire.valid <= T_1303 @[Agents.scala 95:17] - trackerList_5.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1304 = bits(T_1258, 5, 5) @[Agents.scala 98:40] - node T_1305 = and(T_1304, T_1269) @[Agents.scala 98:44] - node T_1306 = and(T_1305, T_1218) @[Agents.scala 98:58] - trackerList_5.io.alloc.iacq.should <= T_1306 @[Agents.scala 98:20] - node T_1307 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1308 = and(T_1307, T_1218) @[Agents.scala 95:41] - trackerList_6.io.inner.acquire.valid <= T_1308 @[Agents.scala 95:17] - trackerList_6.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1309 = bits(T_1258, 6, 6) @[Agents.scala 98:40] - node T_1310 = and(T_1309, T_1269) @[Agents.scala 98:44] - node T_1311 = and(T_1310, T_1218) @[Agents.scala 98:58] - trackerList_6.io.alloc.iacq.should <= T_1311 @[Agents.scala 98:20] - node T_1312 = and(io.inner.acquire.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1313 = and(T_1312, T_1218) @[Agents.scala 95:41] - trackerList_7.io.inner.acquire.valid <= T_1313 @[Agents.scala 95:17] - trackerList_7.io.inner.acquire.bits <- io.inner.acquire.bits @[Agents.scala 96:16] - node T_1314 = bits(T_1258, 7, 7) @[Agents.scala 98:40] - node T_1315 = and(T_1314, T_1269) @[Agents.scala 98:44] - node T_1316 = and(T_1315, T_1218) @[Agents.scala 98:58] - trackerList_7.io.alloc.iacq.should <= T_1316 @[Agents.scala 98:20] - node T_1317 = cat(trackerList_1.io.inner.release.ready, trackerList_0.io.inner.release.ready) @[Cat.scala 20:58] - node T_1318 = cat(trackerList_3.io.inner.release.ready, trackerList_2.io.inner.release.ready) @[Cat.scala 20:58] - node T_1319 = cat(T_1318, T_1317) @[Cat.scala 20:58] - node T_1320 = cat(trackerList_5.io.inner.release.ready, trackerList_4.io.inner.release.ready) @[Cat.scala 20:58] - node T_1321 = cat(trackerList_7.io.inner.release.ready, trackerList_6.io.inner.release.ready) @[Cat.scala 20:58] - node T_1322 = cat(T_1321, T_1320) @[Cat.scala 20:58] - node T_1323 = cat(T_1322, T_1319) @[Cat.scala 20:58] - node T_1324 = cat(trackerList_1.io.alloc.irel.can, trackerList_0.io.alloc.irel.can) @[Cat.scala 20:58] - node T_1325 = cat(trackerList_3.io.alloc.irel.can, trackerList_2.io.alloc.irel.can) @[Cat.scala 20:58] - node T_1326 = cat(T_1325, T_1324) @[Cat.scala 20:58] - node T_1327 = cat(trackerList_5.io.alloc.irel.can, trackerList_4.io.alloc.irel.can) @[Cat.scala 20:58] - node T_1328 = cat(trackerList_7.io.alloc.irel.can, trackerList_6.io.alloc.irel.can) @[Cat.scala 20:58] - node T_1329 = cat(T_1328, T_1327) @[Cat.scala 20:58] - node T_1330 = cat(T_1329, T_1326) @[Cat.scala 20:58] - node T_1331 = bits(T_1330, 0, 0) @[OneHot.scala 63:71] - node T_1332 = bits(T_1330, 1, 1) @[OneHot.scala 63:71] - node T_1333 = bits(T_1330, 2, 2) @[OneHot.scala 63:71] - node T_1334 = bits(T_1330, 3, 3) @[OneHot.scala 63:71] - node T_1335 = bits(T_1330, 4, 4) @[OneHot.scala 63:71] - node T_1336 = bits(T_1330, 5, 5) @[OneHot.scala 63:71] - node T_1337 = bits(T_1330, 6, 6) @[OneHot.scala 63:71] - node T_1338 = bits(T_1330, 7, 7) @[OneHot.scala 63:71] - node T_1349 = mux(T_1338, UInt<8>("h080"), UInt<8>("h00")) @[Mux.scala 31:69] - node T_1350 = mux(T_1337, UInt<8>("h040"), T_1349) @[Mux.scala 31:69] - node T_1351 = mux(T_1336, UInt<8>("h020"), T_1350) @[Mux.scala 31:69] - node T_1352 = mux(T_1335, UInt<8>("h010"), T_1351) @[Mux.scala 31:69] - node T_1353 = mux(T_1334, UInt<8>("h08"), T_1352) @[Mux.scala 31:69] - node T_1354 = mux(T_1333, UInt<8>("h04"), T_1353) @[Mux.scala 31:69] - node T_1355 = mux(T_1332, UInt<8>("h02"), T_1354) @[Mux.scala 31:69] - node T_1356 = mux(T_1331, UInt<8>("h01"), T_1355) @[Mux.scala 31:69] - node T_1357 = cat(trackerList_1.io.alloc.irel.matches, trackerList_0.io.alloc.irel.matches) @[Cat.scala 20:58] - node T_1358 = cat(trackerList_3.io.alloc.irel.matches, trackerList_2.io.alloc.irel.matches) @[Cat.scala 20:58] - node T_1359 = cat(T_1358, T_1357) @[Cat.scala 20:58] - node T_1360 = cat(trackerList_5.io.alloc.irel.matches, trackerList_4.io.alloc.irel.matches) @[Cat.scala 20:58] - node T_1361 = cat(trackerList_7.io.alloc.irel.matches, trackerList_6.io.alloc.irel.matches) @[Cat.scala 20:58] - node T_1362 = cat(T_1361, T_1360) @[Cat.scala 20:58] - node T_1363 = cat(T_1362, T_1359) @[Cat.scala 20:58] - node T_1365 = neq(T_1363, UInt<1>("h00")) @[Agents.scala 90:34] - node T_1367 = eq(T_1365, UInt<1>("h00")) @[Agents.scala 90:22] - node T_1370 = mux(T_1367, T_1330, T_1363) @[Agents.scala 93:21] - node T_1371 = and(T_1370, T_1323) @[Agents.scala 93:62] - node T_1373 = neq(T_1371, UInt<1>("h00")) @[Agents.scala 93:76] - node T_1374 = and(T_1373, UInt<1>("h01")) @[Agents.scala 93:80] - node T_1375 = and(T_1374, UInt<1>("h01")) @[Agents.scala 93:92] - io.inner.release.ready <= T_1375 @[Agents.scala 93:14] - node T_1376 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1377 = and(T_1376, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_0.io.inner.release.valid <= T_1377 @[Agents.scala 95:17] - trackerList_0.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1378 = bits(T_1356, 0, 0) @[Agents.scala 98:40] - node T_1379 = and(T_1378, T_1367) @[Agents.scala 98:44] - node T_1380 = and(T_1379, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_0.io.alloc.irel.should <= T_1380 @[Agents.scala 98:20] - node T_1381 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1382 = and(T_1381, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_1.io.inner.release.valid <= T_1382 @[Agents.scala 95:17] - trackerList_1.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1383 = bits(T_1356, 1, 1) @[Agents.scala 98:40] - node T_1384 = and(T_1383, T_1367) @[Agents.scala 98:44] - node T_1385 = and(T_1384, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_1.io.alloc.irel.should <= T_1385 @[Agents.scala 98:20] - node T_1386 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1387 = and(T_1386, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_2.io.inner.release.valid <= T_1387 @[Agents.scala 95:17] - trackerList_2.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1388 = bits(T_1356, 2, 2) @[Agents.scala 98:40] - node T_1389 = and(T_1388, T_1367) @[Agents.scala 98:44] - node T_1390 = and(T_1389, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_2.io.alloc.irel.should <= T_1390 @[Agents.scala 98:20] - node T_1391 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1392 = and(T_1391, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_3.io.inner.release.valid <= T_1392 @[Agents.scala 95:17] - trackerList_3.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1393 = bits(T_1356, 3, 3) @[Agents.scala 98:40] - node T_1394 = and(T_1393, T_1367) @[Agents.scala 98:44] - node T_1395 = and(T_1394, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_3.io.alloc.irel.should <= T_1395 @[Agents.scala 98:20] - node T_1396 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1397 = and(T_1396, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_4.io.inner.release.valid <= T_1397 @[Agents.scala 95:17] - trackerList_4.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1398 = bits(T_1356, 4, 4) @[Agents.scala 98:40] - node T_1399 = and(T_1398, T_1367) @[Agents.scala 98:44] - node T_1400 = and(T_1399, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_4.io.alloc.irel.should <= T_1400 @[Agents.scala 98:20] - node T_1401 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1402 = and(T_1401, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_5.io.inner.release.valid <= T_1402 @[Agents.scala 95:17] - trackerList_5.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1403 = bits(T_1356, 5, 5) @[Agents.scala 98:40] - node T_1404 = and(T_1403, T_1367) @[Agents.scala 98:44] - node T_1405 = and(T_1404, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_5.io.alloc.irel.should <= T_1405 @[Agents.scala 98:20] - node T_1406 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1407 = and(T_1406, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_6.io.inner.release.valid <= T_1407 @[Agents.scala 95:17] - trackerList_6.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1408 = bits(T_1356, 6, 6) @[Agents.scala 98:40] - node T_1409 = and(T_1408, T_1367) @[Agents.scala 98:44] - node T_1410 = and(T_1409, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_6.io.alloc.irel.should <= T_1410 @[Agents.scala 98:20] - node T_1411 = and(io.inner.release.valid, UInt<1>("h01")) @[Agents.scala 95:29] - node T_1412 = and(T_1411, UInt<1>("h01")) @[Agents.scala 95:41] - trackerList_7.io.inner.release.valid <= T_1412 @[Agents.scala 95:17] - trackerList_7.io.inner.release.bits <- io.inner.release.bits @[Agents.scala 96:16] - node T_1413 = bits(T_1356, 7, 7) @[Agents.scala 98:40] - node T_1414 = and(T_1413, T_1367) @[Agents.scala 98:44] - node T_1415 = and(T_1414, UInt<1>("h01")) @[Agents.scala 98:58] - trackerList_7.io.alloc.irel.should <= T_1415 @[Agents.scala 98:20] - inst LockingRRArbiter_7_1 of LockingRRArbiter_7 @[Agents.scala 52:21] + outer_arb.io.in[0] <- trackerList_0.io.outer + outer_arb.io.in[1] <- trackerList_1.io.outer + outer_arb.io.in[2] <- trackerList_2.io.outer + outer_arb.io.in[3] <- trackerList_3.io.outer + outer_arb.io.in[4] <- trackerList_4.io.outer + outer_arb.io.in[5] <- trackerList_5.io.outer + outer_arb.io.in[6] <- trackerList_6.io.outer + outer_arb.io.in[7] <- trackerList_7.io.outer + io.outer <- outer_arb.io.out + node T_1215 = and(io.inner.acquire.valid, io.inner.release.valid) + node T_1216 = eq(io.inner.release.bits.addr_block, io.inner.acquire.bits.addr_block) + node irel_vs_iacq_conflict = and(T_1215, T_1216) + node T_1218 = eq(irel_vs_iacq_conflict, UInt<1>("h0")) + node T_1219 = cat(trackerList_1.io.inner.acquire.ready, trackerList_0.io.inner.acquire.ready) + node T_1220 = cat(trackerList_3.io.inner.acquire.ready, trackerList_2.io.inner.acquire.ready) + node T_1221 = cat(T_1220, T_1219) + node T_1222 = cat(trackerList_5.io.inner.acquire.ready, trackerList_4.io.inner.acquire.ready) + node T_1223 = cat(trackerList_7.io.inner.acquire.ready, trackerList_6.io.inner.acquire.ready) + node T_1224 = cat(T_1223, T_1222) + node T_1225 = cat(T_1224, T_1221) + node T_1226 = cat(trackerList_1.io.alloc.iacq.can, trackerList_0.io.alloc.iacq.can) + node T_1227 = cat(trackerList_3.io.alloc.iacq.can, trackerList_2.io.alloc.iacq.can) + node T_1228 = cat(T_1227, T_1226) + node T_1229 = cat(trackerList_5.io.alloc.iacq.can, trackerList_4.io.alloc.iacq.can) + node T_1230 = cat(trackerList_7.io.alloc.iacq.can, trackerList_6.io.alloc.iacq.can) + node T_1231 = cat(T_1230, T_1229) + node T_1232 = cat(T_1231, T_1228) + node T_1233 = bits(T_1232, 0, 0) + node T_1234 = bits(T_1232, 1, 1) + node T_1235 = bits(T_1232, 2, 2) + node T_1236 = bits(T_1232, 3, 3) + node T_1237 = bits(T_1232, 4, 4) + node T_1238 = bits(T_1232, 5, 5) + node T_1239 = bits(T_1232, 6, 6) + node T_1240 = bits(T_1232, 7, 7) + node T_1251 = mux(T_1240, UInt<8>("h80"), UInt<8>("h0")) + node T_1252 = mux(T_1239, UInt<8>("h40"), T_1251) + node T_1253 = mux(T_1238, UInt<8>("h20"), T_1252) + node T_1254 = mux(T_1237, UInt<8>("h10"), T_1253) + node T_1255 = mux(T_1236, UInt<8>("h8"), T_1254) + node T_1256 = mux(T_1235, UInt<8>("h4"), T_1255) + node T_1257 = mux(T_1234, UInt<8>("h2"), T_1256) + node T_1258 = mux(T_1233, UInt<8>("h1"), T_1257) + node T_1259 = cat(trackerList_1.io.alloc.iacq.matches, trackerList_0.io.alloc.iacq.matches) + node T_1260 = cat(trackerList_3.io.alloc.iacq.matches, trackerList_2.io.alloc.iacq.matches) + node T_1261 = cat(T_1260, T_1259) + node T_1262 = cat(trackerList_5.io.alloc.iacq.matches, trackerList_4.io.alloc.iacq.matches) + node T_1263 = cat(trackerList_7.io.alloc.iacq.matches, trackerList_6.io.alloc.iacq.matches) + node T_1264 = cat(T_1263, T_1262) + node T_1265 = cat(T_1264, T_1261) + node T_1267 = neq(T_1265, UInt<1>("h0")) + node T_1269 = eq(T_1267, UInt<1>("h0")) + node T_1271 = mux(T_1269, T_1232, T_1265) + node T_1272 = and(T_1271, T_1225) + node T_1274 = neq(T_1272, UInt<1>("h0")) + node T_1275 = and(T_1274, T_1218) + node T_1276 = and(T_1275, UInt<1>("h1")) + io.inner.acquire.ready <= T_1276 + node T_1277 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1278 = and(T_1277, T_1218) + trackerList_0.io.inner.acquire.valid <= T_1278 + trackerList_0.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1279 = bits(T_1258, 0, 0) + node T_1280 = and(T_1279, T_1269) + node T_1281 = and(T_1280, T_1218) + trackerList_0.io.alloc.iacq.should <= T_1281 + node T_1282 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1283 = and(T_1282, T_1218) + trackerList_1.io.inner.acquire.valid <= T_1283 + trackerList_1.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1284 = bits(T_1258, 1, 1) + node T_1285 = and(T_1284, T_1269) + node T_1286 = and(T_1285, T_1218) + trackerList_1.io.alloc.iacq.should <= T_1286 + node T_1287 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1288 = and(T_1287, T_1218) + trackerList_2.io.inner.acquire.valid <= T_1288 + trackerList_2.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1289 = bits(T_1258, 2, 2) + node T_1290 = and(T_1289, T_1269) + node T_1291 = and(T_1290, T_1218) + trackerList_2.io.alloc.iacq.should <= T_1291 + node T_1292 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1293 = and(T_1292, T_1218) + trackerList_3.io.inner.acquire.valid <= T_1293 + trackerList_3.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1294 = bits(T_1258, 3, 3) + node T_1295 = and(T_1294, T_1269) + node T_1296 = and(T_1295, T_1218) + trackerList_3.io.alloc.iacq.should <= T_1296 + node T_1297 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1298 = and(T_1297, T_1218) + trackerList_4.io.inner.acquire.valid <= T_1298 + trackerList_4.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1299 = bits(T_1258, 4, 4) + node T_1300 = and(T_1299, T_1269) + node T_1301 = and(T_1300, T_1218) + trackerList_4.io.alloc.iacq.should <= T_1301 + node T_1302 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1303 = and(T_1302, T_1218) + trackerList_5.io.inner.acquire.valid <= T_1303 + trackerList_5.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1304 = bits(T_1258, 5, 5) + node T_1305 = and(T_1304, T_1269) + node T_1306 = and(T_1305, T_1218) + trackerList_5.io.alloc.iacq.should <= T_1306 + node T_1307 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1308 = and(T_1307, T_1218) + trackerList_6.io.inner.acquire.valid <= T_1308 + trackerList_6.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1309 = bits(T_1258, 6, 6) + node T_1310 = and(T_1309, T_1269) + node T_1311 = and(T_1310, T_1218) + trackerList_6.io.alloc.iacq.should <= T_1311 + node T_1312 = and(io.inner.acquire.valid, UInt<1>("h1")) + node T_1313 = and(T_1312, T_1218) + trackerList_7.io.inner.acquire.valid <= T_1313 + trackerList_7.io.inner.acquire.bits <- io.inner.acquire.bits + node T_1314 = bits(T_1258, 7, 7) + node T_1315 = and(T_1314, T_1269) + node T_1316 = and(T_1315, T_1218) + trackerList_7.io.alloc.iacq.should <= T_1316 + node T_1317 = cat(trackerList_1.io.inner.release.ready, trackerList_0.io.inner.release.ready) + node T_1318 = cat(trackerList_3.io.inner.release.ready, trackerList_2.io.inner.release.ready) + node T_1319 = cat(T_1318, T_1317) + node T_1320 = cat(trackerList_5.io.inner.release.ready, trackerList_4.io.inner.release.ready) + node T_1321 = cat(trackerList_7.io.inner.release.ready, trackerList_6.io.inner.release.ready) + node T_1322 = cat(T_1321, T_1320) + node T_1323 = cat(T_1322, T_1319) + node T_1324 = cat(trackerList_1.io.alloc.irel.can, trackerList_0.io.alloc.irel.can) + node T_1325 = cat(trackerList_3.io.alloc.irel.can, trackerList_2.io.alloc.irel.can) + node T_1326 = cat(T_1325, T_1324) + node T_1327 = cat(trackerList_5.io.alloc.irel.can, trackerList_4.io.alloc.irel.can) + node T_1328 = cat(trackerList_7.io.alloc.irel.can, trackerList_6.io.alloc.irel.can) + node T_1329 = cat(T_1328, T_1327) + node T_1330 = cat(T_1329, T_1326) + node T_1331 = bits(T_1330, 0, 0) + node T_1332 = bits(T_1330, 1, 1) + node T_1333 = bits(T_1330, 2, 2) + node T_1334 = bits(T_1330, 3, 3) + node T_1335 = bits(T_1330, 4, 4) + node T_1336 = bits(T_1330, 5, 5) + node T_1337 = bits(T_1330, 6, 6) + node T_1338 = bits(T_1330, 7, 7) + node T_1349 = mux(T_1338, UInt<8>("h80"), UInt<8>("h0")) + node T_1350 = mux(T_1337, UInt<8>("h40"), T_1349) + node T_1351 = mux(T_1336, UInt<8>("h20"), T_1350) + node T_1352 = mux(T_1335, UInt<8>("h10"), T_1351) + node T_1353 = mux(T_1334, UInt<8>("h8"), T_1352) + node T_1354 = mux(T_1333, UInt<8>("h4"), T_1353) + node T_1355 = mux(T_1332, UInt<8>("h2"), T_1354) + node T_1356 = mux(T_1331, UInt<8>("h1"), T_1355) + node T_1357 = cat(trackerList_1.io.alloc.irel.matches, trackerList_0.io.alloc.irel.matches) + node T_1358 = cat(trackerList_3.io.alloc.irel.matches, trackerList_2.io.alloc.irel.matches) + node T_1359 = cat(T_1358, T_1357) + node T_1360 = cat(trackerList_5.io.alloc.irel.matches, trackerList_4.io.alloc.irel.matches) + node T_1361 = cat(trackerList_7.io.alloc.irel.matches, trackerList_6.io.alloc.irel.matches) + node T_1362 = cat(T_1361, T_1360) + node T_1363 = cat(T_1362, T_1359) + node T_1365 = neq(T_1363, UInt<1>("h0")) + node T_1367 = eq(T_1365, UInt<1>("h0")) + node T_1370 = mux(T_1367, T_1330, T_1363) + node T_1371 = and(T_1370, T_1323) + node T_1373 = neq(T_1371, UInt<1>("h0")) + node T_1374 = and(T_1373, UInt<1>("h1")) + node T_1375 = and(T_1374, UInt<1>("h1")) + io.inner.release.ready <= T_1375 + node T_1376 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1377 = and(T_1376, UInt<1>("h1")) + trackerList_0.io.inner.release.valid <= T_1377 + trackerList_0.io.inner.release.bits <- io.inner.release.bits + node T_1378 = bits(T_1356, 0, 0) + node T_1379 = and(T_1378, T_1367) + node T_1380 = and(T_1379, UInt<1>("h1")) + trackerList_0.io.alloc.irel.should <= T_1380 + node T_1381 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1382 = and(T_1381, UInt<1>("h1")) + trackerList_1.io.inner.release.valid <= T_1382 + trackerList_1.io.inner.release.bits <- io.inner.release.bits + node T_1383 = bits(T_1356, 1, 1) + node T_1384 = and(T_1383, T_1367) + node T_1385 = and(T_1384, UInt<1>("h1")) + trackerList_1.io.alloc.irel.should <= T_1385 + node T_1386 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1387 = and(T_1386, UInt<1>("h1")) + trackerList_2.io.inner.release.valid <= T_1387 + trackerList_2.io.inner.release.bits <- io.inner.release.bits + node T_1388 = bits(T_1356, 2, 2) + node T_1389 = and(T_1388, T_1367) + node T_1390 = and(T_1389, UInt<1>("h1")) + trackerList_2.io.alloc.irel.should <= T_1390 + node T_1391 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1392 = and(T_1391, UInt<1>("h1")) + trackerList_3.io.inner.release.valid <= T_1392 + trackerList_3.io.inner.release.bits <- io.inner.release.bits + node T_1393 = bits(T_1356, 3, 3) + node T_1394 = and(T_1393, T_1367) + node T_1395 = and(T_1394, UInt<1>("h1")) + trackerList_3.io.alloc.irel.should <= T_1395 + node T_1396 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1397 = and(T_1396, UInt<1>("h1")) + trackerList_4.io.inner.release.valid <= T_1397 + trackerList_4.io.inner.release.bits <- io.inner.release.bits + node T_1398 = bits(T_1356, 4, 4) + node T_1399 = and(T_1398, T_1367) + node T_1400 = and(T_1399, UInt<1>("h1")) + trackerList_4.io.alloc.irel.should <= T_1400 + node T_1401 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1402 = and(T_1401, UInt<1>("h1")) + trackerList_5.io.inner.release.valid <= T_1402 + trackerList_5.io.inner.release.bits <- io.inner.release.bits + node T_1403 = bits(T_1356, 5, 5) + node T_1404 = and(T_1403, T_1367) + node T_1405 = and(T_1404, UInt<1>("h1")) + trackerList_5.io.alloc.irel.should <= T_1405 + node T_1406 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1407 = and(T_1406, UInt<1>("h1")) + trackerList_6.io.inner.release.valid <= T_1407 + trackerList_6.io.inner.release.bits <- io.inner.release.bits + node T_1408 = bits(T_1356, 6, 6) + node T_1409 = and(T_1408, T_1367) + node T_1410 = and(T_1409, UInt<1>("h1")) + trackerList_6.io.alloc.irel.should <= T_1410 + node T_1411 = and(io.inner.release.valid, UInt<1>("h1")) + node T_1412 = and(T_1411, UInt<1>("h1")) + trackerList_7.io.inner.release.valid <= T_1412 + trackerList_7.io.inner.release.bits <- io.inner.release.bits + node T_1413 = bits(T_1356, 7, 7) + node T_1414 = and(T_1413, T_1367) + node T_1415 = and(T_1414, UInt<1>("h1")) + trackerList_7.io.alloc.irel.should <= T_1415 + inst LockingRRArbiter_7_1 of LockingRRArbiter_7 LockingRRArbiter_7_1.io is invalid LockingRRArbiter_7_1.clk <= clk LockingRRArbiter_7_1.reset <= reset - io.inner.probe <- LockingRRArbiter_7_1.io.out @[Agents.scala 53:9] - LockingRRArbiter_7_1.io.in[0] <- trackerList_0.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[1] <- trackerList_1.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[2] <- trackerList_2.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[3] <- trackerList_3.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[4] <- trackerList_4.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[5] <- trackerList_5.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[6] <- trackerList_6.io.inner.probe @[Agents.scala 54:15] - LockingRRArbiter_7_1.io.in[7] <- trackerList_7.io.inner.probe @[Agents.scala 54:15] - inst LockingRRArbiter_8_1 of LockingRRArbiter_8 @[Agents.scala 52:21] + io.inner.probe <- LockingRRArbiter_7_1.io.out + LockingRRArbiter_7_1.io.in[0] <- trackerList_0.io.inner.probe + LockingRRArbiter_7_1.io.in[1] <- trackerList_1.io.inner.probe + LockingRRArbiter_7_1.io.in[2] <- trackerList_2.io.inner.probe + LockingRRArbiter_7_1.io.in[3] <- trackerList_3.io.inner.probe + LockingRRArbiter_7_1.io.in[4] <- trackerList_4.io.inner.probe + LockingRRArbiter_7_1.io.in[5] <- trackerList_5.io.inner.probe + LockingRRArbiter_7_1.io.in[6] <- trackerList_6.io.inner.probe + LockingRRArbiter_7_1.io.in[7] <- trackerList_7.io.inner.probe + inst LockingRRArbiter_8_1 of LockingRRArbiter_8 LockingRRArbiter_8_1.io is invalid LockingRRArbiter_8_1.clk <= clk LockingRRArbiter_8_1.reset <= reset - io.inner.grant <- LockingRRArbiter_8_1.io.out @[Agents.scala 53:9] - LockingRRArbiter_8_1.io.in[0] <- trackerList_0.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[1] <- trackerList_1.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[2] <- trackerList_2.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[3] <- trackerList_3.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[4] <- trackerList_4.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[5] <- trackerList_5.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[6] <- trackerList_6.io.inner.grant @[Agents.scala 54:15] - LockingRRArbiter_8_1.io.in[7] <- trackerList_7.io.inner.grant @[Agents.scala 54:15] - trackerList_0.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_1.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_2.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_3.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_4.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_5.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_6.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - trackerList_7.io.inner.finish.bits <- io.inner.finish.bits @[Agents.scala 61:21] - node T_1417 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) @[Agents.scala 62:70] - node T_1418 = and(io.inner.finish.valid, T_1417) @[Agents.scala 62:63] - trackerList_0.io.inner.finish.valid <= T_1418 @[Agents.scala 62:51] - node T_1420 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) @[Agents.scala 62:70] - node T_1421 = and(io.inner.finish.valid, T_1420) @[Agents.scala 62:63] - trackerList_1.io.inner.finish.valid <= T_1421 @[Agents.scala 62:51] - node T_1423 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) @[Agents.scala 62:70] - node T_1424 = and(io.inner.finish.valid, T_1423) @[Agents.scala 62:63] - trackerList_2.io.inner.finish.valid <= T_1424 @[Agents.scala 62:51] - node T_1426 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) @[Agents.scala 62:70] - node T_1427 = and(io.inner.finish.valid, T_1426) @[Agents.scala 62:63] - trackerList_3.io.inner.finish.valid <= T_1427 @[Agents.scala 62:51] - node T_1429 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) @[Agents.scala 62:70] - node T_1430 = and(io.inner.finish.valid, T_1429) @[Agents.scala 62:63] - trackerList_4.io.inner.finish.valid <= T_1430 @[Agents.scala 62:51] - node T_1432 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) @[Agents.scala 62:70] - node T_1433 = and(io.inner.finish.valid, T_1432) @[Agents.scala 62:63] - trackerList_5.io.inner.finish.valid <= T_1433 @[Agents.scala 62:51] - node T_1435 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) @[Agents.scala 62:70] - node T_1436 = and(io.inner.finish.valid, T_1435) @[Agents.scala 62:63] - trackerList_6.io.inner.finish.valid <= T_1436 @[Agents.scala 62:51] - node T_1438 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) @[Agents.scala 62:70] - node T_1439 = and(io.inner.finish.valid, T_1438) @[Agents.scala 62:63] - trackerList_7.io.inner.finish.valid <= T_1439 @[Agents.scala 62:51] - node T_1441 = and(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) @[Package.scala 18:26] - node T_1443 = geq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) @[Package.scala 19:17] - node T_1445 = and(T_1441, UInt<1>("h01")) @[Package.scala 18:26] - node T_1447 = geq(T_1441, UInt<2>("h02")) @[Package.scala 19:17] - node T_1449 = and(T_1445, UInt<1>("h00")) @[Package.scala 18:26] - node T_1451 = geq(T_1445, UInt<1>("h01")) @[Package.scala 19:17] - node T_1452 = mux(T_1451, trackerList_7.io.inner.finish.ready, trackerList_6.io.inner.finish.ready) @[Package.scala 19:12] - node T_1454 = and(T_1445, UInt<1>("h00")) @[Package.scala 18:26] - node T_1456 = geq(T_1445, UInt<1>("h01")) @[Package.scala 19:17] - node T_1457 = mux(T_1456, trackerList_5.io.inner.finish.ready, trackerList_4.io.inner.finish.ready) @[Package.scala 19:12] - node T_1458 = mux(T_1447, T_1452, T_1457) @[Package.scala 19:12] - node T_1460 = and(T_1441, UInt<1>("h01")) @[Package.scala 18:26] - node T_1462 = geq(T_1441, UInt<2>("h02")) @[Package.scala 19:17] - node T_1464 = and(T_1460, UInt<1>("h00")) @[Package.scala 18:26] - node T_1466 = geq(T_1460, UInt<1>("h01")) @[Package.scala 19:17] - node T_1467 = mux(T_1466, trackerList_3.io.inner.finish.ready, trackerList_2.io.inner.finish.ready) @[Package.scala 19:12] - node T_1469 = and(T_1460, UInt<1>("h00")) @[Package.scala 18:26] - node T_1471 = geq(T_1460, UInt<1>("h01")) @[Package.scala 19:17] - node T_1472 = mux(T_1471, trackerList_1.io.inner.finish.ready, trackerList_0.io.inner.finish.ready) @[Package.scala 19:12] - node T_1473 = mux(T_1462, T_1467, T_1472) @[Package.scala 19:12] - node T_1474 = mux(T_1443, T_1458, T_1473) @[Package.scala 19:12] - io.inner.finish.ready <= T_1474 @[Agents.scala 63:14] - io.outer.probe.ready <= UInt<1>("h00") @[Agents.scala 158:26] - io.outer.finish.valid <= UInt<1>("h00") @[Agents.scala 159:27] - node T_1478 = eq(io.outer.probe.valid, UInt<1>("h00")) @[Agents.scala 160:12] - node T_1479 = or(T_1478, reset) @[Agents.scala 160:11] - node T_1481 = eq(T_1479, UInt<1>("h00")) @[Agents.scala 160:11] - when T_1481 : @[Agents.scala 160:11] - printf(clk, UInt<1>(1), "Assertion failed: L2 agent got illegal probe\n at Agents.scala:160 assert(!io.outer.probe.valid, \"L2 agent got illegal probe\")\n") @[Agents.scala 160:11] - stop(clk, UInt<1>(1), 1) @[Agents.scala 160:11] - skip @[Agents.scala 160:11] - - module MMIOTileLinkManager : + io.inner.grant <- LockingRRArbiter_8_1.io.out + LockingRRArbiter_8_1.io.in[0] <- trackerList_0.io.inner.grant + LockingRRArbiter_8_1.io.in[1] <- trackerList_1.io.inner.grant + LockingRRArbiter_8_1.io.in[2] <- trackerList_2.io.inner.grant + LockingRRArbiter_8_1.io.in[3] <- trackerList_3.io.inner.grant + LockingRRArbiter_8_1.io.in[4] <- trackerList_4.io.inner.grant + LockingRRArbiter_8_1.io.in[5] <- trackerList_5.io.inner.grant + LockingRRArbiter_8_1.io.in[6] <- trackerList_6.io.inner.grant + LockingRRArbiter_8_1.io.in[7] <- trackerList_7.io.inner.grant + trackerList_0.io.inner.finish.bits <- io.inner.finish.bits + trackerList_1.io.inner.finish.bits <- io.inner.finish.bits + trackerList_2.io.inner.finish.bits <- io.inner.finish.bits + trackerList_3.io.inner.finish.bits <- io.inner.finish.bits + trackerList_4.io.inner.finish.bits <- io.inner.finish.bits + trackerList_5.io.inner.finish.bits <- io.inner.finish.bits + trackerList_6.io.inner.finish.bits <- io.inner.finish.bits + trackerList_7.io.inner.finish.bits <- io.inner.finish.bits + node T_1417 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h0")) + node T_1418 = and(io.inner.finish.valid, T_1417) + trackerList_0.io.inner.finish.valid <= T_1418 + node T_1420 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h1")) + node T_1421 = and(io.inner.finish.valid, T_1420) + trackerList_1.io.inner.finish.valid <= T_1421 + node T_1423 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h2")) + node T_1424 = and(io.inner.finish.valid, T_1423) + trackerList_2.io.inner.finish.valid <= T_1424 + node T_1426 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h3")) + node T_1427 = and(io.inner.finish.valid, T_1426) + trackerList_3.io.inner.finish.valid <= T_1427 + node T_1429 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h4")) + node T_1430 = and(io.inner.finish.valid, T_1429) + trackerList_4.io.inner.finish.valid <= T_1430 + node T_1432 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h5")) + node T_1433 = and(io.inner.finish.valid, T_1432) + trackerList_5.io.inner.finish.valid <= T_1433 + node T_1435 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h6")) + node T_1436 = and(io.inner.finish.valid, T_1435) + trackerList_6.io.inner.finish.valid <= T_1436 + node T_1438 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h7")) + node T_1439 = and(io.inner.finish.valid, T_1438) + trackerList_7.io.inner.finish.valid <= T_1439 + node T_1441 = and(io.inner.finish.bits.manager_xact_id, UInt<2>("h3")) + node T_1443 = geq(io.inner.finish.bits.manager_xact_id, UInt<3>("h4")) + node T_1445 = and(T_1441, UInt<1>("h1")) + node T_1447 = geq(T_1441, UInt<2>("h2")) + node T_1449 = and(T_1445, UInt<1>("h0")) + node T_1451 = geq(T_1445, UInt<1>("h1")) + node T_1452 = mux(T_1451, trackerList_7.io.inner.finish.ready, trackerList_6.io.inner.finish.ready) + node T_1454 = and(T_1445, UInt<1>("h0")) + node T_1456 = geq(T_1445, UInt<1>("h1")) + node T_1457 = mux(T_1456, trackerList_5.io.inner.finish.ready, trackerList_4.io.inner.finish.ready) + node T_1458 = mux(T_1447, T_1452, T_1457) + node T_1460 = and(T_1441, UInt<1>("h1")) + node T_1462 = geq(T_1441, UInt<2>("h2")) + node T_1464 = and(T_1460, UInt<1>("h0")) + node T_1466 = geq(T_1460, UInt<1>("h1")) + node T_1467 = mux(T_1466, trackerList_3.io.inner.finish.ready, trackerList_2.io.inner.finish.ready) + node T_1469 = and(T_1460, UInt<1>("h0")) + node T_1471 = geq(T_1460, UInt<1>("h1")) + node T_1472 = mux(T_1471, trackerList_1.io.inner.finish.ready, trackerList_0.io.inner.finish.ready) + node T_1473 = mux(T_1462, T_1467, T_1472) + node T_1474 = mux(T_1443, T_1458, T_1473) + io.inner.finish.ready <= T_1474 + io.outer.probe.ready <= UInt<1>("h0") + io.outer.finish.valid <= UInt<1>("h0") + node T_1478 = eq(io.outer.probe.valid, UInt<1>("h0")) + node T_1479 = or(T_1478, reset) + node T_1481 = eq(T_1479, UInt<1>("h0")) + when T_1481 : + printf(clk, UInt<1>("h1"), "Assertion failed: L2 agent got illegal probe\n at Agents.scala:160 assert(!io.outer.probe.valid, \"L2 agent got illegal probe\")\n") + stop(clk, UInt<1>("h1"), 1) + + module MMIOTileLinkManager : input clk : Clock input reset : UInt<1> - output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { inner : { flip acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>, client_id : UInt<1>}}, grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, flip finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<4>}}, probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<1>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>, client_id : UInt<1>}}}, flip incoherent : UInt<1>[1], outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - io.inner.probe.valid <= UInt<1>("h00") @[Mmio.scala 17:24] - io.inner.release.ready <= UInt<1>("h00") @[Mmio.scala 18:26] - node T_880 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_882 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_889 : UInt<3>[1] @[Definitions.scala 355:35] - T_889 is invalid @[Definitions.scala 355:35] - T_889[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_891 = eq(io.outer.acquire.bits.a_type, T_889[0]) @[Package.scala 7:47] - node T_892 = and(T_882, T_891) @[Definitions.scala 231:89] - node multibeat_fire = and(T_880, T_892) @[Mmio.scala 20:48] - node T_894 = eq(io.outer.acquire.bits.addr_beat, UInt<1>("h00")) @[Mmio.scala 21:63] - node multibeat_start = and(multibeat_fire, T_894) @[Mmio.scala 21:40] - node T_896 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h07")) @[Mmio.scala 22:61] - node multibeat_end = and(multibeat_fire, T_896) @[Mmio.scala 22:38] - reg xact_pending : UInt<9>, clk with : (reset => (reset, UInt<9>("h00"))) - node T_898 = not(xact_pending) @[Mmio.scala 29:37] - node T_899 = bits(T_898, 0, 0) @[OneHot.scala 35:40] - node T_900 = bits(T_898, 1, 1) @[OneHot.scala 35:40] - node T_901 = bits(T_898, 2, 2) @[OneHot.scala 35:40] - node T_902 = bits(T_898, 3, 3) @[OneHot.scala 35:40] - node T_903 = bits(T_898, 4, 4) @[OneHot.scala 35:40] - node T_904 = bits(T_898, 5, 5) @[OneHot.scala 35:40] - node T_905 = bits(T_898, 6, 6) @[OneHot.scala 35:40] - node T_906 = bits(T_898, 7, 7) @[OneHot.scala 35:40] - node T_907 = bits(T_898, 8, 8) @[OneHot.scala 35:40] - node T_917 = mux(T_906, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 31:69] - node T_918 = mux(T_905, UInt<3>("h06"), T_917) @[Mux.scala 31:69] - node T_919 = mux(T_904, UInt<3>("h05"), T_918) @[Mux.scala 31:69] - node T_920 = mux(T_903, UInt<3>("h04"), T_919) @[Mux.scala 31:69] - node T_921 = mux(T_902, UInt<2>("h03"), T_920) @[Mux.scala 31:69] - node T_922 = mux(T_901, UInt<2>("h02"), T_921) @[Mux.scala 31:69] - node T_923 = mux(T_900, UInt<1>("h01"), T_922) @[Mux.scala 31:69] - node xact_id_sel = mux(T_899, UInt<1>("h00"), T_923) @[Mux.scala 31:69] - reg xact_id_reg : UInt<4>, clk - when multibeat_start : @[Reg.scala 29:19] - xact_id_reg <= xact_id_sel @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - reg xact_multibeat : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node outer_xact_id = mux(xact_multibeat, xact_id_reg, xact_id_sel) @[Mmio.scala 32:26] - node T_925 = not(xact_pending) @[Mmio.scala 33:33] - node T_927 = eq(T_925, UInt<1>("h00")) @[Mmio.scala 33:33] - node xact_free = eq(T_927, UInt<1>("h00")) @[Mmio.scala 33:19] - reg xact_buffer : {client_id : UInt<1>, client_xact_id : UInt<1>}[9], clk - node T_1464 = and(io.outer.acquire.ready, xact_free) @[Mmio.scala 36:52] - io.inner.acquire.ready <= T_1464 @[Mmio.scala 36:26] - node T_1465 = and(io.inner.acquire.valid, xact_free) @[Mmio.scala 37:52] - io.outer.acquire.valid <= T_1465 @[Mmio.scala 37:26] - io.outer.acquire.bits <- io.inner.acquire.bits @[Mmio.scala 38:26] - io.outer.acquire.bits.client_xact_id <= outer_xact_id @[Mmio.scala 39:40] - node T_1466 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_1468 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1475 : UInt<3>[1] @[Definitions.scala 355:35] - T_1475 is invalid @[Definitions.scala 355:35] - T_1475[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1477 = eq(io.outer.acquire.bits.a_type, T_1475[0]) @[Package.scala 7:47] - node T_1478 = and(T_1468, T_1477) @[Definitions.scala 231:89] - node T_1480 = eq(T_1478, UInt<1>("h00")) @[Mmio.scala 42:5] - node T_1482 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h07")) @[Mmio.scala 42:44] - node T_1483 = or(T_1480, T_1482) @[Mmio.scala 42:28] - node T_1484 = and(T_1466, T_1483) @[Mmio.scala 45:19] - node T_1486 = dshl(UInt<1>("h01"), io.outer.acquire.bits.client_xact_id) @[OneHot.scala 44:15] - node T_1488 = mux(T_1484, T_1486, UInt<1>("h00")) @[Mmio.scala 45:8] - node T_1489 = or(xact_pending, T_1488) @[Mmio.scala 54:33] - node T_1490 = and(io.inner.finish.ready, io.inner.finish.valid) @[Decoupled.scala 21:42] - node T_1492 = dshl(UInt<1>("h01"), io.inner.finish.bits.manager_xact_id) @[OneHot.scala 44:15] - node T_1494 = mux(T_1490, T_1492, UInt<1>("h00")) @[Mmio.scala 52:9] - node T_1495 = not(T_1494) @[Mmio.scala 52:5] - node T_1496 = and(T_1489, T_1495) @[Mmio.scala 54:73] - node T_1497 = and(io.inner.grant.ready, io.inner.grant.valid) @[Decoupled.scala 21:42] - wire T_1505 : UInt<3>[1] @[Definitions.scala 853:34] - T_1505 is invalid @[Definitions.scala 853:34] - T_1505[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1507 = eq(io.inner.grant.bits.g_type, T_1505[0]) @[Package.scala 7:47] - node T_1508 = eq(io.inner.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1509 = mux(io.inner.grant.bits.is_builtin_type, T_1507, T_1508) @[Definitions.scala 274:33] - node T_1510 = and(UInt<1>("h01"), T_1509) @[Definitions.scala 274:27] - node T_1512 = eq(T_1510, UInt<1>("h00")) @[Mmio.scala 42:5] - node T_1514 = eq(io.inner.grant.bits.addr_beat, UInt<3>("h07")) @[Mmio.scala 42:44] - node T_1515 = or(T_1512, T_1514) @[Mmio.scala 42:28] - node T_1516 = and(T_1497, T_1515) @[Mmio.scala 48:20] - node T_1519 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Definitions.scala 278:43] - node T_1521 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) @[Definitions.scala 277:70] - node T_1522 = and(io.inner.grant.bits.is_builtin_type, T_1521) @[Definitions.scala 277:59] - node T_1524 = eq(T_1522, UInt<1>("h00")) @[Definitions.scala 278:92] - node T_1525 = and(T_1519, T_1524) @[Definitions.scala 278:89] - node T_1527 = eq(T_1525, UInt<1>("h00")) @[Mmio.scala 48:46] - node T_1528 = and(T_1516, T_1527) @[Mmio.scala 48:43] - node T_1530 = dshl(UInt<1>("h01"), io.inner.grant.bits.manager_xact_id) @[OneHot.scala 44:15] - node T_1532 = mux(T_1528, T_1530, UInt<1>("h00")) @[Mmio.scala 48:9] - node T_1533 = not(T_1532) @[Mmio.scala 48:5] - node T_1534 = and(T_1496, T_1533) @[Mmio.scala 55:73] - xact_pending <= T_1534 @[Mmio.scala 54:16] - node T_1535 = and(io.outer.acquire.ready, io.outer.acquire.valid) @[Decoupled.scala 21:42] - node T_1537 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1544 : UInt<3>[1] @[Definitions.scala 355:35] - T_1544 is invalid @[Definitions.scala 355:35] - T_1544[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1546 = eq(io.outer.acquire.bits.a_type, T_1544[0]) @[Package.scala 7:47] - node T_1547 = and(T_1537, T_1546) @[Definitions.scala 231:89] - node T_1549 = eq(T_1547, UInt<1>("h00")) @[Mmio.scala 42:5] - node T_1551 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h07")) @[Mmio.scala 42:44] - node T_1552 = or(T_1549, T_1551) @[Mmio.scala 42:28] - node T_1553 = and(T_1535, T_1552) @[Mmio.scala 58:33] - when T_1553 : @[Mmio.scala 58:71] - xact_buffer[outer_xact_id] <- io.inner.acquire.bits @[Mmio.scala 59:32] - skip @[Mmio.scala 58:71] - when multibeat_start : @[Mmio.scala 62:26] - xact_multibeat <= UInt<1>("h01") @[Mmio.scala 62:43] - skip @[Mmio.scala 62:26] - when multibeat_end : @[Mmio.scala 63:26] - xact_multibeat <= UInt<1>("h00") @[Mmio.scala 63:43] - skip @[Mmio.scala 63:26] - io.outer.grant.ready <= io.inner.grant.ready @[Mmio.scala 66:24] - io.inner.grant.valid <= io.outer.grant.valid @[Mmio.scala 67:24] - io.inner.grant.bits <- io.outer.grant.bits @[Mmio.scala 68:24] - io.inner.grant.bits.client_id <= xact_buffer[io.outer.grant.bits.client_xact_id].client_id @[Mmio.scala 69:33] - io.inner.grant.bits.client_xact_id <= xact_buffer[io.outer.grant.bits.client_xact_id].client_xact_id @[Mmio.scala 70:38] - io.inner.grant.bits.manager_xact_id <= io.outer.grant.bits.client_xact_id @[Mmio.scala 71:39] - io.inner.finish.ready <= UInt<1>("h01") @[Mmio.scala 72:25] - - module ClientUncachedTileLinkIOArbiter_1 : + io.inner.probe.valid <= UInt<1>("h0") + io.inner.release.ready <= UInt<1>("h0") + node T_880 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_882 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_889 : UInt<3>[1] + T_889 is invalid + T_889[0] <= UInt<3>("h3") + node T_891 = eq(io.outer.acquire.bits.a_type, T_889[0]) + node T_892 = and(T_882, T_891) + node multibeat_fire = and(T_880, T_892) + node T_894 = eq(io.outer.acquire.bits.addr_beat, UInt<1>("h0")) + node multibeat_start = and(multibeat_fire, T_894) + node T_896 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h7")) + node multibeat_end = and(multibeat_fire, T_896) + reg xact_pending : UInt<9>, clk with : + reset => (reset, UInt<9>("h0")) + node T_898 = not(xact_pending) + node T_899 = bits(T_898, 0, 0) + node T_900 = bits(T_898, 1, 1) + node T_901 = bits(T_898, 2, 2) + node T_902 = bits(T_898, 3, 3) + node T_903 = bits(T_898, 4, 4) + node T_904 = bits(T_898, 5, 5) + node T_905 = bits(T_898, 6, 6) + node T_906 = bits(T_898, 7, 7) + node T_907 = bits(T_898, 8, 8) + node T_917 = mux(T_906, UInt<3>("h7"), UInt<4>("h8")) + node T_918 = mux(T_905, UInt<3>("h6"), T_917) + node T_919 = mux(T_904, UInt<3>("h5"), T_918) + node T_920 = mux(T_903, UInt<3>("h4"), T_919) + node T_921 = mux(T_902, UInt<2>("h3"), T_920) + node T_922 = mux(T_901, UInt<2>("h2"), T_921) + node T_923 = mux(T_900, UInt<1>("h1"), T_922) + node xact_id_sel = mux(T_899, UInt<1>("h0"), T_923) + reg xact_id_reg : UInt<4>, clk with : + reset => (UInt<1>("h0"), xact_id_reg) + when multibeat_start : + xact_id_reg <= xact_id_sel + reg xact_multibeat : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node outer_xact_id = mux(xact_multibeat, xact_id_reg, xact_id_sel) + node T_925 = not(xact_pending) + node T_927 = eq(T_925, UInt<1>("h0")) + node xact_free = eq(T_927, UInt<1>("h0")) + reg xact_buffer : { client_id : UInt<1>, client_xact_id : UInt<1>}[9], clk with : + reset => (UInt<1>("h0"), xact_buffer) + node T_1464 = and(io.outer.acquire.ready, xact_free) + io.inner.acquire.ready <= T_1464 + node T_1465 = and(io.inner.acquire.valid, xact_free) + io.outer.acquire.valid <= T_1465 + io.outer.acquire.bits <- io.inner.acquire.bits + io.outer.acquire.bits.client_xact_id <= outer_xact_id + node T_1466 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_1468 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_1475 : UInt<3>[1] + T_1475 is invalid + T_1475[0] <= UInt<3>("h3") + node T_1477 = eq(io.outer.acquire.bits.a_type, T_1475[0]) + node T_1478 = and(T_1468, T_1477) + node T_1480 = eq(T_1478, UInt<1>("h0")) + node T_1482 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h7")) + node T_1483 = or(T_1480, T_1482) + node T_1484 = and(T_1466, T_1483) + node T_1486 = dshl(UInt<1>("h1"), io.outer.acquire.bits.client_xact_id) + node T_1488 = mux(T_1484, T_1486, UInt<1>("h0")) + node T_1489 = or(xact_pending, T_1488) + node T_1490 = and(io.inner.finish.ready, io.inner.finish.valid) + node T_1492 = dshl(UInt<1>("h1"), io.inner.finish.bits.manager_xact_id) + node T_1494 = mux(T_1490, T_1492, UInt<1>("h0")) + node T_1495 = not(T_1494) + node T_1496 = and(T_1489, T_1495) + node T_1497 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_1505 : UInt<3>[1] + T_1505 is invalid + T_1505[0] <= UInt<3>("h5") + node T_1507 = eq(io.inner.grant.bits.g_type, T_1505[0]) + node T_1508 = eq(io.inner.grant.bits.g_type, UInt<1>("h0")) + node T_1509 = mux(io.inner.grant.bits.is_builtin_type, T_1507, T_1508) + node T_1510 = and(UInt<1>("h1"), T_1509) + node T_1512 = eq(T_1510, UInt<1>("h0")) + node T_1514 = eq(io.inner.grant.bits.addr_beat, UInt<3>("h7")) + node T_1515 = or(T_1512, T_1514) + node T_1516 = and(T_1497, T_1515) + node T_1519 = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_1521 = eq(io.inner.grant.bits.g_type, UInt<3>("h0")) + node T_1522 = and(io.inner.grant.bits.is_builtin_type, T_1521) + node T_1524 = eq(T_1522, UInt<1>("h0")) + node T_1525 = and(T_1519, T_1524) + node T_1527 = eq(T_1525, UInt<1>("h0")) + node T_1528 = and(T_1516, T_1527) + node T_1530 = dshl(UInt<1>("h1"), io.inner.grant.bits.manager_xact_id) + node T_1532 = mux(T_1528, T_1530, UInt<1>("h0")) + node T_1533 = not(T_1532) + node T_1534 = and(T_1496, T_1533) + xact_pending <= T_1534 + node T_1535 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_1537 = and(UInt<1>("h1"), io.outer.acquire.bits.is_builtin_type) + wire T_1544 : UInt<3>[1] + T_1544 is invalid + T_1544[0] <= UInt<3>("h3") + node T_1546 = eq(io.outer.acquire.bits.a_type, T_1544[0]) + node T_1547 = and(T_1537, T_1546) + node T_1549 = eq(T_1547, UInt<1>("h0")) + node T_1551 = eq(io.outer.acquire.bits.addr_beat, UInt<3>("h7")) + node T_1552 = or(T_1549, T_1551) + node T_1553 = and(T_1535, T_1552) + when T_1553 : + xact_buffer[outer_xact_id] <- io.inner.acquire.bits + when multibeat_start : + xact_multibeat <= UInt<1>("h1") + when multibeat_end : + xact_multibeat <= UInt<1>("h0") + io.outer.grant.ready <= io.inner.grant.ready + io.inner.grant.valid <= io.outer.grant.valid + io.inner.grant.bits <- io.outer.grant.bits + io.inner.grant.bits.client_id <= xact_buffer[io.outer.grant.bits.client_xact_id].client_id + io.inner.grant.bits.client_xact_id <= xact_buffer[io.outer.grant.bits.client_xact_id].client_xact_id + io.inner.grant.bits.manager_xact_id <= io.outer.grant.bits.client_xact_id + io.inner.finish.ready <= UInt<1>("h1") + + module ClientUncachedTileLinkIOArbiter_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - io.out <- io.in[0] @[Arbiters.scala 181:19] - - module TileLinkMemoryInterconnect : + io.out <- io.in[0] + + module TileLinkMemoryInterconnect : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} + io is invalid - inst ClientUncachedTileLinkIOArbiter_1_1 of ClientUncachedTileLinkIOArbiter_1 @[Interconnect.scala 309:28] + inst ClientUncachedTileLinkIOArbiter_1_1 of ClientUncachedTileLinkIOArbiter_1 ClientUncachedTileLinkIOArbiter_1_1.io is invalid ClientUncachedTileLinkIOArbiter_1_1.clk <= clk ClientUncachedTileLinkIOArbiter_1_1.reset <= reset - ClientUncachedTileLinkIOArbiter_1_1.io.in[0] <- io.in[0] @[Interconnect.scala 310:22] - io.out[0] <- ClientUncachedTileLinkIOArbiter_1_1.io.out @[Interconnect.scala 299:11] - node T_3009 = dshr(ClientUncachedTileLinkIOArbiter_1_1.io.out.acquire.bits.addr_block, UInt<1>("h00")) @[Interconnect.scala 300:68] - io.out[0].acquire.bits.addr_block <= T_3009 @[Interconnect.scala 300:35] - - module LockingRRArbiter_9 : + ClientUncachedTileLinkIOArbiter_1_1.io.in[0] <- io.in[0] + io.out[0] <- ClientUncachedTileLinkIOArbiter_1_1.io.out + node T_3009 = dshr(ClientUncachedTileLinkIOArbiter_1_1.io.out.acquire.bits.addr_block, UInt<1>("h0")) + io.out[0].acquire.bits.addr_block <= T_3009 + + module LockingRRArbiter_9 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, chosen : UInt<1>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, chosen : UInt<1>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<1>("h01") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_766 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_768 : UInt, clk - node T_770 = neq(T_766, UInt<1>("h00")) @[Arbiter.scala 39:34] - node T_772 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_779 : UInt<3>[1] @[Definitions.scala 355:35] - T_779 is invalid @[Definitions.scala 355:35] - T_779[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_781 = eq(io.out.bits.a_type, T_779[0]) @[Package.scala 7:47] - node T_782 = and(T_772, T_781) @[Definitions.scala 231:89] - node T_783 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_784 = and(T_783, T_782) @[Arbiter.scala 42:25] - when T_784 : @[Arbiter.scala 42:39] - T_768 <= io.chosen @[Arbiter.scala 43:15] - node T_786 = eq(T_766, UInt<3>("h07")) @[Counter.scala 20:24] - node T_788 = add(T_766, UInt<1>("h01")) @[Counter.scala 21:22] - node T_789 = tail(T_788, 1) @[Counter.scala 21:22] - T_766 <= T_789 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_770 : @[Arbiter.scala 47:19] - io.chosen <= T_768 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_791 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<1>, clk - when T_791 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node T_794 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_795 = or(T_794, io.in[0].valid) @[Arbiter.scala 23:72] - node T_797 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_799 = eq(T_794, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_801 = eq(T_795, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_802 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_803 = or(T_802, T_799) @[Arbiter.scala 64:50] - node T_804 = and(T_797, grantMask_1) @[Arbiter.scala 64:34] - node T_805 = or(T_804, T_801) @[Arbiter.scala 64:50] - node T_807 = eq(T_768, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_808 = mux(T_770, T_807, T_803) @[Arbiter.scala 49:22] - node T_809 = and(T_808, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_809 @[Arbiter.scala 49:16] - node T_811 = eq(T_768, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_812 = mux(T_770, T_811, T_805) @[Arbiter.scala 49:22] - node T_813 = and(T_812, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_813 @[Arbiter.scala 49:16] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module ReorderQueue : + choice <= UInt<1>("h1") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_766 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_768 : UInt, clk with : + reset => (UInt<1>("h0"), T_768) + node T_770 = neq(T_766, UInt<1>("h0")) + node T_772 = and(UInt<1>("h1"), io.out.bits.is_builtin_type) + wire T_779 : UInt<3>[1] + T_779 is invalid + T_779[0] <= UInt<3>("h3") + node T_781 = eq(io.out.bits.a_type, T_779[0]) + node T_782 = and(T_772, T_781) + node T_783 = and(io.out.ready, io.out.valid) + node T_784 = and(T_783, T_782) + when T_784 : + T_768 <= io.chosen + node T_786 = eq(T_766, UInt<3>("h7")) + node T_788 = add(T_766, UInt<1>("h1")) + node T_789 = tail(T_788, 1) + T_766 <= T_789 + when T_770 : + io.chosen <= T_768 + node T_791 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<1>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_791 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node T_794 = or(validMask_0, validMask_1) + node T_795 = or(T_794, io.in[0].valid) + node T_797 = eq(validMask_0, UInt<1>("h0")) + node T_799 = eq(T_794, UInt<1>("h0")) + node T_801 = eq(T_795, UInt<1>("h0")) + node T_802 = and(UInt<1>("h1"), grantMask_0) + node T_803 = or(T_802, T_799) + node T_804 = and(T_797, grantMask_1) + node T_805 = or(T_804, T_801) + node T_807 = eq(T_768, UInt<1>("h0")) + node T_808 = mux(T_770, T_807, T_803) + node T_809 = and(T_808, io.out.ready) + io.in[0].ready <= T_809 + node T_811 = eq(T_768, UInt<1>("h1")) + node T_812 = mux(T_770, T_811, T_805) + node T_813 = and(T_812, io.out.ready) + io.in[1].ready <= T_813 + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_1 : + choice <= UInt<1>("h1") + + module ReorderQueue : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<1>, tag : UInt<4>}}, deq : { flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} + io is invalid - cmem T_31 : UInt<1>[16] @[util.scala 220:23] - wire T_53 : UInt<1>[16] @[util.scala 221:53] - T_53 is invalid @[util.scala 221:53] - T_53[0] <= UInt<1>("h01") @[util.scala 221:53] - T_53[1] <= UInt<1>("h01") @[util.scala 221:53] - T_53[2] <= UInt<1>("h01") @[util.scala 221:53] - T_53[3] <= UInt<1>("h01") @[util.scala 221:53] - T_53[4] <= UInt<1>("h01") @[util.scala 221:53] - T_53[5] <= UInt<1>("h01") @[util.scala 221:53] - T_53[6] <= UInt<1>("h01") @[util.scala 221:53] - T_53[7] <= UInt<1>("h01") @[util.scala 221:53] - T_53[8] <= UInt<1>("h01") @[util.scala 221:53] - T_53[9] <= UInt<1>("h01") @[util.scala 221:53] - T_53[10] <= UInt<1>("h01") @[util.scala 221:53] - T_53[11] <= UInt<1>("h01") @[util.scala 221:53] - T_53[12] <= UInt<1>("h01") @[util.scala 221:53] - T_53[13] <= UInt<1>("h01") @[util.scala 221:53] - T_53[14] <= UInt<1>("h01") @[util.scala 221:53] - T_53[15] <= UInt<1>("h01") @[util.scala 221:53] - reg T_57 : UInt<1>[16], clk with : (reset => (reset, T_53)) - io.enq.ready <= T_57[io.enq.bits.tag] @[util.scala 223:18] + cmem T_31 : UInt<1> [16] + wire T_53 : UInt<1>[16] + T_53 is invalid + T_53[0] <= UInt<1>("h1") + T_53[1] <= UInt<1>("h1") + T_53[2] <= UInt<1>("h1") + T_53[3] <= UInt<1>("h1") + T_53[4] <= UInt<1>("h1") + T_53[5] <= UInt<1>("h1") + T_53[6] <= UInt<1>("h1") + T_53[7] <= UInt<1>("h1") + T_53[8] <= UInt<1>("h1") + T_53[9] <= UInt<1>("h1") + T_53[10] <= UInt<1>("h1") + T_53[11] <= UInt<1>("h1") + T_53[12] <= UInt<1>("h1") + T_53[13] <= UInt<1>("h1") + T_53[14] <= UInt<1>("h1") + T_53[15] <= UInt<1>("h1") + reg T_57 : UInt<1>[16], clk with : + reset => (reset, T_53) + io.enq.ready <= T_57[io.enq.bits.tag] infer mport T_59 = T_31[io.deq.tag], clk - io.deq.data <= T_59 @[util.scala 224:17] - node T_61 = eq(T_57[io.deq.tag], UInt<1>("h00")) @[util.scala 225:23] - io.deq.matches <= T_61 @[util.scala 225:20] - node T_62 = and(io.enq.valid, io.enq.ready) @[util.scala 227:24] - when T_62 : @[util.scala 227:41] + io.deq.data <= T_59 + node T_61 = eq(T_57[io.deq.tag], UInt<1>("h0")) + io.deq.matches <= T_61 + node T_62 = and(io.enq.valid, io.enq.ready) + when T_62 : infer mport T_63 = T_31[io.enq.bits.tag], clk - T_63 <= io.enq.bits.data @[util.scala 228:33] - T_57[io.enq.bits.tag] <= UInt<1>("h00") @[util.scala 229:33] - skip @[util.scala 227:41] - when io.deq.valid : @[util.scala 232:25] - T_57[io.deq.tag] <= UInt<1>("h01") @[util.scala 233:28] - skip @[util.scala 232:25] - - module ClientTileLinkIOUnwrapper : + T_63 <= io.enq.bits.data + T_57[io.enq.bits.tag] <= UInt<1>("h0") + when io.deq.valid : + T_57[io.deq.tag] <= UInt<1>("h1") + + module ClientTileLinkIOUnwrapper : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - inst acqArb of LockingRRArbiter_9 @[Tilelink.scala 56:22] + inst acqArb of LockingRRArbiter_9 acqArb.io is invalid acqArb.clk <= clk acqArb.reset <= reset - inst acqRoq of ReorderQueue @[Tilelink.scala 59:22] + inst acqRoq of ReorderQueue acqRoq.io is invalid acqRoq.clk <= clk acqRoq.reset <= reset - inst relRoq of ReorderQueue @[Tilelink.scala 60:22] + inst relRoq of ReorderQueue relRoq.io is invalid relRoq.clk <= clk relRoq.reset <= reset - node T_1359 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_1366 : UInt<3>[1] @[Definitions.scala 355:35] - T_1366 is invalid @[Definitions.scala 355:35] - T_1366[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_1368 = eq(io.in.acquire.bits.a_type, T_1366[0]) @[Package.scala 7:47] - node T_1369 = and(T_1359, T_1368) @[Definitions.scala 231:89] - node T_1371 = eq(T_1369, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1373 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node acq_roq_enq = or(T_1371, T_1373) @[Definitions.scala 141:57] - node T_1375 = eq(io.in.release.bits.r_type, UInt<3>("h00")) @[Package.scala 7:47] - node T_1376 = eq(io.in.release.bits.r_type, UInt<3>("h01")) @[Package.scala 7:47] - node T_1377 = eq(io.in.release.bits.r_type, UInt<3>("h02")) @[Package.scala 7:47] - node T_1378 = or(T_1375, T_1376) @[Package.scala 7:62] - node T_1379 = or(T_1378, T_1377) @[Package.scala 7:62] - node T_1380 = and(UInt<1>("h01"), T_1379) @[Definitions.scala 256:64] - node T_1382 = eq(T_1380, UInt<1>("h00")) @[Definitions.scala 141:37] - node T_1384 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) @[Definitions.scala 141:71] - node rel_roq_enq = or(T_1382, T_1384) @[Definitions.scala 141:57] - node T_1386 = eq(acq_roq_enq, UInt<1>("h00")) @[Tilelink.scala 69:23] - node acq_roq_ready = or(T_1386, acqRoq.io.enq.ready) @[Tilelink.scala 69:36] - node T_1388 = eq(rel_roq_enq, UInt<1>("h00")) @[Tilelink.scala 70:23] - node rel_roq_ready = or(T_1388, relRoq.io.enq.ready) @[Tilelink.scala 70:36] - node T_1389 = and(io.in.acquire.valid, acqArb.io.in[0].ready) @[util.scala 244:53] - node T_1390 = and(T_1389, acq_roq_enq) @[util.scala 244:53] - acqRoq.io.enq.valid <= T_1390 @[Tilelink.scala 82:23] - acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type @[Tilelink.scala 83:27] - acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id @[Tilelink.scala 84:26] - node T_1391 = and(io.in.acquire.valid, acq_roq_ready) @[util.scala 244:53] - acqArb.io.in[0].valid <= T_1391 @[Tilelink.scala 86:25] - node T_1394 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) @[Tilelink.scala 89:17] - wire T_1423 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_1423 is invalid @[Definitions.scala 417:19] - T_1423.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_1423.a_type <= T_1394 @[Definitions.scala 419:16] - T_1423.client_xact_id <= io.in.acquire.bits.client_xact_id @[Definitions.scala 420:24] - T_1423.addr_block <= io.in.acquire.bits.addr_block @[Definitions.scala 421:20] - T_1423.addr_beat <= io.in.acquire.bits.addr_beat @[Definitions.scala 422:19] - T_1423.data <= io.in.acquire.bits.data @[Definitions.scala 423:14] - T_1423.union <= io.in.acquire.bits.union @[Definitions.scala 424:15] - acqArb.io.in[0].bits <- T_1423 @[Tilelink.scala 87:24] - node T_1451 = and(acq_roq_ready, acqArb.io.in[0].ready) @[util.scala 244:53] - io.in.acquire.ready <= T_1451 @[Tilelink.scala 96:23] - node T_1452 = and(io.in.release.valid, acqArb.io.in[1].ready) @[util.scala 244:53] - node T_1453 = and(T_1452, rel_roq_enq) @[util.scala 244:53] - relRoq.io.enq.valid <= T_1453 @[Tilelink.scala 98:23] - relRoq.io.enq.bits.data <= io.in.release.bits.voluntary @[Tilelink.scala 99:27] - relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id @[Tilelink.scala 100:26] - node T_1454 = and(io.in.release.valid, rel_roq_ready) @[util.scala 244:53] - acqArb.io.in[1].valid <= T_1454 @[Tilelink.scala 102:25] - node T_1478 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1504 = or(UInt<3>("h00"), UInt<1>("h00")) @[Definitions.scala 386:49] - node T_1505 = bits(T_1504, 2, 0) @[Definitions.scala 386:61] - node T_1507 = or(UInt<2>("h00"), UInt<1>("h00")) @[Definitions.scala 387:61] - node T_1508 = bits(T_1507, 1, 0) @[Definitions.scala 387:76] - node T_1510 = or(UInt<5>("h00"), UInt<1>("h00")) @[Definitions.scala 388:36] - node T_1511 = bits(T_1510, 4, 0) @[Definitions.scala 388:45] - node T_1513 = or(UInt<8>("h00"), T_1478) @[Definitions.scala 389:46] - node T_1514 = bits(T_1513, 7, 0) @[Definitions.scala 389:54] - node T_1517 = cat(T_1511, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1518 = cat(T_1505, T_1508) @[Cat.scala 20:58] - node T_1519 = cat(T_1518, T_1517) @[Cat.scala 20:58] - node T_1521 = cat(T_1508, T_1511) @[Cat.scala 20:58] - node T_1522 = cat(T_1521, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1524 = cat(T_1514, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1526 = cat(T_1514, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1528 = cat(T_1511, UInt<1>("h01")) @[Cat.scala 20:58] - node T_1529 = cat(T_1505, T_1508) @[Cat.scala 20:58] - node T_1530 = cat(T_1529, T_1528) @[Cat.scala 20:58] - node T_1532 = cat(UInt<5>("h00"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_1534 = cat(UInt<5>("h01"), UInt<1>("h01")) @[Cat.scala 20:58] - node T_1535 = eq(UInt<3>("h06"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1536 = mux(T_1535, T_1534, UInt<1>("h00")) @[Mux.scala 46:16] - node T_1537 = eq(UInt<3>("h05"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1538 = mux(T_1537, T_1532, T_1536) @[Mux.scala 46:16] - node T_1539 = eq(UInt<3>("h04"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1540 = mux(T_1539, T_1530, T_1538) @[Mux.scala 46:16] - node T_1541 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1542 = mux(T_1541, T_1526, T_1540) @[Mux.scala 46:16] - node T_1543 = eq(UInt<3>("h02"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1544 = mux(T_1543, T_1524, T_1542) @[Mux.scala 46:16] - node T_1545 = eq(UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1546 = mux(T_1545, T_1522, T_1544) @[Mux.scala 46:16] - node T_1547 = eq(UInt<3>("h00"), UInt<3>("h03")) @[Mux.scala 46:19] - node T_1548 = mux(T_1547, T_1519, T_1546) @[Mux.scala 46:16] - wire T_1577 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} @[Definitions.scala 417:19] - T_1577 is invalid @[Definitions.scala 417:19] - T_1577.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 418:25] - T_1577.a_type <= UInt<3>("h03") @[Definitions.scala 419:16] - T_1577.client_xact_id <= io.in.release.bits.client_xact_id @[Definitions.scala 420:24] - T_1577.addr_block <= io.in.release.bits.addr_block @[Definitions.scala 421:20] - T_1577.addr_beat <= io.in.release.bits.addr_beat @[Definitions.scala 422:19] - T_1577.data <= io.in.release.bits.data @[Definitions.scala 423:14] - T_1577.union <= T_1548 @[Definitions.scala 424:15] - acqArb.io.in[1].bits <- T_1577 @[Tilelink.scala 103:24] - node T_1605 = and(rel_roq_ready, acqArb.io.in[1].ready) @[util.scala 244:53] - io.in.release.ready <= T_1605 @[Tilelink.scala 108:23] - io.out.acquire <- acqArb.io.out @[Tilelink.scala 110:18] - node T_1606 = and(io.out.grant.ready, io.out.grant.valid) @[Decoupled.scala 21:42] - wire T_1614 : UInt<3>[1] @[Definitions.scala 853:34] - T_1614 is invalid @[Definitions.scala 853:34] - T_1614[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1616 = eq(io.out.grant.bits.g_type, T_1614[0]) @[Package.scala 7:47] - node T_1617 = eq(io.out.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1618 = mux(io.out.grant.bits.is_builtin_type, T_1616, T_1617) @[Definitions.scala 274:33] - node T_1619 = and(UInt<1>("h01"), T_1618) @[Definitions.scala 274:27] - node T_1621 = eq(T_1619, UInt<1>("h00")) @[Definitions.scala 142:36] - node T_1623 = eq(io.out.grant.bits.addr_beat, UInt<3>("h07")) @[Definitions.scala 142:69] - node T_1624 = or(T_1621, T_1623) @[Definitions.scala 142:56] - node grant_deq_roq = and(T_1606, T_1624) @[Tilelink.scala 112:43] - node T_1625 = and(acqRoq.io.deq.matches, grant_deq_roq) @[Tilelink.scala 114:48] - acqRoq.io.deq.valid <= T_1625 @[Tilelink.scala 114:23] - acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id @[Tilelink.scala 115:21] - node T_1627 = eq(acqRoq.io.deq.matches, UInt<1>("h00")) @[Tilelink.scala 117:26] - node T_1628 = and(T_1627, grant_deq_roq) @[Tilelink.scala 117:49] - relRoq.io.deq.valid <= T_1628 @[Tilelink.scala 117:23] - relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id @[Tilelink.scala 118:21] - node T_1630 = eq(grant_deq_roq, UInt<1>("h00")) @[Tilelink.scala 120:10] - node T_1631 = or(T_1630, acqRoq.io.deq.matches) @[Tilelink.scala 120:25] - node T_1632 = or(T_1631, relRoq.io.deq.matches) @[Tilelink.scala 120:50] - node T_1633 = or(T_1632, reset) @[Tilelink.scala 120:9] - node T_1635 = eq(T_1633, UInt<1>("h00")) @[Tilelink.scala 120:9] - when T_1635 : @[Tilelink.scala 120:9] - printf(clk, UInt<1>(1), "Assertion failed: TileLink Unwrapper: client_xact_id mismatch\n at Tilelink.scala:120 assert(!grant_deq_roq || acqRoq.io.deq.matches || relRoq.io.deq.matches,\n") @[Tilelink.scala 120:9] - stop(clk, UInt<1>(1), 1) @[Tilelink.scala 120:9] - skip @[Tilelink.scala 120:9] - node T_1636 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00")) @[Tilelink.scala 128:17] - wire acq_grant : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - acq_grant is invalid @[Definitions.scala 863:19] - acq_grant.is_builtin_type <= acqRoq.io.deq.data @[Definitions.scala 864:25] - acq_grant.g_type <= T_1636 @[Definitions.scala 865:16] - acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id @[Definitions.scala 866:24] - acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id @[Definitions.scala 867:25] - acq_grant.addr_beat <= io.out.grant.bits.addr_beat @[Definitions.scala 868:19] - acq_grant.data <= io.out.grant.bits.data @[Definitions.scala 869:14] - node T_1691 = eq(io.in.release.valid, UInt<1>("h00")) @[Tilelink.scala 134:10] - node T_1692 = or(T_1691, io.in.release.bits.voluntary) @[Tilelink.scala 134:31] - node T_1693 = or(T_1692, reset) @[Tilelink.scala 134:9] - node T_1695 = eq(T_1693, UInt<1>("h00")) @[Tilelink.scala 134:9] - when T_1695 : @[Tilelink.scala 134:9] - printf(clk, UInt<1>(1), "Assertion failed: Unwrapper can only process voluntary releases.\n at Tilelink.scala:134 assert(!io.in.release.valid || io.in.release.bits.isVoluntary(), \"Unwrapper can only process voluntary releases.\")\n") @[Tilelink.scala 134:9] - stop(clk, UInt<1>(1), 1) @[Tilelink.scala 134:9] - skip @[Tilelink.scala 134:9] - wire rel_grant : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - rel_grant is invalid @[Definitions.scala 863:19] - rel_grant.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - rel_grant.g_type <= UInt<3>("h00") @[Definitions.scala 865:16] - rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id @[Definitions.scala 866:24] - rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id @[Definitions.scala 867:25] - rel_grant.addr_beat <= io.out.grant.bits.addr_beat @[Definitions.scala 868:19] - rel_grant.data <= io.out.grant.bits.data @[Definitions.scala 869:14] - io.in.grant.valid <= io.out.grant.valid @[Tilelink.scala 143:21] - node T_1751 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant) @[Tilelink.scala 144:26] - io.in.grant.bits <- T_1751 @[Tilelink.scala 144:20] - io.out.grant.ready <= io.in.grant.ready @[Tilelink.scala 145:22] - io.in.probe.valid <= UInt<1>("h00") @[Tilelink.scala 147:21] - io.in.finish.ready <= UInt<1>("h00") @[Tilelink.scala 148:22] - - module ClientTileLinkEnqueuer : + node T_1359 = and(UInt<1>("h1"), io.in.acquire.bits.is_builtin_type) + wire T_1366 : UInt<3>[1] + T_1366 is invalid + T_1366[0] <= UInt<3>("h3") + node T_1368 = eq(io.in.acquire.bits.a_type, T_1366[0]) + node T_1369 = and(T_1359, T_1368) + node T_1371 = eq(T_1369, UInt<1>("h0")) + node T_1373 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h0")) + node acq_roq_enq = or(T_1371, T_1373) + node T_1375 = eq(io.in.release.bits.r_type, UInt<3>("h0")) + node T_1376 = eq(io.in.release.bits.r_type, UInt<3>("h1")) + node T_1377 = eq(io.in.release.bits.r_type, UInt<3>("h2")) + node T_1378 = or(T_1375, T_1376) + node T_1379 = or(T_1378, T_1377) + node T_1380 = and(UInt<1>("h1"), T_1379) + node T_1382 = eq(T_1380, UInt<1>("h0")) + node T_1384 = eq(io.in.release.bits.addr_beat, UInt<1>("h0")) + node rel_roq_enq = or(T_1382, T_1384) + node T_1386 = eq(acq_roq_enq, UInt<1>("h0")) + node acq_roq_ready = or(T_1386, acqRoq.io.enq.ready) + node T_1388 = eq(rel_roq_enq, UInt<1>("h0")) + node rel_roq_ready = or(T_1388, relRoq.io.enq.ready) + node T_1389 = and(io.in.acquire.valid, acqArb.io.in[0].ready) + node T_1390 = and(T_1389, acq_roq_enq) + acqRoq.io.enq.valid <= T_1390 + acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type + acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id + node T_1391 = and(io.in.acquire.valid, acq_roq_ready) + acqArb.io.in[0].valid <= T_1391 + node T_1394 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h1")) + wire T_1423 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_1423 is invalid + T_1423.is_builtin_type <= UInt<1>("h1") + T_1423.a_type <= T_1394 + T_1423.client_xact_id <= io.in.acquire.bits.client_xact_id + T_1423.addr_block <= io.in.acquire.bits.addr_block + T_1423.addr_beat <= io.in.acquire.bits.addr_beat + T_1423.data <= io.in.acquire.bits.data + T_1423.union <= io.in.acquire.bits.union + acqArb.io.in[0].bits <- T_1423 + node T_1451 = and(acq_roq_ready, acqArb.io.in[0].ready) + io.in.acquire.ready <= T_1451 + node T_1452 = and(io.in.release.valid, acqArb.io.in[1].ready) + node T_1453 = and(T_1452, rel_roq_enq) + relRoq.io.enq.valid <= T_1453 + relRoq.io.enq.bits.data <= io.in.release.bits.voluntary + relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id + node T_1454 = and(io.in.release.valid, rel_roq_ready) + acqArb.io.in[1].valid <= T_1454 + node T_1478 = asUInt(asSInt(UInt<8>("hff"))) + node T_1504 = or(UInt<3>("h0"), UInt<1>("h0")) + node T_1505 = bits(T_1504, 2, 0) + node T_1507 = or(UInt<2>("h0"), UInt<1>("h0")) + node T_1508 = bits(T_1507, 1, 0) + node T_1510 = or(UInt<5>("h0"), UInt<1>("h0")) + node T_1511 = bits(T_1510, 4, 0) + node T_1513 = or(UInt<8>("h0"), T_1478) + node T_1514 = bits(T_1513, 7, 0) + node T_1517 = cat(T_1511, UInt<1>("h1")) + node T_1518 = cat(T_1505, T_1508) + node T_1519 = cat(T_1518, T_1517) + node T_1521 = cat(T_1508, T_1511) + node T_1522 = cat(T_1521, UInt<1>("h1")) + node T_1524 = cat(T_1514, UInt<1>("h1")) + node T_1526 = cat(T_1514, UInt<1>("h1")) + node T_1528 = cat(T_1511, UInt<1>("h1")) + node T_1529 = cat(T_1505, T_1508) + node T_1530 = cat(T_1529, T_1528) + node T_1532 = cat(UInt<5>("h0"), UInt<1>("h1")) + node T_1534 = cat(UInt<5>("h1"), UInt<1>("h1")) + node T_1535 = eq(UInt<3>("h6"), UInt<3>("h3")) + node T_1536 = mux(T_1535, T_1534, UInt<1>("h0")) + node T_1537 = eq(UInt<3>("h5"), UInt<3>("h3")) + node T_1538 = mux(T_1537, T_1532, T_1536) + node T_1539 = eq(UInt<3>("h4"), UInt<3>("h3")) + node T_1540 = mux(T_1539, T_1530, T_1538) + node T_1541 = eq(UInt<3>("h3"), UInt<3>("h3")) + node T_1542 = mux(T_1541, T_1526, T_1540) + node T_1543 = eq(UInt<3>("h2"), UInt<3>("h3")) + node T_1544 = mux(T_1543, T_1524, T_1542) + node T_1545 = eq(UInt<3>("h1"), UInt<3>("h3")) + node T_1546 = mux(T_1545, T_1522, T_1544) + node T_1547 = eq(UInt<3>("h0"), UInt<3>("h3")) + node T_1548 = mux(T_1547, T_1519, T_1546) + wire T_1577 : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} + T_1577 is invalid + T_1577.is_builtin_type <= UInt<1>("h1") + T_1577.a_type <= UInt<3>("h3") + T_1577.client_xact_id <= io.in.release.bits.client_xact_id + T_1577.addr_block <= io.in.release.bits.addr_block + T_1577.addr_beat <= io.in.release.bits.addr_beat + T_1577.data <= io.in.release.bits.data + T_1577.union <= T_1548 + acqArb.io.in[1].bits <- T_1577 + node T_1605 = and(rel_roq_ready, acqArb.io.in[1].ready) + io.in.release.ready <= T_1605 + io.out.acquire <- acqArb.io.out + node T_1606 = and(io.out.grant.ready, io.out.grant.valid) + wire T_1614 : UInt<3>[1] + T_1614 is invalid + T_1614[0] <= UInt<3>("h5") + node T_1616 = eq(io.out.grant.bits.g_type, T_1614[0]) + node T_1617 = eq(io.out.grant.bits.g_type, UInt<1>("h0")) + node T_1618 = mux(io.out.grant.bits.is_builtin_type, T_1616, T_1617) + node T_1619 = and(UInt<1>("h1"), T_1618) + node T_1621 = eq(T_1619, UInt<1>("h0")) + node T_1623 = eq(io.out.grant.bits.addr_beat, UInt<3>("h7")) + node T_1624 = or(T_1621, T_1623) + node grant_deq_roq = and(T_1606, T_1624) + node T_1625 = and(acqRoq.io.deq.matches, grant_deq_roq) + acqRoq.io.deq.valid <= T_1625 + acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id + node T_1627 = eq(acqRoq.io.deq.matches, UInt<1>("h0")) + node T_1628 = and(T_1627, grant_deq_roq) + relRoq.io.deq.valid <= T_1628 + relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id + node T_1630 = eq(grant_deq_roq, UInt<1>("h0")) + node T_1631 = or(T_1630, acqRoq.io.deq.matches) + node T_1632 = or(T_1631, relRoq.io.deq.matches) + node T_1633 = or(T_1632, reset) + node T_1635 = eq(T_1633, UInt<1>("h0")) + when T_1635 : + printf(clk, UInt<1>("h1"), "Assertion failed: TileLink Unwrapper: client_xact_id mismatch\n at Tilelink.scala:120 assert(!grant_deq_roq || acqRoq.io.deq.matches || relRoq.io.deq.matches,\n") + stop(clk, UInt<1>("h1"), 1) + node T_1636 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h0")) + wire acq_grant : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + acq_grant is invalid + acq_grant.is_builtin_type <= acqRoq.io.deq.data + acq_grant.g_type <= T_1636 + acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id + acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id + acq_grant.addr_beat <= io.out.grant.bits.addr_beat + acq_grant.data <= io.out.grant.bits.data + node T_1691 = eq(io.in.release.valid, UInt<1>("h0")) + node T_1692 = or(T_1691, io.in.release.bits.voluntary) + node T_1693 = or(T_1692, reset) + node T_1695 = eq(T_1693, UInt<1>("h0")) + when T_1695 : + printf(clk, UInt<1>("h1"), "Assertion failed: Unwrapper can only process voluntary releases.\n at Tilelink.scala:134 assert(!io.in.release.valid || io.in.release.bits.isVoluntary(), \"Unwrapper can only process voluntary releases.\")\n") + stop(clk, UInt<1>("h1"), 1) + wire rel_grant : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + rel_grant is invalid + rel_grant.is_builtin_type <= UInt<1>("h1") + rel_grant.g_type <= UInt<3>("h0") + rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id + rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id + rel_grant.addr_beat <= io.out.grant.bits.addr_beat + rel_grant.data <= io.out.grant.bits.data + io.in.grant.valid <= io.out.grant.valid + node T_1751 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant) + io.in.grant.bits <- T_1751 + io.out.grant.ready <= io.in.grant.ready + io.in.probe.valid <= UInt<1>("h0") + io.in.finish.ready <= UInt<1>("h0") + + module ClientTileLinkEnqueuer : input clk : Clock input reset : UInt<1> - output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} - + output io : { flip inner : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}, outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip probe : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, p_type : UInt<2>}}, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, manager_id : UInt<1>}}, finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { manager_xact_id : UInt<1>, manager_id : UInt<1>}}}} + io is invalid - io.outer.acquire <- io.inner.acquire @[Enqueuer.scala 41:20] - io.inner.probe <- io.outer.probe @[Enqueuer.scala 42:20] - io.outer.release <- io.inner.release @[Enqueuer.scala 43:20] - io.inner.grant <- io.outer.grant @[Enqueuer.scala 44:20] - io.outer.finish <- io.inner.finish @[Enqueuer.scala 45:20] - - module Queue_15 : + io.outer.acquire <- io.inner.acquire + io.inner.probe <- io.outer.probe + io.outer.release <- io.inner.release + io.inner.grant <- io.outer.grant + io.outer.finish <- io.inner.finish + + module Queue_15 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, count : UInt<1>} + io is invalid - cmem ram : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_266 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_266) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_267 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_266 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_266) + node full = and(ptr_match, maybe_full) + node T_267 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_267 - node T_268 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_268 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_268 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_269 = ram[UInt<1>("h00")], clk - T_269 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_299 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_299 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_301 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_301 @[Decoupled.scala 184:16] - node T_303 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_303 @[Decoupled.scala 185:16] - infer mport T_304 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_304 @[Decoupled.scala 186:15] - node T_332 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_332, 1) @[Decoupled.scala 201:32] - node T_333 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_334 = cat(T_333, ptr_diff) @[Cat.scala 20:58] - io.count <= T_334 @[Decoupled.scala 203:14] - - module Queue_16 : + when do_enq : + infer mport T_269 = ram[UInt<1>("h0")], clk + T_269 <- io.enq.bits + when do_deq : + skip + node T_299 = neq(do_enq, do_deq) + when T_299 : + maybe_full <= do_enq + node T_301 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_301 + node T_303 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_303 + infer mport T_304 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_304 + node T_332 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_332, 1) + node T_333 = and(maybe_full, ptr_match) + node T_334 = cat(T_333, ptr_diff) + io.count <= T_334 + + module Queue_16 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, count : UInt<1>} + io is invalid - cmem ram : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_257 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_257) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_258 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_257 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_257) + node full = and(ptr_match, maybe_full) + node T_258 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_258 - node T_259 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_259 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_259 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_260 = ram[UInt<1>("h00")], clk - T_260 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_289 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_289 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_291 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_291 @[Decoupled.scala 184:16] - node T_293 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_293 @[Decoupled.scala 185:16] - infer mport T_294 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_294 @[Decoupled.scala 186:15] - node T_321 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_321, 1) @[Decoupled.scala 201:32] - node T_322 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_323 = cat(T_322, ptr_diff) @[Cat.scala 20:58] - io.count <= T_323 @[Decoupled.scala 203:14] - - module ClientUncachedTileLinkEnqueuer : + when do_enq : + infer mport T_260 = ram[UInt<1>("h0")], clk + T_260 <- io.enq.bits + when do_deq : + skip + node T_289 = neq(do_enq, do_deq) + when T_289 : + maybe_full <= do_enq + node T_291 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_291 + node T_293 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_293 + infer mport T_294 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_294 + node T_321 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_321, 1) + node T_322 = and(maybe_full, ptr_match) + node T_323 = cat(T_322, ptr_diff) + io.count <= T_323 + + module ClientUncachedTileLinkEnqueuer : input clk : Clock input reset : UInt<1> - output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip inner : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, outer : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - inst Queue_15_1 of Queue_15 @[Decoupled.scala 228:19] + inst Queue_15_1 of Queue_15 Queue_15_1.io is invalid Queue_15_1.clk <= clk Queue_15_1.reset <= reset - Queue_15_1.io.enq.valid <= io.inner.acquire.valid @[Decoupled.scala 229:20] - Queue_15_1.io.enq.bits <- io.inner.acquire.bits @[Decoupled.scala 230:19] - io.inner.acquire.ready <= Queue_15_1.io.enq.ready @[Decoupled.scala 231:15] - io.outer.acquire <- Queue_15_1.io.deq @[Enqueuer.scala 65:20] - inst Queue_16_1 of Queue_16 @[Decoupled.scala 228:19] + Queue_15_1.io.enq.valid <= io.inner.acquire.valid + Queue_15_1.io.enq.bits <- io.inner.acquire.bits + io.inner.acquire.ready <= Queue_15_1.io.enq.ready + io.outer.acquire <- Queue_15_1.io.deq + inst Queue_16_1 of Queue_16 Queue_16_1.io is invalid Queue_16_1.clk <= clk Queue_16_1.reset <= reset - Queue_16_1.io.enq.valid <= io.outer.grant.valid @[Decoupled.scala 229:20] - Queue_16_1.io.enq.bits <- io.outer.grant.bits @[Decoupled.scala 230:19] - io.outer.grant.ready <= Queue_16_1.io.enq.ready @[Decoupled.scala 231:15] - io.inner.grant <- Queue_16_1.io.deq @[Enqueuer.scala 66:20] - - module LockingRRArbiter_10 : + Queue_16_1.io.enq.valid <= io.outer.grant.valid + Queue_16_1.io.enq.bits <- io.outer.grant.bits + io.outer.grant.ready <= Queue_16_1.io.enq.ready + io.inner.grant <- Queue_16_1.io.deq + + module LockingRRArbiter_10 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, chosen : UInt<1>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, chosen : UInt<1>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<1>("h00") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_518 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_520 : UInt, clk - node T_522 = neq(T_518, UInt<1>("h00")) @[Arbiter.scala 39:34] - wire T_530 : UInt<3>[1] @[Definitions.scala 853:34] - T_530 is invalid @[Definitions.scala 853:34] - T_530[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_532 = eq(io.out.bits.g_type, T_530[0]) @[Package.scala 7:47] - node T_533 = eq(io.out.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_534 = mux(io.out.bits.is_builtin_type, T_532, T_533) @[Definitions.scala 274:33] - node T_535 = and(UInt<1>("h01"), T_534) @[Definitions.scala 274:27] - node T_536 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_537 = and(T_536, T_535) @[Arbiter.scala 42:25] - when T_537 : @[Arbiter.scala 42:39] - T_520 <= io.chosen @[Arbiter.scala 43:15] - node T_539 = eq(T_518, UInt<3>("h07")) @[Counter.scala 20:24] - node T_541 = add(T_518, UInt<1>("h01")) @[Counter.scala 21:22] - node T_542 = tail(T_541, 1) @[Counter.scala 21:22] - T_518 <= T_542 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_522 : @[Arbiter.scala 47:19] - io.chosen <= T_520 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_544 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<1>, clk - when T_544 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node T_547 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_548 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_549 = or(T_548, T_547) @[Arbiter.scala 64:50] - node T_551 = eq(T_520, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_552 = mux(T_522, T_551, T_549) @[Arbiter.scala 49:22] - node T_553 = and(T_552, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_553 @[Arbiter.scala 49:16] - - module ClientUncachedTileLinkIORouter : + choice <= UInt<1>("h0") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_518 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_520 : UInt, clk with : + reset => (UInt<1>("h0"), T_520) + node T_522 = neq(T_518, UInt<1>("h0")) + wire T_530 : UInt<3>[1] + T_530 is invalid + T_530[0] <= UInt<3>("h5") + node T_532 = eq(io.out.bits.g_type, T_530[0]) + node T_533 = eq(io.out.bits.g_type, UInt<1>("h0")) + node T_534 = mux(io.out.bits.is_builtin_type, T_532, T_533) + node T_535 = and(UInt<1>("h1"), T_534) + node T_536 = and(io.out.ready, io.out.valid) + node T_537 = and(T_536, T_535) + when T_537 : + T_520 <= io.chosen + node T_539 = eq(T_518, UInt<3>("h7")) + node T_541 = add(T_518, UInt<1>("h1")) + node T_542 = tail(T_541, 1) + T_518 <= T_542 + when T_522 : + io.chosen <= T_520 + node T_544 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<1>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_544 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node T_547 = eq(validMask_0, UInt<1>("h0")) + node T_548 = and(UInt<1>("h1"), grantMask_0) + node T_549 = or(T_548, T_547) + node T_551 = eq(T_520, UInt<1>("h0")) + node T_552 = mux(T_522, T_551, T_549) + node T_553 = and(T_552, io.out.ready) + io.in[0].ready <= T_553 + + module ClientUncachedTileLinkIORouter : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} + io is invalid - wire T_1246 : UInt<3>[2] @[Definitions.scala 357:30] - T_1246 is invalid @[Definitions.scala 357:30] - T_1246[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_1246[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_1248 = eq(io.in.acquire.bits.a_type, T_1246[0]) @[Package.scala 7:47] - node T_1249 = eq(io.in.acquire.bits.a_type, T_1246[1]) @[Package.scala 7:47] - node T_1250 = or(T_1248, T_1249) @[Package.scala 7:62] - node T_1251 = and(io.in.acquire.bits.is_builtin_type, T_1250) @[Definitions.scala 300:27] - node T_1252 = bits(io.in.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_1254 = mux(T_1251, T_1252, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_1255 = cat(io.in.acquire.bits.addr_block, io.in.acquire.bits.addr_beat) @[Cat.scala 20:58] - node T_1256 = cat(T_1255, T_1254) @[Cat.scala 20:58] - node T_1258 = leq(UInt<1>("h00"), T_1256) @[addrmap.scala 26:46] - node T_1260 = lt(T_1256, UInt<13>("h01000")) @[addrmap.scala 26:56] - node T_1261 = and(T_1258, T_1260) @[addrmap.scala 26:51] - node T_1263 = leq(UInt<13>("h01000"), T_1256) @[addrmap.scala 26:46] - node T_1265 = lt(T_1256, UInt<14>("h02000")) @[addrmap.scala 26:56] - node T_1266 = and(T_1263, T_1265) @[addrmap.scala 26:51] - node T_1268 = leq(UInt<31>("h040000000"), T_1256) @[addrmap.scala 26:46] - node T_1270 = lt(T_1256, UInt<31>("h044000000")) @[addrmap.scala 26:56] - node T_1271 = and(T_1268, T_1270) @[addrmap.scala 26:51] - node T_1273 = leq(UInt<31>("h044000000"), T_1256) @[addrmap.scala 26:46] - node T_1275 = lt(T_1256, UInt<31>("h048000000")) @[addrmap.scala 26:56] - node T_1276 = and(T_1273, T_1275) @[addrmap.scala 26:51] - node T_1277 = or(T_1261, T_1266) @[addrmap.scala 157:54] - node T_1278 = or(T_1277, T_1271) @[addrmap.scala 157:54] - node acq_route = or(T_1278, T_1276) @[addrmap.scala 157:54] - io.in.acquire.ready <= UInt<1>("h00") @[Interconnect.scala 206:23] - node T_1280 = bits(acq_route, 0, 0) @[Interconnect.scala 209:58] - node T_1281 = and(io.in.acquire.valid, T_1280) @[Interconnect.scala 209:46] - io.out[0].acquire.valid <= T_1281 @[Interconnect.scala 209:23] - io.out[0].acquire.bits <- io.in.acquire.bits @[Interconnect.scala 210:22] - node T_1282 = bits(acq_route, 0, 0) @[Interconnect.scala 211:20] - when T_1282 : @[Interconnect.scala 211:25] - io.in.acquire.ready <= io.out[0].acquire.ready @[Interconnect.scala 211:47] - skip @[Interconnect.scala 211:25] - inst gnt_arb of LockingRRArbiter_10 @[Interconnect.scala 214:23] + wire T_1246 : UInt<3>[2] + T_1246 is invalid + T_1246[0] <= UInt<3>("h0") + T_1246[1] <= UInt<3>("h4") + node T_1248 = eq(io.in.acquire.bits.a_type, T_1246[0]) + node T_1249 = eq(io.in.acquire.bits.a_type, T_1246[1]) + node T_1250 = or(T_1248, T_1249) + node T_1251 = and(io.in.acquire.bits.is_builtin_type, T_1250) + node T_1252 = bits(io.in.acquire.bits.union, 10, 8) + node T_1254 = mux(T_1251, T_1252, UInt<3>("h0")) + node T_1255 = cat(io.in.acquire.bits.addr_block, io.in.acquire.bits.addr_beat) + node T_1256 = cat(T_1255, T_1254) + node T_1258 = leq(UInt<1>("h0"), T_1256) + node T_1260 = lt(T_1256, UInt<13>("h1000")) + node T_1261 = and(T_1258, T_1260) + node T_1263 = leq(UInt<13>("h1000"), T_1256) + node T_1265 = lt(T_1256, UInt<14>("h2000")) + node T_1266 = and(T_1263, T_1265) + node T_1268 = leq(UInt<31>("h40000000"), T_1256) + node T_1270 = lt(T_1256, UInt<31>("h44000000")) + node T_1271 = and(T_1268, T_1270) + node T_1273 = leq(UInt<31>("h44000000"), T_1256) + node T_1275 = lt(T_1256, UInt<31>("h48000000")) + node T_1276 = and(T_1273, T_1275) + node T_1277 = or(T_1261, T_1266) + node T_1278 = or(T_1277, T_1271) + node acq_route = or(T_1278, T_1276) + io.in.acquire.ready <= UInt<1>("h0") + node T_1280 = bits(acq_route, 0, 0) + node T_1281 = and(io.in.acquire.valid, T_1280) + io.out[0].acquire.valid <= T_1281 + io.out[0].acquire.bits <- io.in.acquire.bits + node T_1282 = bits(acq_route, 0, 0) + when T_1282 : + io.in.acquire.ready <= io.out[0].acquire.ready + inst gnt_arb of LockingRRArbiter_10 gnt_arb.io is invalid gnt_arb.clk <= clk gnt_arb.reset <= reset - gnt_arb.io.in[0] <- io.out[0].grant @[Interconnect.scala 216:17] - io.in.grant <- gnt_arb.io.out @[Interconnect.scala 217:15] - node T_1306 = eq(io.in.acquire.valid, UInt<1>("h00")) @[Interconnect.scala 219:10] - node T_1308 = neq(acq_route, UInt<1>("h00")) @[Interconnect.scala 219:44] - node T_1309 = or(T_1306, T_1308) @[Interconnect.scala 219:31] - node T_1310 = or(T_1309, reset) @[Interconnect.scala 219:9] - node T_1312 = eq(T_1310, UInt<1>("h00")) @[Interconnect.scala 219:9] - when T_1312 : @[Interconnect.scala 219:9] - printf(clk, UInt<1>(1), "Assertion failed: No valid route\n at Interconnect.scala:219 assert(!io.in.acquire.valid || acq_route.orR, \"No valid route\")\n") @[Interconnect.scala 219:9] - stop(clk, UInt<1>(1), 1) @[Interconnect.scala 219:9] - skip @[Interconnect.scala 219:9] - - module ClientUncachedTileLinkIOCrossbar : + gnt_arb.io.in[0] <- io.out[0].grant + io.in.grant <- gnt_arb.io.out + node T_1306 = eq(io.in.acquire.valid, UInt<1>("h0")) + node T_1308 = neq(acq_route, UInt<1>("h0")) + node T_1309 = or(T_1306, T_1308) + node T_1310 = or(T_1309, reset) + node T_1312 = eq(T_1310, UInt<1>("h0")) + when T_1312 : + printf(clk, UInt<1>("h1"), "Assertion failed: No valid route\n at Interconnect.scala:219 assert(!io.in.acquire.valid || acq_route.orR, \"No valid route\")\n") + stop(clk, UInt<1>("h1"), 1) + + module ClientUncachedTileLinkIOCrossbar : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]} + io is invalid - inst ClientUncachedTileLinkIORouter_1 of ClientUncachedTileLinkIORouter @[Interconnect.scala 235:24] + inst ClientUncachedTileLinkIORouter_1 of ClientUncachedTileLinkIORouter ClientUncachedTileLinkIORouter_1.io is invalid ClientUncachedTileLinkIORouter_1.clk <= clk ClientUncachedTileLinkIORouter_1.reset <= reset - ClientUncachedTileLinkIORouter_1.io.in <- io.in[0] @[Interconnect.scala 236:18] - io.out <= ClientUncachedTileLinkIORouter_1.io.out @[Interconnect.scala 237:12] - - module LockingRRArbiter_11 : + ClientUncachedTileLinkIORouter_1.io.in <- io.in[0] + io.out <= ClientUncachedTileLinkIORouter_1.io.out + + module LockingRRArbiter_11 : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, chosen : UInt<2>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}, chosen : UInt<2>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<2>("h03") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_794 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_796 : UInt, clk - node T_798 = neq(T_794, UInt<1>("h00")) @[Arbiter.scala 39:34] - wire T_806 : UInt<3>[1] @[Definitions.scala 853:34] - T_806 is invalid @[Definitions.scala 853:34] - T_806[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_808 = eq(io.out.bits.g_type, T_806[0]) @[Package.scala 7:47] - node T_809 = eq(io.out.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_810 = mux(io.out.bits.is_builtin_type, T_808, T_809) @[Definitions.scala 274:33] - node T_811 = and(UInt<1>("h01"), T_810) @[Definitions.scala 274:27] - node T_812 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_813 = and(T_812, T_811) @[Arbiter.scala 42:25] - when T_813 : @[Arbiter.scala 42:39] - T_796 <= io.chosen @[Arbiter.scala 43:15] - node T_815 = eq(T_794, UInt<3>("h07")) @[Counter.scala 20:24] - node T_817 = add(T_794, UInt<1>("h01")) @[Counter.scala 21:22] - node T_818 = tail(T_817, 1) @[Counter.scala 21:22] - T_794 <= T_818 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_798 : @[Arbiter.scala 47:19] - io.chosen <= T_796 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_820 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - reg lastGrant : UInt<2>, clk - when T_820 : @[Reg.scala 29:19] - lastGrant <= io.chosen @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node grantMask_0 = gt(UInt<1>("h00"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_1 = gt(UInt<1>("h01"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_2 = gt(UInt<2>("h02"), lastGrant) @[Arbiter.scala 59:48] - node grantMask_3 = gt(UInt<2>("h03"), lastGrant) @[Arbiter.scala 59:48] - node validMask_0 = and(io.in[0].valid, grantMask_0) @[Arbiter.scala 60:75] - node validMask_1 = and(io.in[1].valid, grantMask_1) @[Arbiter.scala 60:75] - node validMask_2 = and(io.in[2].valid, grantMask_2) @[Arbiter.scala 60:75] - node validMask_3 = and(io.in[3].valid, grantMask_3) @[Arbiter.scala 60:75] - node T_825 = or(validMask_0, validMask_1) @[Arbiter.scala 23:72] - node T_826 = or(T_825, validMask_2) @[Arbiter.scala 23:72] - node T_827 = or(T_826, validMask_3) @[Arbiter.scala 23:72] - node T_828 = or(T_827, io.in[0].valid) @[Arbiter.scala 23:72] - node T_829 = or(T_828, io.in[1].valid) @[Arbiter.scala 23:72] - node T_830 = or(T_829, io.in[2].valid) @[Arbiter.scala 23:72] - node T_832 = eq(validMask_0, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_834 = eq(T_825, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_836 = eq(T_826, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_838 = eq(T_827, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_840 = eq(T_828, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_842 = eq(T_829, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_844 = eq(T_830, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_845 = and(UInt<1>("h01"), grantMask_0) @[Arbiter.scala 64:34] - node T_846 = or(T_845, T_838) @[Arbiter.scala 64:50] - node T_847 = and(T_832, grantMask_1) @[Arbiter.scala 64:34] - node T_848 = or(T_847, T_840) @[Arbiter.scala 64:50] - node T_849 = and(T_834, grantMask_2) @[Arbiter.scala 64:34] - node T_850 = or(T_849, T_842) @[Arbiter.scala 64:50] - node T_851 = and(T_836, grantMask_3) @[Arbiter.scala 64:34] - node T_852 = or(T_851, T_844) @[Arbiter.scala 64:50] - node T_854 = eq(T_796, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_855 = mux(T_798, T_854, T_846) @[Arbiter.scala 49:22] - node T_856 = and(T_855, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_856 @[Arbiter.scala 49:16] - node T_858 = eq(T_796, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_859 = mux(T_798, T_858, T_848) @[Arbiter.scala 49:22] - node T_860 = and(T_859, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_860 @[Arbiter.scala 49:16] - node T_862 = eq(T_796, UInt<2>("h02")) @[Arbiter.scala 49:39] - node T_863 = mux(T_798, T_862, T_850) @[Arbiter.scala 49:22] - node T_864 = and(T_863, io.out.ready) @[Arbiter.scala 49:55] - io.in[2].ready <= T_864 @[Arbiter.scala 49:16] - node T_866 = eq(T_796, UInt<2>("h03")) @[Arbiter.scala 49:39] - node T_867 = mux(T_798, T_866, T_852) @[Arbiter.scala 49:22] - node T_868 = and(T_867, io.out.ready) @[Arbiter.scala 49:55] - io.in[3].ready <= T_868 @[Arbiter.scala 49:16] - when io.in[2].valid : @[Arbiter.scala 69:27] - choice <= UInt<2>("h02") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[1].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h01") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when io.in[0].valid : @[Arbiter.scala 69:27] - choice <= UInt<1>("h00") @[Arbiter.scala 69:36] - skip @[Arbiter.scala 69:27] - when validMask_3 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h03") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_2 : @[Arbiter.scala 71:25] - choice <= UInt<2>("h02") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - when validMask_1 : @[Arbiter.scala 71:25] - choice <= UInt<1>("h01") @[Arbiter.scala 71:34] - skip @[Arbiter.scala 71:25] - - module ClientUncachedTileLinkIORouter_1 : + choice <= UInt<2>("h3") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_794 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_796 : UInt, clk with : + reset => (UInt<1>("h0"), T_796) + node T_798 = neq(T_794, UInt<1>("h0")) + wire T_806 : UInt<3>[1] + T_806 is invalid + T_806[0] <= UInt<3>("h5") + node T_808 = eq(io.out.bits.g_type, T_806[0]) + node T_809 = eq(io.out.bits.g_type, UInt<1>("h0")) + node T_810 = mux(io.out.bits.is_builtin_type, T_808, T_809) + node T_811 = and(UInt<1>("h1"), T_810) + node T_812 = and(io.out.ready, io.out.valid) + node T_813 = and(T_812, T_811) + when T_813 : + T_796 <= io.chosen + node T_815 = eq(T_794, UInt<3>("h7")) + node T_817 = add(T_794, UInt<1>("h1")) + node T_818 = tail(T_817, 1) + T_794 <= T_818 + when T_798 : + io.chosen <= T_796 + node T_820 = and(io.out.ready, io.out.valid) + reg lastGrant : UInt<2>, clk with : + reset => (UInt<1>("h0"), lastGrant) + when T_820 : + lastGrant <= io.chosen + node grantMask_0 = gt(UInt<1>("h0"), lastGrant) + node grantMask_1 = gt(UInt<1>("h1"), lastGrant) + node grantMask_2 = gt(UInt<2>("h2"), lastGrant) + node grantMask_3 = gt(UInt<2>("h3"), lastGrant) + node validMask_0 = and(io.in[0].valid, grantMask_0) + node validMask_1 = and(io.in[1].valid, grantMask_1) + node validMask_2 = and(io.in[2].valid, grantMask_2) + node validMask_3 = and(io.in[3].valid, grantMask_3) + node T_825 = or(validMask_0, validMask_1) + node T_826 = or(T_825, validMask_2) + node T_827 = or(T_826, validMask_3) + node T_828 = or(T_827, io.in[0].valid) + node T_829 = or(T_828, io.in[1].valid) + node T_830 = or(T_829, io.in[2].valid) + node T_832 = eq(validMask_0, UInt<1>("h0")) + node T_834 = eq(T_825, UInt<1>("h0")) + node T_836 = eq(T_826, UInt<1>("h0")) + node T_838 = eq(T_827, UInt<1>("h0")) + node T_840 = eq(T_828, UInt<1>("h0")) + node T_842 = eq(T_829, UInt<1>("h0")) + node T_844 = eq(T_830, UInt<1>("h0")) + node T_845 = and(UInt<1>("h1"), grantMask_0) + node T_846 = or(T_845, T_838) + node T_847 = and(T_832, grantMask_1) + node T_848 = or(T_847, T_840) + node T_849 = and(T_834, grantMask_2) + node T_850 = or(T_849, T_842) + node T_851 = and(T_836, grantMask_3) + node T_852 = or(T_851, T_844) + node T_854 = eq(T_796, UInt<1>("h0")) + node T_855 = mux(T_798, T_854, T_846) + node T_856 = and(T_855, io.out.ready) + io.in[0].ready <= T_856 + node T_858 = eq(T_796, UInt<1>("h1")) + node T_859 = mux(T_798, T_858, T_848) + node T_860 = and(T_859, io.out.ready) + io.in[1].ready <= T_860 + node T_862 = eq(T_796, UInt<2>("h2")) + node T_863 = mux(T_798, T_862, T_850) + node T_864 = and(T_863, io.out.ready) + io.in[2].ready <= T_864 + node T_866 = eq(T_796, UInt<2>("h3")) + node T_867 = mux(T_798, T_866, T_852) + node T_868 = and(T_867, io.out.ready) + io.in[3].ready <= T_868 + when io.in[2].valid : + choice <= UInt<2>("h2") + when io.in[1].valid : + choice <= UInt<1>("h1") + when io.in[0].valid : + choice <= UInt<1>("h0") + when validMask_3 : + choice <= UInt<2>("h3") + when validMask_2 : + choice <= UInt<2>("h2") + when validMask_1 : + choice <= UInt<1>("h1") + + module ClientUncachedTileLinkIORouter_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} + io is invalid - wire T_1855 : UInt<3>[2] @[Definitions.scala 357:30] - T_1855 is invalid @[Definitions.scala 357:30] - T_1855[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_1855[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_1857 = eq(io.in.acquire.bits.a_type, T_1855[0]) @[Package.scala 7:47] - node T_1858 = eq(io.in.acquire.bits.a_type, T_1855[1]) @[Package.scala 7:47] - node T_1859 = or(T_1857, T_1858) @[Package.scala 7:62] - node T_1860 = and(io.in.acquire.bits.is_builtin_type, T_1859) @[Definitions.scala 300:27] - node T_1861 = bits(io.in.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_1863 = mux(T_1860, T_1861, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_1864 = cat(io.in.acquire.bits.addr_block, io.in.acquire.bits.addr_beat) @[Cat.scala 20:58] - node T_1865 = cat(T_1864, T_1863) @[Cat.scala 20:58] - node T_1867 = leq(UInt<1>("h00"), T_1865) @[addrmap.scala 26:46] - node T_1869 = lt(T_1865, UInt<13>("h01000")) @[addrmap.scala 26:56] - node T_1870 = and(T_1867, T_1869) @[addrmap.scala 26:51] - node T_1872 = leq(UInt<13>("h01000"), T_1865) @[addrmap.scala 26:46] - node T_1874 = lt(T_1865, UInt<14>("h02000")) @[addrmap.scala 26:56] - node T_1875 = and(T_1872, T_1874) @[addrmap.scala 26:51] - node T_1877 = leq(UInt<31>("h040000000"), T_1865) @[addrmap.scala 26:46] - node T_1879 = lt(T_1865, UInt<31>("h044000000")) @[addrmap.scala 26:56] - node T_1880 = and(T_1877, T_1879) @[addrmap.scala 26:51] - node T_1882 = leq(UInt<31>("h044000000"), T_1865) @[addrmap.scala 26:46] - node T_1884 = lt(T_1865, UInt<31>("h048000000")) @[addrmap.scala 26:56] - node T_1885 = and(T_1882, T_1884) @[addrmap.scala 26:51] - node T_1886 = cat(T_1875, T_1870) @[Cat.scala 20:58] - node T_1887 = cat(T_1885, T_1880) @[Cat.scala 20:58] - node acq_route = cat(T_1887, T_1886) @[Cat.scala 20:58] - io.in.acquire.ready <= UInt<1>("h00") @[Interconnect.scala 206:23] - node T_1889 = bits(acq_route, 0, 0) @[Interconnect.scala 209:58] - node T_1890 = and(io.in.acquire.valid, T_1889) @[Interconnect.scala 209:46] - io.out[0].acquire.valid <= T_1890 @[Interconnect.scala 209:23] - io.out[0].acquire.bits <- io.in.acquire.bits @[Interconnect.scala 210:22] - node T_1891 = bits(acq_route, 0, 0) @[Interconnect.scala 211:20] - when T_1891 : @[Interconnect.scala 211:25] - io.in.acquire.ready <= io.out[0].acquire.ready @[Interconnect.scala 211:47] - skip @[Interconnect.scala 211:25] - node T_1892 = bits(acq_route, 1, 1) @[Interconnect.scala 209:58] - node T_1893 = and(io.in.acquire.valid, T_1892) @[Interconnect.scala 209:46] - io.out[1].acquire.valid <= T_1893 @[Interconnect.scala 209:23] - io.out[1].acquire.bits <- io.in.acquire.bits @[Interconnect.scala 210:22] - node T_1894 = bits(acq_route, 1, 1) @[Interconnect.scala 211:20] - when T_1894 : @[Interconnect.scala 211:25] - io.in.acquire.ready <= io.out[1].acquire.ready @[Interconnect.scala 211:47] - skip @[Interconnect.scala 211:25] - node T_1895 = bits(acq_route, 2, 2) @[Interconnect.scala 209:58] - node T_1896 = and(io.in.acquire.valid, T_1895) @[Interconnect.scala 209:46] - io.out[2].acquire.valid <= T_1896 @[Interconnect.scala 209:23] - io.out[2].acquire.bits <- io.in.acquire.bits @[Interconnect.scala 210:22] - node T_1897 = bits(acq_route, 2, 2) @[Interconnect.scala 211:20] - when T_1897 : @[Interconnect.scala 211:25] - io.in.acquire.ready <= io.out[2].acquire.ready @[Interconnect.scala 211:47] - skip @[Interconnect.scala 211:25] - node T_1898 = bits(acq_route, 3, 3) @[Interconnect.scala 209:58] - node T_1899 = and(io.in.acquire.valid, T_1898) @[Interconnect.scala 209:46] - io.out[3].acquire.valid <= T_1899 @[Interconnect.scala 209:23] - io.out[3].acquire.bits <- io.in.acquire.bits @[Interconnect.scala 210:22] - node T_1900 = bits(acq_route, 3, 3) @[Interconnect.scala 211:20] - when T_1900 : @[Interconnect.scala 211:25] - io.in.acquire.ready <= io.out[3].acquire.ready @[Interconnect.scala 211:47] - skip @[Interconnect.scala 211:25] - inst gnt_arb of LockingRRArbiter_11 @[Interconnect.scala 214:23] + wire T_1855 : UInt<3>[2] + T_1855 is invalid + T_1855[0] <= UInt<3>("h0") + T_1855[1] <= UInt<3>("h4") + node T_1857 = eq(io.in.acquire.bits.a_type, T_1855[0]) + node T_1858 = eq(io.in.acquire.bits.a_type, T_1855[1]) + node T_1859 = or(T_1857, T_1858) + node T_1860 = and(io.in.acquire.bits.is_builtin_type, T_1859) + node T_1861 = bits(io.in.acquire.bits.union, 10, 8) + node T_1863 = mux(T_1860, T_1861, UInt<3>("h0")) + node T_1864 = cat(io.in.acquire.bits.addr_block, io.in.acquire.bits.addr_beat) + node T_1865 = cat(T_1864, T_1863) + node T_1867 = leq(UInt<1>("h0"), T_1865) + node T_1869 = lt(T_1865, UInt<13>("h1000")) + node T_1870 = and(T_1867, T_1869) + node T_1872 = leq(UInt<13>("h1000"), T_1865) + node T_1874 = lt(T_1865, UInt<14>("h2000")) + node T_1875 = and(T_1872, T_1874) + node T_1877 = leq(UInt<31>("h40000000"), T_1865) + node T_1879 = lt(T_1865, UInt<31>("h44000000")) + node T_1880 = and(T_1877, T_1879) + node T_1882 = leq(UInt<31>("h44000000"), T_1865) + node T_1884 = lt(T_1865, UInt<31>("h48000000")) + node T_1885 = and(T_1882, T_1884) + node T_1886 = cat(T_1875, T_1870) + node T_1887 = cat(T_1885, T_1880) + node acq_route = cat(T_1887, T_1886) + io.in.acquire.ready <= UInt<1>("h0") + node T_1889 = bits(acq_route, 0, 0) + node T_1890 = and(io.in.acquire.valid, T_1889) + io.out[0].acquire.valid <= T_1890 + io.out[0].acquire.bits <- io.in.acquire.bits + node T_1891 = bits(acq_route, 0, 0) + when T_1891 : + io.in.acquire.ready <= io.out[0].acquire.ready + node T_1892 = bits(acq_route, 1, 1) + node T_1893 = and(io.in.acquire.valid, T_1892) + io.out[1].acquire.valid <= T_1893 + io.out[1].acquire.bits <- io.in.acquire.bits + node T_1894 = bits(acq_route, 1, 1) + when T_1894 : + io.in.acquire.ready <= io.out[1].acquire.ready + node T_1895 = bits(acq_route, 2, 2) + node T_1896 = and(io.in.acquire.valid, T_1895) + io.out[2].acquire.valid <= T_1896 + io.out[2].acquire.bits <- io.in.acquire.bits + node T_1897 = bits(acq_route, 2, 2) + when T_1897 : + io.in.acquire.ready <= io.out[2].acquire.ready + node T_1898 = bits(acq_route, 3, 3) + node T_1899 = and(io.in.acquire.valid, T_1898) + io.out[3].acquire.valid <= T_1899 + io.out[3].acquire.bits <- io.in.acquire.bits + node T_1900 = bits(acq_route, 3, 3) + when T_1900 : + io.in.acquire.ready <= io.out[3].acquire.ready + inst gnt_arb of LockingRRArbiter_11 gnt_arb.io is invalid gnt_arb.clk <= clk gnt_arb.reset <= reset - gnt_arb.io.in[0] <- io.out[0].grant @[Interconnect.scala 216:17] - gnt_arb.io.in[1] <- io.out[1].grant @[Interconnect.scala 216:17] - gnt_arb.io.in[2] <- io.out[2].grant @[Interconnect.scala 216:17] - gnt_arb.io.in[3] <- io.out[3].grant @[Interconnect.scala 216:17] - io.in.grant <- gnt_arb.io.out @[Interconnect.scala 217:15] - node T_1924 = eq(io.in.acquire.valid, UInt<1>("h00")) @[Interconnect.scala 219:10] - node T_1926 = neq(acq_route, UInt<1>("h00")) @[Interconnect.scala 219:44] - node T_1927 = or(T_1924, T_1926) @[Interconnect.scala 219:31] - node T_1928 = or(T_1927, reset) @[Interconnect.scala 219:9] - node T_1930 = eq(T_1928, UInt<1>("h00")) @[Interconnect.scala 219:9] - when T_1930 : @[Interconnect.scala 219:9] - printf(clk, UInt<1>(1), "Assertion failed: No valid route\n at Interconnect.scala:219 assert(!io.in.acquire.valid || acq_route.orR, \"No valid route\")\n") @[Interconnect.scala 219:9] - stop(clk, UInt<1>(1), 1) @[Interconnect.scala 219:9] - skip @[Interconnect.scala 219:9] - - module ClientUncachedTileLinkIOCrossbar_1 : + gnt_arb.io.in[0] <- io.out[0].grant + gnt_arb.io.in[1] <- io.out[1].grant + gnt_arb.io.in[2] <- io.out[2].grant + gnt_arb.io.in[3] <- io.out[3].grant + io.in.grant <- gnt_arb.io.out + node T_1924 = eq(io.in.acquire.valid, UInt<1>("h0")) + node T_1926 = neq(acq_route, UInt<1>("h0")) + node T_1927 = or(T_1924, T_1926) + node T_1928 = or(T_1927, reset) + node T_1930 = eq(T_1928, UInt<1>("h0")) + when T_1930 : + printf(clk, UInt<1>("h1"), "Assertion failed: No valid route\n at Interconnect.scala:219 assert(!io.in.acquire.valid || acq_route.orR, \"No valid route\")\n") + stop(clk, UInt<1>("h1"), 1) + + module ClientUncachedTileLinkIOCrossbar_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} + io is invalid - inst ClientUncachedTileLinkIORouter_1_1 of ClientUncachedTileLinkIORouter_1 @[Interconnect.scala 235:24] + inst ClientUncachedTileLinkIORouter_1_1 of ClientUncachedTileLinkIORouter_1 ClientUncachedTileLinkIORouter_1_1.io is invalid ClientUncachedTileLinkIORouter_1_1.clk <= clk ClientUncachedTileLinkIORouter_1_1.reset <= reset - ClientUncachedTileLinkIORouter_1_1.io.in <- io.in[0] @[Interconnect.scala 236:18] - io.out <= ClientUncachedTileLinkIORouter_1_1.io.out @[Interconnect.scala 237:12] - - module TileLinkRecursiveInterconnect_1 : + ClientUncachedTileLinkIORouter_1_1.io.in <- io.in[0] + io.out <= ClientUncachedTileLinkIORouter_1_1.io.out + + module TileLinkRecursiveInterconnect_1 : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} + io is invalid - inst xbar of ClientUncachedTileLinkIOCrossbar_1 @[Interconnect.scala 269:20] + inst xbar of ClientUncachedTileLinkIOCrossbar_1 xbar.io is invalid xbar.clk <= clk xbar.reset <= reset - xbar.io.in <= io.in @[Interconnect.scala 270:14] - io.out[0] <- xbar.io.out[0] @[Interconnect.scala 272:10] - io.out[1] <- xbar.io.out[1] @[Interconnect.scala 272:10] - io.out[2] <- xbar.io.out[2] @[Interconnect.scala 272:10] - io.out[3] <- xbar.io.out[3] @[Interconnect.scala 272:10] - - module TileLinkRecursiveInterconnect : + xbar.io.in <= io.in + io.out[0] <- xbar.io.out[0] + io.out[1] <- xbar.io.out[1] + io.out[2] <- xbar.io.out[2] + io.out[3] <- xbar.io.out[3] + + module TileLinkRecursiveInterconnect : input clk : Clock input reset : UInt<1> - output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} - + output io : { flip in : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1], out : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[4]} + io is invalid - inst xbar of ClientUncachedTileLinkIOCrossbar @[Interconnect.scala 269:20] + inst xbar of ClientUncachedTileLinkIOCrossbar xbar.io is invalid xbar.clk <= clk xbar.reset <= reset - xbar.io.in <= io.in @[Interconnect.scala 270:14] - inst TileLinkRecursiveInterconnect_1_1 of TileLinkRecursiveInterconnect_1 @[Interconnect.scala 280:26] + xbar.io.in <= io.in + inst TileLinkRecursiveInterconnect_1_1 of TileLinkRecursiveInterconnect_1 TileLinkRecursiveInterconnect_1_1.io is invalid TileLinkRecursiveInterconnect_1_1.clk <= clk TileLinkRecursiveInterconnect_1_1.reset <= reset - TileLinkRecursiveInterconnect_1_1.io.in[0] <- xbar.io.out[0] @[Interconnect.scala 281:25] - io.out[0] <- TileLinkRecursiveInterconnect_1_1.io.out[0] @[Interconnect.scala 272:10] - io.out[1] <- TileLinkRecursiveInterconnect_1_1.io.out[1] @[Interconnect.scala 272:10] - io.out[2] <- TileLinkRecursiveInterconnect_1_1.io.out[2] @[Interconnect.scala 272:10] - io.out[3] <- TileLinkRecursiveInterconnect_1_1.io.out[3] @[Interconnect.scala 272:10] - - module Queue_17 : + TileLinkRecursiveInterconnect_1_1.io.in[0] <- xbar.io.out[0] + io.out[0] <- TileLinkRecursiveInterconnect_1_1.io.out[0] + io.out[1] <- TileLinkRecursiveInterconnect_1_1.io.out[1] + io.out[2] <- TileLinkRecursiveInterconnect_1_1.io.out[2] + io.out[3] <- TileLinkRecursiveInterconnect_1_1.io.out[3] + + module Queue_17 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, count : UInt<1>} + io is invalid - cmem ram : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_221 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_221) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_222 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_221 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_221) + node full = and(ptr_match, maybe_full) + node T_222 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_222 - node T_223 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_223 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_223 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_224 = ram[UInt<1>("h00")], clk - T_224 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_249 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_249 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_251 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_251 @[Decoupled.scala 184:16] - node T_253 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_253 @[Decoupled.scala 185:16] - infer mport T_254 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_254 @[Decoupled.scala 186:15] - node T_277 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_277, 1) @[Decoupled.scala 201:32] - node T_278 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_279 = cat(T_278, ptr_diff) @[Cat.scala 20:58] - io.count <= T_279 @[Decoupled.scala 203:14] - - module PLIC : + when do_enq : + infer mport T_224 = ram[UInt<1>("h0")], clk + T_224 <- io.enq.bits + when do_deq : + skip + node T_249 = neq(do_enq, do_deq) + when T_249 : + maybe_full <= do_enq + node T_251 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_251 + node T_253 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_253 + infer mport T_254 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_254 + node T_277 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_277, 1) + node T_278 = and(maybe_full, ptr_match) + node T_279 = cat(T_278, ptr_diff) + io.count <= T_279 + + module PLIC : input clk : Clock input reset : UInt<1> - output io : {flip devices : {valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}[2], harts : UInt<1>[2], flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - + output io : { flip devices : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}[2], harts : UInt<1>[2], flip tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} + io is invalid - wire T_477 : UInt<1>[3] @[Plic.scala 71:44] - T_477 is invalid @[Plic.scala 71:44] - T_477[0] <= UInt<1>("h01") @[Plic.scala 71:44] - T_477[1] <= UInt<1>("h01") @[Plic.scala 71:44] - T_477[2] <= UInt<1>("h01") @[Plic.scala 71:44] + wire T_477 : UInt<1>[3] + T_477 is invalid + T_477[0] <= UInt<1>("h1") + T_477[1] <= UInt<1>("h1") + T_477[2] <= UInt<1>("h1") wire priority : UInt<1>[3] priority is invalid priority <= T_477 - wire T_489 : UInt<1>[2] @[Plic.scala 74:40] - T_489 is invalid @[Plic.scala 74:40] - T_489[0] <= UInt<1>("h00") @[Plic.scala 74:40] - T_489[1] <= UInt<1>("h00") @[Plic.scala 74:40] + wire T_489 : UInt<1>[2] + T_489 is invalid + T_489[0] <= UInt<1>("h0") + T_489[1] <= UInt<1>("h0") wire threshold : UInt<1>[2] threshold is invalid threshold <= T_489 - wire T_502 : UInt<1>[3] @[Plic.scala 75:50] - T_502 is invalid @[Plic.scala 75:50] - T_502[0] <= UInt<1>("h00") @[Plic.scala 75:50] - T_502[1] <= UInt<1>("h00") @[Plic.scala 75:50] - T_502[2] <= UInt<1>("h00") @[Plic.scala 75:50] - reg pending : UInt<1>[3], clk with : (reset => (reset, T_502)) - reg enables : UInt<1>[3][2], clk - node T_545 = eq(pending[1], UInt<1>("h00")) @[Plic.scala 79:16] - io.devices[0].ready <= T_545 @[Plic.scala 79:13] - io.devices[0].complete <= UInt<1>("h00") @[Plic.scala 80:16] - when io.devices[0].valid : @[Plic.scala 81:20] - pending[1] <= UInt<1>("h01") @[Plic.scala 81:24] - skip @[Plic.scala 81:20] - node T_549 = eq(pending[2], UInt<1>("h00")) @[Plic.scala 79:16] - io.devices[1].ready <= T_549 @[Plic.scala 79:13] - io.devices[1].complete <= UInt<1>("h00") @[Plic.scala 80:16] - when io.devices[1].valid : @[Plic.scala 81:20] - pending[2] <= UInt<1>("h01") @[Plic.scala 81:24] - skip @[Plic.scala 81:20] - wire maxDevs : UInt<2>[2] @[Plic.scala 94:21] - maxDevs is invalid @[Plic.scala 94:21] - node T_559 = and(pending[1], enables[0][1]) @[Plic.scala 98:21] - node T_560 = cat(T_559, priority[1]) @[Cat.scala 20:58] - node T_561 = and(pending[2], enables[0][2]) @[Plic.scala 98:21] - node T_562 = cat(T_561, priority[2]) @[Cat.scala 20:58] - node T_564 = shl(UInt<1>("h01"), 1) @[Plic.scala 99:45] - node T_567 = geq(T_564, T_560) @[Plic.scala 89:29] - node T_568 = mux(T_567, T_564, T_560) @[Plic.scala 90:11] - node T_570 = add(UInt<1>("h01"), UInt<1>("h00")) @[Plic.scala 90:73] - node T_571 = tail(T_570, 1) @[Plic.scala 90:73] - node T_572 = mux(T_567, UInt<1>("h00"), T_571) @[Plic.scala 90:43] - node T_574 = geq(T_568, T_562) @[Plic.scala 89:29] - node T_575 = mux(T_574, T_568, T_562) @[Plic.scala 90:11] - node T_577 = add(UInt<2>("h02"), UInt<1>("h00")) @[Plic.scala 90:73] - node T_578 = tail(T_577, 1) @[Plic.scala 90:73] - node T_579 = mux(T_574, T_572, T_578) @[Plic.scala 90:43] - reg T_580 : UInt, clk + wire T_502 : UInt<1>[3] + T_502 is invalid + T_502[0] <= UInt<1>("h0") + T_502[1] <= UInt<1>("h0") + T_502[2] <= UInt<1>("h0") + reg pending : UInt<1>[3], clk with : + reset => (reset, T_502) + reg enables : UInt<1>[3][2], clk with : + reset => (UInt<1>("h0"), enables) + node T_545 = eq(pending[1], UInt<1>("h0")) + io.devices[0].ready <= T_545 + io.devices[0].complete <= UInt<1>("h0") + when io.devices[0].valid : + pending[1] <= UInt<1>("h1") + node T_549 = eq(pending[2], UInt<1>("h0")) + io.devices[1].ready <= T_549 + io.devices[1].complete <= UInt<1>("h0") + when io.devices[1].valid : + pending[2] <= UInt<1>("h1") + wire maxDevs : UInt<2>[2] + maxDevs is invalid + node T_559 = and(pending[1], enables[0][1]) + node T_560 = cat(T_559, priority[1]) + node T_561 = and(pending[2], enables[0][2]) + node T_562 = cat(T_561, priority[2]) + node T_564 = shl(UInt<1>("h1"), 1) + node T_567 = geq(T_564, T_560) + node T_568 = mux(T_567, T_564, T_560) + node T_570 = add(UInt<1>("h1"), UInt<1>("h0")) + node T_571 = tail(T_570, 1) + node T_572 = mux(T_567, UInt<1>("h0"), T_571) + node T_574 = geq(T_568, T_562) + node T_575 = mux(T_574, T_568, T_562) + node T_577 = add(UInt<2>("h2"), UInt<1>("h0")) + node T_578 = tail(T_577, 1) + node T_579 = mux(T_574, T_572, T_578) + reg T_580 : UInt, clk with : + reset => (UInt<1>("h0"), T_580) T_580 <= T_579 - maxDevs[0] <= T_580 @[Plic.scala 101:19] - reg T_581 : UInt, clk + maxDevs[0] <= T_580 + reg T_581 : UInt, clk with : + reset => (UInt<1>("h0"), T_581) T_581 <= T_575 - node T_583 = cat(UInt<1>("h01"), threshold[0]) @[Cat.scala 20:58] - node T_584 = gt(T_581, T_583) @[Plic.scala 102:42] - io.harts[0] <= T_584 @[Plic.scala 102:20] - node T_585 = and(pending[1], enables[1][1]) @[Plic.scala 98:21] - node T_586 = cat(T_585, priority[1]) @[Cat.scala 20:58] - node T_587 = and(pending[2], enables[1][2]) @[Plic.scala 98:21] - node T_588 = cat(T_587, priority[2]) @[Cat.scala 20:58] - node T_590 = shl(UInt<1>("h01"), 1) @[Plic.scala 99:45] - node T_593 = geq(T_590, T_586) @[Plic.scala 89:29] - node T_594 = mux(T_593, T_590, T_586) @[Plic.scala 90:11] - node T_596 = add(UInt<1>("h01"), UInt<1>("h00")) @[Plic.scala 90:73] - node T_597 = tail(T_596, 1) @[Plic.scala 90:73] - node T_598 = mux(T_593, UInt<1>("h00"), T_597) @[Plic.scala 90:43] - node T_600 = geq(T_594, T_588) @[Plic.scala 89:29] - node T_601 = mux(T_600, T_594, T_588) @[Plic.scala 90:11] - node T_603 = add(UInt<2>("h02"), UInt<1>("h00")) @[Plic.scala 90:73] - node T_604 = tail(T_603, 1) @[Plic.scala 90:73] - node T_605 = mux(T_600, T_598, T_604) @[Plic.scala 90:43] - reg T_606 : UInt, clk + node T_583 = cat(UInt<1>("h1"), threshold[0]) + node T_584 = gt(T_581, T_583) + io.harts[0] <= T_584 + node T_585 = and(pending[1], enables[1][1]) + node T_586 = cat(T_585, priority[1]) + node T_587 = and(pending[2], enables[1][2]) + node T_588 = cat(T_587, priority[2]) + node T_590 = shl(UInt<1>("h1"), 1) + node T_593 = geq(T_590, T_586) + node T_594 = mux(T_593, T_590, T_586) + node T_596 = add(UInt<1>("h1"), UInt<1>("h0")) + node T_597 = tail(T_596, 1) + node T_598 = mux(T_593, UInt<1>("h0"), T_597) + node T_600 = geq(T_594, T_588) + node T_601 = mux(T_600, T_594, T_588) + node T_603 = add(UInt<2>("h2"), UInt<1>("h0")) + node T_604 = tail(T_603, 1) + node T_605 = mux(T_600, T_598, T_604) + reg T_606 : UInt, clk with : + reset => (UInt<1>("h0"), T_606) T_606 <= T_605 - maxDevs[1] <= T_606 @[Plic.scala 101:19] - reg T_607 : UInt, clk + maxDevs[1] <= T_606 + reg T_607 : UInt, clk with : + reset => (UInt<1>("h0"), T_607) T_607 <= T_601 - node T_609 = cat(UInt<1>("h01"), threshold[1]) @[Cat.scala 20:58] - node T_610 = gt(T_607, T_609) @[Plic.scala 102:42] - io.harts[1] <= T_610 @[Plic.scala 102:20] - inst acq of Queue_17 @[Decoupled.scala 228:19] + node T_609 = cat(UInt<1>("h1"), threshold[1]) + node T_610 = gt(T_607, T_609) + io.harts[1] <= T_610 + inst acq of Queue_17 acq.io is invalid acq.clk <= clk acq.reset <= reset - acq.io.enq.valid <= io.tl.acquire.valid @[Decoupled.scala 229:20] - acq.io.enq.bits <- io.tl.acquire.bits @[Decoupled.scala 230:19] - io.tl.acquire.ready <= acq.io.enq.ready @[Decoupled.scala 231:15] - node T_634 = and(acq.io.deq.ready, acq.io.deq.valid) @[Decoupled.scala 21:42] - node T_636 = eq(acq.io.deq.bits.a_type, UInt<3>("h00")) @[Definitions.scala 212:64] - node T_637 = and(acq.io.deq.bits.is_builtin_type, T_636) @[Definitions.scala 212:54] - node read = and(T_634, T_637) @[Plic.scala 106:25] - node T_638 = and(acq.io.deq.ready, acq.io.deq.valid) @[Decoupled.scala 21:42] - node T_640 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_641 = and(acq.io.deq.bits.is_builtin_type, T_640) @[Definitions.scala 212:54] - node write = and(T_638, T_641) @[Plic.scala 107:26] - node T_642 = and(acq.io.deq.ready, acq.io.deq.valid) @[Decoupled.scala 21:42] - node T_644 = eq(T_642, UInt<1>("h00")) @[Plic.scala 108:10] - node T_645 = or(T_644, read) @[Plic.scala 108:22] - node T_646 = or(T_645, write) @[Plic.scala 108:30] - node T_647 = or(T_646, reset) @[Plic.scala 108:9] - node T_649 = eq(T_647, UInt<1>("h00")) @[Plic.scala 108:9] - when T_649 : @[Plic.scala 108:9] - printf(clk, UInt<1>(1), "Assertion failed: unsupported PLIC operation\n at Plic.scala:108 assert(!acq.fire() || read || write, \"unsupported PLIC operation\")\n") @[Plic.scala 108:9] - stop(clk, UInt<1>(1), 1) @[Plic.scala 108:9] - skip @[Plic.scala 108:9] - wire T_657 : UInt<3>[2] @[Definitions.scala 357:30] - T_657 is invalid @[Definitions.scala 357:30] - T_657[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_657[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_659 = eq(acq.io.deq.bits.a_type, T_657[0]) @[Package.scala 7:47] - node T_660 = eq(acq.io.deq.bits.a_type, T_657[1]) @[Package.scala 7:47] - node T_661 = or(T_659, T_660) @[Package.scala 7:62] - node T_662 = and(acq.io.deq.bits.is_builtin_type, T_661) @[Definitions.scala 300:27] - node T_663 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_665 = mux(T_662, T_663, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_666 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_667 = cat(T_666, T_665) @[Cat.scala 20:58] - node addr = bits(T_667, 25, 0) @[Plic.scala 109:34] - node T_669 = sub(addr, UInt<22>("h0200000")) @[Plic.scala 113:16] - node T_670 = tail(T_669, 1) @[Plic.scala 113:16] - node claimant = bits(T_670, 12, 12) @[Plic.scala 113:31] + acq.io.enq.valid <= io.tl.acquire.valid + acq.io.enq.bits <- io.tl.acquire.bits + io.tl.acquire.ready <= acq.io.enq.ready + node T_634 = and(acq.io.deq.ready, acq.io.deq.valid) + node T_636 = eq(acq.io.deq.bits.a_type, UInt<3>("h0")) + node T_637 = and(acq.io.deq.bits.is_builtin_type, T_636) + node read = and(T_634, T_637) + node T_638 = and(acq.io.deq.ready, acq.io.deq.valid) + node T_640 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_641 = and(acq.io.deq.bits.is_builtin_type, T_640) + node write = and(T_638, T_641) + node T_642 = and(acq.io.deq.ready, acq.io.deq.valid) + node T_644 = eq(T_642, UInt<1>("h0")) + node T_645 = or(T_644, read) + node T_646 = or(T_645, write) + node T_647 = or(T_646, reset) + node T_649 = eq(T_647, UInt<1>("h0")) + when T_649 : + printf(clk, UInt<1>("h1"), "Assertion failed: unsupported PLIC operation\n at Plic.scala:108 assert(!acq.fire() || read || write, \"unsupported PLIC operation\")\n") + stop(clk, UInt<1>("h1"), 1) + wire T_657 : UInt<3>[2] + T_657 is invalid + T_657[0] <= UInt<3>("h0") + T_657[1] <= UInt<3>("h4") + node T_659 = eq(acq.io.deq.bits.a_type, T_657[0]) + node T_660 = eq(acq.io.deq.bits.a_type, T_657[1]) + node T_661 = or(T_659, T_660) + node T_662 = and(acq.io.deq.bits.is_builtin_type, T_661) + node T_663 = bits(acq.io.deq.bits.union, 10, 8) + node T_665 = mux(T_662, T_663, UInt<3>("h0")) + node T_666 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_667 = cat(T_666, T_665) + node addr = bits(T_667, 25, 0) + node T_669 = sub(addr, UInt<22>("h200000")) + node T_670 = tail(T_669, 1) + node claimant = bits(T_670, 12, 12) wire hart : UInt hart is invalid hart <= claimant wire rdata : UInt<64> rdata is invalid - rdata <= UInt<64>("h00") - node T_676 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_677 = and(acq.io.deq.bits.is_builtin_type, T_676) @[Definitions.scala 212:54] - node T_694 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_696 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_697 = and(acq.io.deq.bits.is_builtin_type, T_696) @[Definitions.scala 212:54] - node T_699 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_700 = and(acq.io.deq.bits.is_builtin_type, T_699) @[Definitions.scala 212:54] - node T_701 = or(T_697, T_700) @[Definitions.scala 190:56] - node T_702 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_704 = mux(T_701, T_702, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_705 = mux(T_677, T_694, T_704) @[Definitions.scala 192:8] - node T_706 = bits(T_705, 0, 0) @[Bitwise.scala 13:51] - node T_707 = bits(T_705, 1, 1) @[Bitwise.scala 13:51] - node T_708 = bits(T_705, 2, 2) @[Bitwise.scala 13:51] - node T_709 = bits(T_705, 3, 3) @[Bitwise.scala 13:51] - node T_710 = bits(T_705, 4, 4) @[Bitwise.scala 13:51] - node T_711 = bits(T_705, 5, 5) @[Bitwise.scala 13:51] - node T_712 = bits(T_705, 6, 6) @[Bitwise.scala 13:51] - node T_713 = bits(T_705, 7, 7) @[Bitwise.scala 13:51] - node T_714 = bits(T_706, 0, 0) @[Bitwise.scala 33:15] - node T_717 = mux(T_714, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_718 = bits(T_707, 0, 0) @[Bitwise.scala 33:15] - node T_721 = mux(T_718, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_722 = bits(T_708, 0, 0) @[Bitwise.scala 33:15] - node T_725 = mux(T_722, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_726 = bits(T_709, 0, 0) @[Bitwise.scala 33:15] - node T_729 = mux(T_726, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_730 = bits(T_710, 0, 0) @[Bitwise.scala 33:15] - node T_733 = mux(T_730, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_734 = bits(T_711, 0, 0) @[Bitwise.scala 33:15] - node T_737 = mux(T_734, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_738 = bits(T_712, 0, 0) @[Bitwise.scala 33:15] - node T_741 = mux(T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_742 = bits(T_713, 0, 0) @[Bitwise.scala 33:15] - node T_745 = mux(T_742, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_746 = cat(T_721, T_717) @[Cat.scala 20:58] - node T_747 = cat(T_729, T_725) @[Cat.scala 20:58] - node T_748 = cat(T_747, T_746) @[Cat.scala 20:58] - node T_749 = cat(T_737, T_733) @[Cat.scala 20:58] - node T_750 = cat(T_745, T_741) @[Cat.scala 20:58] - node T_751 = cat(T_750, T_749) @[Cat.scala 20:58] - node T_752 = cat(T_751, T_748) @[Cat.scala 20:58] - node T_753 = and(acq.io.deq.bits.data, T_752) @[Plic.scala 118:37] - node T_755 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_756 = and(acq.io.deq.bits.is_builtin_type, T_755) @[Definitions.scala 212:54] - node T_773 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_775 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_776 = and(acq.io.deq.bits.is_builtin_type, T_775) @[Definitions.scala 212:54] - node T_778 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_779 = and(acq.io.deq.bits.is_builtin_type, T_778) @[Definitions.scala 212:54] - node T_780 = or(T_776, T_779) @[Definitions.scala 190:56] - node T_781 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_783 = mux(T_780, T_781, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_784 = mux(T_756, T_773, T_783) @[Definitions.scala 192:8] - node T_785 = bits(T_784, 0, 0) @[Bitwise.scala 13:51] - node T_786 = bits(T_784, 1, 1) @[Bitwise.scala 13:51] - node T_787 = bits(T_784, 2, 2) @[Bitwise.scala 13:51] - node T_788 = bits(T_784, 3, 3) @[Bitwise.scala 13:51] - node T_789 = bits(T_784, 4, 4) @[Bitwise.scala 13:51] - node T_790 = bits(T_784, 5, 5) @[Bitwise.scala 13:51] - node T_791 = bits(T_784, 6, 6) @[Bitwise.scala 13:51] - node T_792 = bits(T_784, 7, 7) @[Bitwise.scala 13:51] - node T_793 = bits(T_785, 0, 0) @[Bitwise.scala 33:15] - node T_796 = mux(T_793, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_797 = bits(T_786, 0, 0) @[Bitwise.scala 33:15] - node T_800 = mux(T_797, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_801 = bits(T_787, 0, 0) @[Bitwise.scala 33:15] - node T_804 = mux(T_801, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_805 = bits(T_788, 0, 0) @[Bitwise.scala 33:15] - node T_808 = mux(T_805, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_809 = bits(T_789, 0, 0) @[Bitwise.scala 33:15] - node T_812 = mux(T_809, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_813 = bits(T_790, 0, 0) @[Bitwise.scala 33:15] - node T_816 = mux(T_813, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_817 = bits(T_791, 0, 0) @[Bitwise.scala 33:15] - node T_820 = mux(T_817, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_821 = bits(T_792, 0, 0) @[Bitwise.scala 33:15] - node T_824 = mux(T_821, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_825 = cat(T_800, T_796) @[Cat.scala 20:58] - node T_826 = cat(T_808, T_804) @[Cat.scala 20:58] - node T_827 = cat(T_826, T_825) @[Cat.scala 20:58] - node T_828 = cat(T_816, T_812) @[Cat.scala 20:58] - node T_829 = cat(T_824, T_820) @[Cat.scala 20:58] - node T_830 = cat(T_829, T_828) @[Cat.scala 20:58] - node T_831 = cat(T_830, T_827) @[Cat.scala 20:58] - node T_832 = not(T_831) @[Plic.scala 118:73] - node T_833 = and(rdata, T_832) @[Plic.scala 118:71] - node masked_wdata = or(T_753, T_833) @[Plic.scala 118:62] - node T_835 = geq(addr, UInt<22>("h0200000")) @[Plic.scala 120:36] - when T_835 : @[Plic.scala 120:53] - node T_838 = cat(maxDevs[claimant], UInt<31>("h00")) @[Cat.scala 20:58] - node T_839 = cat(T_838, threshold[claimant]) @[Cat.scala 20:58] - node T_841 = mul(UInt<1>("h00"), UInt<7>("h040")) @[Plic.scala 124:110] - node T_842 = dshr(T_839, T_841) @[Plic.scala 124:101] - rdata <= T_842 @[Plic.scala 124:11] - node T_843 = bits(addr, 2, 2) @[Plic.scala 126:23] - node T_844 = and(read, T_843) @[Plic.scala 126:16] - when T_844 : @[Plic.scala 126:52] - pending[maxDevs[claimant]] <= UInt<1>("h00") @[Plic.scala 127:25] - skip @[Plic.scala 126:52] - when write : @[Plic.scala 129:18] - node T_847 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_848 = and(acq.io.deq.bits.is_builtin_type, T_847) @[Definitions.scala 212:54] - node T_865 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_867 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_868 = and(acq.io.deq.bits.is_builtin_type, T_867) @[Definitions.scala 212:54] - node T_870 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_871 = and(acq.io.deq.bits.is_builtin_type, T_870) @[Definitions.scala 212:54] - node T_872 = or(T_868, T_871) @[Definitions.scala 190:56] - node T_873 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_875 = mux(T_872, T_873, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_876 = mux(T_848, T_865, T_875) @[Definitions.scala 192:8] - node T_877 = bits(T_876, 4, 4) @[Plic.scala 130:64] - when T_877 : @[Plic.scala 130:120] - node T_878 = shr(acq.io.deq.bits.data, 32) @[Plic.scala 131:34] - node T_879 = bits(T_878, 1, 0) @[Plic.scala 131:74] - when enables[hart][T_879] : @[Plic.scala 132:31] - node T_881 = sub(T_879, UInt<1>("h01")) @[Plic.scala 132:47] - node T_882 = tail(T_881, 1) @[Plic.scala 132:47] - io.devices[T_882].complete <= UInt<1>("h01") @[Plic.scala 132:60] - skip @[Plic.scala 132:31] - skip @[Plic.scala 130:120] - node T_888 = eq(T_877, UInt<1>("h00")) @[Plic.scala 130:120] - when T_888 : @[Plic.scala 133:19] - skip @[Plic.scala 133:19] - skip @[Plic.scala 129:18] - skip @[Plic.scala 120:53] - node T_890 = geq(addr, UInt<14>("h02000")) @[Plic.scala 137:20] - node T_892 = eq(T_835, UInt<1>("h00")) @[Plic.scala 120:53] - node T_893 = and(T_892, T_890) @[Plic.scala 137:39] - when T_893 : @[Plic.scala 137:39] - node T_895 = sub(addr, UInt<14>("h02000")) @[Plic.scala 139:33] - node T_896 = tail(T_895, 1) @[Plic.scala 139:33] - node T_897 = bits(T_896, 7, 7) @[Plic.scala 139:50] - hart <= T_897 @[Plic.scala 141:10] - node T_900 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Plic.scala 146:18] - when T_900 : @[Plic.scala 146:36] - node T_901 = cat(enables[hart][2], enables[hart][1]) @[Cat.scala 20:58] - node T_902 = cat(T_901, enables[hart][0]) @[Cat.scala 20:58] - rdata <= T_902 @[Plic.scala 147:15] - when write : @[Plic.scala 149:24] - node T_906 = bits(masked_wdata, 0, 0) @[Plic.scala 149:66] - enables[T_897][0] <= T_906 @[Plic.scala 149:51] - skip @[Plic.scala 149:24] - when write : @[Plic.scala 149:24] - node T_910 = bits(masked_wdata, 1, 1) @[Plic.scala 149:66] - enables[T_897][1] <= T_910 @[Plic.scala 149:51] - skip @[Plic.scala 149:24] - when write : @[Plic.scala 149:24] - node T_914 = bits(masked_wdata, 2, 2) @[Plic.scala 149:66] - enables[T_897][2] <= T_914 @[Plic.scala 149:51] - skip @[Plic.scala 149:24] - skip @[Plic.scala 146:36] - skip @[Plic.scala 137:39] - node T_916 = geq(addr, UInt<13>("h01000")) @[Plic.scala 153:20] - node T_918 = eq(T_835, UInt<1>("h00")) @[Plic.scala 120:53] - node T_920 = eq(T_890, UInt<1>("h00")) @[Plic.scala 137:39] - node T_921 = and(T_918, T_920) @[Plic.scala 137:39] - node T_922 = and(T_921, T_916) @[Plic.scala 153:40] - when T_922 : @[Plic.scala 153:40] - node T_924 = cat(pending[2], pending[1]) @[Plic.scala 157:22] - node T_925 = cat(T_924, pending[0]) @[Plic.scala 157:22] - node T_927 = mul(UInt<1>("h00"), UInt<7>("h040")) @[Plic.scala 157:38] - node T_928 = dshr(T_925, T_927) @[Plic.scala 157:29] - rdata <= T_928 @[Plic.scala 157:11] - skip @[Plic.scala 153:40] - node T_930 = eq(T_835, UInt<1>("h00")) @[Plic.scala 120:53] - node T_932 = eq(T_890, UInt<1>("h00")) @[Plic.scala 137:39] - node T_933 = and(T_930, T_932) @[Plic.scala 137:39] - node T_935 = eq(T_916, UInt<1>("h00")) @[Plic.scala 153:40] - node T_936 = and(T_933, T_935) @[Plic.scala 153:40] - when T_936 : @[Plic.scala 158:15] - node T_937 = bits(addr, 3, 3) @[Plic.scala 162:16] - node T_939 = eq(T_937, UInt<1>("h00")) @[Plic.scala 164:18] - when T_939 : @[Plic.scala 164:37] - node T_941 = cat(UInt<31>("h00"), priority[0]) @[Cat.scala 20:58] - node T_943 = cat(UInt<31>("h00"), priority[1]) @[Cat.scala 20:58] - node T_944 = cat(T_943, T_941) @[Cat.scala 20:58] - rdata <= T_944 @[Plic.scala 165:15] - skip @[Plic.scala 164:37] - node T_946 = eq(T_937, UInt<1>("h01")) @[Plic.scala 164:18] - when T_946 : @[Plic.scala 164:37] - node T_948 = cat(UInt<31>("h00"), priority[2]) @[Cat.scala 20:58] - rdata <= T_948 @[Plic.scala 165:15] - skip @[Plic.scala 164:37] - skip @[Plic.scala 158:15] - priority[0] <= UInt<1>("h00") @[Plic.scala 173:15] - pending[0] <= UInt<1>("h00") @[Plic.scala 174:14] - enables[0][0] <= UInt<1>("h00") @[Plic.scala 176:10] - enables[1][0] <= UInt<1>("h00") @[Plic.scala 176:10] - io.tl.grant.valid <= acq.io.deq.valid @[Plic.scala 178:21] - acq.io.deq.ready <= io.tl.grant.ready @[Plic.scala 179:13] - node T_969 = eq(UInt<3>("h06"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_970 = mux(T_969, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_971 = eq(UInt<3>("h05"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_972 = mux(T_971, UInt<3>("h01"), T_970) @[Mux.scala 46:16] - node T_973 = eq(UInt<3>("h04"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_974 = mux(T_973, UInt<3>("h04"), T_972) @[Mux.scala 46:16] - node T_975 = eq(UInt<3>("h03"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_976 = mux(T_975, UInt<3>("h03"), T_974) @[Mux.scala 46:16] - node T_977 = eq(UInt<3>("h02"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_978 = mux(T_977, UInt<3>("h03"), T_976) @[Mux.scala 46:16] - node T_979 = eq(UInt<3>("h01"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_980 = mux(T_979, UInt<3>("h05"), T_978) @[Mux.scala 46:16] - node T_981 = eq(UInt<3>("h00"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_982 = mux(T_981, UInt<3>("h04"), T_980) @[Mux.scala 46:16] - wire T_1007 : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_1007 is invalid @[Definitions.scala 863:19] - T_1007.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_1007.g_type <= T_982 @[Definitions.scala 865:16] - T_1007.client_xact_id <= acq.io.deq.bits.client_xact_id @[Definitions.scala 866:24] - T_1007.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_1007.addr_beat <= UInt<1>("h00") @[Definitions.scala 868:19] - T_1007.data <= rdata @[Definitions.scala 869:14] - io.tl.grant.bits <- T_1007 @[Plic.scala 180:20] - - module LevelGateway : + rdata <= UInt<64>("h0") + node T_676 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_677 = and(acq.io.deq.bits.is_builtin_type, T_676) + node T_694 = asUInt(asSInt(UInt<8>("hff"))) + node T_696 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_697 = and(acq.io.deq.bits.is_builtin_type, T_696) + node T_699 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_700 = and(acq.io.deq.bits.is_builtin_type, T_699) + node T_701 = or(T_697, T_700) + node T_702 = bits(acq.io.deq.bits.union, 8, 1) + node T_704 = mux(T_701, T_702, UInt<1>("h0")) + node T_705 = mux(T_677, T_694, T_704) + node T_706 = bits(T_705, 0, 0) + node T_707 = bits(T_705, 1, 1) + node T_708 = bits(T_705, 2, 2) + node T_709 = bits(T_705, 3, 3) + node T_710 = bits(T_705, 4, 4) + node T_711 = bits(T_705, 5, 5) + node T_712 = bits(T_705, 6, 6) + node T_713 = bits(T_705, 7, 7) + node T_714 = bits(T_706, 0, 0) + node T_717 = mux(T_714, UInt<8>("hff"), UInt<8>("h0")) + node T_718 = bits(T_707, 0, 0) + node T_721 = mux(T_718, UInt<8>("hff"), UInt<8>("h0")) + node T_722 = bits(T_708, 0, 0) + node T_725 = mux(T_722, UInt<8>("hff"), UInt<8>("h0")) + node T_726 = bits(T_709, 0, 0) + node T_729 = mux(T_726, UInt<8>("hff"), UInt<8>("h0")) + node T_730 = bits(T_710, 0, 0) + node T_733 = mux(T_730, UInt<8>("hff"), UInt<8>("h0")) + node T_734 = bits(T_711, 0, 0) + node T_737 = mux(T_734, UInt<8>("hff"), UInt<8>("h0")) + node T_738 = bits(T_712, 0, 0) + node T_741 = mux(T_738, UInt<8>("hff"), UInt<8>("h0")) + node T_742 = bits(T_713, 0, 0) + node T_745 = mux(T_742, UInt<8>("hff"), UInt<8>("h0")) + node T_746 = cat(T_721, T_717) + node T_747 = cat(T_729, T_725) + node T_748 = cat(T_747, T_746) + node T_749 = cat(T_737, T_733) + node T_750 = cat(T_745, T_741) + node T_751 = cat(T_750, T_749) + node T_752 = cat(T_751, T_748) + node T_753 = and(acq.io.deq.bits.data, T_752) + node T_755 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_756 = and(acq.io.deq.bits.is_builtin_type, T_755) + node T_773 = asUInt(asSInt(UInt<8>("hff"))) + node T_775 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_776 = and(acq.io.deq.bits.is_builtin_type, T_775) + node T_778 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_779 = and(acq.io.deq.bits.is_builtin_type, T_778) + node T_780 = or(T_776, T_779) + node T_781 = bits(acq.io.deq.bits.union, 8, 1) + node T_783 = mux(T_780, T_781, UInt<1>("h0")) + node T_784 = mux(T_756, T_773, T_783) + node T_785 = bits(T_784, 0, 0) + node T_786 = bits(T_784, 1, 1) + node T_787 = bits(T_784, 2, 2) + node T_788 = bits(T_784, 3, 3) + node T_789 = bits(T_784, 4, 4) + node T_790 = bits(T_784, 5, 5) + node T_791 = bits(T_784, 6, 6) + node T_792 = bits(T_784, 7, 7) + node T_793 = bits(T_785, 0, 0) + node T_796 = mux(T_793, UInt<8>("hff"), UInt<8>("h0")) + node T_797 = bits(T_786, 0, 0) + node T_800 = mux(T_797, UInt<8>("hff"), UInt<8>("h0")) + node T_801 = bits(T_787, 0, 0) + node T_804 = mux(T_801, UInt<8>("hff"), UInt<8>("h0")) + node T_805 = bits(T_788, 0, 0) + node T_808 = mux(T_805, UInt<8>("hff"), UInt<8>("h0")) + node T_809 = bits(T_789, 0, 0) + node T_812 = mux(T_809, UInt<8>("hff"), UInt<8>("h0")) + node T_813 = bits(T_790, 0, 0) + node T_816 = mux(T_813, UInt<8>("hff"), UInt<8>("h0")) + node T_817 = bits(T_791, 0, 0) + node T_820 = mux(T_817, UInt<8>("hff"), UInt<8>("h0")) + node T_821 = bits(T_792, 0, 0) + node T_824 = mux(T_821, UInt<8>("hff"), UInt<8>("h0")) + node T_825 = cat(T_800, T_796) + node T_826 = cat(T_808, T_804) + node T_827 = cat(T_826, T_825) + node T_828 = cat(T_816, T_812) + node T_829 = cat(T_824, T_820) + node T_830 = cat(T_829, T_828) + node T_831 = cat(T_830, T_827) + node T_832 = not(T_831) + node T_833 = and(rdata, T_832) + node masked_wdata = or(T_753, T_833) + node T_835 = geq(addr, UInt<22>("h200000")) + when T_835 : + node T_838 = cat(maxDevs[claimant], UInt<31>("h0")) + node T_839 = cat(T_838, threshold[claimant]) + node T_841 = mul(UInt<1>("h0"), UInt<7>("h40")) + node T_842 = dshr(T_839, T_841) + rdata <= T_842 + node T_843 = bits(addr, 2, 2) + node T_844 = and(read, T_843) + when T_844 : + pending[maxDevs[claimant]] <= UInt<1>("h0") + when write : + node T_847 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_848 = and(acq.io.deq.bits.is_builtin_type, T_847) + node T_865 = asUInt(asSInt(UInt<8>("hff"))) + node T_867 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_868 = and(acq.io.deq.bits.is_builtin_type, T_867) + node T_870 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_871 = and(acq.io.deq.bits.is_builtin_type, T_870) + node T_872 = or(T_868, T_871) + node T_873 = bits(acq.io.deq.bits.union, 8, 1) + node T_875 = mux(T_872, T_873, UInt<1>("h0")) + node T_876 = mux(T_848, T_865, T_875) + node T_877 = bits(T_876, 4, 4) + when T_877 : + node T_878 = shr(acq.io.deq.bits.data, 32) + node T_879 = bits(T_878, 1, 0) + when enables[hart][T_879] : + node T_881 = sub(T_879, UInt<1>("h1")) + node T_882 = tail(T_881, 1) + io.devices[T_882].complete <= UInt<1>("h1") + node T_888 = eq(T_877, UInt<1>("h0")) + when T_888 : + skip + node T_890 = geq(addr, UInt<14>("h2000")) + node T_892 = eq(T_835, UInt<1>("h0")) + node T_893 = and(T_892, T_890) + when T_893 : + node T_895 = sub(addr, UInt<14>("h2000")) + node T_896 = tail(T_895, 1) + node T_897 = bits(T_896, 7, 7) + hart <= T_897 + node T_900 = eq(UInt<1>("h0"), UInt<1>("h0")) + when T_900 : + node T_901 = cat(enables[hart][2], enables[hart][1]) + node T_902 = cat(T_901, enables[hart][0]) + rdata <= T_902 + when write : + node T_906 = bits(masked_wdata, 0, 0) + enables[T_897][0] <= T_906 + when write : + node T_910 = bits(masked_wdata, 1, 1) + enables[T_897][1] <= T_910 + when write : + node T_914 = bits(masked_wdata, 2, 2) + enables[T_897][2] <= T_914 + node T_916 = geq(addr, UInt<13>("h1000")) + node T_918 = eq(T_835, UInt<1>("h0")) + node T_920 = eq(T_890, UInt<1>("h0")) + node T_921 = and(T_918, T_920) + node T_922 = and(T_921, T_916) + when T_922 : + node T_924 = cat(pending[2], pending[1]) + node T_925 = cat(T_924, pending[0]) + node T_927 = mul(UInt<1>("h0"), UInt<7>("h40")) + node T_928 = dshr(T_925, T_927) + rdata <= T_928 + node T_930 = eq(T_835, UInt<1>("h0")) + node T_932 = eq(T_890, UInt<1>("h0")) + node T_933 = and(T_930, T_932) + node T_935 = eq(T_916, UInt<1>("h0")) + node T_936 = and(T_933, T_935) + when T_936 : + node T_937 = bits(addr, 3, 3) + node T_939 = eq(T_937, UInt<1>("h0")) + when T_939 : + node T_941 = cat(UInt<31>("h0"), priority[0]) + node T_943 = cat(UInt<31>("h0"), priority[1]) + node T_944 = cat(T_943, T_941) + rdata <= T_944 + node T_946 = eq(T_937, UInt<1>("h1")) + when T_946 : + node T_948 = cat(UInt<31>("h0"), priority[2]) + rdata <= T_948 + priority[0] <= UInt<1>("h0") + pending[0] <= UInt<1>("h0") + enables[0][0] <= UInt<1>("h0") + enables[1][0] <= UInt<1>("h0") + io.tl.grant.valid <= acq.io.deq.valid + acq.io.deq.ready <= io.tl.grant.ready + node T_969 = eq(UInt<3>("h6"), acq.io.deq.bits.a_type) + node T_970 = mux(T_969, UInt<3>("h1"), UInt<3>("h3")) + node T_971 = eq(UInt<3>("h5"), acq.io.deq.bits.a_type) + node T_972 = mux(T_971, UInt<3>("h1"), T_970) + node T_973 = eq(UInt<3>("h4"), acq.io.deq.bits.a_type) + node T_974 = mux(T_973, UInt<3>("h4"), T_972) + node T_975 = eq(UInt<3>("h3"), acq.io.deq.bits.a_type) + node T_976 = mux(T_975, UInt<3>("h3"), T_974) + node T_977 = eq(UInt<3>("h2"), acq.io.deq.bits.a_type) + node T_978 = mux(T_977, UInt<3>("h3"), T_976) + node T_979 = eq(UInt<3>("h1"), acq.io.deq.bits.a_type) + node T_980 = mux(T_979, UInt<3>("h5"), T_978) + node T_981 = eq(UInt<3>("h0"), acq.io.deq.bits.a_type) + node T_982 = mux(T_981, UInt<3>("h4"), T_980) + wire T_1007 : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1007 is invalid + T_1007.is_builtin_type <= UInt<1>("h1") + T_1007.g_type <= T_982 + T_1007.client_xact_id <= acq.io.deq.bits.client_xact_id + T_1007.manager_xact_id <= UInt<1>("h0") + T_1007.addr_beat <= UInt<1>("h0") + T_1007.data <= rdata + io.tl.grant.bits <- T_1007 + + module LevelGateway : input clk : Clock input reset : UInt<1> - output io : {flip interrupt : UInt<1>, plic : {valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} - + output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} + io is invalid - reg inFlight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_6 = and(io.interrupt, io.plic.ready) @[Plic.scala 25:22] - when T_6 : @[Plic.scala 25:40] - inFlight <= UInt<1>("h01") @[Plic.scala 25:51] - skip @[Plic.scala 25:40] - when io.plic.complete : @[Plic.scala 26:27] - inFlight <= UInt<1>("h00") @[Plic.scala 26:38] - skip @[Plic.scala 26:27] - node T_10 = eq(inFlight, UInt<1>("h00")) @[Plic.scala 27:36] - node T_11 = and(io.interrupt, T_10) @[Plic.scala 27:33] - io.plic.valid <= T_11 @[Plic.scala 27:17] - - module DebugModule : + reg inFlight : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_6 = and(io.interrupt, io.plic.ready) + when T_6 : + inFlight <= UInt<1>("h1") + when io.plic.complete : + inFlight <= UInt<1>("h0") + node T_10 = eq(inFlight, UInt<1>("h0")) + node T_11 = and(io.interrupt, T_10) + io.plic.valid <= T_11 + + module DebugModule : input clk : Clock input reset : UInt<1> - output io : {flip db : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}}, debugInterrupts : UInt<1>[1], flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, ndreset : UInt<1>, fullreset : UInt<1>} - + output io : { flip db : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<34>, resp : UInt<2>}}}, debugInterrupts : UInt<1>[1], flip tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, ndreset : UInt<1>, fullreset : UInt<1>} + io is invalid - wire CONTROLReset : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 423:26] - CONTROLReset is invalid @[Debug.scala 423:26] - wire CONTROLWrEn : UInt<1> @[Debug.scala 424:25] - CONTROLWrEn is invalid @[Debug.scala 424:25] - reg CONTROLReg : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>}, clk - wire CONTROLWrData : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 426:28] - CONTROLWrData is invalid @[Debug.scala 426:28] - wire CONTROLRdData : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 427:28] - CONTROLRdData is invalid @[Debug.scala 427:28] - reg ndresetCtrReg : UInt<1>, clk - wire DMINFORdData : {reserved0 : UInt<2>, abussize : UInt<7>, serialcount : UInt<4>, access128 : UInt<1>, access64 : UInt<1>, access32 : UInt<1>, access16 : UInt<1>, accesss8 : UInt<1>, dramsize : UInt<6>, haltsum : UInt<1>, reserved1 : UInt<3>, authenticated : UInt<1>, authbusy : UInt<1>, authtype : UInt<2>, version : UInt<2>} @[Debug.scala 430:27] - DMINFORdData is invalid @[Debug.scala 430:27] - wire HALTSUMRdData : {serialfull : UInt<1>, serialvalid : UInt<1>, acks : UInt<32>} @[Debug.scala 432:28] - HALTSUMRdData is invalid @[Debug.scala 432:28] - wire RAMWrData : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 434:24] - RAMWrData is invalid @[Debug.scala 434:24] - wire RAMRdData : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 435:24] - RAMRdData is invalid @[Debug.scala 435:24] - wire SETHALTNOTWrEn : UInt<1> @[Debug.scala 439:28] - SETHALTNOTWrEn is invalid @[Debug.scala 439:28] - wire SETHALTNOTWrData : UInt<10> @[Debug.scala 440:30] - SETHALTNOTWrData is invalid @[Debug.scala 440:30] - wire CLEARDEBINTWrEn : UInt<1> @[Debug.scala 441:29] - CLEARDEBINTWrEn is invalid @[Debug.scala 441:29] - wire CLEARDEBINTWrData : UInt<10> @[Debug.scala 442:31] - CLEARDEBINTWrData is invalid @[Debug.scala 442:31] - wire T_655 : UInt<1>[1] @[Debug.scala 446:57] - T_655 is invalid @[Debug.scala 446:57] - T_655[0] <= UInt<1>("h00") @[Debug.scala 446:57] - reg interruptRegs : UInt<1>[1], clk with : (reset => (reset, T_655)) - wire T_666 : UInt<1>[1] @[Debug.scala 448:59] - T_666 is invalid @[Debug.scala 448:59] - T_666[0] <= UInt<1>("h00") @[Debug.scala 448:59] - reg haltnotRegs : UInt<1>[1], clk with : (reset => (reset, T_666)) - wire haltnotStatus : UInt<32>[1] @[Debug.scala 451:27] - haltnotStatus is invalid @[Debug.scala 451:27] - wire rdHaltnotStatus : UInt<32> @[Debug.scala 452:29] - rdHaltnotStatus is invalid @[Debug.scala 452:29] - node haltnotSummary = neq(haltnotStatus[0], UInt<1>("h00")) @[Debug.scala 454:48] - cmem ramMem : UInt<64>[8] @[Debug.scala 470:22] - wire ramAddr : UInt<3> @[Debug.scala 471:23] - ramAddr is invalid @[Debug.scala 471:23] - wire ramRdData : UInt<64> @[Debug.scala 472:23] - ramRdData is invalid @[Debug.scala 472:23] - wire ramWrData : UInt<64> @[Debug.scala 473:23] - ramWrData is invalid @[Debug.scala 473:23] - wire ramWrMask : UInt<64> @[Debug.scala 474:23] - ramWrMask is invalid @[Debug.scala 474:23] - wire ramWrEn : UInt<1> @[Debug.scala 475:23] - ramWrEn is invalid @[Debug.scala 475:23] - wire dbRamAddr : UInt<4> @[Debug.scala 477:25] - dbRamAddr is invalid @[Debug.scala 477:25] - wire dbRamRdData : UInt<32> @[Debug.scala 478:26] - dbRamRdData is invalid @[Debug.scala 478:26] - wire dbRamWrData : UInt<32> @[Debug.scala 479:25] - dbRamWrData is invalid @[Debug.scala 479:25] - wire dbRamWrEn : UInt<1> @[Debug.scala 480:25] - dbRamWrEn is invalid @[Debug.scala 480:25] - wire dbRamRdEn : UInt<1> @[Debug.scala 481:25] - dbRamRdEn is invalid @[Debug.scala 481:25] - wire sbRamAddr : UInt<3> @[Debug.scala 483:25] - sbRamAddr is invalid @[Debug.scala 483:25] - wire sbRamRdData : UInt<64> @[Debug.scala 484:26] - sbRamRdData is invalid @[Debug.scala 484:26] - wire sbRamWrData : UInt<64> @[Debug.scala 485:25] - sbRamWrData is invalid @[Debug.scala 485:25] - wire sbRamWrEn : UInt<1> @[Debug.scala 486:25] - sbRamWrEn is invalid @[Debug.scala 486:25] - wire sbRamRdEn : UInt<1> @[Debug.scala 487:25] - sbRamRdEn is invalid @[Debug.scala 487:25] - wire sbRomRdData : UInt<64> @[Debug.scala 489:31] - sbRomRdData is invalid @[Debug.scala 489:31] - wire dbRdEn : UInt<1> @[Debug.scala 494:22] - dbRdEn is invalid @[Debug.scala 494:22] - wire dbWrEn : UInt<1> @[Debug.scala 495:22] - dbWrEn is invalid @[Debug.scala 495:22] - wire dbRdData : UInt<34> @[Debug.scala 496:22] - dbRdData is invalid @[Debug.scala 496:22] - reg dbStateReg : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - wire dbResult : {data : UInt<34>, resp : UInt<2>} @[Debug.scala 501:23] - dbResult is invalid @[Debug.scala 501:23] - wire dbReq : {addr : UInt<5>, data : UInt<34>, op : UInt<2>} @[Debug.scala 503:23] - dbReq is invalid @[Debug.scala 503:23] - reg dbRespReg : {data : UInt<34>, resp : UInt<2>}, clk - wire rdCondWrFailure : UInt<1> @[Debug.scala 506:29] - rdCondWrFailure is invalid @[Debug.scala 506:29] - wire dbWrNeeded : UInt<1> @[Debug.scala 507:24] - dbWrNeeded is invalid @[Debug.scala 507:24] - wire sbAddr : UInt<12> @[Debug.scala 510:22] - sbAddr is invalid @[Debug.scala 510:22] - wire sbRdData : UInt<64> @[Debug.scala 511:22] - sbRdData is invalid @[Debug.scala 511:22] - wire sbWrData : UInt<64> @[Debug.scala 512:22] - sbWrData is invalid @[Debug.scala 512:22] - wire sbWrMask : UInt<64> @[Debug.scala 513:22] - sbWrMask is invalid @[Debug.scala 513:22] - wire sbWrEn : UInt<1> @[Debug.scala 514:22] - sbWrEn is invalid @[Debug.scala 514:22] - wire sbRdEn : UInt<1> @[Debug.scala 515:22] - sbRdEn is invalid @[Debug.scala 515:22] - wire stallFromDb : UInt<1> @[Debug.scala 517:25] - stallFromDb is invalid @[Debug.scala 517:25] - wire stallFromSb : UInt<1> @[Debug.scala 518:25] - stallFromSb is invalid @[Debug.scala 518:25] - io.debugInterrupts[0] <= interruptRegs[0] @[Debug.scala 524:35] - when CONTROLWrEn : @[Debug.scala 534:24] - node T_720 = eq(CONTROLWrData.hartid, UInt<1>("h00")) @[Debug.scala 535:34] - when T_720 : @[Debug.scala 535:55] - node T_721 = or(interruptRegs[0], CONTROLWrData.interrupt) @[Debug.scala 536:62] - interruptRegs[0] <= T_721 @[Debug.scala 536:34] - skip @[Debug.scala 535:55] - skip @[Debug.scala 534:24] - node T_723 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 534:24] - node T_724 = and(T_723, dbRamWrEn) @[Debug.scala 538:28] - when T_724 : @[Debug.scala 538:28] - node T_726 = eq(CONTROLReg.hartid, UInt<1>("h00")) @[Debug.scala 539:31] - when T_726 : @[Debug.scala 539:51] - node T_727 = or(interruptRegs[0], RAMWrData.interrupt) @[Debug.scala 540:63] - interruptRegs[0] <= T_727 @[Debug.scala 540:34] - skip @[Debug.scala 539:51] - skip @[Debug.scala 538:28] - node T_729 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 534:24] - node T_731 = eq(dbRamWrEn, UInt<1>("h00")) @[Debug.scala 538:28] - node T_732 = and(T_729, T_731) @[Debug.scala 538:28] - node T_733 = and(T_732, CLEARDEBINTWrEn) @[Debug.scala 542:33] - when T_733 : @[Debug.scala 542:33] - node T_735 = eq(CLEARDEBINTWrData, UInt<10>("h00")) @[Debug.scala 543:31] - when T_735 : @[Debug.scala 543:71] - interruptRegs[0] <= UInt<1>("h00") @[Debug.scala 544:34] - skip @[Debug.scala 543:71] - skip @[Debug.scala 542:33] - when SETHALTNOTWrEn : @[Debug.scala 560:26] - node T_738 = eq(SETHALTNOTWrData, UInt<10>("h00")) @[Debug.scala 561:30] - when T_738 : @[Debug.scala 561:70] - haltnotRegs[0] <= UInt<1>("h01") @[Debug.scala 562:32] - skip @[Debug.scala 561:70] - skip @[Debug.scala 560:26] - node T_741 = eq(SETHALTNOTWrEn, UInt<1>("h00")) @[Debug.scala 560:26] - node T_742 = and(T_741, CONTROLWrEn) @[Debug.scala 564:31] - when T_742 : @[Debug.scala 564:31] - node T_744 = eq(CONTROLWrData.hartid, UInt<1>("h00")) @[Debug.scala 565:34] - when T_744 : @[Debug.scala 565:55] - node T_745 = and(haltnotRegs[0], CONTROLWrData.haltnot) @[Debug.scala 566:58] - haltnotRegs[0] <= T_745 @[Debug.scala 566:32] - skip @[Debug.scala 565:55] - skip @[Debug.scala 564:31] - node T_747 = eq(SETHALTNOTWrEn, UInt<1>("h00")) @[Debug.scala 560:26] - node T_749 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 564:31] - node T_750 = and(T_747, T_749) @[Debug.scala 564:31] - node T_751 = and(T_750, dbRamWrEn) @[Debug.scala 568:28] - when T_751 : @[Debug.scala 568:28] - node T_753 = eq(CONTROLReg.hartid, UInt<1>("h00")) @[Debug.scala 569:31] - when T_753 : @[Debug.scala 569:51] - node T_754 = and(haltnotRegs[0], RAMWrData.haltnot) @[Debug.scala 570:59] - haltnotRegs[0] <= T_754 @[Debug.scala 570:32] - skip @[Debug.scala 569:51] - skip @[Debug.scala 568:28] - haltnotStatus[0] <= haltnotRegs[0] @[Debug.scala 576:23] - CONTROLReset.interrupt <= UInt<1>("h00") @[Debug.scala 583:30] - CONTROLReset.haltnot <= UInt<1>("h00") @[Debug.scala 584:30] - CONTROLReset.reserved0 <= UInt<1>("h00") @[Debug.scala 585:30] - CONTROLReset.buserror <= UInt<1>("h00") @[Debug.scala 586:30] - CONTROLReset.serial <= UInt<1>("h00") @[Debug.scala 587:30] - CONTROLReset.autoincrement <= UInt<1>("h00") @[Debug.scala 588:30] - CONTROLReset.access <= UInt<2>("h02") @[Debug.scala 589:30] - CONTROLReset.hartid <= UInt<1>("h00") @[Debug.scala 590:30] - CONTROLReset.ndreset <= UInt<1>("h00") @[Debug.scala 591:30] - CONTROLReset.fullreset <= UInt<1>("h00") @[Debug.scala 592:30] - DMINFORdData.reserved0 <= UInt<1>("h00") @[Debug.scala 597:30] - DMINFORdData.abussize <= UInt<1>("h00") @[Debug.scala 598:30] - DMINFORdData.serialcount <= UInt<1>("h00") @[Debug.scala 599:30] - DMINFORdData.access128 <= UInt<1>("h00") @[Debug.scala 600:30] - DMINFORdData.access64 <= UInt<1>("h00") @[Debug.scala 601:30] - DMINFORdData.access32 <= UInt<1>("h00") @[Debug.scala 602:30] - DMINFORdData.access16 <= UInt<1>("h00") @[Debug.scala 603:30] - DMINFORdData.accesss8 <= UInt<1>("h00") @[Debug.scala 604:30] - DMINFORdData.dramsize <= UInt<4>("h0f") @[Debug.scala 605:30] - DMINFORdData.haltsum <= UInt<1>("h00") @[Debug.scala 606:30] - DMINFORdData.reserved1 <= UInt<1>("h00") @[Debug.scala 607:30] - DMINFORdData.authenticated <= UInt<1>("h01") @[Debug.scala 608:30] - DMINFORdData.authbusy <= UInt<1>("h00") @[Debug.scala 609:30] - DMINFORdData.authtype <= UInt<1>("h00") @[Debug.scala 610:30] - DMINFORdData.version <= UInt<1>("h01") @[Debug.scala 611:30] - HALTSUMRdData.serialfull <= UInt<1>("h00") @[Debug.scala 613:29] - HALTSUMRdData.serialvalid <= UInt<1>("h00") @[Debug.scala 614:29] - HALTSUMRdData.acks <= haltnotSummary @[Debug.scala 615:29] - dbReq <- io.db.req.bits @[Debug.scala 621:9] - node T_782 = bits(dbReq.addr, 3, 0) @[Debug.scala 625:28] - dbRamAddr <= T_782 @[Debug.scala 625:15] - dbRamWrData <= dbReq.data @[Debug.scala 626:15] - node T_783 = bits(sbAddr, 5, 3) @[Debug.scala 627:24] - sbRamAddr <= T_783 @[Debug.scala 627:15] - sbRamWrData <= sbWrData @[Debug.scala 628:15] - node T_788 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - node T_793 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - wire T_799 : UInt<32>[2] @[Debug.scala 631:77] - T_799 is invalid @[Debug.scala 631:77] - T_799[0] <= T_788 @[Debug.scala 631:77] - T_799[1] <= T_793 @[Debug.scala 631:77] + wire CONTROLReset : { interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} + CONTROLReset is invalid + wire CONTROLWrEn : UInt<1> + CONTROLWrEn is invalid + reg CONTROLReg : { interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>}, clk with : + reset => (UInt<1>("h0"), CONTROLReg) + wire CONTROLWrData : { interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} + CONTROLWrData is invalid + wire CONTROLRdData : { interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} + CONTROLRdData is invalid + reg ndresetCtrReg : UInt<1>, clk with : + reset => (UInt<1>("h0"), ndresetCtrReg) + wire DMINFORdData : { reserved0 : UInt<2>, abussize : UInt<7>, serialcount : UInt<4>, access128 : UInt<1>, access64 : UInt<1>, access32 : UInt<1>, access16 : UInt<1>, accesss8 : UInt<1>, dramsize : UInt<6>, haltsum : UInt<1>, reserved1 : UInt<3>, authenticated : UInt<1>, authbusy : UInt<1>, authtype : UInt<2>, version : UInt<2>} + DMINFORdData is invalid + wire HALTSUMRdData : { serialfull : UInt<1>, serialvalid : UInt<1>, acks : UInt<32>} + HALTSUMRdData is invalid + wire RAMWrData : { interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} + RAMWrData is invalid + wire RAMRdData : { interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} + RAMRdData is invalid + wire SETHALTNOTWrEn : UInt<1> + SETHALTNOTWrEn is invalid + wire SETHALTNOTWrData : UInt<10> + SETHALTNOTWrData is invalid + wire CLEARDEBINTWrEn : UInt<1> + CLEARDEBINTWrEn is invalid + wire CLEARDEBINTWrData : UInt<10> + CLEARDEBINTWrData is invalid + wire T_655 : UInt<1>[1] + T_655 is invalid + T_655[0] <= UInt<1>("h0") + reg interruptRegs : UInt<1>[1], clk with : + reset => (reset, T_655) + wire T_666 : UInt<1>[1] + T_666 is invalid + T_666[0] <= UInt<1>("h0") + reg haltnotRegs : UInt<1>[1], clk with : + reset => (reset, T_666) + wire haltnotStatus : UInt<32>[1] + haltnotStatus is invalid + wire rdHaltnotStatus : UInt<32> + rdHaltnotStatus is invalid + node haltnotSummary = neq(haltnotStatus[0], UInt<1>("h0")) + cmem ramMem : UInt<64> [8] + wire ramAddr : UInt<3> + ramAddr is invalid + wire ramRdData : UInt<64> + ramRdData is invalid + wire ramWrData : UInt<64> + ramWrData is invalid + wire ramWrMask : UInt<64> + ramWrMask is invalid + wire ramWrEn : UInt<1> + ramWrEn is invalid + wire dbRamAddr : UInt<4> + dbRamAddr is invalid + wire dbRamRdData : UInt<32> + dbRamRdData is invalid + wire dbRamWrData : UInt<32> + dbRamWrData is invalid + wire dbRamWrEn : UInt<1> + dbRamWrEn is invalid + wire dbRamRdEn : UInt<1> + dbRamRdEn is invalid + wire sbRamAddr : UInt<3> + sbRamAddr is invalid + wire sbRamRdData : UInt<64> + sbRamRdData is invalid + wire sbRamWrData : UInt<64> + sbRamWrData is invalid + wire sbRamWrEn : UInt<1> + sbRamWrEn is invalid + wire sbRamRdEn : UInt<1> + sbRamRdEn is invalid + wire sbRomRdData : UInt<64> + sbRomRdData is invalid + wire dbRdEn : UInt<1> + dbRdEn is invalid + wire dbWrEn : UInt<1> + dbWrEn is invalid + wire dbRdData : UInt<34> + dbRdData is invalid + reg dbStateReg : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + wire dbResult : { data : UInt<34>, resp : UInt<2>} + dbResult is invalid + wire dbReq : { addr : UInt<5>, data : UInt<34>, op : UInt<2>} + dbReq is invalid + reg dbRespReg : { data : UInt<34>, resp : UInt<2>}, clk with : + reset => (UInt<1>("h0"), dbRespReg) + wire rdCondWrFailure : UInt<1> + rdCondWrFailure is invalid + wire dbWrNeeded : UInt<1> + dbWrNeeded is invalid + wire sbAddr : UInt<12> + sbAddr is invalid + wire sbRdData : UInt<64> + sbRdData is invalid + wire sbWrData : UInt<64> + sbWrData is invalid + wire sbWrMask : UInt<64> + sbWrMask is invalid + wire sbWrEn : UInt<1> + sbWrEn is invalid + wire sbRdEn : UInt<1> + sbRdEn is invalid + wire stallFromDb : UInt<1> + stallFromDb is invalid + wire stallFromSb : UInt<1> + stallFromSb is invalid + io.debugInterrupts[0] <= interruptRegs[0] + when CONTROLWrEn : + node T_720 = eq(CONTROLWrData.hartid, UInt<1>("h0")) + when T_720 : + node T_721 = or(interruptRegs[0], CONTROLWrData.interrupt) + interruptRegs[0] <= T_721 + node T_723 = eq(CONTROLWrEn, UInt<1>("h0")) + node T_724 = and(T_723, dbRamWrEn) + when T_724 : + node T_726 = eq(CONTROLReg.hartid, UInt<1>("h0")) + when T_726 : + node T_727 = or(interruptRegs[0], RAMWrData.interrupt) + interruptRegs[0] <= T_727 + node T_729 = eq(CONTROLWrEn, UInt<1>("h0")) + node T_731 = eq(dbRamWrEn, UInt<1>("h0")) + node T_732 = and(T_729, T_731) + node T_733 = and(T_732, CLEARDEBINTWrEn) + when T_733 : + node T_735 = eq(CLEARDEBINTWrData, UInt<10>("h0")) + when T_735 : + interruptRegs[0] <= UInt<1>("h0") + when SETHALTNOTWrEn : + node T_738 = eq(SETHALTNOTWrData, UInt<10>("h0")) + when T_738 : + haltnotRegs[0] <= UInt<1>("h1") + node T_741 = eq(SETHALTNOTWrEn, UInt<1>("h0")) + node T_742 = and(T_741, CONTROLWrEn) + when T_742 : + node T_744 = eq(CONTROLWrData.hartid, UInt<1>("h0")) + when T_744 : + node T_745 = and(haltnotRegs[0], CONTROLWrData.haltnot) + haltnotRegs[0] <= T_745 + node T_747 = eq(SETHALTNOTWrEn, UInt<1>("h0")) + node T_749 = eq(CONTROLWrEn, UInt<1>("h0")) + node T_750 = and(T_747, T_749) + node T_751 = and(T_750, dbRamWrEn) + when T_751 : + node T_753 = eq(CONTROLReg.hartid, UInt<1>("h0")) + when T_753 : + node T_754 = and(haltnotRegs[0], RAMWrData.haltnot) + haltnotRegs[0] <= T_754 + haltnotStatus[0] <= haltnotRegs[0] + CONTROLReset.interrupt <= UInt<1>("h0") + CONTROLReset.haltnot <= UInt<1>("h0") + CONTROLReset.reserved0 <= UInt<1>("h0") + CONTROLReset.buserror <= UInt<1>("h0") + CONTROLReset.serial <= UInt<1>("h0") + CONTROLReset.autoincrement <= UInt<1>("h0") + CONTROLReset.access <= UInt<2>("h2") + CONTROLReset.hartid <= UInt<1>("h0") + CONTROLReset.ndreset <= UInt<1>("h0") + CONTROLReset.fullreset <= UInt<1>("h0") + DMINFORdData.reserved0 <= UInt<1>("h0") + DMINFORdData.abussize <= UInt<1>("h0") + DMINFORdData.serialcount <= UInt<1>("h0") + DMINFORdData.access128 <= UInt<1>("h0") + DMINFORdData.access64 <= UInt<1>("h0") + DMINFORdData.access32 <= UInt<1>("h0") + DMINFORdData.access16 <= UInt<1>("h0") + DMINFORdData.accesss8 <= UInt<1>("h0") + DMINFORdData.dramsize <= UInt<4>("hf") + DMINFORdData.haltsum <= UInt<1>("h0") + DMINFORdData.reserved1 <= UInt<1>("h0") + DMINFORdData.authenticated <= UInt<1>("h1") + DMINFORdData.authbusy <= UInt<1>("h0") + DMINFORdData.authtype <= UInt<1>("h0") + DMINFORdData.version <= UInt<1>("h1") + HALTSUMRdData.serialfull <= UInt<1>("h0") + HALTSUMRdData.serialvalid <= UInt<1>("h0") + HALTSUMRdData.acks <= haltnotSummary + dbReq <- io.db.req.bits + node T_782 = bits(dbReq.addr, 3, 0) + dbRamAddr <= T_782 + dbRamWrData <= dbReq.data + node T_783 = bits(sbAddr, 5, 3) + sbRamAddr <= T_783 + sbRamWrData <= sbWrData + node T_788 = mux(UInt<1>("h1"), UInt<32>("hffffffff"), UInt<32>("h0")) + node T_793 = mux(UInt<1>("h1"), UInt<32>("hffffffff"), UInt<32>("h0")) + wire T_799 : UInt<32>[2] + T_799 is invalid + T_799[0] <= T_788 + T_799[1] <= T_793 wire dbRamWrMask : UInt<32>[2] dbRamWrMask is invalid dbRamWrMask <= T_799 - node T_804 = bits(dbRamAddr, 0, 0) @[Debug.scala 635:29] - node T_805 = bits(ramRdData, 31, 0) @[Debug.scala 637:16] - node T_806 = bits(ramRdData, 63, 32) @[Debug.scala 637:16] - wire T_812 : UInt<32>[2] @[Debug.scala 636:73] - T_812 is invalid @[Debug.scala 636:73] - T_812[0] <= T_805 @[Debug.scala 636:73] - T_812[1] <= T_806 @[Debug.scala 636:73] - wire T_821 : UInt<32>[2] @[Debug.scala 639:66] - T_821 is invalid @[Debug.scala 639:66] - T_821[0] <= UInt<32>("h00") @[Debug.scala 639:66] - T_821[1] <= UInt<32>("h00") @[Debug.scala 639:66] - dbRamWrMask <= T_821 @[Debug.scala 639:17] - node T_827 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 33:12] - dbRamWrMask[T_804] <= T_827 @[Debug.scala 640:27] - dbRamRdData <= T_812[T_804] @[Debug.scala 641:17] - sbRamRdData <= ramRdData @[Debug.scala 646:15] - node T_828 = cat(dbRamWrMask[1], dbRamWrMask[0]) @[Debug.scala 648:53] - node T_829 = mux(sbRamWrEn, sbWrMask, T_828) @[Debug.scala 648:19] - ramWrMask <= T_829 @[Debug.scala 648:13] - node T_830 = or(dbRamWrEn, dbRamRdEn) @[Debug.scala 650:24] - node T_831 = or(sbRamRdEn, sbRamWrEn) @[Debug.scala 650:50] - node T_832 = and(T_830, T_831) @[Debug.scala 650:37] - node T_834 = eq(T_832, UInt<1>("h00")) @[Debug.scala 650:11] - node T_835 = or(T_834, reset) @[Debug.scala 650:10] - node T_837 = eq(T_835, UInt<1>("h00")) @[Debug.scala 650:10] - when T_837 : @[Debug.scala 650:10] - printf(clk, UInt<1>(1), "Assertion failed: Stall logic should have prevented concurrent SB/DB RAM Access\n at Debug.scala:650 assert (!((dbRamWrEn | dbRamRdEn) & (sbRamRdEn | sbRamWrEn)), \"Stall logic should have prevented concurrent SB/DB RAM Access\")\n") @[Debug.scala 650:10] - stop(clk, UInt<1>(1), 1) @[Debug.scala 650:10] - skip @[Debug.scala 650:10] - node dbRamWrDataVec = cat(dbRamWrData, dbRamWrData) @[Cat.scala 20:58] - node T_838 = and(ramWrMask, sbRamWrData) @[Debug.scala 655:16] - node T_839 = not(ramWrMask) @[Debug.scala 655:37] - node T_840 = and(T_839, ramRdData) @[Debug.scala 655:48] - node T_841 = or(T_838, T_840) @[Debug.scala 655:34] - node T_842 = and(ramWrMask, dbRamWrDataVec) @[Debug.scala 656:16] - node T_843 = not(ramWrMask) @[Debug.scala 656:37] - node T_844 = and(T_843, ramRdData) @[Debug.scala 656:48] - node T_845 = or(T_842, T_844) @[Debug.scala 656:34] - node T_846 = mux(sbRamWrEn, T_841, T_845) @[Debug.scala 654:19] - ramWrData <= T_846 @[Debug.scala 654:13] - node T_847 = or(sbRamWrEn, sbRamRdEn) @[Debug.scala 658:30] - node T_848 = shr(dbRamAddr, 1) @[Debug.scala 659:15] - node T_849 = mux(T_847, sbRamAddr, T_848) @[Debug.scala 658:19] - ramAddr <= T_849 @[Debug.scala 658:13] + node T_804 = bits(dbRamAddr, 0, 0) + node T_805 = bits(ramRdData, 31, 0) + node T_806 = bits(ramRdData, 63, 32) + wire T_812 : UInt<32>[2] + T_812 is invalid + T_812[0] <= T_805 + T_812[1] <= T_806 + wire T_821 : UInt<32>[2] + T_821 is invalid + T_821[0] <= UInt<32>("h0") + T_821[1] <= UInt<32>("h0") + dbRamWrMask <= T_821 + node T_827 = mux(UInt<1>("h1"), UInt<32>("hffffffff"), UInt<32>("h0")) + dbRamWrMask[T_804] <= T_827 + dbRamRdData <= T_812[T_804] + sbRamRdData <= ramRdData + node T_828 = cat(dbRamWrMask[1], dbRamWrMask[0]) + node T_829 = mux(sbRamWrEn, sbWrMask, T_828) + ramWrMask <= T_829 + node T_830 = or(dbRamWrEn, dbRamRdEn) + node T_831 = or(sbRamRdEn, sbRamWrEn) + node T_832 = and(T_830, T_831) + node T_834 = eq(T_832, UInt<1>("h0")) + node T_835 = or(T_834, reset) + node T_837 = eq(T_835, UInt<1>("h0")) + when T_837 : + printf(clk, UInt<1>("h1"), "Assertion failed: Stall logic should have prevented concurrent SB/DB RAM Access\n at Debug.scala:650 assert (!((dbRamWrEn | dbRamRdEn) & (sbRamRdEn | sbRamWrEn)), \"Stall logic should have prevented concurrent SB/DB RAM Access\")\n") + stop(clk, UInt<1>("h1"), 1) + node dbRamWrDataVec = cat(dbRamWrData, dbRamWrData) + node T_838 = and(ramWrMask, sbRamWrData) + node T_839 = not(ramWrMask) + node T_840 = and(T_839, ramRdData) + node T_841 = or(T_838, T_840) + node T_842 = and(ramWrMask, dbRamWrDataVec) + node T_843 = not(ramWrMask) + node T_844 = and(T_843, ramRdData) + node T_845 = or(T_842, T_844) + node T_846 = mux(sbRamWrEn, T_841, T_845) + ramWrData <= T_846 + node T_847 = or(sbRamWrEn, sbRamRdEn) + node T_848 = shr(dbRamAddr, 1) + node T_849 = mux(T_847, sbRamAddr, T_848) + ramAddr <= T_849 infer mport T_850 = ramMem[ramAddr], clk - ramRdData <= T_850 @[Debug.scala 661:13] - when ramWrEn : @[Debug.scala 662:18] + ramRdData <= T_850 + when ramWrEn : infer mport T_851 = ramMem[ramAddr], clk - T_851 <= ramWrData @[Debug.scala 662:36] - skip @[Debug.scala 662:18] - node T_852 = or(sbRamWrEn, dbRamWrEn) @[Debug.scala 664:24] - ramWrEn <= T_852 @[Debug.scala 664:11] - wire T_875 : {interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} @[Debug.scala 680:48] - T_875 is invalid @[Debug.scala 680:48] - node T_886 = bits(dbReq.data, 0, 0) @[Debug.scala 680:48] - T_875.fullreset <= T_886 @[Debug.scala 680:48] - node T_887 = bits(dbReq.data, 1, 1) @[Debug.scala 680:48] - T_875.ndreset <= T_887 @[Debug.scala 680:48] - node T_888 = bits(dbReq.data, 11, 2) @[Debug.scala 680:48] - T_875.hartid <= T_888 @[Debug.scala 680:48] - node T_889 = bits(dbReq.data, 14, 12) @[Debug.scala 680:48] - T_875.access <= T_889 @[Debug.scala 680:48] - node T_890 = bits(dbReq.data, 15, 15) @[Debug.scala 680:48] - T_875.autoincrement <= T_890 @[Debug.scala 680:48] - node T_891 = bits(dbReq.data, 18, 16) @[Debug.scala 680:48] - T_875.serial <= T_891 @[Debug.scala 680:48] - node T_892 = bits(dbReq.data, 21, 19) @[Debug.scala 680:48] - T_875.buserror <= T_892 @[Debug.scala 680:48] - node T_893 = bits(dbReq.data, 31, 22) @[Debug.scala 680:48] - T_875.reserved0 <= T_893 @[Debug.scala 680:48] - node T_894 = bits(dbReq.data, 32, 32) @[Debug.scala 680:48] - T_875.haltnot <= T_894 @[Debug.scala 680:48] - node T_895 = bits(dbReq.data, 33, 33) @[Debug.scala 680:48] - T_875.interrupt <= T_895 @[Debug.scala 680:48] - CONTROLWrData <- T_875 @[Debug.scala 680:17] - wire T_904 : {interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} @[Debug.scala 681:44] - T_904 is invalid @[Debug.scala 681:44] - node T_908 = bits(dbReq.data, 31, 0) @[Debug.scala 681:44] - T_904.data <= T_908 @[Debug.scala 681:44] - node T_909 = bits(dbReq.data, 32, 32) @[Debug.scala 681:44] - T_904.haltnot <= T_909 @[Debug.scala 681:44] - node T_910 = bits(dbReq.data, 33, 33) @[Debug.scala 681:44] - T_904.interrupt <= T_910 @[Debug.scala 681:44] - RAMWrData <- T_904 @[Debug.scala 681:17] - dbRamWrEn <= UInt<1>("h00") @[Debug.scala 683:14] - CONTROLWrEn <= UInt<1>("h00") @[Debug.scala 684:15] - node T_913 = shr(dbReq.addr, 4) @[Debug.scala 685:21] - node T_915 = eq(T_913, UInt<1>("h00")) @[Debug.scala 685:27] - when T_915 : @[Debug.scala 685:40] - dbRamWrEn <= dbWrEn @[Debug.scala 686:15] - skip @[Debug.scala 685:40] - node T_917 = eq(dbReq.addr, UInt<5>("h010")) @[Debug.scala 687:27] - node T_919 = eq(T_915, UInt<1>("h00")) @[Debug.scala 685:40] - node T_920 = and(T_919, T_917) @[Debug.scala 687:42] - when T_920 : @[Debug.scala 687:42] - CONTROLWrEn <= dbWrEn @[Debug.scala 688:18] - skip @[Debug.scala 687:42] - node T_922 = eq(T_915, UInt<1>("h00")) @[Debug.scala 685:40] - node T_924 = eq(T_917, UInt<1>("h00")) @[Debug.scala 687:42] - node T_925 = and(T_922, T_924) @[Debug.scala 687:42] - when T_925 : @[Debug.scala 689:15] - skip @[Debug.scala 689:15] - when reset : @[Debug.scala 693:16] - CONTROLReg <- CONTROLReset @[Debug.scala 694:16] - ndresetCtrReg <= UInt<1>("h00") @[Debug.scala 695:19] - skip @[Debug.scala 693:16] - node T_928 = eq(reset, UInt<1>("h00")) @[Debug.scala 693:16] - node T_929 = and(T_928, CONTROLWrEn) @[Debug.scala 696:28] - when T_929 : @[Debug.scala 696:28] - CONTROLReg.hartid <= CONTROLWrData.hartid @[Debug.scala 708:30] - node T_930 = or(CONTROLReg.fullreset, CONTROLWrData.fullreset) @[Debug.scala 709:54] - CONTROLReg.fullreset <= T_930 @[Debug.scala 709:30] - when CONTROLWrData.ndreset : @[Debug.scala 710:33] - ndresetCtrReg <= UInt<1>("h01") @[Debug.scala 711:21] - skip @[Debug.scala 710:33] - node T_933 = eq(CONTROLWrData.ndreset, UInt<1>("h00")) @[Debug.scala 710:33] - when T_933 : @[Debug.scala 712:17] - node T_935 = eq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 713:42] - node T_938 = sub(ndresetCtrReg, UInt<1>("h01")) @[Debug.scala 713:79] - node T_939 = tail(T_938, 1) @[Debug.scala 713:79] - node T_940 = mux(T_935, UInt<1>("h00"), T_939) @[Debug.scala 713:27] - ndresetCtrReg <= T_940 @[Debug.scala 713:21] - skip @[Debug.scala 712:17] - skip @[Debug.scala 696:28] - node T_942 = eq(reset, UInt<1>("h00")) @[Debug.scala 693:16] - node T_944 = eq(CONTROLWrEn, UInt<1>("h00")) @[Debug.scala 696:28] - node T_945 = and(T_942, T_944) @[Debug.scala 696:28] - when T_945 : @[Debug.scala 715:15] - node T_947 = eq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 716:40] - node T_950 = sub(ndresetCtrReg, UInt<1>("h01")) @[Debug.scala 716:77] - node T_951 = tail(T_950, 1) @[Debug.scala 716:77] - node T_952 = mux(T_947, UInt<1>("h00"), T_951) @[Debug.scala 716:25] - ndresetCtrReg <= T_952 @[Debug.scala 716:19] - skip @[Debug.scala 715:15] - CONTROLRdData <- CONTROLReg @[Debug.scala 722:17] - CONTROLRdData.interrupt <= interruptRegs[CONTROLReg.hartid] @[Debug.scala 723:27] - CONTROLRdData.haltnot <= haltnotRegs[CONTROLReg.hartid] @[Debug.scala 724:27] - node T_954 = neq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 725:44] - CONTROLRdData.ndreset <= T_954 @[Debug.scala 725:27] - RAMRdData.interrupt <= interruptRegs[CONTROLReg.hartid] @[Debug.scala 727:23] - RAMRdData.haltnot <= haltnotRegs[CONTROLReg.hartid] @[Debug.scala 728:23] - RAMRdData.data <= dbRamRdData @[Debug.scala 729:23] - dbRdData <= UInt<1>("h00") @[Debug.scala 731:12] - rdHaltnotStatus <= UInt<1>("h00") @[Debug.scala 735:19] - node T_958 = eq(dbReq.addr, UInt<1>("h00")) @[Debug.scala 737:22] - when T_958 : @[Debug.scala 737:36] - rdHaltnotStatus <= haltnotStatus[0] @[Debug.scala 738:23] - skip @[Debug.scala 737:36] - dbRamRdEn <= UInt<1>("h00") @[Debug.scala 742:13] - node T_960 = shr(dbReq.addr, 4) @[Debug.scala 743:21] - node T_962 = eq(T_960, UInt<1>("h00")) @[Debug.scala 743:27] - when T_962 : @[Debug.scala 743:40] - node T_963 = cat(RAMRdData.interrupt, RAMRdData.haltnot) @[Debug.scala 744:28] - node T_964 = cat(T_963, RAMRdData.data) @[Debug.scala 744:28] - dbRdData <= T_964 @[Debug.scala 744:15] - dbRamRdEn <= dbRdEn @[Debug.scala 745:15] - skip @[Debug.scala 743:40] - node T_966 = eq(dbReq.addr, UInt<5>("h010")) @[Debug.scala 746:26] - node T_968 = eq(T_962, UInt<1>("h00")) @[Debug.scala 743:40] - node T_969 = and(T_968, T_966) @[Debug.scala 746:41] - when T_969 : @[Debug.scala 746:41] - node T_970 = cat(CONTROLRdData.ndreset, CONTROLRdData.fullreset) @[Debug.scala 747:31] - node T_971 = cat(CONTROLRdData.autoincrement, CONTROLRdData.access) @[Debug.scala 747:31] - node T_972 = cat(T_971, CONTROLRdData.hartid) @[Debug.scala 747:31] - node T_973 = cat(T_972, T_970) @[Debug.scala 747:31] - node T_974 = cat(CONTROLRdData.buserror, CONTROLRdData.serial) @[Debug.scala 747:31] - node T_975 = cat(CONTROLRdData.interrupt, CONTROLRdData.haltnot) @[Debug.scala 747:31] - node T_976 = cat(T_975, CONTROLRdData.reserved0) @[Debug.scala 747:31] - node T_977 = cat(T_976, T_974) @[Debug.scala 747:31] - node T_978 = cat(T_977, T_973) @[Debug.scala 747:31] - dbRdData <= T_978 @[Debug.scala 747:14] - skip @[Debug.scala 746:41] - node T_980 = eq(dbReq.addr, UInt<5>("h011")) @[Debug.scala 748:26] - node T_982 = eq(T_962, UInt<1>("h00")) @[Debug.scala 743:40] - node T_984 = eq(T_966, UInt<1>("h00")) @[Debug.scala 746:41] - node T_985 = and(T_982, T_984) @[Debug.scala 746:41] - node T_986 = and(T_985, T_980) @[Debug.scala 748:38] - when T_986 : @[Debug.scala 748:38] - node T_987 = cat(DMINFORdData.authbusy, DMINFORdData.authtype) @[Debug.scala 749:30] - node T_988 = cat(T_987, DMINFORdData.version) @[Debug.scala 749:30] - node T_989 = cat(DMINFORdData.reserved1, DMINFORdData.authenticated) @[Debug.scala 749:30] - node T_990 = cat(DMINFORdData.dramsize, DMINFORdData.haltsum) @[Debug.scala 749:30] - node T_991 = cat(T_990, T_989) @[Debug.scala 749:30] - node T_992 = cat(T_991, T_988) @[Debug.scala 749:30] - node T_993 = cat(DMINFORdData.access16, DMINFORdData.accesss8) @[Debug.scala 749:30] - node T_994 = cat(DMINFORdData.access64, DMINFORdData.access32) @[Debug.scala 749:30] - node T_995 = cat(T_994, T_993) @[Debug.scala 749:30] - node T_996 = cat(DMINFORdData.serialcount, DMINFORdData.access128) @[Debug.scala 749:30] - node T_997 = cat(DMINFORdData.reserved0, DMINFORdData.abussize) @[Debug.scala 749:30] - node T_998 = cat(T_997, T_996) @[Debug.scala 749:30] - node T_999 = cat(T_998, T_995) @[Debug.scala 749:30] - node T_1000 = cat(T_999, T_992) @[Debug.scala 749:30] - dbRdData <= T_1000 @[Debug.scala 749:14] - skip @[Debug.scala 748:38] - node T_1002 = eq(dbReq.addr, UInt<5>("h01b")) @[Debug.scala 750:26] - node T_1004 = eq(T_962, UInt<1>("h00")) @[Debug.scala 743:40] - node T_1006 = eq(T_966, UInt<1>("h00")) @[Debug.scala 746:41] - node T_1007 = and(T_1004, T_1006) @[Debug.scala 746:41] - node T_1009 = eq(T_980, UInt<1>("h00")) @[Debug.scala 748:38] - node T_1010 = and(T_1007, T_1009) @[Debug.scala 748:38] - node T_1011 = and(T_1010, T_1002) @[Debug.scala 750:39] - when T_1011 : @[Debug.scala 750:39] - dbRdData <= UInt<1>("h00") @[Debug.scala 754:16] - skip @[Debug.scala 750:39] - node T_1013 = shr(dbReq.addr, 2) @[Debug.scala 756:27] - node T_1015 = eq(T_1013, UInt<3>("h07")) @[Debug.scala 756:33] - node T_1017 = eq(T_962, UInt<1>("h00")) @[Debug.scala 743:40] - node T_1019 = eq(T_966, UInt<1>("h00")) @[Debug.scala 746:41] - node T_1020 = and(T_1017, T_1019) @[Debug.scala 746:41] - node T_1022 = eq(T_980, UInt<1>("h00")) @[Debug.scala 748:38] - node T_1023 = and(T_1020, T_1022) @[Debug.scala 748:38] - node T_1025 = eq(T_1002, UInt<1>("h00")) @[Debug.scala 750:39] - node T_1026 = and(T_1023, T_1025) @[Debug.scala 750:39] - node T_1027 = and(T_1026, T_1015) @[Debug.scala 756:46] - when T_1027 : @[Debug.scala 756:46] - dbRdData <= rdHaltnotStatus @[Debug.scala 757:14] - skip @[Debug.scala 756:46] - node T_1029 = eq(T_962, UInt<1>("h00")) @[Debug.scala 743:40] - node T_1031 = eq(T_966, UInt<1>("h00")) @[Debug.scala 746:41] - node T_1032 = and(T_1029, T_1031) @[Debug.scala 746:41] - node T_1034 = eq(T_980, UInt<1>("h00")) @[Debug.scala 748:38] - node T_1035 = and(T_1032, T_1034) @[Debug.scala 748:38] - node T_1037 = eq(T_1002, UInt<1>("h00")) @[Debug.scala 750:39] - node T_1038 = and(T_1035, T_1037) @[Debug.scala 750:39] - node T_1040 = eq(T_1015, UInt<1>("h00")) @[Debug.scala 756:46] - node T_1041 = and(T_1038, T_1040) @[Debug.scala 756:46] - when T_1041 : @[Debug.scala 758:16] - dbRdData <= UInt<1>("h00") @[Debug.scala 773:14] - skip @[Debug.scala 758:16] - node T_1043 = bits(dbRdData, 33, 33) @[Debug.scala 777:30] - node T_1045 = eq(dbReq.op, UInt<2>("h03")) @[Debug.scala 778:13] - node T_1046 = and(T_1043, T_1045) @[Debug.scala 777:48] - rdCondWrFailure <= T_1046 @[Debug.scala 777:19] - node T_1048 = eq(dbReq.op, UInt<2>("h02")) @[Debug.scala 780:27] - node T_1050 = eq(dbReq.op, UInt<2>("h03")) @[Debug.scala 781:14] - node T_1051 = not(rdCondWrFailure) @[Debug.scala 781:44] - node T_1052 = and(T_1050, T_1051) @[Debug.scala 781:41] - node T_1053 = or(T_1048, T_1052) @[Debug.scala 780:49] - dbWrNeeded <= T_1053 @[Debug.scala 780:14] - node T_1056 = mux(rdCondWrFailure, UInt<2>("h01"), UInt<2>("h00")) @[Debug.scala 784:23] - dbResult.resp <= T_1056 @[Debug.scala 784:17] - dbResult.data <= dbRdData @[Debug.scala 787:17] - node T_1058 = eq(stallFromSb, UInt<1>("h00")) @[Debug.scala 791:22] - node T_1059 = eq(dbStateReg, UInt<1>("h00")) @[Debug.scala 791:51] - node T_1060 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 792:17] - node T_1061 = and(io.db.resp.ready, io.db.resp.valid) @[Decoupled.scala 21:42] - node T_1062 = and(T_1060, T_1061) @[Debug.scala 792:31] - node T_1063 = or(T_1059, T_1062) @[Debug.scala 791:67] - node T_1064 = and(T_1058, T_1063) @[Debug.scala 791:35] - io.db.req.ready <= T_1064 @[Debug.scala 791:19] - node T_1065 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 794:35] - io.db.resp.valid <= T_1065 @[Debug.scala 794:20] - io.db.resp.bits <- dbRespReg @[Debug.scala 795:20] - node T_1066 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 21:42] - dbRdEn <= T_1066 @[Debug.scala 797:10] - node T_1067 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 21:42] - node T_1068 = and(dbWrNeeded, T_1067) @[Debug.scala 798:24] - dbWrEn <= T_1068 @[Debug.scala 798:10] - node T_1069 = eq(dbStateReg, UInt<1>("h00")) @[Debug.scala 803:20] - when T_1069 : @[Debug.scala 803:35] - node T_1070 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 21:42] - when T_1070 : @[Debug.scala 804:28] - dbStateReg <= UInt<1>("h01") @[Debug.scala 805:18] - dbRespReg <- dbResult @[Debug.scala 806:17] - skip @[Debug.scala 804:28] - skip @[Debug.scala 803:35] - node T_1071 = eq(dbStateReg, UInt<1>("h01")) @[Debug.scala 808:27] - node T_1073 = eq(T_1069, UInt<1>("h00")) @[Debug.scala 803:35] - node T_1074 = and(T_1073, T_1071) @[Debug.scala 808:41] - when T_1074 : @[Debug.scala 808:41] - node T_1075 = and(io.db.req.ready, io.db.req.valid) @[Decoupled.scala 21:42] - when T_1075 : @[Debug.scala 809:28] - dbStateReg <= UInt<1>("h01") @[Debug.scala 810:18] - dbRespReg <- dbResult @[Debug.scala 811:17] - skip @[Debug.scala 809:28] - node T_1076 = and(io.db.resp.ready, io.db.resp.valid) @[Decoupled.scala 21:42] - node T_1078 = eq(T_1075, UInt<1>("h00")) @[Debug.scala 809:28] - node T_1079 = and(T_1078, T_1076) @[Debug.scala 812:35] - when T_1079 : @[Debug.scala 812:35] - dbStateReg <= UInt<1>("h00") @[Debug.scala 813:18] - skip @[Debug.scala 812:35] - skip @[Debug.scala 808:41] - sbRomRdData <= UInt<1>("h00") @[Debug.scala 822:15] - wire T_1101 : UInt<64>[15] @[Debug.scala 828:40] - T_1101 is invalid @[Debug.scala 828:40] - T_1101[0] <= UInt<64>("h0c0006f03c0006f") @[Debug.scala 828:40] - T_1101[1] <= UInt<64>("h080006ffff00413") @[Debug.scala 828:40] - T_1101[2] <= UInt<64>("h0ff0000f00000413") @[Debug.scala 828:40] - T_1101[3] <= UInt<64>("h042802e2343803483") @[Debug.scala 828:40] - T_1101[4] <= UInt<64>("h010802023f1402473") @[Debug.scala 828:40] - T_1101[5] <= UInt<64>("h08474137b002473") @[Debug.scala 828:40] - T_1101[6] <= UInt<64>("h07b20247302041a63") @[Debug.scala 828:40] - T_1101[7] <= UInt<64>("h07b2410737b200073") @[Debug.scala 828:40] - T_1101[8] <= UInt<64>("h01c0474137b002473") @[Debug.scala 828:40] - T_1101[9] <= UInt<64>("h041663f4040413") @[Debug.scala 828:40] - T_1101[10] <= UInt<64>("h04000006742903c23") @[Debug.scala 828:40] - T_1101[11] <= UInt<64>("h010802623f1402473") @[Debug.scala 828:40] - T_1101[12] <= UInt<64>("h07b0024737b046073") @[Debug.scala 828:40] - T_1101[13] <= UInt<64>("h0fe040ce302047413") @[Debug.scala 828:40] - T_1101[14] <= UInt<64>("h0fe1ff06f") @[Debug.scala 828:40] - wire T_1104 : UInt @[Debug.scala 833:27] - T_1104 is invalid @[Debug.scala 833:27] - node T_1105 = bits(sbAddr, 6, 3) @[Debug.scala 838:28] - T_1104 <= T_1105 @[Debug.scala 838:19] - sbRomRdData <= T_1101[T_1104] @[Debug.scala 840:17] - sbRamWrEn <= UInt<1>("h00") @[Debug.scala 851:14] - SETHALTNOTWrEn <= UInt<1>("h00") @[Debug.scala 852:18] - CLEARDEBINTWrEn <= UInt<1>("h00") @[Debug.scala 853:19] - node T_1109 = bits(sbWrData, 31, 0) @[Debug.scala 871:71] - node T_1110 = bits(sbWrData, 63, 32) @[Debug.scala 871:71] - wire T_1116 : UInt<32>[2] @[Debug.scala 871:56] - T_1116 is invalid @[Debug.scala 871:56] - T_1116[0] <= T_1109 @[Debug.scala 871:56] - T_1116[1] <= T_1110 @[Debug.scala 871:56] - node T_1118 = bits(sbWrMask, 31, 0) @[Debug.scala 872:72] - node T_1119 = bits(sbWrMask, 63, 32) @[Debug.scala 872:72] - wire T_1125 : UInt<32>[2] @[Debug.scala 872:56] - T_1125 is invalid @[Debug.scala 872:56] - T_1125[0] <= T_1118 @[Debug.scala 872:56] - T_1125[1] <= T_1119 @[Debug.scala 872:56] - SETHALTNOTWrData <= T_1116[UInt<1>("h01")] @[Debug.scala 877:23] - CLEARDEBINTWrData <= T_1116[UInt<1>("h00")] @[Debug.scala 878:23] - node T_1131 = bits(sbAddr, 11, 8) @[Debug.scala 880:17] - node T_1133 = eq(T_1131, UInt<3>("h04")) @[Debug.scala 880:24] - when T_1133 : @[Debug.scala 880:36] - sbRamWrEn <= sbWrEn @[Debug.scala 881:17] - sbRamRdEn <= sbRdEn @[Debug.scala 882:17] - skip @[Debug.scala 880:36] - node T_1134 = bits(sbAddr, 11, 3) @[Debug.scala 885:29] - node T_1137 = eq(T_1134, UInt<9>("h021")) @[Debug.scala 885:63] - node T_1141 = neq(T_1125[UInt<1>("h01")], UInt<1>("h00")) @[Debug.scala 886:60] - node T_1142 = and(T_1137, T_1141) @[Debug.scala 885:109] - node T_1143 = and(T_1142, sbWrEn) @[Debug.scala 886:64] - SETHALTNOTWrEn <= T_1143 @[Debug.scala 885:20] - node T_1144 = bits(sbAddr, 11, 3) @[Debug.scala 889:30] - node T_1147 = eq(T_1144, UInt<9>("h020")) @[Debug.scala 889:64] - node T_1151 = neq(T_1125[UInt<1>("h00")], UInt<1>("h00")) @[Debug.scala 890:61] - node T_1152 = and(T_1147, T_1151) @[Debug.scala 889:111] - node T_1153 = and(T_1152, sbWrEn) @[Debug.scala 890:65] - CLEARDEBINTWrEn <= T_1153 @[Debug.scala 889:21] - sbRdData <= UInt<1>("h00") @[Debug.scala 898:12] - sbRamRdEn <= UInt<1>("h00") @[Debug.scala 899:13] - dbRamRdEn <= UInt<1>("h00") @[Debug.scala 901:13] - node T_1157 = bits(sbAddr, 11, 8) @[Debug.scala 902:15] - node T_1159 = eq(T_1157, UInt<3>("h04")) @[Debug.scala 902:23] - when T_1159 : @[Debug.scala 902:36] - sbRdData <= sbRamRdData @[Debug.scala 903:15] - sbRamRdEn <= sbRdEn @[Debug.scala 904:15] - skip @[Debug.scala 902:36] - node T_1160 = bits(sbAddr, 11, 8) @[Debug.scala 905:21] - node T_1163 = eq(T_1160, UInt<4>("h08")) @[Package.scala 7:47] - node T_1164 = eq(T_1160, UInt<4>("h09")) @[Package.scala 7:47] - node T_1165 = or(T_1163, T_1164) @[Package.scala 7:62] - node T_1167 = eq(T_1159, UInt<1>("h00")) @[Debug.scala 902:36] - node T_1168 = and(T_1167, T_1165) @[Debug.scala 905:54] - when T_1168 : @[Debug.scala 905:54] - sbRdData <= sbRomRdData @[Debug.scala 907:16] - skip @[Debug.scala 905:54] - node T_1170 = eq(T_1159, UInt<1>("h00")) @[Debug.scala 902:36] - node T_1172 = eq(T_1165, UInt<1>("h00")) @[Debug.scala 905:54] - node T_1173 = and(T_1170, T_1172) @[Debug.scala 905:54] - when T_1173 : @[Debug.scala 911:16] - sbRdData <= UInt<1>("h00") @[Debug.scala 913:14] - skip @[Debug.scala 911:16] - reg sbAcqReg : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}, clk - reg sbAcqValidReg : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_1202 = eq(sbAcqReg.a_type, UInt<3>("h00")) @[Definitions.scala 212:64] - node sbReg_get = and(sbAcqReg.is_builtin_type, T_1202) @[Definitions.scala 212:54] - node T_1203 = eq(sbAcqReg.a_type, UInt<3>("h01")) @[Definitions.scala 212:64] - node sbReg_getblk = and(sbAcqReg.is_builtin_type, T_1203) @[Definitions.scala 212:54] - node T_1204 = eq(sbAcqReg.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node sbReg_put = and(sbAcqReg.is_builtin_type, T_1204) @[Definitions.scala 212:54] - node T_1205 = eq(sbAcqReg.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node sbReg_putblk = and(sbAcqReg.is_builtin_type, T_1205) @[Definitions.scala 212:54] - node sbMultibeat = and(sbReg_getblk, sbAcqValidReg) @[Debug.scala 926:34] - node T_1207 = add(sbAcqReg.addr_beat, UInt<1>("h01")) @[Debug.scala 928:39] - node sbBeatInc1 = tail(T_1207, 1) @[Debug.scala 928:39] - node sbLast = eq(sbAcqReg.addr_beat, UInt<3>("h07")) @[Debug.scala 930:36] - wire T_1216 : UInt<3>[2] @[Definitions.scala 357:30] - T_1216 is invalid @[Definitions.scala 357:30] - T_1216[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_1216[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_1218 = eq(sbAcqReg.a_type, T_1216[0]) @[Package.scala 7:47] - node T_1219 = eq(sbAcqReg.a_type, T_1216[1]) @[Package.scala 7:47] - node T_1220 = or(T_1218, T_1219) @[Package.scala 7:62] - node T_1221 = and(sbAcqReg.is_builtin_type, T_1220) @[Definitions.scala 300:27] - node T_1222 = bits(sbAcqReg.union, 10, 8) @[Definitions.scala 178:40] - node T_1224 = mux(T_1221, T_1222, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_1225 = cat(sbAcqReg.addr_block, sbAcqReg.addr_beat) @[Cat.scala 20:58] - node T_1226 = cat(T_1225, T_1224) @[Cat.scala 20:58] - sbAddr <= T_1226 @[Debug.scala 932:10] - node T_1227 = or(sbReg_get, sbReg_getblk) @[Debug.scala 933:42] - node T_1228 = and(sbAcqValidReg, T_1227) @[Debug.scala 933:28] - sbRdEn <= T_1228 @[Debug.scala 933:10] - node T_1229 = or(sbReg_put, sbReg_putblk) @[Debug.scala 934:42] - node T_1230 = and(sbAcqValidReg, T_1229) @[Debug.scala 934:28] - sbWrEn <= T_1230 @[Debug.scala 934:10] - sbWrData <= sbAcqReg.data @[Debug.scala 935:12] - node T_1232 = eq(sbAcqReg.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_1233 = and(sbAcqReg.is_builtin_type, T_1232) @[Definitions.scala 212:54] - node T_1250 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1252 = eq(sbAcqReg.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1253 = and(sbAcqReg.is_builtin_type, T_1252) @[Definitions.scala 212:54] - node T_1255 = eq(sbAcqReg.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1256 = and(sbAcqReg.is_builtin_type, T_1255) @[Definitions.scala 212:54] - node T_1257 = or(T_1253, T_1256) @[Definitions.scala 190:56] - node T_1258 = bits(sbAcqReg.union, 8, 1) @[Definitions.scala 191:25] - node T_1260 = mux(T_1257, T_1258, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_1261 = mux(T_1233, T_1250, T_1260) @[Definitions.scala 192:8] - node T_1262 = bits(T_1261, 0, 0) @[Bitwise.scala 13:51] - node T_1263 = bits(T_1261, 1, 1) @[Bitwise.scala 13:51] - node T_1264 = bits(T_1261, 2, 2) @[Bitwise.scala 13:51] - node T_1265 = bits(T_1261, 3, 3) @[Bitwise.scala 13:51] - node T_1266 = bits(T_1261, 4, 4) @[Bitwise.scala 13:51] - node T_1267 = bits(T_1261, 5, 5) @[Bitwise.scala 13:51] - node T_1268 = bits(T_1261, 6, 6) @[Bitwise.scala 13:51] - node T_1269 = bits(T_1261, 7, 7) @[Bitwise.scala 13:51] - node T_1270 = bits(T_1262, 0, 0) @[Bitwise.scala 33:15] - node T_1273 = mux(T_1270, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1274 = bits(T_1263, 0, 0) @[Bitwise.scala 33:15] - node T_1277 = mux(T_1274, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1278 = bits(T_1264, 0, 0) @[Bitwise.scala 33:15] - node T_1281 = mux(T_1278, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1282 = bits(T_1265, 0, 0) @[Bitwise.scala 33:15] - node T_1285 = mux(T_1282, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1286 = bits(T_1266, 0, 0) @[Bitwise.scala 33:15] - node T_1289 = mux(T_1286, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1290 = bits(T_1267, 0, 0) @[Bitwise.scala 33:15] - node T_1293 = mux(T_1290, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1294 = bits(T_1268, 0, 0) @[Bitwise.scala 33:15] - node T_1297 = mux(T_1294, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1298 = bits(T_1269, 0, 0) @[Bitwise.scala 33:15] - node T_1301 = mux(T_1298, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1302 = cat(T_1277, T_1273) @[Cat.scala 20:58] - node T_1303 = cat(T_1285, T_1281) @[Cat.scala 20:58] - node T_1304 = cat(T_1303, T_1302) @[Cat.scala 20:58] - node T_1305 = cat(T_1293, T_1289) @[Cat.scala 20:58] - node T_1306 = cat(T_1301, T_1297) @[Cat.scala 20:58] - node T_1307 = cat(T_1306, T_1305) @[Cat.scala 20:58] - node T_1308 = cat(T_1307, T_1304) @[Cat.scala 20:58] - sbWrMask <= T_1308 @[Debug.scala 936:12] - node T_1309 = and(io.tl.acquire.ready, io.tl.acquire.valid) @[Decoupled.scala 21:42] - when T_1309 : @[Debug.scala 941:30] - sbAcqReg <- io.tl.acquire.bits @[Debug.scala 942:20] - sbAcqValidReg <= UInt<1>("h01") @[Debug.scala 943:20] - skip @[Debug.scala 941:30] - node T_1311 = and(io.tl.grant.ready, io.tl.grant.valid) @[Decoupled.scala 21:42] - node T_1313 = eq(T_1309, UInt<1>("h00")) @[Debug.scala 941:30] - node T_1314 = and(T_1313, T_1311) @[Debug.scala 944:36] - when T_1314 : @[Debug.scala 944:36] - when sbMultibeat : @[Debug.scala 945:23] - sbAcqReg.addr_beat <= sbBeatInc1 @[Debug.scala 946:26] - when sbLast : @[Debug.scala 947:21] - sbAcqValidReg <= UInt<1>("h00") @[Debug.scala 948:23] - skip @[Debug.scala 947:21] - skip @[Debug.scala 945:23] - node T_1317 = eq(sbMultibeat, UInt<1>("h00")) @[Debug.scala 945:23] - when T_1317 : @[Debug.scala 950:19] - sbAcqValidReg <= UInt<1>("h00") @[Debug.scala 951:21] - skip @[Debug.scala 950:19] - skip @[Debug.scala 944:36] - io.tl.grant.valid <= sbAcqValidReg @[Debug.scala 956:21] - node T_1335 = eq(UInt<3>("h06"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1336 = mux(T_1335, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_1337 = eq(UInt<3>("h05"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1338 = mux(T_1337, UInt<3>("h01"), T_1336) @[Mux.scala 46:16] - node T_1339 = eq(UInt<3>("h04"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1340 = mux(T_1339, UInt<3>("h04"), T_1338) @[Mux.scala 46:16] - node T_1341 = eq(UInt<3>("h03"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1342 = mux(T_1341, UInt<3>("h03"), T_1340) @[Mux.scala 46:16] - node T_1343 = eq(UInt<3>("h02"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1344 = mux(T_1343, UInt<3>("h03"), T_1342) @[Mux.scala 46:16] - node T_1345 = eq(UInt<3>("h01"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1346 = mux(T_1345, UInt<3>("h05"), T_1344) @[Mux.scala 46:16] - node T_1347 = eq(UInt<3>("h00"), sbAcqReg.a_type) @[Mux.scala 46:19] - node T_1348 = mux(T_1347, UInt<3>("h04"), T_1346) @[Mux.scala 46:16] - wire T_1372 : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_1372 is invalid @[Definitions.scala 863:19] - T_1372.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_1372.g_type <= T_1348 @[Definitions.scala 865:16] - T_1372.client_xact_id <= sbAcqReg.client_xact_id @[Definitions.scala 866:24] - T_1372.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_1372.addr_beat <= sbAcqReg.addr_beat @[Definitions.scala 868:19] - T_1372.data <= sbRdData @[Definitions.scala 869:14] - io.tl.grant.bits <- T_1372 @[Debug.scala 957:20] - stallFromDb <= UInt<1>("h00") @[Debug.scala 966:15] - node T_1395 = or(sbRamRdEn, sbRamWrEn) @[Debug.scala 968:28] - stallFromSb <= T_1395 @[Debug.scala 968:15] - node T_1397 = eq(sbLast, UInt<1>("h00")) @[Debug.scala 972:32] - node T_1398 = and(sbMultibeat, T_1397) @[Debug.scala 972:30] - node T_1400 = eq(io.tl.grant.ready, UInt<1>("h00")) @[Debug.scala 972:67] - node T_1401 = and(io.tl.grant.valid, T_1400) @[Debug.scala 972:64] - node T_1402 = or(T_1398, T_1401) @[Debug.scala 972:41] - node sbStall = or(T_1402, stallFromDb) @[Debug.scala 972:87] - node T_1404 = eq(sbStall, UInt<1>("h00")) @[Debug.scala 974:26] - io.tl.acquire.ready <= T_1404 @[Debug.scala 974:23] - node T_1406 = neq(ndresetCtrReg, UInt<1>("h00")) @[Debug.scala 980:33] - io.ndreset <= T_1406 @[Debug.scala 980:16] - io.fullreset <= CONTROLReg.fullreset @[Debug.scala 981:16] - - module PRCI : + T_851 <= ramWrData + node T_852 = or(sbRamWrEn, dbRamWrEn) + ramWrEn <= T_852 + wire T_875 : { interrupt : UInt<1>, haltnot : UInt<1>, reserved0 : UInt<10>, buserror : UInt<3>, serial : UInt<3>, autoincrement : UInt<1>, access : UInt<3>, hartid : UInt<10>, ndreset : UInt<1>, fullreset : UInt<1>} + T_875 is invalid + node T_886 = bits(dbReq.data, 0, 0) + T_875.fullreset <= T_886 + node T_887 = bits(dbReq.data, 1, 1) + T_875.ndreset <= T_887 + node T_888 = bits(dbReq.data, 11, 2) + T_875.hartid <= T_888 + node T_889 = bits(dbReq.data, 14, 12) + T_875.access <= T_889 + node T_890 = bits(dbReq.data, 15, 15) + T_875.autoincrement <= T_890 + node T_891 = bits(dbReq.data, 18, 16) + T_875.serial <= T_891 + node T_892 = bits(dbReq.data, 21, 19) + T_875.buserror <= T_892 + node T_893 = bits(dbReq.data, 31, 22) + T_875.reserved0 <= T_893 + node T_894 = bits(dbReq.data, 32, 32) + T_875.haltnot <= T_894 + node T_895 = bits(dbReq.data, 33, 33) + T_875.interrupt <= T_895 + CONTROLWrData <- T_875 + wire T_904 : { interrupt : UInt<1>, haltnot : UInt<1>, data : UInt<32>} + T_904 is invalid + node T_908 = bits(dbReq.data, 31, 0) + T_904.data <= T_908 + node T_909 = bits(dbReq.data, 32, 32) + T_904.haltnot <= T_909 + node T_910 = bits(dbReq.data, 33, 33) + T_904.interrupt <= T_910 + RAMWrData <- T_904 + dbRamWrEn <= UInt<1>("h0") + CONTROLWrEn <= UInt<1>("h0") + node T_913 = shr(dbReq.addr, 4) + node T_915 = eq(T_913, UInt<1>("h0")) + when T_915 : + dbRamWrEn <= dbWrEn + node T_917 = eq(dbReq.addr, UInt<5>("h10")) + node T_919 = eq(T_915, UInt<1>("h0")) + node T_920 = and(T_919, T_917) + when T_920 : + CONTROLWrEn <= dbWrEn + node T_922 = eq(T_915, UInt<1>("h0")) + node T_924 = eq(T_917, UInt<1>("h0")) + node T_925 = and(T_922, T_924) + when T_925 : + skip + when reset : + CONTROLReg <- CONTROLReset + ndresetCtrReg <= UInt<1>("h0") + node T_928 = eq(reset, UInt<1>("h0")) + node T_929 = and(T_928, CONTROLWrEn) + when T_929 : + CONTROLReg.hartid <= CONTROLWrData.hartid + node T_930 = or(CONTROLReg.fullreset, CONTROLWrData.fullreset) + CONTROLReg.fullreset <= T_930 + when CONTROLWrData.ndreset : + ndresetCtrReg <= UInt<1>("h1") + node T_933 = eq(CONTROLWrData.ndreset, UInt<1>("h0")) + when T_933 : + node T_935 = eq(ndresetCtrReg, UInt<1>("h0")) + node T_938 = sub(ndresetCtrReg, UInt<1>("h1")) + node T_939 = tail(T_938, 1) + node T_940 = mux(T_935, UInt<1>("h0"), T_939) + ndresetCtrReg <= T_940 + node T_942 = eq(reset, UInt<1>("h0")) + node T_944 = eq(CONTROLWrEn, UInt<1>("h0")) + node T_945 = and(T_942, T_944) + when T_945 : + node T_947 = eq(ndresetCtrReg, UInt<1>("h0")) + node T_950 = sub(ndresetCtrReg, UInt<1>("h1")) + node T_951 = tail(T_950, 1) + node T_952 = mux(T_947, UInt<1>("h0"), T_951) + ndresetCtrReg <= T_952 + CONTROLRdData <- CONTROLReg + CONTROLRdData.interrupt <= interruptRegs[CONTROLReg.hartid] + CONTROLRdData.haltnot <= haltnotRegs[CONTROLReg.hartid] + node T_954 = neq(ndresetCtrReg, UInt<1>("h0")) + CONTROLRdData.ndreset <= T_954 + RAMRdData.interrupt <= interruptRegs[CONTROLReg.hartid] + RAMRdData.haltnot <= haltnotRegs[CONTROLReg.hartid] + RAMRdData.data <= dbRamRdData + dbRdData <= UInt<1>("h0") + rdHaltnotStatus <= UInt<1>("h0") + node T_958 = eq(dbReq.addr, UInt<1>("h0")) + when T_958 : + rdHaltnotStatus <= haltnotStatus[0] + dbRamRdEn <= UInt<1>("h0") + node T_960 = shr(dbReq.addr, 4) + node T_962 = eq(T_960, UInt<1>("h0")) + when T_962 : + node T_963 = cat(RAMRdData.interrupt, RAMRdData.haltnot) + node T_964 = cat(T_963, RAMRdData.data) + dbRdData <= T_964 + dbRamRdEn <= dbRdEn + node T_966 = eq(dbReq.addr, UInt<5>("h10")) + node T_968 = eq(T_962, UInt<1>("h0")) + node T_969 = and(T_968, T_966) + when T_969 : + node T_970 = cat(CONTROLRdData.ndreset, CONTROLRdData.fullreset) + node T_971 = cat(CONTROLRdData.autoincrement, CONTROLRdData.access) + node T_972 = cat(T_971, CONTROLRdData.hartid) + node T_973 = cat(T_972, T_970) + node T_974 = cat(CONTROLRdData.buserror, CONTROLRdData.serial) + node T_975 = cat(CONTROLRdData.interrupt, CONTROLRdData.haltnot) + node T_976 = cat(T_975, CONTROLRdData.reserved0) + node T_977 = cat(T_976, T_974) + node T_978 = cat(T_977, T_973) + dbRdData <= T_978 + node T_980 = eq(dbReq.addr, UInt<5>("h11")) + node T_982 = eq(T_962, UInt<1>("h0")) + node T_984 = eq(T_966, UInt<1>("h0")) + node T_985 = and(T_982, T_984) + node T_986 = and(T_985, T_980) + when T_986 : + node T_987 = cat(DMINFORdData.authbusy, DMINFORdData.authtype) + node T_988 = cat(T_987, DMINFORdData.version) + node T_989 = cat(DMINFORdData.reserved1, DMINFORdData.authenticated) + node T_990 = cat(DMINFORdData.dramsize, DMINFORdData.haltsum) + node T_991 = cat(T_990, T_989) + node T_992 = cat(T_991, T_988) + node T_993 = cat(DMINFORdData.access16, DMINFORdData.accesss8) + node T_994 = cat(DMINFORdData.access64, DMINFORdData.access32) + node T_995 = cat(T_994, T_993) + node T_996 = cat(DMINFORdData.serialcount, DMINFORdData.access128) + node T_997 = cat(DMINFORdData.reserved0, DMINFORdData.abussize) + node T_998 = cat(T_997, T_996) + node T_999 = cat(T_998, T_995) + node T_1000 = cat(T_999, T_992) + dbRdData <= T_1000 + node T_1002 = eq(dbReq.addr, UInt<5>("h1b")) + node T_1004 = eq(T_962, UInt<1>("h0")) + node T_1006 = eq(T_966, UInt<1>("h0")) + node T_1007 = and(T_1004, T_1006) + node T_1009 = eq(T_980, UInt<1>("h0")) + node T_1010 = and(T_1007, T_1009) + node T_1011 = and(T_1010, T_1002) + when T_1011 : + dbRdData <= UInt<1>("h0") + node T_1013 = shr(dbReq.addr, 2) + node T_1015 = eq(T_1013, UInt<3>("h7")) + node T_1017 = eq(T_962, UInt<1>("h0")) + node T_1019 = eq(T_966, UInt<1>("h0")) + node T_1020 = and(T_1017, T_1019) + node T_1022 = eq(T_980, UInt<1>("h0")) + node T_1023 = and(T_1020, T_1022) + node T_1025 = eq(T_1002, UInt<1>("h0")) + node T_1026 = and(T_1023, T_1025) + node T_1027 = and(T_1026, T_1015) + when T_1027 : + dbRdData <= rdHaltnotStatus + node T_1029 = eq(T_962, UInt<1>("h0")) + node T_1031 = eq(T_966, UInt<1>("h0")) + node T_1032 = and(T_1029, T_1031) + node T_1034 = eq(T_980, UInt<1>("h0")) + node T_1035 = and(T_1032, T_1034) + node T_1037 = eq(T_1002, UInt<1>("h0")) + node T_1038 = and(T_1035, T_1037) + node T_1040 = eq(T_1015, UInt<1>("h0")) + node T_1041 = and(T_1038, T_1040) + when T_1041 : + dbRdData <= UInt<1>("h0") + node T_1043 = bits(dbRdData, 33, 33) + node T_1045 = eq(dbReq.op, UInt<2>("h3")) + node T_1046 = and(T_1043, T_1045) + rdCondWrFailure <= T_1046 + node T_1048 = eq(dbReq.op, UInt<2>("h2")) + node T_1050 = eq(dbReq.op, UInt<2>("h3")) + node T_1051 = not(rdCondWrFailure) + node T_1052 = and(T_1050, T_1051) + node T_1053 = or(T_1048, T_1052) + dbWrNeeded <= T_1053 + node T_1056 = mux(rdCondWrFailure, UInt<2>("h1"), UInt<2>("h0")) + dbResult.resp <= T_1056 + dbResult.data <= dbRdData + node T_1058 = eq(stallFromSb, UInt<1>("h0")) + node T_1059 = eq(dbStateReg, UInt<1>("h0")) + node T_1060 = eq(dbStateReg, UInt<1>("h1")) + node T_1061 = and(io.db.resp.ready, io.db.resp.valid) + node T_1062 = and(T_1060, T_1061) + node T_1063 = or(T_1059, T_1062) + node T_1064 = and(T_1058, T_1063) + io.db.req.ready <= T_1064 + node T_1065 = eq(dbStateReg, UInt<1>("h1")) + io.db.resp.valid <= T_1065 + io.db.resp.bits <- dbRespReg + node T_1066 = and(io.db.req.ready, io.db.req.valid) + dbRdEn <= T_1066 + node T_1067 = and(io.db.req.ready, io.db.req.valid) + node T_1068 = and(dbWrNeeded, T_1067) + dbWrEn <= T_1068 + node T_1069 = eq(dbStateReg, UInt<1>("h0")) + when T_1069 : + node T_1070 = and(io.db.req.ready, io.db.req.valid) + when T_1070 : + dbStateReg <= UInt<1>("h1") + dbRespReg <- dbResult + node T_1071 = eq(dbStateReg, UInt<1>("h1")) + node T_1073 = eq(T_1069, UInt<1>("h0")) + node T_1074 = and(T_1073, T_1071) + when T_1074 : + node T_1075 = and(io.db.req.ready, io.db.req.valid) + when T_1075 : + dbStateReg <= UInt<1>("h1") + dbRespReg <- dbResult + node T_1076 = and(io.db.resp.ready, io.db.resp.valid) + node T_1078 = eq(T_1075, UInt<1>("h0")) + node T_1079 = and(T_1078, T_1076) + when T_1079 : + dbStateReg <= UInt<1>("h0") + sbRomRdData <= UInt<1>("h0") + wire T_1101 : UInt<64>[15] + T_1101 is invalid + T_1101[0] <= UInt<64>("hc0006f03c0006f") + T_1101[1] <= UInt<64>("h80006ffff00413") + T_1101[2] <= UInt<64>("hff0000f00000413") + T_1101[3] <= UInt<64>("h42802e2343803483") + T_1101[4] <= UInt<64>("h10802023f1402473") + T_1101[5] <= UInt<64>("h8474137b002473") + T_1101[6] <= UInt<64>("h7b20247302041a63") + T_1101[7] <= UInt<64>("h7b2410737b200073") + T_1101[8] <= UInt<64>("h1c0474137b002473") + T_1101[9] <= UInt<64>("h41663f4040413") + T_1101[10] <= UInt<64>("h4000006742903c23") + T_1101[11] <= UInt<64>("h10802623f1402473") + T_1101[12] <= UInt<64>("h7b0024737b046073") + T_1101[13] <= UInt<64>("hfe040ce302047413") + T_1101[14] <= UInt<64>("hfe1ff06f") + wire T_1104 : UInt + T_1104 is invalid + node T_1105 = bits(sbAddr, 6, 3) + T_1104 <= T_1105 + sbRomRdData <= T_1101[T_1104] + sbRamWrEn <= UInt<1>("h0") + SETHALTNOTWrEn <= UInt<1>("h0") + CLEARDEBINTWrEn <= UInt<1>("h0") + node T_1109 = bits(sbWrData, 31, 0) + node T_1110 = bits(sbWrData, 63, 32) + wire T_1116 : UInt<32>[2] + T_1116 is invalid + T_1116[0] <= T_1109 + T_1116[1] <= T_1110 + node T_1118 = bits(sbWrMask, 31, 0) + node T_1119 = bits(sbWrMask, 63, 32) + wire T_1125 : UInt<32>[2] + T_1125 is invalid + T_1125[0] <= T_1118 + T_1125[1] <= T_1119 + SETHALTNOTWrData <= T_1116[UInt<1>("h1")] + CLEARDEBINTWrData <= T_1116[UInt<1>("h0")] + node T_1131 = bits(sbAddr, 11, 8) + node T_1133 = eq(T_1131, UInt<3>("h4")) + when T_1133 : + sbRamWrEn <= sbWrEn + sbRamRdEn <= sbRdEn + node T_1134 = bits(sbAddr, 11, 3) + node T_1137 = eq(T_1134, UInt<9>("h21")) + node T_1141 = neq(T_1125[UInt<1>("h1")], UInt<1>("h0")) + node T_1142 = and(T_1137, T_1141) + node T_1143 = and(T_1142, sbWrEn) + SETHALTNOTWrEn <= T_1143 + node T_1144 = bits(sbAddr, 11, 3) + node T_1147 = eq(T_1144, UInt<9>("h20")) + node T_1151 = neq(T_1125[UInt<1>("h0")], UInt<1>("h0")) + node T_1152 = and(T_1147, T_1151) + node T_1153 = and(T_1152, sbWrEn) + CLEARDEBINTWrEn <= T_1153 + sbRdData <= UInt<1>("h0") + sbRamRdEn <= UInt<1>("h0") + dbRamRdEn <= UInt<1>("h0") + node T_1157 = bits(sbAddr, 11, 8) + node T_1159 = eq(T_1157, UInt<3>("h4")) + when T_1159 : + sbRdData <= sbRamRdData + sbRamRdEn <= sbRdEn + node T_1160 = bits(sbAddr, 11, 8) + node T_1163 = eq(T_1160, UInt<4>("h8")) + node T_1164 = eq(T_1160, UInt<4>("h9")) + node T_1165 = or(T_1163, T_1164) + node T_1167 = eq(T_1159, UInt<1>("h0")) + node T_1168 = and(T_1167, T_1165) + when T_1168 : + sbRdData <= sbRomRdData + node T_1170 = eq(T_1159, UInt<1>("h0")) + node T_1172 = eq(T_1165, UInt<1>("h0")) + node T_1173 = and(T_1170, T_1172) + when T_1173 : + sbRdData <= UInt<1>("h0") + reg sbAcqReg : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}, clk with : + reset => (UInt<1>("h0"), sbAcqReg) + reg sbAcqValidReg : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_1202 = eq(sbAcqReg.a_type, UInt<3>("h0")) + node sbReg_get = and(sbAcqReg.is_builtin_type, T_1202) + node T_1203 = eq(sbAcqReg.a_type, UInt<3>("h1")) + node sbReg_getblk = and(sbAcqReg.is_builtin_type, T_1203) + node T_1204 = eq(sbAcqReg.a_type, UInt<3>("h2")) + node sbReg_put = and(sbAcqReg.is_builtin_type, T_1204) + node T_1205 = eq(sbAcqReg.a_type, UInt<3>("h3")) + node sbReg_putblk = and(sbAcqReg.is_builtin_type, T_1205) + node sbMultibeat = and(sbReg_getblk, sbAcqValidReg) + node T_1207 = add(sbAcqReg.addr_beat, UInt<1>("h1")) + node sbBeatInc1 = tail(T_1207, 1) + node sbLast = eq(sbAcqReg.addr_beat, UInt<3>("h7")) + wire T_1216 : UInt<3>[2] + T_1216 is invalid + T_1216[0] <= UInt<3>("h0") + T_1216[1] <= UInt<3>("h4") + node T_1218 = eq(sbAcqReg.a_type, T_1216[0]) + node T_1219 = eq(sbAcqReg.a_type, T_1216[1]) + node T_1220 = or(T_1218, T_1219) + node T_1221 = and(sbAcqReg.is_builtin_type, T_1220) + node T_1222 = bits(sbAcqReg.union, 10, 8) + node T_1224 = mux(T_1221, T_1222, UInt<3>("h0")) + node T_1225 = cat(sbAcqReg.addr_block, sbAcqReg.addr_beat) + node T_1226 = cat(T_1225, T_1224) + sbAddr <= T_1226 + node T_1227 = or(sbReg_get, sbReg_getblk) + node T_1228 = and(sbAcqValidReg, T_1227) + sbRdEn <= T_1228 + node T_1229 = or(sbReg_put, sbReg_putblk) + node T_1230 = and(sbAcqValidReg, T_1229) + sbWrEn <= T_1230 + sbWrData <= sbAcqReg.data + node T_1232 = eq(sbAcqReg.a_type, UInt<3>("h4")) + node T_1233 = and(sbAcqReg.is_builtin_type, T_1232) + node T_1250 = asUInt(asSInt(UInt<8>("hff"))) + node T_1252 = eq(sbAcqReg.a_type, UInt<3>("h3")) + node T_1253 = and(sbAcqReg.is_builtin_type, T_1252) + node T_1255 = eq(sbAcqReg.a_type, UInt<3>("h2")) + node T_1256 = and(sbAcqReg.is_builtin_type, T_1255) + node T_1257 = or(T_1253, T_1256) + node T_1258 = bits(sbAcqReg.union, 8, 1) + node T_1260 = mux(T_1257, T_1258, UInt<1>("h0")) + node T_1261 = mux(T_1233, T_1250, T_1260) + node T_1262 = bits(T_1261, 0, 0) + node T_1263 = bits(T_1261, 1, 1) + node T_1264 = bits(T_1261, 2, 2) + node T_1265 = bits(T_1261, 3, 3) + node T_1266 = bits(T_1261, 4, 4) + node T_1267 = bits(T_1261, 5, 5) + node T_1268 = bits(T_1261, 6, 6) + node T_1269 = bits(T_1261, 7, 7) + node T_1270 = bits(T_1262, 0, 0) + node T_1273 = mux(T_1270, UInt<8>("hff"), UInt<8>("h0")) + node T_1274 = bits(T_1263, 0, 0) + node T_1277 = mux(T_1274, UInt<8>("hff"), UInt<8>("h0")) + node T_1278 = bits(T_1264, 0, 0) + node T_1281 = mux(T_1278, UInt<8>("hff"), UInt<8>("h0")) + node T_1282 = bits(T_1265, 0, 0) + node T_1285 = mux(T_1282, UInt<8>("hff"), UInt<8>("h0")) + node T_1286 = bits(T_1266, 0, 0) + node T_1289 = mux(T_1286, UInt<8>("hff"), UInt<8>("h0")) + node T_1290 = bits(T_1267, 0, 0) + node T_1293 = mux(T_1290, UInt<8>("hff"), UInt<8>("h0")) + node T_1294 = bits(T_1268, 0, 0) + node T_1297 = mux(T_1294, UInt<8>("hff"), UInt<8>("h0")) + node T_1298 = bits(T_1269, 0, 0) + node T_1301 = mux(T_1298, UInt<8>("hff"), UInt<8>("h0")) + node T_1302 = cat(T_1277, T_1273) + node T_1303 = cat(T_1285, T_1281) + node T_1304 = cat(T_1303, T_1302) + node T_1305 = cat(T_1293, T_1289) + node T_1306 = cat(T_1301, T_1297) + node T_1307 = cat(T_1306, T_1305) + node T_1308 = cat(T_1307, T_1304) + sbWrMask <= T_1308 + node T_1309 = and(io.tl.acquire.ready, io.tl.acquire.valid) + when T_1309 : + sbAcqReg <- io.tl.acquire.bits + sbAcqValidReg <= UInt<1>("h1") + node T_1311 = and(io.tl.grant.ready, io.tl.grant.valid) + node T_1313 = eq(T_1309, UInt<1>("h0")) + node T_1314 = and(T_1313, T_1311) + when T_1314 : + when sbMultibeat : + sbAcqReg.addr_beat <= sbBeatInc1 + when sbLast : + sbAcqValidReg <= UInt<1>("h0") + node T_1317 = eq(sbMultibeat, UInt<1>("h0")) + when T_1317 : + sbAcqValidReg <= UInt<1>("h0") + io.tl.grant.valid <= sbAcqValidReg + node T_1335 = eq(UInt<3>("h6"), sbAcqReg.a_type) + node T_1336 = mux(T_1335, UInt<3>("h1"), UInt<3>("h3")) + node T_1337 = eq(UInt<3>("h5"), sbAcqReg.a_type) + node T_1338 = mux(T_1337, UInt<3>("h1"), T_1336) + node T_1339 = eq(UInt<3>("h4"), sbAcqReg.a_type) + node T_1340 = mux(T_1339, UInt<3>("h4"), T_1338) + node T_1341 = eq(UInt<3>("h3"), sbAcqReg.a_type) + node T_1342 = mux(T_1341, UInt<3>("h3"), T_1340) + node T_1343 = eq(UInt<3>("h2"), sbAcqReg.a_type) + node T_1344 = mux(T_1343, UInt<3>("h3"), T_1342) + node T_1345 = eq(UInt<3>("h1"), sbAcqReg.a_type) + node T_1346 = mux(T_1345, UInt<3>("h5"), T_1344) + node T_1347 = eq(UInt<3>("h0"), sbAcqReg.a_type) + node T_1348 = mux(T_1347, UInt<3>("h4"), T_1346) + wire T_1372 : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1372 is invalid + T_1372.is_builtin_type <= UInt<1>("h1") + T_1372.g_type <= T_1348 + T_1372.client_xact_id <= sbAcqReg.client_xact_id + T_1372.manager_xact_id <= UInt<1>("h0") + T_1372.addr_beat <= sbAcqReg.addr_beat + T_1372.data <= sbRdData + io.tl.grant.bits <- T_1372 + stallFromDb <= UInt<1>("h0") + node T_1395 = or(sbRamRdEn, sbRamWrEn) + stallFromSb <= T_1395 + node T_1397 = eq(sbLast, UInt<1>("h0")) + node T_1398 = and(sbMultibeat, T_1397) + node T_1400 = eq(io.tl.grant.ready, UInt<1>("h0")) + node T_1401 = and(io.tl.grant.valid, T_1400) + node T_1402 = or(T_1398, T_1401) + node sbStall = or(T_1402, stallFromDb) + node T_1404 = eq(sbStall, UInt<1>("h0")) + io.tl.acquire.ready <= T_1404 + node T_1406 = neq(ndresetCtrReg, UInt<1>("h0")) + io.ndreset <= T_1406 + io.fullreset <= CONTROLReg.fullreset + + module PRCI : input clk : Clock input reset : UInt<1> - output io : {flip interrupts : {meip : UInt<1>, seip : UInt<1>, debug : UInt<1>}[1], flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, tiles : {reset : UInt<1>, id : UInt<1>, interrupts : {meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}[1], flip rtcTick : UInt<1>} - + output io : { flip interrupts : { meip : UInt<1>, seip : UInt<1>, debug : UInt<1>}[1], flip tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, tiles : { reset : UInt<1>, id : UInt<1>, interrupts : { meip : UInt<1>, seip : UInt<1>, debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>}}[1], flip rtcTick : UInt<1>} + io is invalid - reg timecmp : UInt<64>[1], clk - reg time : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) - when io.rtcTick : @[Prci.scala 59:21] - node T_525 = add(time, UInt<1>("h01")) @[Prci.scala 59:36] - node T_526 = tail(T_525, 1) @[Prci.scala 59:36] - time <= T_526 @[Prci.scala 59:28] - skip @[Prci.scala 59:21] - wire T_533 : UInt<32>[1] @[Prci.scala 61:41] - T_533 is invalid @[Prci.scala 61:41] - T_533[0] <= UInt<32>("h00") @[Prci.scala 61:41] - reg ipi : UInt<32>[1], clk with : (reset => (reset, T_533)) - inst acq of Queue_17 @[Decoupled.scala 228:19] + reg timecmp : UInt<64>[1], clk with : + reset => (UInt<1>("h0"), timecmp) + reg time : UInt<64>, clk with : + reset => (reset, UInt<64>("h0")) + when io.rtcTick : + node T_525 = add(time, UInt<1>("h1")) + node T_526 = tail(T_525, 1) + time <= T_526 + wire T_533 : UInt<32>[1] + T_533 is invalid + T_533[0] <= UInt<32>("h0") + reg ipi : UInt<32>[1], clk with : + reset => (reset, T_533) + inst acq of Queue_17 acq.io is invalid acq.clk <= clk acq.reset <= reset - acq.io.enq.valid <= io.tl.acquire.valid @[Decoupled.scala 229:20] - acq.io.enq.bits <- io.tl.acquire.bits @[Decoupled.scala 230:19] - io.tl.acquire.ready <= acq.io.enq.ready @[Decoupled.scala 231:15] - wire T_568 : UInt<3>[2] @[Definitions.scala 357:30] - T_568 is invalid @[Definitions.scala 357:30] - T_568[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_568[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_570 = eq(acq.io.deq.bits.a_type, T_568[0]) @[Package.scala 7:47] - node T_571 = eq(acq.io.deq.bits.a_type, T_568[1]) @[Package.scala 7:47] - node T_572 = or(T_570, T_571) @[Package.scala 7:62] - node T_573 = and(acq.io.deq.bits.is_builtin_type, T_572) @[Definitions.scala 300:27] - node T_574 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_576 = mux(T_573, T_574, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_577 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_578 = cat(T_577, T_576) @[Cat.scala 20:58] - node addr = bits(T_578, 15, 0) @[Prci.scala 64:34] - node T_580 = eq(acq.io.deq.bits.a_type, UInt<3>("h00")) @[Definitions.scala 212:64] - node read = and(acq.io.deq.bits.is_builtin_type, T_580) @[Definitions.scala 212:54] + acq.io.enq.valid <= io.tl.acquire.valid + acq.io.enq.bits <- io.tl.acquire.bits + io.tl.acquire.ready <= acq.io.enq.ready + wire T_568 : UInt<3>[2] + T_568 is invalid + T_568[0] <= UInt<3>("h0") + T_568[1] <= UInt<3>("h4") + node T_570 = eq(acq.io.deq.bits.a_type, T_568[0]) + node T_571 = eq(acq.io.deq.bits.a_type, T_568[1]) + node T_572 = or(T_570, T_571) + node T_573 = and(acq.io.deq.bits.is_builtin_type, T_572) + node T_574 = bits(acq.io.deq.bits.union, 10, 8) + node T_576 = mux(T_573, T_574, UInt<3>("h0")) + node T_577 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_578 = cat(T_577, T_576) + node addr = bits(T_578, 15, 0) + node T_580 = eq(acq.io.deq.bits.a_type, UInt<3>("h0")) + node read = and(acq.io.deq.bits.is_builtin_type, T_580) wire rdata : UInt rdata is invalid - rdata <= UInt<1>("h00") - io.tl.grant.valid <= acq.io.deq.valid @[Prci.scala 67:21] - acq.io.deq.ready <= io.tl.grant.ready @[Prci.scala 68:13] - node T_598 = eq(UInt<3>("h06"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_599 = mux(T_598, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_600 = eq(UInt<3>("h05"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_601 = mux(T_600, UInt<3>("h01"), T_599) @[Mux.scala 46:16] - node T_602 = eq(UInt<3>("h04"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_603 = mux(T_602, UInt<3>("h04"), T_601) @[Mux.scala 46:16] - node T_604 = eq(UInt<3>("h03"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_605 = mux(T_604, UInt<3>("h03"), T_603) @[Mux.scala 46:16] - node T_606 = eq(UInt<3>("h02"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_607 = mux(T_606, UInt<3>("h03"), T_605) @[Mux.scala 46:16] - node T_608 = eq(UInt<3>("h01"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_609 = mux(T_608, UInt<3>("h05"), T_607) @[Mux.scala 46:16] - node T_610 = eq(UInt<3>("h00"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_611 = mux(T_610, UInt<3>("h04"), T_609) @[Mux.scala 46:16] - wire T_636 : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_636 is invalid @[Definitions.scala 863:19] - T_636.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_636.g_type <= T_611 @[Definitions.scala 865:16] - T_636.client_xact_id <= acq.io.deq.bits.client_xact_id @[Definitions.scala 866:24] - T_636.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_636.addr_beat <= UInt<1>("h00") @[Definitions.scala 868:19] - T_636.data <= rdata @[Definitions.scala 869:14] - io.tl.grant.bits <- T_636 @[Prci.scala 69:20] - node T_658 = bits(addr, 15, 15) @[Prci.scala 77:13] - when T_658 : @[Prci.scala 77:37] - node T_659 = and(io.tl.grant.ready, io.tl.grant.valid) @[Decoupled.scala 21:42] - wire T_667 : UInt<3>[2] @[Definitions.scala 357:30] - T_667 is invalid @[Definitions.scala 357:30] - T_667[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_667[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_669 = eq(acq.io.deq.bits.a_type, T_667[0]) @[Package.scala 7:47] - node T_670 = eq(acq.io.deq.bits.a_type, T_667[1]) @[Package.scala 7:47] - node T_671 = or(T_669, T_670) @[Package.scala 7:62] - node T_672 = and(acq.io.deq.bits.is_builtin_type, T_671) @[Definitions.scala 300:27] - node T_673 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_675 = mux(T_672, T_673, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_676 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_677 = cat(T_676, T_675) @[Cat.scala 20:58] - wire T_685 : UInt<3>[2] @[Definitions.scala 357:30] - T_685 is invalid @[Definitions.scala 357:30] - T_685[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_685[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_687 = eq(acq.io.deq.bits.a_type, T_685[0]) @[Package.scala 7:47] - node T_688 = eq(acq.io.deq.bits.a_type, T_685[1]) @[Package.scala 7:47] - node T_689 = or(T_687, T_688) @[Package.scala 7:62] - node T_690 = and(acq.io.deq.bits.is_builtin_type, T_689) @[Definitions.scala 300:27] - node T_691 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_693 = mux(T_690, T_691, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_694 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_695 = cat(T_694, T_693) @[Cat.scala 20:58] - node T_697 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_698 = and(acq.io.deq.bits.is_builtin_type, T_697) @[Definitions.scala 212:54] - node T_715 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_717 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_718 = and(acq.io.deq.bits.is_builtin_type, T_717) @[Definitions.scala 212:54] - node T_720 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_721 = and(acq.io.deq.bits.is_builtin_type, T_720) @[Definitions.scala 212:54] - node T_722 = or(T_718, T_721) @[Definitions.scala 190:56] - node T_723 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_725 = mux(T_722, T_723, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_726 = mux(T_698, T_715, T_725) @[Definitions.scala 192:8] - node T_727 = bits(T_726, 0, 0) @[Bitwise.scala 13:51] - node T_728 = bits(T_726, 1, 1) @[Bitwise.scala 13:51] - node T_729 = bits(T_726, 2, 2) @[Bitwise.scala 13:51] - node T_730 = bits(T_726, 3, 3) @[Bitwise.scala 13:51] - node T_731 = bits(T_726, 4, 4) @[Bitwise.scala 13:51] - node T_732 = bits(T_726, 5, 5) @[Bitwise.scala 13:51] - node T_733 = bits(T_726, 6, 6) @[Bitwise.scala 13:51] - node T_734 = bits(T_726, 7, 7) @[Bitwise.scala 13:51] - node T_735 = bits(T_727, 0, 0) @[Bitwise.scala 33:15] - node T_738 = mux(T_735, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_739 = bits(T_728, 0, 0) @[Bitwise.scala 33:15] - node T_742 = mux(T_739, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_743 = bits(T_729, 0, 0) @[Bitwise.scala 33:15] - node T_746 = mux(T_743, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_747 = bits(T_730, 0, 0) @[Bitwise.scala 33:15] - node T_750 = mux(T_747, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_751 = bits(T_731, 0, 0) @[Bitwise.scala 33:15] - node T_754 = mux(T_751, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_755 = bits(T_732, 0, 0) @[Bitwise.scala 33:15] - node T_758 = mux(T_755, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_759 = bits(T_733, 0, 0) @[Bitwise.scala 33:15] - node T_762 = mux(T_759, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_763 = bits(T_734, 0, 0) @[Bitwise.scala 33:15] - node T_766 = mux(T_763, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_767 = cat(T_742, T_738) @[Cat.scala 20:58] - node T_768 = cat(T_750, T_746) @[Cat.scala 20:58] - node T_769 = cat(T_768, T_767) @[Cat.scala 20:58] - node T_770 = cat(T_758, T_754) @[Cat.scala 20:58] - node T_771 = cat(T_766, T_762) @[Cat.scala 20:58] - node T_772 = cat(T_771, T_770) @[Cat.scala 20:58] - node T_773 = cat(T_772, T_769) @[Cat.scala 20:58] - node T_774 = and(acq.io.deq.bits.data, T_773) @[Prci.scala 113:27] - node T_776 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_777 = and(acq.io.deq.bits.is_builtin_type, T_776) @[Definitions.scala 212:54] - node T_794 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_796 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_797 = and(acq.io.deq.bits.is_builtin_type, T_796) @[Definitions.scala 212:54] - node T_799 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_800 = and(acq.io.deq.bits.is_builtin_type, T_799) @[Definitions.scala 212:54] - node T_801 = or(T_797, T_800) @[Definitions.scala 190:56] - node T_802 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_804 = mux(T_801, T_802, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_805 = mux(T_777, T_794, T_804) @[Definitions.scala 192:8] - node T_806 = bits(T_805, 0, 0) @[Bitwise.scala 13:51] - node T_807 = bits(T_805, 1, 1) @[Bitwise.scala 13:51] - node T_808 = bits(T_805, 2, 2) @[Bitwise.scala 13:51] - node T_809 = bits(T_805, 3, 3) @[Bitwise.scala 13:51] - node T_810 = bits(T_805, 4, 4) @[Bitwise.scala 13:51] - node T_811 = bits(T_805, 5, 5) @[Bitwise.scala 13:51] - node T_812 = bits(T_805, 6, 6) @[Bitwise.scala 13:51] - node T_813 = bits(T_805, 7, 7) @[Bitwise.scala 13:51] - node T_814 = bits(T_806, 0, 0) @[Bitwise.scala 33:15] - node T_817 = mux(T_814, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_818 = bits(T_807, 0, 0) @[Bitwise.scala 33:15] - node T_821 = mux(T_818, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_822 = bits(T_808, 0, 0) @[Bitwise.scala 33:15] - node T_825 = mux(T_822, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_826 = bits(T_809, 0, 0) @[Bitwise.scala 33:15] - node T_829 = mux(T_826, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_830 = bits(T_810, 0, 0) @[Bitwise.scala 33:15] - node T_833 = mux(T_830, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_834 = bits(T_811, 0, 0) @[Bitwise.scala 33:15] - node T_837 = mux(T_834, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_838 = bits(T_812, 0, 0) @[Bitwise.scala 33:15] - node T_841 = mux(T_838, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_842 = bits(T_813, 0, 0) @[Bitwise.scala 33:15] - node T_845 = mux(T_842, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_846 = cat(T_821, T_817) @[Cat.scala 20:58] - node T_847 = cat(T_829, T_825) @[Cat.scala 20:58] - node T_848 = cat(T_847, T_846) @[Cat.scala 20:58] - node T_849 = cat(T_837, T_833) @[Cat.scala 20:58] - node T_850 = cat(T_845, T_841) @[Cat.scala 20:58] - node T_851 = cat(T_850, T_849) @[Cat.scala 20:58] - node T_852 = cat(T_851, T_848) @[Cat.scala 20:58] - node T_853 = not(T_852) @[Prci.scala 113:58] - node T_854 = and(time, T_853) @[Prci.scala 113:56] - node T_855 = or(T_774, T_854) @[Prci.scala 113:47] - node T_857 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_858 = and(acq.io.deq.bits.is_builtin_type, T_857) @[Definitions.scala 212:54] - node T_859 = and(T_659, T_858) @[Prci.scala 114:14] - when T_859 : @[Prci.scala 114:53] - node T_862 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Prci.scala 119:46] - when T_862 : @[Prci.scala 119:68] - node T_863 = shr(T_855, 0) @[Prci.scala 121:25] - time <= T_863 @[Prci.scala 121:16] - skip @[Prci.scala 119:68] - skip @[Prci.scala 114:53] - rdata <= time @[Prci.scala 79:11] - skip @[Prci.scala 77:37] - node T_865 = geq(addr, UInt<15>("h04000")) @[Prci.scala 80:20] - node T_867 = eq(T_658, UInt<1>("h00")) @[Prci.scala 77:37] - node T_868 = and(T_867, T_865) @[Prci.scala 80:40] - when T_868 : @[Prci.scala 80:40] - node T_869 = and(io.tl.grant.ready, io.tl.grant.valid) @[Decoupled.scala 21:42] - wire T_877 : UInt<3>[2] @[Definitions.scala 357:30] - T_877 is invalid @[Definitions.scala 357:30] - T_877[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_877[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_879 = eq(acq.io.deq.bits.a_type, T_877[0]) @[Package.scala 7:47] - node T_880 = eq(acq.io.deq.bits.a_type, T_877[1]) @[Package.scala 7:47] - node T_881 = or(T_879, T_880) @[Package.scala 7:62] - node T_882 = and(acq.io.deq.bits.is_builtin_type, T_881) @[Definitions.scala 300:27] - node T_883 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_885 = mux(T_882, T_883, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_886 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_887 = cat(T_886, T_885) @[Cat.scala 20:58] - wire T_895 : UInt<3>[2] @[Definitions.scala 357:30] - T_895 is invalid @[Definitions.scala 357:30] - T_895[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_895[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_897 = eq(acq.io.deq.bits.a_type, T_895[0]) @[Package.scala 7:47] - node T_898 = eq(acq.io.deq.bits.a_type, T_895[1]) @[Package.scala 7:47] - node T_899 = or(T_897, T_898) @[Package.scala 7:62] - node T_900 = and(acq.io.deq.bits.is_builtin_type, T_899) @[Definitions.scala 300:27] - node T_901 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_903 = mux(T_900, T_901, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_904 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_905 = cat(T_904, T_903) @[Cat.scala 20:58] - node T_907 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_908 = and(acq.io.deq.bits.is_builtin_type, T_907) @[Definitions.scala 212:54] - node T_925 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_927 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_928 = and(acq.io.deq.bits.is_builtin_type, T_927) @[Definitions.scala 212:54] - node T_930 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_931 = and(acq.io.deq.bits.is_builtin_type, T_930) @[Definitions.scala 212:54] - node T_932 = or(T_928, T_931) @[Definitions.scala 190:56] - node T_933 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_935 = mux(T_932, T_933, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_936 = mux(T_908, T_925, T_935) @[Definitions.scala 192:8] - node T_937 = bits(T_936, 0, 0) @[Bitwise.scala 13:51] - node T_938 = bits(T_936, 1, 1) @[Bitwise.scala 13:51] - node T_939 = bits(T_936, 2, 2) @[Bitwise.scala 13:51] - node T_940 = bits(T_936, 3, 3) @[Bitwise.scala 13:51] - node T_941 = bits(T_936, 4, 4) @[Bitwise.scala 13:51] - node T_942 = bits(T_936, 5, 5) @[Bitwise.scala 13:51] - node T_943 = bits(T_936, 6, 6) @[Bitwise.scala 13:51] - node T_944 = bits(T_936, 7, 7) @[Bitwise.scala 13:51] - node T_945 = bits(T_937, 0, 0) @[Bitwise.scala 33:15] - node T_948 = mux(T_945, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_949 = bits(T_938, 0, 0) @[Bitwise.scala 33:15] - node T_952 = mux(T_949, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_953 = bits(T_939, 0, 0) @[Bitwise.scala 33:15] - node T_956 = mux(T_953, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_957 = bits(T_940, 0, 0) @[Bitwise.scala 33:15] - node T_960 = mux(T_957, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_961 = bits(T_941, 0, 0) @[Bitwise.scala 33:15] - node T_964 = mux(T_961, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_965 = bits(T_942, 0, 0) @[Bitwise.scala 33:15] - node T_968 = mux(T_965, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_969 = bits(T_943, 0, 0) @[Bitwise.scala 33:15] - node T_972 = mux(T_969, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_973 = bits(T_944, 0, 0) @[Bitwise.scala 33:15] - node T_976 = mux(T_973, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_977 = cat(T_952, T_948) @[Cat.scala 20:58] - node T_978 = cat(T_960, T_956) @[Cat.scala 20:58] - node T_979 = cat(T_978, T_977) @[Cat.scala 20:58] - node T_980 = cat(T_968, T_964) @[Cat.scala 20:58] - node T_981 = cat(T_976, T_972) @[Cat.scala 20:58] - node T_982 = cat(T_981, T_980) @[Cat.scala 20:58] - node T_983 = cat(T_982, T_979) @[Cat.scala 20:58] - node T_984 = and(acq.io.deq.bits.data, T_983) @[Prci.scala 113:27] - node T_986 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_987 = and(acq.io.deq.bits.is_builtin_type, T_986) @[Definitions.scala 212:54] - node T_1004 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1006 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1007 = and(acq.io.deq.bits.is_builtin_type, T_1006) @[Definitions.scala 212:54] - node T_1009 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1010 = and(acq.io.deq.bits.is_builtin_type, T_1009) @[Definitions.scala 212:54] - node T_1011 = or(T_1007, T_1010) @[Definitions.scala 190:56] - node T_1012 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_1014 = mux(T_1011, T_1012, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_1015 = mux(T_987, T_1004, T_1014) @[Definitions.scala 192:8] - node T_1016 = bits(T_1015, 0, 0) @[Bitwise.scala 13:51] - node T_1017 = bits(T_1015, 1, 1) @[Bitwise.scala 13:51] - node T_1018 = bits(T_1015, 2, 2) @[Bitwise.scala 13:51] - node T_1019 = bits(T_1015, 3, 3) @[Bitwise.scala 13:51] - node T_1020 = bits(T_1015, 4, 4) @[Bitwise.scala 13:51] - node T_1021 = bits(T_1015, 5, 5) @[Bitwise.scala 13:51] - node T_1022 = bits(T_1015, 6, 6) @[Bitwise.scala 13:51] - node T_1023 = bits(T_1015, 7, 7) @[Bitwise.scala 13:51] - node T_1024 = bits(T_1016, 0, 0) @[Bitwise.scala 33:15] - node T_1027 = mux(T_1024, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1028 = bits(T_1017, 0, 0) @[Bitwise.scala 33:15] - node T_1031 = mux(T_1028, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1032 = bits(T_1018, 0, 0) @[Bitwise.scala 33:15] - node T_1035 = mux(T_1032, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1036 = bits(T_1019, 0, 0) @[Bitwise.scala 33:15] - node T_1039 = mux(T_1036, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1040 = bits(T_1020, 0, 0) @[Bitwise.scala 33:15] - node T_1043 = mux(T_1040, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1044 = bits(T_1021, 0, 0) @[Bitwise.scala 33:15] - node T_1047 = mux(T_1044, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1048 = bits(T_1022, 0, 0) @[Bitwise.scala 33:15] - node T_1051 = mux(T_1048, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1052 = bits(T_1023, 0, 0) @[Bitwise.scala 33:15] - node T_1055 = mux(T_1052, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1056 = cat(T_1031, T_1027) @[Cat.scala 20:58] - node T_1057 = cat(T_1039, T_1035) @[Cat.scala 20:58] - node T_1058 = cat(T_1057, T_1056) @[Cat.scala 20:58] - node T_1059 = cat(T_1047, T_1043) @[Cat.scala 20:58] - node T_1060 = cat(T_1055, T_1051) @[Cat.scala 20:58] - node T_1061 = cat(T_1060, T_1059) @[Cat.scala 20:58] - node T_1062 = cat(T_1061, T_1058) @[Cat.scala 20:58] - node T_1063 = not(T_1062) @[Prci.scala 113:58] - node T_1064 = and(timecmp[0], T_1063) @[Prci.scala 113:56] - node T_1065 = or(T_984, T_1064) @[Prci.scala 113:47] - node T_1067 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1068 = and(acq.io.deq.bits.is_builtin_type, T_1067) @[Definitions.scala 212:54] - node T_1069 = and(T_869, T_1068) @[Prci.scala 114:14] - when T_1069 : @[Prci.scala 114:53] - node T_1072 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Prci.scala 119:46] - when T_1072 : @[Prci.scala 119:68] - node T_1073 = shr(T_1065, 0) @[Prci.scala 121:25] - timecmp[0] <= T_1073 @[Prci.scala 121:16] - skip @[Prci.scala 119:68] - skip @[Prci.scala 114:53] - rdata <= timecmp[0] @[Prci.scala 81:11] - skip @[Prci.scala 80:40] - node T_1075 = eq(T_658, UInt<1>("h00")) @[Prci.scala 77:37] - node T_1077 = eq(T_865, UInt<1>("h00")) @[Prci.scala 80:40] - node T_1078 = and(T_1075, T_1077) @[Prci.scala 80:40] - when T_1078 : @[Prci.scala 82:15] - node T_1079 = and(io.tl.grant.ready, io.tl.grant.valid) @[Decoupled.scala 21:42] - wire T_1087 : UInt<3>[2] @[Definitions.scala 357:30] - T_1087 is invalid @[Definitions.scala 357:30] - T_1087[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_1087[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_1089 = eq(acq.io.deq.bits.a_type, T_1087[0]) @[Package.scala 7:47] - node T_1090 = eq(acq.io.deq.bits.a_type, T_1087[1]) @[Package.scala 7:47] - node T_1091 = or(T_1089, T_1090) @[Package.scala 7:62] - node T_1092 = and(acq.io.deq.bits.is_builtin_type, T_1091) @[Definitions.scala 300:27] - node T_1093 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_1095 = mux(T_1092, T_1093, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_1096 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_1097 = cat(T_1096, T_1095) @[Cat.scala 20:58] - wire T_1105 : UInt<3>[2] @[Definitions.scala 357:30] - T_1105 is invalid @[Definitions.scala 357:30] - T_1105[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_1105[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_1107 = eq(acq.io.deq.bits.a_type, T_1105[0]) @[Package.scala 7:47] - node T_1108 = eq(acq.io.deq.bits.a_type, T_1105[1]) @[Package.scala 7:47] - node T_1109 = or(T_1107, T_1108) @[Package.scala 7:62] - node T_1110 = and(acq.io.deq.bits.is_builtin_type, T_1109) @[Definitions.scala 300:27] - node T_1111 = bits(acq.io.deq.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_1113 = mux(T_1110, T_1111, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_1114 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) @[Cat.scala 20:58] - node T_1115 = cat(T_1114, T_1113) @[Cat.scala 20:58] - node T_1117 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_1118 = and(acq.io.deq.bits.is_builtin_type, T_1117) @[Definitions.scala 212:54] - node T_1135 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1137 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1138 = and(acq.io.deq.bits.is_builtin_type, T_1137) @[Definitions.scala 212:54] - node T_1140 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1141 = and(acq.io.deq.bits.is_builtin_type, T_1140) @[Definitions.scala 212:54] - node T_1142 = or(T_1138, T_1141) @[Definitions.scala 190:56] - node T_1143 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_1145 = mux(T_1142, T_1143, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_1146 = mux(T_1118, T_1135, T_1145) @[Definitions.scala 192:8] - node T_1147 = bits(T_1146, 0, 0) @[Bitwise.scala 13:51] - node T_1148 = bits(T_1146, 1, 1) @[Bitwise.scala 13:51] - node T_1149 = bits(T_1146, 2, 2) @[Bitwise.scala 13:51] - node T_1150 = bits(T_1146, 3, 3) @[Bitwise.scala 13:51] - node T_1151 = bits(T_1146, 4, 4) @[Bitwise.scala 13:51] - node T_1152 = bits(T_1146, 5, 5) @[Bitwise.scala 13:51] - node T_1153 = bits(T_1146, 6, 6) @[Bitwise.scala 13:51] - node T_1154 = bits(T_1146, 7, 7) @[Bitwise.scala 13:51] - node T_1155 = bits(T_1147, 0, 0) @[Bitwise.scala 33:15] - node T_1158 = mux(T_1155, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1159 = bits(T_1148, 0, 0) @[Bitwise.scala 33:15] - node T_1162 = mux(T_1159, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1163 = bits(T_1149, 0, 0) @[Bitwise.scala 33:15] - node T_1166 = mux(T_1163, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1167 = bits(T_1150, 0, 0) @[Bitwise.scala 33:15] - node T_1170 = mux(T_1167, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1171 = bits(T_1151, 0, 0) @[Bitwise.scala 33:15] - node T_1174 = mux(T_1171, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1175 = bits(T_1152, 0, 0) @[Bitwise.scala 33:15] - node T_1178 = mux(T_1175, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1179 = bits(T_1153, 0, 0) @[Bitwise.scala 33:15] - node T_1182 = mux(T_1179, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1183 = bits(T_1154, 0, 0) @[Bitwise.scala 33:15] - node T_1186 = mux(T_1183, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1187 = cat(T_1162, T_1158) @[Cat.scala 20:58] - node T_1188 = cat(T_1170, T_1166) @[Cat.scala 20:58] - node T_1189 = cat(T_1188, T_1187) @[Cat.scala 20:58] - node T_1190 = cat(T_1178, T_1174) @[Cat.scala 20:58] - node T_1191 = cat(T_1186, T_1182) @[Cat.scala 20:58] - node T_1192 = cat(T_1191, T_1190) @[Cat.scala 20:58] - node T_1193 = cat(T_1192, T_1189) @[Cat.scala 20:58] - node T_1194 = and(acq.io.deq.bits.data, T_1193) @[Prci.scala 113:27] - node T_1196 = eq(acq.io.deq.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_1197 = and(acq.io.deq.bits.is_builtin_type, T_1196) @[Definitions.scala 212:54] - node T_1214 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1216 = eq(acq.io.deq.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1217 = and(acq.io.deq.bits.is_builtin_type, T_1216) @[Definitions.scala 212:54] - node T_1219 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1220 = and(acq.io.deq.bits.is_builtin_type, T_1219) @[Definitions.scala 212:54] - node T_1221 = or(T_1217, T_1220) @[Definitions.scala 190:56] - node T_1222 = bits(acq.io.deq.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_1224 = mux(T_1221, T_1222, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_1225 = mux(T_1197, T_1214, T_1224) @[Definitions.scala 192:8] - node T_1226 = bits(T_1225, 0, 0) @[Bitwise.scala 13:51] - node T_1227 = bits(T_1225, 1, 1) @[Bitwise.scala 13:51] - node T_1228 = bits(T_1225, 2, 2) @[Bitwise.scala 13:51] - node T_1229 = bits(T_1225, 3, 3) @[Bitwise.scala 13:51] - node T_1230 = bits(T_1225, 4, 4) @[Bitwise.scala 13:51] - node T_1231 = bits(T_1225, 5, 5) @[Bitwise.scala 13:51] - node T_1232 = bits(T_1225, 6, 6) @[Bitwise.scala 13:51] - node T_1233 = bits(T_1225, 7, 7) @[Bitwise.scala 13:51] - node T_1234 = bits(T_1226, 0, 0) @[Bitwise.scala 33:15] - node T_1237 = mux(T_1234, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1238 = bits(T_1227, 0, 0) @[Bitwise.scala 33:15] - node T_1241 = mux(T_1238, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1242 = bits(T_1228, 0, 0) @[Bitwise.scala 33:15] - node T_1245 = mux(T_1242, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1246 = bits(T_1229, 0, 0) @[Bitwise.scala 33:15] - node T_1249 = mux(T_1246, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1250 = bits(T_1230, 0, 0) @[Bitwise.scala 33:15] - node T_1253 = mux(T_1250, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1254 = bits(T_1231, 0, 0) @[Bitwise.scala 33:15] - node T_1257 = mux(T_1254, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1258 = bits(T_1232, 0, 0) @[Bitwise.scala 33:15] - node T_1261 = mux(T_1258, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1262 = bits(T_1233, 0, 0) @[Bitwise.scala 33:15] - node T_1265 = mux(T_1262, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_1266 = cat(T_1241, T_1237) @[Cat.scala 20:58] - node T_1267 = cat(T_1249, T_1245) @[Cat.scala 20:58] - node T_1268 = cat(T_1267, T_1266) @[Cat.scala 20:58] - node T_1269 = cat(T_1257, T_1253) @[Cat.scala 20:58] - node T_1270 = cat(T_1265, T_1261) @[Cat.scala 20:58] - node T_1271 = cat(T_1270, T_1269) @[Cat.scala 20:58] - node T_1272 = cat(T_1271, T_1268) @[Cat.scala 20:58] - node T_1273 = not(T_1272) @[Prci.scala 113:58] - node T_1274 = and(ipi[0], T_1273) @[Prci.scala 113:56] - node T_1275 = or(T_1194, T_1274) @[Prci.scala 113:47] - node T_1277 = eq(acq.io.deq.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1278 = and(acq.io.deq.bits.is_builtin_type, T_1277) @[Definitions.scala 212:54] - node T_1279 = and(T_1079, T_1278) @[Prci.scala 114:14] - when T_1279 : @[Prci.scala 114:53] - node T_1282 = eq(UInt<1>("h00"), UInt<1>("h00")) @[Prci.scala 119:46] - when T_1282 : @[Prci.scala 119:68] - node T_1283 = shr(T_1275, 0) @[Prci.scala 121:25] - ipi[0] <= T_1283 @[Prci.scala 121:16] - skip @[Prci.scala 119:68] - skip @[Prci.scala 114:53] - node T_1285 = cat(UInt<32>("h01"), UInt<32>("h01")) @[Cat.scala 20:58] - node T_1286 = and(ipi[0], T_1285) @[Prci.scala 83:55] - rdata <= T_1286 @[Prci.scala 83:11] - skip @[Prci.scala 82:15] - io.tiles[0].interrupts <- io.interrupts[0] @[Prci.scala 87:21] - node T_1287 = bits(ipi[0], 0, 0) @[Prci.scala 88:35] - io.tiles[0].interrupts.msip <= T_1287 @[Prci.scala 88:26] - node T_1288 = geq(time, timecmp[0]) @[Prci.scala 89:34] - io.tiles[0].interrupts.mtip <= T_1288 @[Prci.scala 89:26] - io.tiles[0].id <= UInt<1>("h00") @[Prci.scala 90:13] - - module ROMSlave : + rdata <= UInt<1>("h0") + io.tl.grant.valid <= acq.io.deq.valid + acq.io.deq.ready <= io.tl.grant.ready + node T_598 = eq(UInt<3>("h6"), acq.io.deq.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h1"), UInt<3>("h3")) + node T_600 = eq(UInt<3>("h5"), acq.io.deq.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h1"), T_599) + node T_602 = eq(UInt<3>("h4"), acq.io.deq.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h4"), T_601) + node T_604 = eq(UInt<3>("h3"), acq.io.deq.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h3"), T_603) + node T_606 = eq(UInt<3>("h2"), acq.io.deq.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h3"), T_605) + node T_608 = eq(UInt<3>("h1"), acq.io.deq.bits.a_type) + node T_609 = mux(T_608, UInt<3>("h5"), T_607) + node T_610 = eq(UInt<3>("h0"), acq.io.deq.bits.a_type) + node T_611 = mux(T_610, UInt<3>("h4"), T_609) + wire T_636 : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_636 is invalid + T_636.is_builtin_type <= UInt<1>("h1") + T_636.g_type <= T_611 + T_636.client_xact_id <= acq.io.deq.bits.client_xact_id + T_636.manager_xact_id <= UInt<1>("h0") + T_636.addr_beat <= UInt<1>("h0") + T_636.data <= rdata + io.tl.grant.bits <- T_636 + node T_658 = bits(addr, 15, 15) + when T_658 : + node T_659 = and(io.tl.grant.ready, io.tl.grant.valid) + wire T_667 : UInt<3>[2] + T_667 is invalid + T_667[0] <= UInt<3>("h0") + T_667[1] <= UInt<3>("h4") + node T_669 = eq(acq.io.deq.bits.a_type, T_667[0]) + node T_670 = eq(acq.io.deq.bits.a_type, T_667[1]) + node T_671 = or(T_669, T_670) + node T_672 = and(acq.io.deq.bits.is_builtin_type, T_671) + node T_673 = bits(acq.io.deq.bits.union, 10, 8) + node T_675 = mux(T_672, T_673, UInt<3>("h0")) + node T_676 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_677 = cat(T_676, T_675) + wire T_685 : UInt<3>[2] + T_685 is invalid + T_685[0] <= UInt<3>("h0") + T_685[1] <= UInt<3>("h4") + node T_687 = eq(acq.io.deq.bits.a_type, T_685[0]) + node T_688 = eq(acq.io.deq.bits.a_type, T_685[1]) + node T_689 = or(T_687, T_688) + node T_690 = and(acq.io.deq.bits.is_builtin_type, T_689) + node T_691 = bits(acq.io.deq.bits.union, 10, 8) + node T_693 = mux(T_690, T_691, UInt<3>("h0")) + node T_694 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_695 = cat(T_694, T_693) + node T_697 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_698 = and(acq.io.deq.bits.is_builtin_type, T_697) + node T_715 = asUInt(asSInt(UInt<8>("hff"))) + node T_717 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_718 = and(acq.io.deq.bits.is_builtin_type, T_717) + node T_720 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_721 = and(acq.io.deq.bits.is_builtin_type, T_720) + node T_722 = or(T_718, T_721) + node T_723 = bits(acq.io.deq.bits.union, 8, 1) + node T_725 = mux(T_722, T_723, UInt<1>("h0")) + node T_726 = mux(T_698, T_715, T_725) + node T_727 = bits(T_726, 0, 0) + node T_728 = bits(T_726, 1, 1) + node T_729 = bits(T_726, 2, 2) + node T_730 = bits(T_726, 3, 3) + node T_731 = bits(T_726, 4, 4) + node T_732 = bits(T_726, 5, 5) + node T_733 = bits(T_726, 6, 6) + node T_734 = bits(T_726, 7, 7) + node T_735 = bits(T_727, 0, 0) + node T_738 = mux(T_735, UInt<8>("hff"), UInt<8>("h0")) + node T_739 = bits(T_728, 0, 0) + node T_742 = mux(T_739, UInt<8>("hff"), UInt<8>("h0")) + node T_743 = bits(T_729, 0, 0) + node T_746 = mux(T_743, UInt<8>("hff"), UInt<8>("h0")) + node T_747 = bits(T_730, 0, 0) + node T_750 = mux(T_747, UInt<8>("hff"), UInt<8>("h0")) + node T_751 = bits(T_731, 0, 0) + node T_754 = mux(T_751, UInt<8>("hff"), UInt<8>("h0")) + node T_755 = bits(T_732, 0, 0) + node T_758 = mux(T_755, UInt<8>("hff"), UInt<8>("h0")) + node T_759 = bits(T_733, 0, 0) + node T_762 = mux(T_759, UInt<8>("hff"), UInt<8>("h0")) + node T_763 = bits(T_734, 0, 0) + node T_766 = mux(T_763, UInt<8>("hff"), UInt<8>("h0")) + node T_767 = cat(T_742, T_738) + node T_768 = cat(T_750, T_746) + node T_769 = cat(T_768, T_767) + node T_770 = cat(T_758, T_754) + node T_771 = cat(T_766, T_762) + node T_772 = cat(T_771, T_770) + node T_773 = cat(T_772, T_769) + node T_774 = and(acq.io.deq.bits.data, T_773) + node T_776 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_777 = and(acq.io.deq.bits.is_builtin_type, T_776) + node T_794 = asUInt(asSInt(UInt<8>("hff"))) + node T_796 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_797 = and(acq.io.deq.bits.is_builtin_type, T_796) + node T_799 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_800 = and(acq.io.deq.bits.is_builtin_type, T_799) + node T_801 = or(T_797, T_800) + node T_802 = bits(acq.io.deq.bits.union, 8, 1) + node T_804 = mux(T_801, T_802, UInt<1>("h0")) + node T_805 = mux(T_777, T_794, T_804) + node T_806 = bits(T_805, 0, 0) + node T_807 = bits(T_805, 1, 1) + node T_808 = bits(T_805, 2, 2) + node T_809 = bits(T_805, 3, 3) + node T_810 = bits(T_805, 4, 4) + node T_811 = bits(T_805, 5, 5) + node T_812 = bits(T_805, 6, 6) + node T_813 = bits(T_805, 7, 7) + node T_814 = bits(T_806, 0, 0) + node T_817 = mux(T_814, UInt<8>("hff"), UInt<8>("h0")) + node T_818 = bits(T_807, 0, 0) + node T_821 = mux(T_818, UInt<8>("hff"), UInt<8>("h0")) + node T_822 = bits(T_808, 0, 0) + node T_825 = mux(T_822, UInt<8>("hff"), UInt<8>("h0")) + node T_826 = bits(T_809, 0, 0) + node T_829 = mux(T_826, UInt<8>("hff"), UInt<8>("h0")) + node T_830 = bits(T_810, 0, 0) + node T_833 = mux(T_830, UInt<8>("hff"), UInt<8>("h0")) + node T_834 = bits(T_811, 0, 0) + node T_837 = mux(T_834, UInt<8>("hff"), UInt<8>("h0")) + node T_838 = bits(T_812, 0, 0) + node T_841 = mux(T_838, UInt<8>("hff"), UInt<8>("h0")) + node T_842 = bits(T_813, 0, 0) + node T_845 = mux(T_842, UInt<8>("hff"), UInt<8>("h0")) + node T_846 = cat(T_821, T_817) + node T_847 = cat(T_829, T_825) + node T_848 = cat(T_847, T_846) + node T_849 = cat(T_837, T_833) + node T_850 = cat(T_845, T_841) + node T_851 = cat(T_850, T_849) + node T_852 = cat(T_851, T_848) + node T_853 = not(T_852) + node T_854 = and(time, T_853) + node T_855 = or(T_774, T_854) + node T_857 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_858 = and(acq.io.deq.bits.is_builtin_type, T_857) + node T_859 = and(T_659, T_858) + when T_859 : + node T_862 = eq(UInt<1>("h0"), UInt<1>("h0")) + when T_862 : + node T_863 = shr(T_855, 0) + time <= T_863 + rdata <= time + node T_865 = geq(addr, UInt<15>("h4000")) + node T_867 = eq(T_658, UInt<1>("h0")) + node T_868 = and(T_867, T_865) + when T_868 : + node T_869 = and(io.tl.grant.ready, io.tl.grant.valid) + wire T_877 : UInt<3>[2] + T_877 is invalid + T_877[0] <= UInt<3>("h0") + T_877[1] <= UInt<3>("h4") + node T_879 = eq(acq.io.deq.bits.a_type, T_877[0]) + node T_880 = eq(acq.io.deq.bits.a_type, T_877[1]) + node T_881 = or(T_879, T_880) + node T_882 = and(acq.io.deq.bits.is_builtin_type, T_881) + node T_883 = bits(acq.io.deq.bits.union, 10, 8) + node T_885 = mux(T_882, T_883, UInt<3>("h0")) + node T_886 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_887 = cat(T_886, T_885) + wire T_895 : UInt<3>[2] + T_895 is invalid + T_895[0] <= UInt<3>("h0") + T_895[1] <= UInt<3>("h4") + node T_897 = eq(acq.io.deq.bits.a_type, T_895[0]) + node T_898 = eq(acq.io.deq.bits.a_type, T_895[1]) + node T_899 = or(T_897, T_898) + node T_900 = and(acq.io.deq.bits.is_builtin_type, T_899) + node T_901 = bits(acq.io.deq.bits.union, 10, 8) + node T_903 = mux(T_900, T_901, UInt<3>("h0")) + node T_904 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_905 = cat(T_904, T_903) + node T_907 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_908 = and(acq.io.deq.bits.is_builtin_type, T_907) + node T_925 = asUInt(asSInt(UInt<8>("hff"))) + node T_927 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_928 = and(acq.io.deq.bits.is_builtin_type, T_927) + node T_930 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_931 = and(acq.io.deq.bits.is_builtin_type, T_930) + node T_932 = or(T_928, T_931) + node T_933 = bits(acq.io.deq.bits.union, 8, 1) + node T_935 = mux(T_932, T_933, UInt<1>("h0")) + node T_936 = mux(T_908, T_925, T_935) + node T_937 = bits(T_936, 0, 0) + node T_938 = bits(T_936, 1, 1) + node T_939 = bits(T_936, 2, 2) + node T_940 = bits(T_936, 3, 3) + node T_941 = bits(T_936, 4, 4) + node T_942 = bits(T_936, 5, 5) + node T_943 = bits(T_936, 6, 6) + node T_944 = bits(T_936, 7, 7) + node T_945 = bits(T_937, 0, 0) + node T_948 = mux(T_945, UInt<8>("hff"), UInt<8>("h0")) + node T_949 = bits(T_938, 0, 0) + node T_952 = mux(T_949, UInt<8>("hff"), UInt<8>("h0")) + node T_953 = bits(T_939, 0, 0) + node T_956 = mux(T_953, UInt<8>("hff"), UInt<8>("h0")) + node T_957 = bits(T_940, 0, 0) + node T_960 = mux(T_957, UInt<8>("hff"), UInt<8>("h0")) + node T_961 = bits(T_941, 0, 0) + node T_964 = mux(T_961, UInt<8>("hff"), UInt<8>("h0")) + node T_965 = bits(T_942, 0, 0) + node T_968 = mux(T_965, UInt<8>("hff"), UInt<8>("h0")) + node T_969 = bits(T_943, 0, 0) + node T_972 = mux(T_969, UInt<8>("hff"), UInt<8>("h0")) + node T_973 = bits(T_944, 0, 0) + node T_976 = mux(T_973, UInt<8>("hff"), UInt<8>("h0")) + node T_977 = cat(T_952, T_948) + node T_978 = cat(T_960, T_956) + node T_979 = cat(T_978, T_977) + node T_980 = cat(T_968, T_964) + node T_981 = cat(T_976, T_972) + node T_982 = cat(T_981, T_980) + node T_983 = cat(T_982, T_979) + node T_984 = and(acq.io.deq.bits.data, T_983) + node T_986 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_987 = and(acq.io.deq.bits.is_builtin_type, T_986) + node T_1004 = asUInt(asSInt(UInt<8>("hff"))) + node T_1006 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_1007 = and(acq.io.deq.bits.is_builtin_type, T_1006) + node T_1009 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_1010 = and(acq.io.deq.bits.is_builtin_type, T_1009) + node T_1011 = or(T_1007, T_1010) + node T_1012 = bits(acq.io.deq.bits.union, 8, 1) + node T_1014 = mux(T_1011, T_1012, UInt<1>("h0")) + node T_1015 = mux(T_987, T_1004, T_1014) + node T_1016 = bits(T_1015, 0, 0) + node T_1017 = bits(T_1015, 1, 1) + node T_1018 = bits(T_1015, 2, 2) + node T_1019 = bits(T_1015, 3, 3) + node T_1020 = bits(T_1015, 4, 4) + node T_1021 = bits(T_1015, 5, 5) + node T_1022 = bits(T_1015, 6, 6) + node T_1023 = bits(T_1015, 7, 7) + node T_1024 = bits(T_1016, 0, 0) + node T_1027 = mux(T_1024, UInt<8>("hff"), UInt<8>("h0")) + node T_1028 = bits(T_1017, 0, 0) + node T_1031 = mux(T_1028, UInt<8>("hff"), UInt<8>("h0")) + node T_1032 = bits(T_1018, 0, 0) + node T_1035 = mux(T_1032, UInt<8>("hff"), UInt<8>("h0")) + node T_1036 = bits(T_1019, 0, 0) + node T_1039 = mux(T_1036, UInt<8>("hff"), UInt<8>("h0")) + node T_1040 = bits(T_1020, 0, 0) + node T_1043 = mux(T_1040, UInt<8>("hff"), UInt<8>("h0")) + node T_1044 = bits(T_1021, 0, 0) + node T_1047 = mux(T_1044, UInt<8>("hff"), UInt<8>("h0")) + node T_1048 = bits(T_1022, 0, 0) + node T_1051 = mux(T_1048, UInt<8>("hff"), UInt<8>("h0")) + node T_1052 = bits(T_1023, 0, 0) + node T_1055 = mux(T_1052, UInt<8>("hff"), UInt<8>("h0")) + node T_1056 = cat(T_1031, T_1027) + node T_1057 = cat(T_1039, T_1035) + node T_1058 = cat(T_1057, T_1056) + node T_1059 = cat(T_1047, T_1043) + node T_1060 = cat(T_1055, T_1051) + node T_1061 = cat(T_1060, T_1059) + node T_1062 = cat(T_1061, T_1058) + node T_1063 = not(T_1062) + node T_1064 = and(timecmp[0], T_1063) + node T_1065 = or(T_984, T_1064) + node T_1067 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_1068 = and(acq.io.deq.bits.is_builtin_type, T_1067) + node T_1069 = and(T_869, T_1068) + when T_1069 : + node T_1072 = eq(UInt<1>("h0"), UInt<1>("h0")) + when T_1072 : + node T_1073 = shr(T_1065, 0) + timecmp[0] <= T_1073 + rdata <= timecmp[0] + node T_1075 = eq(T_658, UInt<1>("h0")) + node T_1077 = eq(T_865, UInt<1>("h0")) + node T_1078 = and(T_1075, T_1077) + when T_1078 : + node T_1079 = and(io.tl.grant.ready, io.tl.grant.valid) + wire T_1087 : UInt<3>[2] + T_1087 is invalid + T_1087[0] <= UInt<3>("h0") + T_1087[1] <= UInt<3>("h4") + node T_1089 = eq(acq.io.deq.bits.a_type, T_1087[0]) + node T_1090 = eq(acq.io.deq.bits.a_type, T_1087[1]) + node T_1091 = or(T_1089, T_1090) + node T_1092 = and(acq.io.deq.bits.is_builtin_type, T_1091) + node T_1093 = bits(acq.io.deq.bits.union, 10, 8) + node T_1095 = mux(T_1092, T_1093, UInt<3>("h0")) + node T_1096 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_1097 = cat(T_1096, T_1095) + wire T_1105 : UInt<3>[2] + T_1105 is invalid + T_1105[0] <= UInt<3>("h0") + T_1105[1] <= UInt<3>("h4") + node T_1107 = eq(acq.io.deq.bits.a_type, T_1105[0]) + node T_1108 = eq(acq.io.deq.bits.a_type, T_1105[1]) + node T_1109 = or(T_1107, T_1108) + node T_1110 = and(acq.io.deq.bits.is_builtin_type, T_1109) + node T_1111 = bits(acq.io.deq.bits.union, 10, 8) + node T_1113 = mux(T_1110, T_1111, UInt<3>("h0")) + node T_1114 = cat(acq.io.deq.bits.addr_block, acq.io.deq.bits.addr_beat) + node T_1115 = cat(T_1114, T_1113) + node T_1117 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_1118 = and(acq.io.deq.bits.is_builtin_type, T_1117) + node T_1135 = asUInt(asSInt(UInt<8>("hff"))) + node T_1137 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_1138 = and(acq.io.deq.bits.is_builtin_type, T_1137) + node T_1140 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_1141 = and(acq.io.deq.bits.is_builtin_type, T_1140) + node T_1142 = or(T_1138, T_1141) + node T_1143 = bits(acq.io.deq.bits.union, 8, 1) + node T_1145 = mux(T_1142, T_1143, UInt<1>("h0")) + node T_1146 = mux(T_1118, T_1135, T_1145) + node T_1147 = bits(T_1146, 0, 0) + node T_1148 = bits(T_1146, 1, 1) + node T_1149 = bits(T_1146, 2, 2) + node T_1150 = bits(T_1146, 3, 3) + node T_1151 = bits(T_1146, 4, 4) + node T_1152 = bits(T_1146, 5, 5) + node T_1153 = bits(T_1146, 6, 6) + node T_1154 = bits(T_1146, 7, 7) + node T_1155 = bits(T_1147, 0, 0) + node T_1158 = mux(T_1155, UInt<8>("hff"), UInt<8>("h0")) + node T_1159 = bits(T_1148, 0, 0) + node T_1162 = mux(T_1159, UInt<8>("hff"), UInt<8>("h0")) + node T_1163 = bits(T_1149, 0, 0) + node T_1166 = mux(T_1163, UInt<8>("hff"), UInt<8>("h0")) + node T_1167 = bits(T_1150, 0, 0) + node T_1170 = mux(T_1167, UInt<8>("hff"), UInt<8>("h0")) + node T_1171 = bits(T_1151, 0, 0) + node T_1174 = mux(T_1171, UInt<8>("hff"), UInt<8>("h0")) + node T_1175 = bits(T_1152, 0, 0) + node T_1178 = mux(T_1175, UInt<8>("hff"), UInt<8>("h0")) + node T_1179 = bits(T_1153, 0, 0) + node T_1182 = mux(T_1179, UInt<8>("hff"), UInt<8>("h0")) + node T_1183 = bits(T_1154, 0, 0) + node T_1186 = mux(T_1183, UInt<8>("hff"), UInt<8>("h0")) + node T_1187 = cat(T_1162, T_1158) + node T_1188 = cat(T_1170, T_1166) + node T_1189 = cat(T_1188, T_1187) + node T_1190 = cat(T_1178, T_1174) + node T_1191 = cat(T_1186, T_1182) + node T_1192 = cat(T_1191, T_1190) + node T_1193 = cat(T_1192, T_1189) + node T_1194 = and(acq.io.deq.bits.data, T_1193) + node T_1196 = eq(acq.io.deq.bits.a_type, UInt<3>("h4")) + node T_1197 = and(acq.io.deq.bits.is_builtin_type, T_1196) + node T_1214 = asUInt(asSInt(UInt<8>("hff"))) + node T_1216 = eq(acq.io.deq.bits.a_type, UInt<3>("h3")) + node T_1217 = and(acq.io.deq.bits.is_builtin_type, T_1216) + node T_1219 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_1220 = and(acq.io.deq.bits.is_builtin_type, T_1219) + node T_1221 = or(T_1217, T_1220) + node T_1222 = bits(acq.io.deq.bits.union, 8, 1) + node T_1224 = mux(T_1221, T_1222, UInt<1>("h0")) + node T_1225 = mux(T_1197, T_1214, T_1224) + node T_1226 = bits(T_1225, 0, 0) + node T_1227 = bits(T_1225, 1, 1) + node T_1228 = bits(T_1225, 2, 2) + node T_1229 = bits(T_1225, 3, 3) + node T_1230 = bits(T_1225, 4, 4) + node T_1231 = bits(T_1225, 5, 5) + node T_1232 = bits(T_1225, 6, 6) + node T_1233 = bits(T_1225, 7, 7) + node T_1234 = bits(T_1226, 0, 0) + node T_1237 = mux(T_1234, UInt<8>("hff"), UInt<8>("h0")) + node T_1238 = bits(T_1227, 0, 0) + node T_1241 = mux(T_1238, UInt<8>("hff"), UInt<8>("h0")) + node T_1242 = bits(T_1228, 0, 0) + node T_1245 = mux(T_1242, UInt<8>("hff"), UInt<8>("h0")) + node T_1246 = bits(T_1229, 0, 0) + node T_1249 = mux(T_1246, UInt<8>("hff"), UInt<8>("h0")) + node T_1250 = bits(T_1230, 0, 0) + node T_1253 = mux(T_1250, UInt<8>("hff"), UInt<8>("h0")) + node T_1254 = bits(T_1231, 0, 0) + node T_1257 = mux(T_1254, UInt<8>("hff"), UInt<8>("h0")) + node T_1258 = bits(T_1232, 0, 0) + node T_1261 = mux(T_1258, UInt<8>("hff"), UInt<8>("h0")) + node T_1262 = bits(T_1233, 0, 0) + node T_1265 = mux(T_1262, UInt<8>("hff"), UInt<8>("h0")) + node T_1266 = cat(T_1241, T_1237) + node T_1267 = cat(T_1249, T_1245) + node T_1268 = cat(T_1267, T_1266) + node T_1269 = cat(T_1257, T_1253) + node T_1270 = cat(T_1265, T_1261) + node T_1271 = cat(T_1270, T_1269) + node T_1272 = cat(T_1271, T_1268) + node T_1273 = not(T_1272) + node T_1274 = and(ipi[0], T_1273) + node T_1275 = or(T_1194, T_1274) + node T_1277 = eq(acq.io.deq.bits.a_type, UInt<3>("h2")) + node T_1278 = and(acq.io.deq.bits.is_builtin_type, T_1277) + node T_1279 = and(T_1079, T_1278) + when T_1279 : + node T_1282 = eq(UInt<1>("h0"), UInt<1>("h0")) + when T_1282 : + node T_1283 = shr(T_1275, 0) + ipi[0] <= T_1283 + node T_1285 = cat(UInt<32>("h1"), UInt<32>("h1")) + node T_1286 = and(ipi[0], T_1285) + rdata <= T_1286 + io.tiles[0].interrupts <- io.interrupts[0] + node T_1287 = bits(ipi[0], 0, 0) + io.tiles[0].interrupts.msip <= T_1287 + node T_1288 = geq(time, timecmp[0]) + io.tiles[0].interrupts.mtip <= T_1288 + io.tiles[0].id <= UInt<1>("h0") + + module ROMSlave : input clk : Clock input reset : UInt<1> - input io : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} - + input io : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}} + io is invalid - inst acq of Queue_17 @[Decoupled.scala 228:19] + inst acq of Queue_17 acq.io is invalid acq.clk <= clk acq.reset <= reset - acq.io.enq.valid <= io.acquire.valid @[Decoupled.scala 229:20] - acq.io.enq.bits <- io.acquire.bits @[Decoupled.scala 230:19] - io.acquire.ready <= acq.io.enq.ready @[Decoupled.scala 231:15] - node T_446 = eq(acq.io.deq.bits.a_type, UInt<3>("h00")) @[Definitions.scala 212:64] - node single_beat = and(acq.io.deq.bits.is_builtin_type, T_446) @[Definitions.scala 212:54] - node T_448 = eq(acq.io.deq.bits.a_type, UInt<3>("h01")) @[Definitions.scala 212:64] - node multi_beat = and(acq.io.deq.bits.is_builtin_type, T_448) @[Definitions.scala 212:54] - node T_450 = eq(acq.io.deq.valid, UInt<1>("h00")) @[Rom.scala 17:10] - node T_451 = or(T_450, single_beat) @[Rom.scala 17:21] - node T_452 = or(T_451, multi_beat) @[Rom.scala 17:36] - node T_453 = or(T_452, reset) @[Rom.scala 17:9] - node T_455 = eq(T_453, UInt<1>("h00")) @[Rom.scala 17:9] - when T_455 : @[Rom.scala 17:9] - printf(clk, UInt<1>(1), "Assertion failed: unsupported ROMSlave operation\n at Rom.scala:17 assert(!acq.valid || single_beat || multi_beat, \"unsupported ROMSlave operation\")\n") @[Rom.scala 17:9] - stop(clk, UInt<1>(1), 1) @[Rom.scala 17:9] - skip @[Rom.scala 17:9] - reg addr_beat : UInt, clk - node T_457 = and(io.grant.ready, io.grant.valid) @[Decoupled.scala 21:42] - when T_457 : @[Rom.scala 20:26] - node T_459 = add(addr_beat, UInt<1>("h01")) @[Rom.scala 20:51] - node T_460 = tail(T_459, 1) @[Rom.scala 20:51] - addr_beat <= T_460 @[Rom.scala 20:38] - skip @[Rom.scala 20:26] - node T_461 = and(io.acquire.ready, io.acquire.valid) @[Decoupled.scala 21:42] - when T_461 : @[Rom.scala 21:28] - addr_beat <= io.acquire.bits.addr_beat @[Rom.scala 21:40] - skip @[Rom.scala 21:28] - wire rom : UInt<64>[66] @[Rom.scala 25:32] - rom is invalid @[Rom.scala 25:32] - rom[0] <= UInt<64>("h06f") @[Rom.scala 25:32] - rom[1] <= UInt<64>("h0102000000000") @[Rom.scala 25:32] - rom[2] <= UInt<64>("h00") @[Rom.scala 25:32] - rom[3] <= UInt<64>("h00") @[Rom.scala 25:32] - rom[4] <= UInt<64>("h0200a7b2063696c70") @[Rom.scala 25:32] - rom[5] <= UInt<64>("h07469726f69727020") @[Rom.scala 25:32] - rom[6] <= UInt<64>("h03030303478302079") @[Rom.scala 25:32] - rom[7] <= UInt<64>("h020200a3b30303030") @[Rom.scala 25:32] - rom[8] <= UInt<64>("h020676e69646e6570") @[Rom.scala 25:32] - rom[9] <= UInt<64>("h03031303030347830") @[Rom.scala 25:32] - rom[10] <= UInt<64>("h0646e20200a3b3030") @[Rom.scala 25:32] - rom[11] <= UInt<64>("h07d0a3b3220737665") @[Rom.scala 25:32] - rom[12] <= UInt<64>("h0a7b206374720a3b") @[Rom.scala 25:32] - rom[13] <= UInt<64>("h03020726464612020") @[Rom.scala 25:32] - rom[14] <= UInt<64>("h06666623030343478") @[Rom.scala 25:32] - rom[15] <= UInt<64>("h061720a3b7d0a3b38") @[Rom.scala 25:32] - rom[16] <= UInt<64>("h0203020200a7b206d") @[Rom.scala 25:32] - rom[17] <= UInt<64>("h06461202020200a7b") @[Rom.scala 25:32] - rom[18] <= UInt<64>("h03030387830207264") @[Rom.scala 25:32] - rom[19] <= UInt<64>("h0200a3b3030303030") @[Rom.scala 25:32] - rom[20] <= UInt<64>("h020657a6973202020") @[Rom.scala 25:32] - rom[21] <= UInt<64>("h03030303030317830") @[Rom.scala 25:32] - rom[22] <= UInt<64>("h03b7d20200a3b3030") @[Rom.scala 25:32] - rom[23] <= UInt<64>("h065726f630a3b7d0a") @[Rom.scala 25:32] - rom[24] <= UInt<64>("h07b203020200a7b20") @[Rom.scala 25:32] - rom[25] <= UInt<64>("h07b2030202020200a") @[Rom.scala 25:32] - rom[26] <= UInt<64>("h0692020202020200a") @[Rom.scala 25:32] - rom[27] <= UInt<64>("h06934367672206173") @[Rom.scala 25:32] - rom[28] <= UInt<64>("h0200a3b736466616d") @[Rom.scala 25:32] - rom[29] <= UInt<64>("h06d69742020202020") @[Rom.scala 25:32] - rom[30] <= UInt<64>("h034783020706d6365") @[Rom.scala 25:32] - rom[31] <= UInt<64>("h03b30303034303034") @[Rom.scala 25:32] - rom[32] <= UInt<64>("h0692020202020200a") @[Rom.scala 25:32] - rom[33] <= UInt<64>("h03034347830206970") @[Rom.scala 25:32] - rom[34] <= UInt<64>("h0200a3b3030303030") @[Rom.scala 25:32] - rom[35] <= UInt<64>("h0696c702020202020") @[Rom.scala 25:32] - rom[36] <= UInt<64>("h0202020200a7b2063") @[Rom.scala 25:32] - rom[37] <= UInt<64>("h0a7b206d20202020") @[Rom.scala 25:32] - rom[38] <= UInt<64>("h02020202020202020") @[Rom.scala 25:32] - rom[39] <= UInt<64>("h03034783020656920") @[Rom.scala 25:32] - rom[40] <= UInt<64>("h0a3b303030323030") @[Rom.scala 25:32] - rom[41] <= UInt<64>("h02020202020202020") @[Rom.scala 25:32] - rom[42] <= UInt<64>("h02068736572687420") @[Rom.scala 25:32] - rom[43] <= UInt<64>("h03030303230347830") @[Rom.scala 25:32] - rom[44] <= UInt<64>("h0202020200a3b3030") @[Rom.scala 25:32] - rom[45] <= UInt<64>("h0616c632020202020") @[Rom.scala 25:32] - rom[46] <= UInt<64>("h03230347830206d69") @[Rom.scala 25:32] - rom[47] <= UInt<64>("h0200a3b3430303030") @[Rom.scala 25:32] - rom[48] <= UInt<64>("h07d20202020202020") @[Rom.scala 25:32] - rom[49] <= UInt<64>("h02020202020200a3b") @[Rom.scala 25:32] - rom[50] <= UInt<64>("h020200a7b20732020") @[Rom.scala 25:32] - rom[51] <= UInt<64>("h06920202020202020") @[Rom.scala 25:32] - rom[52] <= UInt<64>("h03030303478302065") @[Rom.scala 25:32] - rom[53] <= UInt<64>("h020200a3b30383032") @[Rom.scala 25:32] - rom[54] <= UInt<64>("h07420202020202020") @[Rom.scala 25:32] - rom[55] <= UInt<64>("h07830206873657268") @[Rom.scala 25:32] - rom[56] <= UInt<64>("h03030303130323034") @[Rom.scala 25:32] - rom[57] <= UInt<64>("h02020202020200a3b") @[Rom.scala 25:32] - rom[58] <= UInt<64>("h06d69616c63202020") @[Rom.scala 25:32] - rom[59] <= UInt<64>("h03130323034783020") @[Rom.scala 25:32] - rom[60] <= UInt<64>("h02020200a3b343030") @[Rom.scala 25:32] - rom[61] <= UInt<64>("h0a3b7d2020202020") @[Rom.scala 25:32] - rom[62] <= UInt<64>("h03b7d202020202020") @[Rom.scala 25:32] - rom[63] <= UInt<64>("h0a3b7d202020200a") @[Rom.scala 25:32] - rom[64] <= UInt<64>("h0a3b7d0a3b7d2020") @[Rom.scala 25:32] - rom[65] <= UInt<64>("h00") @[Rom.scala 25:32] - node raddr = cat(acq.io.deq.bits.addr_block, addr_beat) @[Cat.scala 20:58] - node T_534 = bits(raddr, 6, 0) @[Rom.scala 30:52] - node T_536 = eq(multi_beat, UInt<1>("h00")) @[Rom.scala 32:14] - node T_538 = eq(addr_beat, UInt<3>("h07")) @[Rom.scala 32:39] - node last = or(T_536, T_538) @[Rom.scala 32:26] - io.grant.valid <= acq.io.deq.valid @[Rom.scala 33:18] - node T_539 = and(io.grant.ready, last) @[Rom.scala 34:31] - acq.io.deq.ready <= T_539 @[Rom.scala 34:13] - node T_556 = eq(UInt<3>("h06"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_557 = mux(T_556, UInt<3>("h01"), UInt<3>("h03")) @[Mux.scala 46:16] - node T_558 = eq(UInt<3>("h05"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_559 = mux(T_558, UInt<3>("h01"), T_557) @[Mux.scala 46:16] - node T_560 = eq(UInt<3>("h04"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_561 = mux(T_560, UInt<3>("h04"), T_559) @[Mux.scala 46:16] - node T_562 = eq(UInt<3>("h03"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_563 = mux(T_562, UInt<3>("h03"), T_561) @[Mux.scala 46:16] - node T_564 = eq(UInt<3>("h02"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_565 = mux(T_564, UInt<3>("h03"), T_563) @[Mux.scala 46:16] - node T_566 = eq(UInt<3>("h01"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_567 = mux(T_566, UInt<3>("h05"), T_565) @[Mux.scala 46:16] - node T_568 = eq(UInt<3>("h00"), acq.io.deq.bits.a_type) @[Mux.scala 46:19] - node T_569 = mux(T_568, UInt<3>("h04"), T_567) @[Mux.scala 46:16] - wire T_593 : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_593 is invalid @[Definitions.scala 863:19] - T_593.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_593.g_type <= T_569 @[Definitions.scala 865:16] - T_593.client_xact_id <= acq.io.deq.bits.client_xact_id @[Definitions.scala 866:24] - T_593.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_593.addr_beat <= addr_beat @[Definitions.scala 868:19] - T_593.data <= rom[T_534] @[Definitions.scala 869:14] - io.grant.bits <- T_593 @[Rom.scala 35:17] - - module DefaultCoreplex : + acq.io.enq.valid <= io.acquire.valid + acq.io.enq.bits <- io.acquire.bits + io.acquire.ready <= acq.io.enq.ready + node T_446 = eq(acq.io.deq.bits.a_type, UInt<3>("h0")) + node single_beat = and(acq.io.deq.bits.is_builtin_type, T_446) + node T_448 = eq(acq.io.deq.bits.a_type, UInt<3>("h1")) + node multi_beat = and(acq.io.deq.bits.is_builtin_type, T_448) + node T_450 = eq(acq.io.deq.valid, UInt<1>("h0")) + node T_451 = or(T_450, single_beat) + node T_452 = or(T_451, multi_beat) + node T_453 = or(T_452, reset) + node T_455 = eq(T_453, UInt<1>("h0")) + when T_455 : + printf(clk, UInt<1>("h1"), "Assertion failed: unsupported ROMSlave operation\n at Rom.scala:17 assert(!acq.valid || single_beat || multi_beat, \"unsupported ROMSlave operation\")\n") + stop(clk, UInt<1>("h1"), 1) + reg addr_beat : UInt, clk with : + reset => (UInt<1>("h0"), addr_beat) + node T_457 = and(io.grant.ready, io.grant.valid) + when T_457 : + node T_459 = add(addr_beat, UInt<1>("h1")) + node T_460 = tail(T_459, 1) + addr_beat <= T_460 + node T_461 = and(io.acquire.ready, io.acquire.valid) + when T_461 : + addr_beat <= io.acquire.bits.addr_beat + wire rom : UInt<64>[66] + rom is invalid + rom[0] <= UInt<64>("h6f") + rom[1] <= UInt<64>("h102000000000") + rom[2] <= UInt<64>("h0") + rom[3] <= UInt<64>("h0") + rom[4] <= UInt<64>("h200a7b2063696c70") + rom[5] <= UInt<64>("h7469726f69727020") + rom[6] <= UInt<64>("h3030303478302079") + rom[7] <= UInt<64>("h20200a3b30303030") + rom[8] <= UInt<64>("h20676e69646e6570") + rom[9] <= UInt<64>("h3031303030347830") + rom[10] <= UInt<64>("h646e20200a3b3030") + rom[11] <= UInt<64>("h7d0a3b3220737665") + rom[12] <= UInt<64>("ha7b206374720a3b") + rom[13] <= UInt<64>("h3020726464612020") + rom[14] <= UInt<64>("h6666623030343478") + rom[15] <= UInt<64>("h61720a3b7d0a3b38") + rom[16] <= UInt<64>("h203020200a7b206d") + rom[17] <= UInt<64>("h6461202020200a7b") + rom[18] <= UInt<64>("h3030387830207264") + rom[19] <= UInt<64>("h200a3b3030303030") + rom[20] <= UInt<64>("h20657a6973202020") + rom[21] <= UInt<64>("h3030303030317830") + rom[22] <= UInt<64>("h3b7d20200a3b3030") + rom[23] <= UInt<64>("h65726f630a3b7d0a") + rom[24] <= UInt<64>("h7b203020200a7b20") + rom[25] <= UInt<64>("h7b2030202020200a") + rom[26] <= UInt<64>("h692020202020200a") + rom[27] <= UInt<64>("h6934367672206173") + rom[28] <= UInt<64>("h200a3b736466616d") + rom[29] <= UInt<64>("h6d69742020202020") + rom[30] <= UInt<64>("h34783020706d6365") + rom[31] <= UInt<64>("h3b30303034303034") + rom[32] <= UInt<64>("h692020202020200a") + rom[33] <= UInt<64>("h3034347830206970") + rom[34] <= UInt<64>("h200a3b3030303030") + rom[35] <= UInt<64>("h696c702020202020") + rom[36] <= UInt<64>("h202020200a7b2063") + rom[37] <= UInt<64>("ha7b206d20202020") + rom[38] <= UInt<64>("h2020202020202020") + rom[39] <= UInt<64>("h3034783020656920") + rom[40] <= UInt<64>("ha3b303030323030") + rom[41] <= UInt<64>("h2020202020202020") + rom[42] <= UInt<64>("h2068736572687420") + rom[43] <= UInt<64>("h3030303230347830") + rom[44] <= UInt<64>("h202020200a3b3030") + rom[45] <= UInt<64>("h616c632020202020") + rom[46] <= UInt<64>("h3230347830206d69") + rom[47] <= UInt<64>("h200a3b3430303030") + rom[48] <= UInt<64>("h7d20202020202020") + rom[49] <= UInt<64>("h2020202020200a3b") + rom[50] <= UInt<64>("h20200a7b20732020") + rom[51] <= UInt<64>("h6920202020202020") + rom[52] <= UInt<64>("h3030303478302065") + rom[53] <= UInt<64>("h20200a3b30383032") + rom[54] <= UInt<64>("h7420202020202020") + rom[55] <= UInt<64>("h7830206873657268") + rom[56] <= UInt<64>("h3030303130323034") + rom[57] <= UInt<64>("h2020202020200a3b") + rom[58] <= UInt<64>("h6d69616c63202020") + rom[59] <= UInt<64>("h3130323034783020") + rom[60] <= UInt<64>("h2020200a3b343030") + rom[61] <= UInt<64>("ha3b7d2020202020") + rom[62] <= UInt<64>("h3b7d202020202020") + rom[63] <= UInt<64>("ha3b7d202020200a") + rom[64] <= UInt<64>("ha3b7d0a3b7d2020") + rom[65] <= UInt<64>("h0") + node raddr = cat(acq.io.deq.bits.addr_block, addr_beat) + node T_534 = bits(raddr, 6, 0) + node T_536 = eq(multi_beat, UInt<1>("h0")) + node T_538 = eq(addr_beat, UInt<3>("h7")) + node last = or(T_536, T_538) + io.grant.valid <= acq.io.deq.valid + node T_539 = and(io.grant.ready, last) + acq.io.deq.ready <= T_539 + node T_556 = eq(UInt<3>("h6"), acq.io.deq.bits.a_type) + node T_557 = mux(T_556, UInt<3>("h1"), UInt<3>("h3")) + node T_558 = eq(UInt<3>("h5"), acq.io.deq.bits.a_type) + node T_559 = mux(T_558, UInt<3>("h1"), T_557) + node T_560 = eq(UInt<3>("h4"), acq.io.deq.bits.a_type) + node T_561 = mux(T_560, UInt<3>("h4"), T_559) + node T_562 = eq(UInt<3>("h3"), acq.io.deq.bits.a_type) + node T_563 = mux(T_562, UInt<3>("h3"), T_561) + node T_564 = eq(UInt<3>("h2"), acq.io.deq.bits.a_type) + node T_565 = mux(T_564, UInt<3>("h3"), T_563) + node T_566 = eq(UInt<3>("h1"), acq.io.deq.bits.a_type) + node T_567 = mux(T_566, UInt<3>("h5"), T_565) + node T_568 = eq(UInt<3>("h0"), acq.io.deq.bits.a_type) + node T_569 = mux(T_568, UInt<3>("h4"), T_567) + wire T_593 : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_593 is invalid + T_593.is_builtin_type <= UInt<1>("h1") + T_593.g_type <= T_569 + T_593.client_xact_id <= acq.io.deq.bits.client_xact_id + T_593.manager_xact_id <= UInt<1>("h0") + T_593.addr_beat <= addr_beat + T_593.data <= rom[T_534] + io.grant.bits <- T_593 + + module DefaultCoreplex : input clk : Clock input reset : UInt<1> - output io : {master : {mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]}, flip slave : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], flip interrupts : UInt<1>[2], flip debug : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}}, flip rtcTick : UInt<1>} - + output io : { master : { mem : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[1]}, flip slave : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], flip interrupts : UInt<1>[2], flip debug : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<34>, resp : UInt<2>}}}, flip rtcTick : UInt<1>} + io is invalid - wire tileResets : UInt<1>[1] @[Coreplex.scala 72:24] - tileResets is invalid @[Coreplex.scala 72:24] - inst tileList_0 of RocketTile @[Configs.scala 104:17] + wire tileResets : UInt<1>[1] + tileResets is invalid + inst tileList_0 of RocketTile tileList_0.io is invalid tileList_0.clk <= clk tileList_0.reset <= tileResets[0] - inst PortedTileLinkCrossbar_1 of PortedTileLinkCrossbar @[Coreplex.scala 98:27] + inst PortedTileLinkCrossbar_1 of PortedTileLinkCrossbar PortedTileLinkCrossbar_1.io is invalid PortedTileLinkCrossbar_1.clk <= clk PortedTileLinkCrossbar_1.reset <= reset - inst L2BroadcastHub_1 of L2BroadcastHub @[Configs.scala 74:15] + inst L2BroadcastHub_1 of L2BroadcastHub L2BroadcastHub_1.io is invalid L2BroadcastHub_1.clk <= clk L2BroadcastHub_1.reset <= reset - L2BroadcastHub_1.io.incoherent[0] <= UInt<1>("h00") @[Coreplex.scala 102:54] - inst MMIOTileLinkManager_1 of MMIOTileLinkManager @[Coreplex.scala 104:29] + L2BroadcastHub_1.io.incoherent[0] <= UInt<1>("h0") + inst MMIOTileLinkManager_1 of MMIOTileLinkManager MMIOTileLinkManager_1.io is invalid MMIOTileLinkManager_1.clk <= clk MMIOTileLinkManager_1.reset <= reset - PortedTileLinkCrossbar_1.io.clients_cached[0] <- tileList_0.io.cached[0] @[Coreplex.scala 112:33] - PortedTileLinkCrossbar_1.io.clients_uncached[0] <- tileList_0.io.uncached[0] @[Coreplex.scala 113:35] - PortedTileLinkCrossbar_1.io.managers[0] <- L2BroadcastHub_1.io.inner @[Coreplex.scala 114:27] - PortedTileLinkCrossbar_1.io.managers[1] <- MMIOTileLinkManager_1.io.inner @[Coreplex.scala 114:27] - inst TileLinkMemoryInterconnect_1 of TileLinkMemoryInterconnect @[Coreplex.scala 117:24] + PortedTileLinkCrossbar_1.io.clients_cached[0] <- tileList_0.io.cached[0] + PortedTileLinkCrossbar_1.io.clients_uncached[0] <- tileList_0.io.uncached[0] + PortedTileLinkCrossbar_1.io.managers[0] <- L2BroadcastHub_1.io.inner + PortedTileLinkCrossbar_1.io.managers[1] <- MMIOTileLinkManager_1.io.inner + inst TileLinkMemoryInterconnect_1 of TileLinkMemoryInterconnect TileLinkMemoryInterconnect_1.io is invalid TileLinkMemoryInterconnect_1.clk <= clk TileLinkMemoryInterconnect_1.reset <= reset - inst ClientTileLinkIOUnwrapper_1 of ClientTileLinkIOUnwrapper @[Coreplex.scala 122:26] + inst ClientTileLinkIOUnwrapper_1 of ClientTileLinkIOUnwrapper ClientTileLinkIOUnwrapper_1.io is invalid ClientTileLinkIOUnwrapper_1.clk <= clk ClientTileLinkIOUnwrapper_1.reset <= reset - inst ClientTileLinkEnqueuer_1 of ClientTileLinkEnqueuer @[Enqueuer.scala 50:19] + inst ClientTileLinkEnqueuer_1 of ClientTileLinkEnqueuer ClientTileLinkEnqueuer_1.io is invalid ClientTileLinkEnqueuer_1.clk <= clk ClientTileLinkEnqueuer_1.reset <= reset - ClientTileLinkEnqueuer_1.io.inner <- L2BroadcastHub_1.io.outer @[Enqueuer.scala 51:16] - ClientTileLinkIOUnwrapper_1.io.in <- ClientTileLinkEnqueuer_1.io.outer @[Coreplex.scala 123:20] - TileLinkMemoryInterconnect_1.io.in[0] <- ClientTileLinkIOUnwrapper_1.io.out @[Tilelink.scala 174:9] - io.master.mem <= TileLinkMemoryInterconnect_1.io.out @[Coreplex.scala 127:19] - inst ClientUncachedTileLinkEnqueuer_1 of ClientUncachedTileLinkEnqueuer @[Enqueuer.scala 71:19] + ClientTileLinkEnqueuer_1.io.inner <- L2BroadcastHub_1.io.outer + ClientTileLinkIOUnwrapper_1.io.in <- ClientTileLinkEnqueuer_1.io.outer + TileLinkMemoryInterconnect_1.io.in[0] <- ClientTileLinkIOUnwrapper_1.io.out + io.master.mem <= TileLinkMemoryInterconnect_1.io.out + inst ClientUncachedTileLinkEnqueuer_1 of ClientUncachedTileLinkEnqueuer ClientUncachedTileLinkEnqueuer_1.io is invalid ClientUncachedTileLinkEnqueuer_1.clk <= clk ClientUncachedTileLinkEnqueuer_1.reset <= reset - ClientUncachedTileLinkEnqueuer_1.io.inner <- MMIOTileLinkManager_1.io.outer @[Enqueuer.scala 72:16] - inst TileLinkRecursiveInterconnect_2 of TileLinkRecursiveInterconnect @[Coreplex.scala 158:29] + ClientUncachedTileLinkEnqueuer_1.io.inner <- MMIOTileLinkManager_1.io.outer + inst TileLinkRecursiveInterconnect_2 of TileLinkRecursiveInterconnect TileLinkRecursiveInterconnect_2.io is invalid TileLinkRecursiveInterconnect_2.clk <= clk TileLinkRecursiveInterconnect_2.reset <= reset - TileLinkRecursiveInterconnect_2.io.in[0] <- ClientUncachedTileLinkEnqueuer_1.io.outer @[Coreplex.scala 159:28] - inst PLIC_1 of PLIC @[Coreplex.scala 161:22] + TileLinkRecursiveInterconnect_2.io.in[0] <- ClientUncachedTileLinkEnqueuer_1.io.outer + inst PLIC_1 of PLIC PLIC_1.io is invalid PLIC_1.clk <= clk PLIC_1.reset <= reset - PLIC_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[2] @[Coreplex.scala 162:16] - inst LevelGateway_2 of LevelGateway @[Coreplex.scala 164:27] + PLIC_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[2] + inst LevelGateway_2 of LevelGateway LevelGateway_2.io is invalid LevelGateway_2.clk <= clk LevelGateway_2.reset <= reset - LevelGateway_2.io.interrupt <= io.interrupts[0] @[Coreplex.scala 165:28] - PLIC_1.io.devices[0] <- LevelGateway_2.io.plic @[Coreplex.scala 166:26] - inst LevelGateway_1_1 of LevelGateway @[Coreplex.scala 164:27] + LevelGateway_2.io.interrupt <= io.interrupts[0] + PLIC_1.io.devices[0] <- LevelGateway_2.io.plic + inst LevelGateway_1_1 of LevelGateway LevelGateway_1_1.io is invalid LevelGateway_1_1.clk <= clk LevelGateway_1_1.reset <= reset - LevelGateway_1_1.io.interrupt <= io.interrupts[1] @[Coreplex.scala 165:28] - PLIC_1.io.devices[1] <- LevelGateway_1_1.io.plic @[Coreplex.scala 166:26] - inst DebugModule_1 of DebugModule @[Coreplex.scala 169:29] + LevelGateway_1_1.io.interrupt <= io.interrupts[1] + PLIC_1.io.devices[1] <- LevelGateway_1_1.io.plic + inst DebugModule_1 of DebugModule DebugModule_1.io is invalid DebugModule_1.clk <= clk DebugModule_1.reset <= reset - DebugModule_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[0] @[Coreplex.scala 170:23] - DebugModule_1.io.db <- io.debug @[Coreplex.scala 171:23] - inst PRCI_1 of PRCI @[Coreplex.scala 173:22] + DebugModule_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[0] + DebugModule_1.io.db <- io.debug + inst PRCI_1 of PRCI PRCI_1.io is invalid PRCI_1.clk <= clk PRCI_1.reset <= reset - PRCI_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[3] @[Coreplex.scala 174:16] - PRCI_1.io.rtcTick <= io.rtcTick @[Coreplex.scala 175:21] - tileResets[0] <= reset @[Coreplex.scala 179:13] - tileList_0.io.prci <- PRCI_1.io.tiles[0] @[Coreplex.scala 180:22] - PRCI_1.io.interrupts[0].meip <= PLIC_1.io.harts[0] @[Coreplex.scala 184:34] - PRCI_1.io.interrupts[0].seip <= PLIC_1.io.harts[1] @[Coreplex.scala 186:36] - PRCI_1.io.interrupts[0].debug <= DebugModule_1.io.debugInterrupts[0] @[Coreplex.scala 187:35] - inst ROMSlave_1 of ROMSlave @[Coreplex.scala 194:25] + PRCI_1.io.tl <- TileLinkRecursiveInterconnect_2.io.out[3] + PRCI_1.io.rtcTick <= io.rtcTick + tileResets[0] <= reset + tileList_0.io.prci <- PRCI_1.io.tiles[0] + PRCI_1.io.interrupts[0].meip <= PLIC_1.io.harts[0] + PRCI_1.io.interrupts[0].seip <= PLIC_1.io.harts[1] + PRCI_1.io.interrupts[0].debug <= DebugModule_1.io.debugInterrupts[0] + inst ROMSlave_1 of ROMSlave ROMSlave_1.io is invalid ROMSlave_1.clk <= clk ROMSlave_1.reset <= reset - ROMSlave_1.io <- TileLinkRecursiveInterconnect_2.io.out[1] @[Coreplex.scala 195:16] - - module ReorderQueue_2 : + ROMSlave_1.io <- TileLinkRecursiveInterconnect_2.io.out[1] + + module ReorderQueue_2 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {addr_beat : UInt<3>, subblock : UInt<1>}, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : {addr_beat : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : { addr_beat : UInt<3>, subblock : UInt<1>}, tag : UInt<4>}}, deq : { flip valid : UInt<1>, flip tag : UInt<4>, data : { addr_beat : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} + io is invalid - cmem T_229 : {addr_beat : UInt<3>, subblock : UInt<1>}[16] @[util.scala 220:23] - wire T_251 : UInt<1>[16] @[util.scala 221:53] - T_251 is invalid @[util.scala 221:53] - T_251[0] <= UInt<1>("h01") @[util.scala 221:53] - T_251[1] <= UInt<1>("h01") @[util.scala 221:53] - T_251[2] <= UInt<1>("h01") @[util.scala 221:53] - T_251[3] <= UInt<1>("h01") @[util.scala 221:53] - T_251[4] <= UInt<1>("h01") @[util.scala 221:53] - T_251[5] <= UInt<1>("h01") @[util.scala 221:53] - T_251[6] <= UInt<1>("h01") @[util.scala 221:53] - T_251[7] <= UInt<1>("h01") @[util.scala 221:53] - T_251[8] <= UInt<1>("h01") @[util.scala 221:53] - T_251[9] <= UInt<1>("h01") @[util.scala 221:53] - T_251[10] <= UInt<1>("h01") @[util.scala 221:53] - T_251[11] <= UInt<1>("h01") @[util.scala 221:53] - T_251[12] <= UInt<1>("h01") @[util.scala 221:53] - T_251[13] <= UInt<1>("h01") @[util.scala 221:53] - T_251[14] <= UInt<1>("h01") @[util.scala 221:53] - T_251[15] <= UInt<1>("h01") @[util.scala 221:53] - reg T_255 : UInt<1>[16], clk with : (reset => (reset, T_251)) - io.enq.ready <= T_255[io.enq.bits.tag] @[util.scala 223:18] + cmem T_229 : { addr_beat : UInt<3>, subblock : UInt<1>} [16] + wire T_251 : UInt<1>[16] + T_251 is invalid + T_251[0] <= UInt<1>("h1") + T_251[1] <= UInt<1>("h1") + T_251[2] <= UInt<1>("h1") + T_251[3] <= UInt<1>("h1") + T_251[4] <= UInt<1>("h1") + T_251[5] <= UInt<1>("h1") + T_251[6] <= UInt<1>("h1") + T_251[7] <= UInt<1>("h1") + T_251[8] <= UInt<1>("h1") + T_251[9] <= UInt<1>("h1") + T_251[10] <= UInt<1>("h1") + T_251[11] <= UInt<1>("h1") + T_251[12] <= UInt<1>("h1") + T_251[13] <= UInt<1>("h1") + T_251[14] <= UInt<1>("h1") + T_251[15] <= UInt<1>("h1") + reg T_255 : UInt<1>[16], clk with : + reset => (reset, T_251) + io.enq.ready <= T_255[io.enq.bits.tag] infer mport T_257 = T_229[io.deq.tag], clk - io.deq.data <- T_257 @[util.scala 224:17] - node T_281 = eq(T_255[io.deq.tag], UInt<1>("h00")) @[util.scala 225:23] - io.deq.matches <= T_281 @[util.scala 225:20] - node T_282 = and(io.enq.valid, io.enq.ready) @[util.scala 227:24] - when T_282 : @[util.scala 227:41] + io.deq.data <- T_257 + node T_281 = eq(T_255[io.deq.tag], UInt<1>("h0")) + io.deq.matches <= T_281 + node T_282 = and(io.enq.valid, io.enq.ready) + when T_282 : infer mport T_283 = T_229[io.enq.bits.tag], clk - T_283 <- io.enq.bits.data @[util.scala 228:33] - T_255[io.enq.bits.tag] <= UInt<1>("h00") @[util.scala 229:33] - skip @[util.scala 227:41] - when io.deq.valid : @[util.scala 232:25] - T_255[io.deq.tag] <= UInt<1>("h01") @[util.scala 233:28] - skip @[util.scala 232:25] - - module IdMapper : + T_283 <- io.enq.bits.data + T_255[io.enq.bits.tag] <= UInt<1>("h0") + when io.deq.valid : + T_255[io.deq.tag] <= UInt<1>("h1") + + module IdMapper : input clk : Clock input reset : UInt<1> - output io : {req : {flip valid : UInt<1>, ready : UInt<1>, flip in_id : UInt<4>, out_id : UInt<5>}, resp : {flip valid : UInt<1>, matches : UInt<1>, flip out_id : UInt<5>, in_id : UInt<4>}} - + output io : { req : { flip valid : UInt<1>, ready : UInt<1>, flip in_id : UInt<4>, out_id : UInt<5>}, resp : { flip valid : UInt<1>, matches : UInt<1>, flip out_id : UInt<5>, in_id : UInt<4>}} + io is invalid - io.req.ready <= UInt<1>("h01") @[Nasti.scala 31:18] - io.req.out_id <= io.req.in_id @[Nasti.scala 32:19] - io.resp.matches <= UInt<1>("h01") @[Nasti.scala 33:21] - io.resp.in_id <= io.resp.out_id @[Nasti.scala 34:19] - - module LockingArbiter : + io.req.ready <= UInt<1>("h1") + io.req.out_id <= io.req.in_id + io.resp.matches <= UInt<1>("h1") + io.resp.in_id <= io.resp.out_id + + module LockingArbiter : input clk : Clock input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} - + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} + io is invalid wire choice : UInt choice is invalid - choice <= UInt<1>("h01") - io.chosen <= choice @[Arbiter.scala 32:13] - io.out.valid <= io.in[io.chosen].valid @[Arbiter.scala 33:16] - io.out.bits <- io.in[io.chosen].bits @[Arbiter.scala 34:15] - reg T_766 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - reg T_768 : UInt, clk - node T_770 = neq(T_766, UInt<1>("h00")) @[Arbiter.scala 39:34] - wire T_778 : UInt<3>[1] @[Definitions.scala 853:34] - T_778 is invalid @[Definitions.scala 853:34] - T_778[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_780 = eq(io.out.bits.g_type, T_778[0]) @[Package.scala 7:47] - node T_781 = eq(io.out.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_782 = mux(io.out.bits.is_builtin_type, T_780, T_781) @[Definitions.scala 274:33] - node T_783 = and(UInt<1>("h01"), T_782) @[Definitions.scala 274:27] - node T_784 = and(io.out.ready, io.out.valid) @[Decoupled.scala 21:42] - node T_785 = and(T_784, T_783) @[Arbiter.scala 42:25] - when T_785 : @[Arbiter.scala 42:39] - T_768 <= io.chosen @[Arbiter.scala 43:15] - node T_787 = eq(T_766, UInt<3>("h07")) @[Counter.scala 20:24] - node T_789 = add(T_766, UInt<1>("h01")) @[Counter.scala 21:22] - node T_790 = tail(T_789, 1) @[Counter.scala 21:22] - T_766 <= T_790 @[Counter.scala 21:13] - skip @[Arbiter.scala 42:39] - when T_770 : @[Arbiter.scala 47:19] - io.chosen <= T_768 @[Arbiter.scala 47:31] - skip @[Arbiter.scala 47:19] - node T_793 = eq(io.in[0].valid, UInt<1>("h00")) @[Arbiter.scala 23:82] - node T_795 = eq(T_768, UInt<1>("h00")) @[Arbiter.scala 49:39] - node T_796 = mux(T_770, T_795, UInt<1>("h01")) @[Arbiter.scala 49:22] - node T_797 = and(T_796, io.out.ready) @[Arbiter.scala 49:55] - io.in[0].ready <= T_797 @[Arbiter.scala 49:16] - node T_799 = eq(T_768, UInt<1>("h01")) @[Arbiter.scala 49:39] - node T_800 = mux(T_770, T_799, T_793) @[Arbiter.scala 49:22] - node T_801 = and(T_800, io.out.ready) @[Arbiter.scala 49:55] - io.in[1].ready <= T_801 @[Arbiter.scala 49:16] - when io.in[0].valid : @[Arbiter.scala 80:27] - choice <= UInt<1>("h00") @[Arbiter.scala 80:36] - skip @[Arbiter.scala 80:27] - - module NastiIOTileLinkIOConverter : + choice <= UInt<1>("h1") + io.chosen <= choice + io.out.valid <= io.in[io.chosen].valid + io.out.bits <- io.in[io.chosen].bits + reg T_766 : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + reg T_768 : UInt, clk with : + reset => (UInt<1>("h0"), T_768) + node T_770 = neq(T_766, UInt<1>("h0")) + wire T_778 : UInt<3>[1] + T_778 is invalid + T_778[0] <= UInt<3>("h5") + node T_780 = eq(io.out.bits.g_type, T_778[0]) + node T_781 = eq(io.out.bits.g_type, UInt<1>("h0")) + node T_782 = mux(io.out.bits.is_builtin_type, T_780, T_781) + node T_783 = and(UInt<1>("h1"), T_782) + node T_784 = and(io.out.ready, io.out.valid) + node T_785 = and(T_784, T_783) + when T_785 : + T_768 <= io.chosen + node T_787 = eq(T_766, UInt<3>("h7")) + node T_789 = add(T_766, UInt<1>("h1")) + node T_790 = tail(T_789, 1) + T_766 <= T_790 + when T_770 : + io.chosen <= T_768 + node T_793 = eq(io.in[0].valid, UInt<1>("h0")) + node T_795 = eq(T_768, UInt<1>("h0")) + node T_796 = mux(T_770, T_795, UInt<1>("h1")) + node T_797 = and(T_796, io.out.ready) + io.in[0].ready <= T_797 + node T_799 = eq(T_768, UInt<1>("h1")) + node T_800 = mux(T_770, T_799, T_793) + node T_801 = and(T_800, io.out.ready) + io.in[1].ready <= T_801 + when io.in[0].valid : + choice <= UInt<1>("h0") + + module NastiIOTileLinkIOConverter : input clk : Clock input reset : UInt<1> - output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - + output io : { flip tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + + wire T_725 : UInt<1> + T_725 is invalid + wire T_1075 : UInt<1> + T_1075 is invalid + wire T_766 : UInt<1> + T_766 is invalid io is invalid - wire T_688 : UInt<3>[3] @[Definitions.scala 354:26] - T_688 is invalid @[Definitions.scala 354:26] - T_688[0] <= UInt<3>("h02") @[Definitions.scala 354:26] - T_688[1] <= UInt<3>("h03") @[Definitions.scala 354:26] - T_688[2] <= UInt<3>("h04") @[Definitions.scala 354:26] - node T_690 = eq(io.tl.acquire.bits.a_type, T_688[0]) @[Package.scala 7:47] - node T_691 = eq(io.tl.acquire.bits.a_type, T_688[1]) @[Package.scala 7:47] - node T_692 = eq(io.tl.acquire.bits.a_type, T_688[2]) @[Package.scala 7:47] - node T_693 = or(T_690, T_691) @[Package.scala 7:62] - node T_694 = or(T_693, T_692) @[Package.scala 7:62] - node has_data = and(io.tl.acquire.bits.is_builtin_type, T_694) @[Definitions.scala 228:55] - wire T_703 : UInt<3>[3] @[Definitions.scala 356:29] - T_703 is invalid @[Definitions.scala 356:29] - T_703[0] <= UInt<3>("h02") @[Definitions.scala 356:29] - T_703[1] <= UInt<3>("h00") @[Definitions.scala 356:29] - T_703[2] <= UInt<3>("h04") @[Definitions.scala 356:29] - node T_705 = eq(io.tl.acquire.bits.a_type, T_703[0]) @[Package.scala 7:47] - node T_706 = eq(io.tl.acquire.bits.a_type, T_703[1]) @[Package.scala 7:47] - node T_707 = eq(io.tl.acquire.bits.a_type, T_703[2]) @[Package.scala 7:47] - node T_708 = or(T_705, T_706) @[Package.scala 7:62] - node T_709 = or(T_708, T_707) @[Package.scala 7:62] - node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_709) @[Definitions.scala 215:62] - node T_711 = and(UInt<1>("h01"), io.tl.acquire.bits.is_builtin_type) @[Definitions.scala 231:70] - wire T_718 : UInt<3>[1] @[Definitions.scala 355:35] - T_718 is invalid @[Definitions.scala 355:35] - T_718[0] <= UInt<3>("h03") @[Definitions.scala 355:35] - node T_720 = eq(io.tl.acquire.bits.a_type, T_718[0]) @[Package.scala 7:47] - node is_multibeat = and(T_711, T_720) @[Definitions.scala 231:89] - node T_721 = and(io.tl.acquire.ready, io.tl.acquire.valid) @[Decoupled.scala 21:42] - node T_722 = and(T_721, is_multibeat) @[Nasti.scala 85:26] - reg tl_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_722 : @[Counter.scala 43:17] - node T_725 = eq(tl_cnt_out, UInt<3>("h07")) @[Counter.scala 20:24] - node T_727 = add(tl_cnt_out, UInt<1>("h01")) @[Counter.scala 21:22] - node T_728 = tail(T_727, 1) @[Counter.scala 21:22] - tl_cnt_out <= T_728 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node tl_wrap_out = and(T_722, T_725) @[Counter.scala 44:20] - node T_730 = eq(has_data, UInt<1>("h00")) @[Nasti.scala 87:42] - node get_valid = and(io.tl.acquire.valid, T_730) @[Nasti.scala 87:39] - node put_valid = and(io.tl.acquire.valid, has_data) @[Nasti.scala 88:39] - inst roq of ReorderQueue_2 @[Nasti.scala 93:19] + wire T_688 : UInt<3>[3] + T_688 is invalid + T_688[0] <= UInt<3>("h2") + T_688[1] <= UInt<3>("h3") + T_688[2] <= UInt<3>("h4") + node T_690 = eq(io.tl.acquire.bits.a_type, T_688[0]) + node T_691 = eq(io.tl.acquire.bits.a_type, T_688[1]) + node T_692 = eq(io.tl.acquire.bits.a_type, T_688[2]) + node T_693 = or(T_690, T_691) + node T_694 = or(T_693, T_692) + node has_data = and(io.tl.acquire.bits.is_builtin_type, T_694) + wire T_703 : UInt<3>[3] + T_703 is invalid + T_703[0] <= UInt<3>("h2") + T_703[1] <= UInt<3>("h0") + T_703[2] <= UInt<3>("h4") + node T_705 = eq(io.tl.acquire.bits.a_type, T_703[0]) + node T_706 = eq(io.tl.acquire.bits.a_type, T_703[1]) + node T_707 = eq(io.tl.acquire.bits.a_type, T_703[2]) + node T_708 = or(T_705, T_706) + node T_709 = or(T_708, T_707) + node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_709) + node T_711 = and(UInt<1>("h1"), io.tl.acquire.bits.is_builtin_type) + wire T_718 : UInt<3>[1] + T_718 is invalid + T_718[0] <= UInt<3>("h3") + node T_720 = eq(io.tl.acquire.bits.a_type, T_718[0]) + node is_multibeat = and(T_711, T_720) + node T_721 = and(io.tl.acquire.ready, io.tl.acquire.valid) + node T_722 = and(T_721, is_multibeat) + reg tl_cnt_out : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_722 : + T_725 <= eq(tl_cnt_out, UInt<3>("h7")) + node T_727 = add(tl_cnt_out, UInt<1>("h1")) + node T_728 = tail(T_727, 1) + tl_cnt_out <= T_728 + node tl_wrap_out = and(T_722, T_725) + node T_730 = eq(has_data, UInt<1>("h0")) + node get_valid = and(io.tl.acquire.valid, T_730) + node put_valid = and(io.tl.acquire.valid, has_data) + inst roq of ReorderQueue_2 roq.io is invalid roq.clk <= clk roq.reset <= reset - inst get_id_mapper of IdMapper @[Nasti.scala 96:29] + inst get_id_mapper of IdMapper get_id_mapper.io is invalid get_id_mapper.clk <= clk get_id_mapper.reset <= reset - inst put_id_mapper of IdMapper @[Nasti.scala 97:29] + inst put_id_mapper of IdMapper put_id_mapper.io is invalid put_id_mapper.clk <= clk put_id_mapper.reset <= reset - node T_755 = eq(io.tl.acquire.bits.addr_beat, UInt<1>("h00")) @[Nasti.scala 100:65] - node put_id_mask = or(is_subblock, T_755) @[Nasti.scala 100:33] - node T_757 = eq(put_id_mask, UInt<1>("h00")) @[Nasti.scala 101:52] - node put_id_ready = or(put_id_mapper.io.req.ready, T_757) @[Nasti.scala 101:49] - reg w_inflight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg w_id_reg : UInt<5>, clk with : (reset => (reset, UInt<5>("h00"))) - node w_id = mux(w_inflight, w_id_reg, put_id_mapper.io.req.out_id) @[Nasti.scala 112:17] - node aw_ready = or(w_inflight, io.nasti.aw.ready) @[Nasti.scala 116:29] - node T_760 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 21:42] - node T_762 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) @[Nasti.scala 124:26] - node T_763 = and(T_760, T_762) @[Nasti.scala 124:23] - reg nasti_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_763 : @[Counter.scala 43:17] - node T_766 = eq(nasti_cnt_out, UInt<3>("h07")) @[Counter.scala 20:24] - node T_768 = add(nasti_cnt_out, UInt<1>("h01")) @[Counter.scala 21:22] - node T_769 = tail(T_768, 1) @[Counter.scala 21:22] - nasti_cnt_out <= T_769 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node nasti_wrap_out = and(T_763, T_766) @[Counter.scala 44:20] - node T_770 = and(get_valid, io.nasti.ar.ready) @[util.scala 244:53] - node T_771 = and(T_770, get_id_mapper.io.req.ready) @[util.scala 244:53] - roq.io.enq.valid <= T_771 @[Nasti.scala 126:20] - roq.io.enq.bits.tag <= io.nasti.ar.bits.id @[Nasti.scala 127:23] - roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat @[Nasti.scala 128:34] - roq.io.enq.bits.data.subblock <= is_subblock @[Nasti.scala 129:33] - node T_772 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 21:42] - node T_773 = or(nasti_wrap_out, roq.io.deq.data.subblock) @[Nasti.scala 130:60] - node T_774 = and(T_772, T_773) @[Nasti.scala 130:41] - roq.io.deq.valid <= T_774 @[Nasti.scala 130:20] - roq.io.deq.tag <= io.nasti.r.bits.id @[Nasti.scala 131:18] - node T_775 = and(get_valid, roq.io.enq.ready) @[util.scala 244:53] - node T_776 = and(T_775, io.nasti.ar.ready) @[util.scala 244:53] - get_id_mapper.io.req.valid <= T_776 @[Nasti.scala 133:30] - get_id_mapper.io.req.in_id <= io.tl.acquire.bits.client_xact_id @[Nasti.scala 134:30] - node T_777 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 21:42] - node T_778 = and(T_777, io.nasti.r.bits.last) @[Nasti.scala 135:52] - get_id_mapper.io.resp.valid <= T_778 @[Nasti.scala 135:31] - get_id_mapper.io.resp.out_id <= io.nasti.r.bits.id @[Nasti.scala 136:32] - node T_779 = and(put_valid, aw_ready) @[util.scala 244:53] - node T_780 = and(T_779, io.nasti.w.ready) @[util.scala 244:53] - node T_781 = and(T_780, put_id_mask) @[util.scala 244:53] - put_id_mapper.io.req.valid <= T_781 @[Nasti.scala 138:30] - put_id_mapper.io.req.in_id <= io.tl.acquire.bits.client_xact_id @[Nasti.scala 139:30] - node T_782 = and(io.nasti.b.ready, io.nasti.b.valid) @[Decoupled.scala 21:42] - put_id_mapper.io.resp.valid <= T_782 @[Nasti.scala 140:31] - put_id_mapper.io.resp.out_id <= io.nasti.b.bits.id @[Nasti.scala 141:32] - node T_783 = and(get_valid, roq.io.enq.ready) @[util.scala 244:53] - node T_784 = and(T_783, get_id_mapper.io.req.ready) @[util.scala 244:53] - io.nasti.ar.valid <= T_784 @[Nasti.scala 144:21] - wire T_792 : UInt<3>[2] @[Definitions.scala 357:30] - T_792 is invalid @[Definitions.scala 357:30] - T_792[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_792[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_794 = eq(io.tl.acquire.bits.a_type, T_792[0]) @[Package.scala 7:47] - node T_795 = eq(io.tl.acquire.bits.a_type, T_792[1]) @[Package.scala 7:47] - node T_796 = or(T_794, T_795) @[Package.scala 7:62] - node T_797 = and(io.tl.acquire.bits.is_builtin_type, T_796) @[Definitions.scala 300:27] - node T_798 = bits(io.tl.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_800 = mux(T_797, T_798, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_801 = cat(io.tl.acquire.bits.addr_block, io.tl.acquire.bits.addr_beat) @[Cat.scala 20:58] - node T_802 = cat(T_801, T_800) @[Cat.scala 20:58] - node T_803 = bits(io.tl.acquire.bits.union, 7, 6) @[Definitions.scala 176:38] - node T_805 = mux(is_subblock, T_803, UInt<2>("h03")) @[Nasti.scala 148:15] - node T_808 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07")) @[Nasti.scala 151:14] - wire T_828 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 165:18] - T_828 is invalid @[nasti.scala 165:18] - T_828.id <= get_id_mapper.io.req.out_id @[nasti.scala 166:11] - T_828.addr <= T_802 @[nasti.scala 167:13] - T_828.len <= T_808 @[nasti.scala 168:12] - T_828.size <= T_805 @[nasti.scala 169:13] - T_828.burst <= UInt<2>("h01") @[nasti.scala 170:14] - T_828.lock <= UInt<1>("h00") @[nasti.scala 171:13] - T_828.cache <= UInt<1>("h00") @[nasti.scala 172:14] - T_828.prot <= UInt<1>("h00") @[nasti.scala 173:13] - T_828.qos <= UInt<1>("h00") @[nasti.scala 174:12] - T_828.region <= UInt<1>("h00") @[nasti.scala 175:15] - T_828.user <= UInt<1>("h00") @[nasti.scala 176:13] - io.nasti.ar.bits <- T_828 @[Nasti.scala 145:20] - node T_847 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_848 = and(io.tl.acquire.bits.is_builtin_type, T_847) @[Definitions.scala 212:54] - node T_870 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_872 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_873 = and(io.tl.acquire.bits.is_builtin_type, T_872) @[Definitions.scala 212:54] - node T_875 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_876 = and(io.tl.acquire.bits.is_builtin_type, T_875) @[Definitions.scala 212:54] - node T_877 = or(T_873, T_876) @[Definitions.scala 190:56] - node T_878 = bits(io.tl.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_880 = mux(T_877, T_878, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_881 = mux(T_848, T_870, T_880) @[Definitions.scala 192:8] - node T_882 = not(T_881) @[Nasti.scala 170:23] - node all_inside_0_0 = bits(T_882, 0, 0) @[Nasti.scala 170:52] - node all_inside_0_1 = bits(T_882, 1, 1) @[Nasti.scala 170:52] - node all_inside_0_2 = bits(T_882, 2, 2) @[Nasti.scala 170:52] - node all_inside_0_3 = bits(T_882, 3, 3) @[Nasti.scala 170:52] - node all_inside_0_4 = bits(T_882, 4, 4) @[Nasti.scala 170:52] - node all_inside_0_5 = bits(T_882, 5, 5) @[Nasti.scala 170:52] - node all_inside_0_6 = bits(T_882, 6, 6) @[Nasti.scala 170:52] - node all_inside_0_7 = bits(T_882, 7, 7) @[Nasti.scala 170:52] - node T_883 = and(all_inside_0_0, all_inside_0_1) @[Nasti.scala 158:72] - node T_884 = and(all_inside_0_2, all_inside_0_3) @[Nasti.scala 158:72] - node T_885 = and(all_inside_0_4, all_inside_0_5) @[Nasti.scala 158:72] - node T_886 = and(all_inside_0_6, all_inside_0_7) @[Nasti.scala 158:72] - node T_887 = and(T_883, T_884) @[Nasti.scala 158:72] - node T_888 = and(T_885, T_886) @[Nasti.scala 158:72] - node T_889 = and(T_887, T_888) @[Nasti.scala 158:72] - node T_893 = and(UInt<1>("h01"), T_888) @[Nasti.scala 160:72] - node T_894 = and(UInt<1>("h01"), T_887) @[Nasti.scala 160:72] - node T_895 = or(T_893, T_894) @[Nasti.scala 163:49] - node T_896 = cat(UInt<1>("h00"), T_894) @[Cat.scala 20:58] - node T_898 = mux(T_895, UInt<2>("h02"), UInt<2>("h03")) @[Nasti.scala 165:21] - node T_899 = and(T_893, T_884) @[Nasti.scala 160:72] - node T_900 = and(T_893, T_883) @[Nasti.scala 160:72] - node T_901 = and(T_894, T_886) @[Nasti.scala 160:72] - node T_902 = and(T_894, T_885) @[Nasti.scala 160:72] - node T_903 = or(T_900, T_902) @[Nasti.scala 162:49] - node T_904 = or(T_899, T_900) @[Nasti.scala 163:49] - node T_905 = or(T_904, T_901) @[Nasti.scala 163:49] - node T_906 = or(T_905, T_902) @[Nasti.scala 163:49] - node T_907 = cat(T_896, T_903) @[Cat.scala 20:58] - node T_909 = mux(T_906, UInt<1>("h01"), T_898) @[Nasti.scala 165:21] - node T_910 = and(T_899, all_inside_0_1) @[Nasti.scala 160:72] - node T_911 = and(T_899, all_inside_0_0) @[Nasti.scala 160:72] - node T_912 = and(T_900, all_inside_0_3) @[Nasti.scala 160:72] - node T_913 = and(T_900, all_inside_0_2) @[Nasti.scala 160:72] - node T_914 = and(T_901, all_inside_0_5) @[Nasti.scala 160:72] - node T_915 = and(T_901, all_inside_0_4) @[Nasti.scala 160:72] - node T_916 = and(T_902, all_inside_0_7) @[Nasti.scala 160:72] - node T_917 = and(T_902, all_inside_0_6) @[Nasti.scala 160:72] - node T_918 = or(T_911, T_913) @[Nasti.scala 162:49] - node T_919 = or(T_918, T_915) @[Nasti.scala 162:49] - node T_920 = or(T_919, T_917) @[Nasti.scala 162:49] - node T_921 = or(T_910, T_911) @[Nasti.scala 163:49] - node T_922 = or(T_921, T_912) @[Nasti.scala 163:49] - node T_923 = or(T_922, T_913) @[Nasti.scala 163:49] - node T_924 = or(T_923, T_914) @[Nasti.scala 163:49] - node T_925 = or(T_924, T_915) @[Nasti.scala 163:49] - node T_926 = or(T_925, T_916) @[Nasti.scala 163:49] - node T_927 = or(T_926, T_917) @[Nasti.scala 163:49] - node put_offset = cat(T_907, T_920) @[Cat.scala 20:58] - node put_size = mux(T_927, UInt<1>("h00"), T_909) @[Nasti.scala 165:21] - node T_930 = eq(w_inflight, UInt<1>("h00")) @[Nasti.scala 173:50] - node T_931 = and(put_valid, io.nasti.w.ready) @[util.scala 244:53] - node T_932 = and(T_931, put_id_ready) @[util.scala 244:53] - node T_933 = and(T_932, T_930) @[util.scala 244:53] - io.nasti.aw.valid <= T_933 @[Nasti.scala 173:21] - wire T_941 : UInt<3>[2] @[Definitions.scala 357:30] - T_941 is invalid @[Definitions.scala 357:30] - T_941[0] <= UInt<3>("h00") @[Definitions.scala 357:30] - T_941[1] <= UInt<3>("h04") @[Definitions.scala 357:30] - node T_943 = eq(io.tl.acquire.bits.a_type, T_941[0]) @[Package.scala 7:47] - node T_944 = eq(io.tl.acquire.bits.a_type, T_941[1]) @[Package.scala 7:47] - node T_945 = or(T_943, T_944) @[Package.scala 7:62] - node T_946 = and(io.tl.acquire.bits.is_builtin_type, T_945) @[Definitions.scala 300:27] - node T_947 = bits(io.tl.acquire.bits.union, 10, 8) @[Definitions.scala 178:40] - node T_949 = mux(T_946, T_947, UInt<3>("h00")) @[Definitions.scala 300:10] - node T_950 = cat(io.tl.acquire.bits.addr_block, io.tl.acquire.bits.addr_beat) @[Cat.scala 20:58] - node T_951 = cat(T_950, T_949) @[Cat.scala 20:58] - node T_953 = mux(is_multibeat, UInt<1>("h00"), put_offset) @[Nasti.scala 177:15] - node T_954 = or(T_951, T_953) @[Nasti.scala 176:43] - node T_956 = mux(is_multibeat, UInt<2>("h03"), put_size) @[Nasti.scala 178:15] - node T_959 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00")) @[Nasti.scala 179:14] - wire T_972 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 145:18] - T_972 is invalid @[nasti.scala 145:18] - T_972.id <= put_id_mapper.io.req.out_id @[nasti.scala 146:11] - T_972.addr <= T_954 @[nasti.scala 147:13] - T_972.len <= T_959 @[nasti.scala 148:12] - T_972.size <= T_956 @[nasti.scala 149:13] - T_972.burst <= UInt<2>("h01") @[nasti.scala 150:14] - T_972.lock <= UInt<1>("h00") @[nasti.scala 151:13] - T_972.cache <= UInt<4>("h00") @[nasti.scala 152:14] - T_972.prot <= UInt<3>("h00") @[nasti.scala 153:13] - T_972.qos <= UInt<4>("h00") @[nasti.scala 154:12] - T_972.region <= UInt<4>("h00") @[nasti.scala 155:15] - T_972.user <= UInt<1>("h00") @[nasti.scala 156:13] - io.nasti.aw.bits <- T_972 @[Nasti.scala 174:20] - node T_990 = and(put_valid, aw_ready) @[util.scala 244:53] - node T_991 = and(T_990, put_id_ready) @[util.scala 244:53] - io.nasti.w.valid <= T_991 @[Nasti.scala 181:20] - node T_993 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) @[Definitions.scala 212:64] - node T_994 = and(io.tl.acquire.bits.is_builtin_type, T_993) @[Definitions.scala 212:54] - node T_1016 = asUInt(asSInt(UInt<8>("h0ff"))) @[Definitions.scala 401:97] - node T_1018 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) @[Definitions.scala 212:64] - node T_1019 = and(io.tl.acquire.bits.is_builtin_type, T_1018) @[Definitions.scala 212:54] - node T_1021 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) @[Definitions.scala 212:64] - node T_1022 = and(io.tl.acquire.bits.is_builtin_type, T_1021) @[Definitions.scala 212:54] - node T_1023 = or(T_1019, T_1022) @[Definitions.scala 190:56] - node T_1024 = bits(io.tl.acquire.bits.union, 8, 1) @[Definitions.scala 191:25] - node T_1026 = mux(T_1023, T_1024, UInt<1>("h00")) @[Definitions.scala 192:30] - node T_1027 = mux(T_994, T_1016, T_1026) @[Definitions.scala 192:8] - node T_1029 = eq(tl_cnt_out, UInt<3>("h07")) @[Nasti.scala 187:18] - node T_1031 = eq(is_multibeat, UInt<1>("h00")) @[Nasti.scala 187:45] - node T_1032 = mux(w_inflight, T_1029, T_1031) @[Nasti.scala 186:15] - wire T_1039 : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>} @[nasti.scala 185:17] - T_1039 is invalid @[nasti.scala 185:17] - T_1039.strb <= T_1027 @[nasti.scala 186:12] - T_1039.data <= io.tl.acquire.bits.data @[nasti.scala 187:12] - T_1039.last <= T_1032 @[nasti.scala 188:12] - T_1039.id <= w_id @[nasti.scala 189:12] - T_1039.user <= UInt<1>("h00") @[nasti.scala 190:12] - io.nasti.w.bits <- T_1039 @[Nasti.scala 182:19] - node T_1046 = and(aw_ready, io.nasti.w.ready) @[util.scala 244:53] - node T_1047 = and(T_1046, put_id_ready) @[util.scala 244:53] - node T_1048 = and(roq.io.enq.ready, io.nasti.ar.ready) @[util.scala 244:53] - node T_1049 = and(T_1048, get_id_mapper.io.req.ready) @[util.scala 244:53] - node T_1050 = mux(has_data, T_1047, T_1049) @[Nasti.scala 189:29] - io.tl.acquire.ready <= T_1050 @[Nasti.scala 189:23] - node T_1052 = eq(w_inflight, UInt<1>("h00")) @[Nasti.scala 193:9] - node T_1053 = and(io.tl.acquire.ready, io.tl.acquire.valid) @[Decoupled.scala 21:42] - node T_1054 = and(T_1052, T_1053) @[Nasti.scala 193:21] - node T_1055 = and(T_1054, is_multibeat) @[Nasti.scala 193:45] - when T_1055 : @[Nasti.scala 193:62] - w_inflight <= UInt<1>("h01") @[Nasti.scala 194:16] - w_id_reg <= w_id @[Nasti.scala 195:14] - skip @[Nasti.scala 193:62] - when w_inflight : @[Nasti.scala 198:21] - when tl_wrap_out : @[Nasti.scala 199:24] - w_inflight <= UInt<1>("h00") @[Nasti.scala 199:37] - skip @[Nasti.scala 199:24] - skip @[Nasti.scala 198:21] - node T_1058 = and(io.tl.grant.ready, io.tl.grant.valid) @[Decoupled.scala 21:42] - wire T_1066 : UInt<3>[1] @[Definitions.scala 853:34] - T_1066 is invalid @[Definitions.scala 853:34] - T_1066[0] <= UInt<3>("h05") @[Definitions.scala 853:34] - node T_1068 = eq(io.tl.grant.bits.g_type, T_1066[0]) @[Package.scala 7:47] - node T_1069 = eq(io.tl.grant.bits.g_type, UInt<1>("h00")) @[Package.scala 7:47] - node T_1070 = mux(io.tl.grant.bits.is_builtin_type, T_1068, T_1069) @[Definitions.scala 274:33] - node T_1071 = and(UInt<1>("h01"), T_1070) @[Definitions.scala 274:27] - node T_1072 = and(T_1058, T_1071) @[Nasti.scala 204:24] - reg tl_cnt_in : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) - when T_1072 : @[Counter.scala 43:17] - node T_1075 = eq(tl_cnt_in, UInt<3>("h07")) @[Counter.scala 20:24] - node T_1077 = add(tl_cnt_in, UInt<1>("h01")) @[Counter.scala 21:22] - node T_1078 = tail(T_1077, 1) @[Counter.scala 21:22] - tl_cnt_in <= T_1078 @[Counter.scala 21:13] - skip @[Counter.scala 43:17] - node tl_wrap_in = and(T_1072, T_1075) @[Counter.scala 44:20] - inst gnt_arb of LockingArbiter @[Nasti.scala 205:23] + node T_755 = eq(io.tl.acquire.bits.addr_beat, UInt<1>("h0")) + node put_id_mask = or(is_subblock, T_755) + node T_757 = eq(put_id_mask, UInt<1>("h0")) + node put_id_ready = or(put_id_mapper.io.req.ready, T_757) + reg w_inflight : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg w_id_reg : UInt<5>, clk with : + reset => (reset, UInt<5>("h0")) + node w_id = mux(w_inflight, w_id_reg, put_id_mapper.io.req.out_id) + node aw_ready = or(w_inflight, io.nasti.aw.ready) + node T_760 = and(io.nasti.r.ready, io.nasti.r.valid) + node T_762 = eq(roq.io.deq.data.subblock, UInt<1>("h0")) + node T_763 = and(T_760, T_762) + reg nasti_cnt_out : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_763 : + T_766 <= eq(nasti_cnt_out, UInt<3>("h7")) + node T_768 = add(nasti_cnt_out, UInt<1>("h1")) + node T_769 = tail(T_768, 1) + nasti_cnt_out <= T_769 + node nasti_wrap_out = and(T_763, T_766) + node T_770 = and(get_valid, io.nasti.ar.ready) + node T_771 = and(T_770, get_id_mapper.io.req.ready) + roq.io.enq.valid <= T_771 + roq.io.enq.bits.tag <= io.nasti.ar.bits.id + roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat + roq.io.enq.bits.data.subblock <= is_subblock + node T_772 = and(io.nasti.r.ready, io.nasti.r.valid) + node T_773 = or(nasti_wrap_out, roq.io.deq.data.subblock) + node T_774 = and(T_772, T_773) + roq.io.deq.valid <= T_774 + roq.io.deq.tag <= io.nasti.r.bits.id + node T_775 = and(get_valid, roq.io.enq.ready) + node T_776 = and(T_775, io.nasti.ar.ready) + get_id_mapper.io.req.valid <= T_776 + get_id_mapper.io.req.in_id <= io.tl.acquire.bits.client_xact_id + node T_777 = and(io.nasti.r.ready, io.nasti.r.valid) + node T_778 = and(T_777, io.nasti.r.bits.last) + get_id_mapper.io.resp.valid <= T_778 + get_id_mapper.io.resp.out_id <= io.nasti.r.bits.id + node T_779 = and(put_valid, aw_ready) + node T_780 = and(T_779, io.nasti.w.ready) + node T_781 = and(T_780, put_id_mask) + put_id_mapper.io.req.valid <= T_781 + put_id_mapper.io.req.in_id <= io.tl.acquire.bits.client_xact_id + node T_782 = and(io.nasti.b.ready, io.nasti.b.valid) + put_id_mapper.io.resp.valid <= T_782 + put_id_mapper.io.resp.out_id <= io.nasti.b.bits.id + node T_783 = and(get_valid, roq.io.enq.ready) + node T_784 = and(T_783, get_id_mapper.io.req.ready) + io.nasti.ar.valid <= T_784 + wire T_792 : UInt<3>[2] + T_792 is invalid + T_792[0] <= UInt<3>("h0") + T_792[1] <= UInt<3>("h4") + node T_794 = eq(io.tl.acquire.bits.a_type, T_792[0]) + node T_795 = eq(io.tl.acquire.bits.a_type, T_792[1]) + node T_796 = or(T_794, T_795) + node T_797 = and(io.tl.acquire.bits.is_builtin_type, T_796) + node T_798 = bits(io.tl.acquire.bits.union, 10, 8) + node T_800 = mux(T_797, T_798, UInt<3>("h0")) + node T_801 = cat(io.tl.acquire.bits.addr_block, io.tl.acquire.bits.addr_beat) + node T_802 = cat(T_801, T_800) + node T_803 = bits(io.tl.acquire.bits.union, 7, 6) + node T_805 = mux(is_subblock, T_803, UInt<2>("h3")) + node T_808 = mux(is_subblock, UInt<1>("h0"), UInt<3>("h7")) + wire T_828 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} + T_828 is invalid + T_828.id <= get_id_mapper.io.req.out_id + T_828.addr <= T_802 + T_828.len <= T_808 + T_828.size <= T_805 + T_828.burst <= UInt<2>("h1") + T_828.lock <= UInt<1>("h0") + T_828.cache <= UInt<1>("h0") + T_828.prot <= UInt<1>("h0") + T_828.qos <= UInt<1>("h0") + T_828.region <= UInt<1>("h0") + T_828.user <= UInt<1>("h0") + io.nasti.ar.bits <- T_828 + node T_847 = eq(io.tl.acquire.bits.a_type, UInt<3>("h4")) + node T_848 = and(io.tl.acquire.bits.is_builtin_type, T_847) + node T_870 = asUInt(asSInt(UInt<8>("hff"))) + node T_872 = eq(io.tl.acquire.bits.a_type, UInt<3>("h3")) + node T_873 = and(io.tl.acquire.bits.is_builtin_type, T_872) + node T_875 = eq(io.tl.acquire.bits.a_type, UInt<3>("h2")) + node T_876 = and(io.tl.acquire.bits.is_builtin_type, T_875) + node T_877 = or(T_873, T_876) + node T_878 = bits(io.tl.acquire.bits.union, 8, 1) + node T_880 = mux(T_877, T_878, UInt<1>("h0")) + node T_881 = mux(T_848, T_870, T_880) + node T_882 = not(T_881) + node all_inside_0_0 = bits(T_882, 0, 0) + node all_inside_0_1 = bits(T_882, 1, 1) + node all_inside_0_2 = bits(T_882, 2, 2) + node all_inside_0_3 = bits(T_882, 3, 3) + node all_inside_0_4 = bits(T_882, 4, 4) + node all_inside_0_5 = bits(T_882, 5, 5) + node all_inside_0_6 = bits(T_882, 6, 6) + node all_inside_0_7 = bits(T_882, 7, 7) + node T_883 = and(all_inside_0_0, all_inside_0_1) + node T_884 = and(all_inside_0_2, all_inside_0_3) + node T_885 = and(all_inside_0_4, all_inside_0_5) + node T_886 = and(all_inside_0_6, all_inside_0_7) + node T_887 = and(T_883, T_884) + node T_888 = and(T_885, T_886) + node T_889 = and(T_887, T_888) + node T_893 = and(UInt<1>("h1"), T_888) + node T_894 = and(UInt<1>("h1"), T_887) + node T_895 = or(T_893, T_894) + node T_896 = cat(UInt<1>("h0"), T_894) + node T_898 = mux(T_895, UInt<2>("h2"), UInt<2>("h3")) + node T_899 = and(T_893, T_884) + node T_900 = and(T_893, T_883) + node T_901 = and(T_894, T_886) + node T_902 = and(T_894, T_885) + node T_903 = or(T_900, T_902) + node T_904 = or(T_899, T_900) + node T_905 = or(T_904, T_901) + node T_906 = or(T_905, T_902) + node T_907 = cat(T_896, T_903) + node T_909 = mux(T_906, UInt<1>("h1"), T_898) + node T_910 = and(T_899, all_inside_0_1) + node T_911 = and(T_899, all_inside_0_0) + node T_912 = and(T_900, all_inside_0_3) + node T_913 = and(T_900, all_inside_0_2) + node T_914 = and(T_901, all_inside_0_5) + node T_915 = and(T_901, all_inside_0_4) + node T_916 = and(T_902, all_inside_0_7) + node T_917 = and(T_902, all_inside_0_6) + node T_918 = or(T_911, T_913) + node T_919 = or(T_918, T_915) + node T_920 = or(T_919, T_917) + node T_921 = or(T_910, T_911) + node T_922 = or(T_921, T_912) + node T_923 = or(T_922, T_913) + node T_924 = or(T_923, T_914) + node T_925 = or(T_924, T_915) + node T_926 = or(T_925, T_916) + node T_927 = or(T_926, T_917) + node put_offset = cat(T_907, T_920) + node put_size = mux(T_927, UInt<1>("h0"), T_909) + node T_930 = eq(w_inflight, UInt<1>("h0")) + node T_931 = and(put_valid, io.nasti.w.ready) + node T_932 = and(T_931, put_id_ready) + node T_933 = and(T_932, T_930) + io.nasti.aw.valid <= T_933 + wire T_941 : UInt<3>[2] + T_941 is invalid + T_941[0] <= UInt<3>("h0") + T_941[1] <= UInt<3>("h4") + node T_943 = eq(io.tl.acquire.bits.a_type, T_941[0]) + node T_944 = eq(io.tl.acquire.bits.a_type, T_941[1]) + node T_945 = or(T_943, T_944) + node T_946 = and(io.tl.acquire.bits.is_builtin_type, T_945) + node T_947 = bits(io.tl.acquire.bits.union, 10, 8) + node T_949 = mux(T_946, T_947, UInt<3>("h0")) + node T_950 = cat(io.tl.acquire.bits.addr_block, io.tl.acquire.bits.addr_beat) + node T_951 = cat(T_950, T_949) + node T_953 = mux(is_multibeat, UInt<1>("h0"), put_offset) + node T_954 = or(T_951, T_953) + node T_956 = mux(is_multibeat, UInt<2>("h3"), put_size) + node T_959 = mux(is_multibeat, UInt<3>("h7"), UInt<1>("h0")) + wire T_972 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} + T_972 is invalid + T_972.id <= put_id_mapper.io.req.out_id + T_972.addr <= T_954 + T_972.len <= T_959 + T_972.size <= T_956 + T_972.burst <= UInt<2>("h1") + T_972.lock <= UInt<1>("h0") + T_972.cache <= UInt<4>("h0") + T_972.prot <= UInt<3>("h0") + T_972.qos <= UInt<4>("h0") + T_972.region <= UInt<4>("h0") + T_972.user <= UInt<1>("h0") + io.nasti.aw.bits <- T_972 + node T_990 = and(put_valid, aw_ready) + node T_991 = and(T_990, put_id_ready) + io.nasti.w.valid <= T_991 + node T_993 = eq(io.tl.acquire.bits.a_type, UInt<3>("h4")) + node T_994 = and(io.tl.acquire.bits.is_builtin_type, T_993) + node T_1016 = asUInt(asSInt(UInt<8>("hff"))) + node T_1018 = eq(io.tl.acquire.bits.a_type, UInt<3>("h3")) + node T_1019 = and(io.tl.acquire.bits.is_builtin_type, T_1018) + node T_1021 = eq(io.tl.acquire.bits.a_type, UInt<3>("h2")) + node T_1022 = and(io.tl.acquire.bits.is_builtin_type, T_1021) + node T_1023 = or(T_1019, T_1022) + node T_1024 = bits(io.tl.acquire.bits.union, 8, 1) + node T_1026 = mux(T_1023, T_1024, UInt<1>("h0")) + node T_1027 = mux(T_994, T_1016, T_1026) + node T_1029 = eq(tl_cnt_out, UInt<3>("h7")) + node T_1031 = eq(is_multibeat, UInt<1>("h0")) + node T_1032 = mux(w_inflight, T_1029, T_1031) + wire T_1039 : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>} + T_1039 is invalid + T_1039.strb <= T_1027 + T_1039.data <= io.tl.acquire.bits.data + T_1039.last <= T_1032 + T_1039.id <= w_id + T_1039.user <= UInt<1>("h0") + io.nasti.w.bits <- T_1039 + node T_1046 = and(aw_ready, io.nasti.w.ready) + node T_1047 = and(T_1046, put_id_ready) + node T_1048 = and(roq.io.enq.ready, io.nasti.ar.ready) + node T_1049 = and(T_1048, get_id_mapper.io.req.ready) + node T_1050 = mux(has_data, T_1047, T_1049) + io.tl.acquire.ready <= T_1050 + node T_1052 = eq(w_inflight, UInt<1>("h0")) + node T_1053 = and(io.tl.acquire.ready, io.tl.acquire.valid) + node T_1054 = and(T_1052, T_1053) + node T_1055 = and(T_1054, is_multibeat) + when T_1055 : + w_inflight <= UInt<1>("h1") + w_id_reg <= w_id + when w_inflight : + when tl_wrap_out : + w_inflight <= UInt<1>("h0") + node T_1058 = and(io.tl.grant.ready, io.tl.grant.valid) + wire T_1066 : UInt<3>[1] + T_1066 is invalid + T_1066[0] <= UInt<3>("h5") + node T_1068 = eq(io.tl.grant.bits.g_type, T_1066[0]) + node T_1069 = eq(io.tl.grant.bits.g_type, UInt<1>("h0")) + node T_1070 = mux(io.tl.grant.bits.is_builtin_type, T_1068, T_1069) + node T_1071 = and(UInt<1>("h1"), T_1070) + node T_1072 = and(T_1058, T_1071) + reg tl_cnt_in : UInt<3>, clk with : + reset => (reset, UInt<3>("h0")) + when T_1072 : + T_1075 <= eq(tl_cnt_in, UInt<3>("h7")) + node T_1077 = add(tl_cnt_in, UInt<1>("h1")) + node T_1078 = tail(T_1077, 1) + tl_cnt_in <= T_1078 + node tl_wrap_in = and(T_1072, T_1075) + inst gnt_arb of LockingArbiter gnt_arb.io is invalid gnt_arb.clk <= clk gnt_arb.reset <= reset - io.tl.grant <- gnt_arb.io.out @[Nasti.scala 207:15] - gnt_arb.io.in[0].valid <= io.nasti.r.valid @[Nasti.scala 209:26] - io.nasti.r.ready <= gnt_arb.io.in[0].ready @[Nasti.scala 210:20] - node T_1110 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) @[Nasti.scala 213:17] - node T_1112 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) @[Nasti.scala 217:20] - wire T_1140 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_1140 is invalid @[Definitions.scala 863:19] - T_1140.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_1140.g_type <= T_1110 @[Definitions.scala 865:16] - T_1140.client_xact_id <= get_id_mapper.io.resp.in_id @[Definitions.scala 866:24] - T_1140.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_1140.addr_beat <= T_1112 @[Definitions.scala 868:19] - T_1140.data <= io.nasti.r.bits.data @[Definitions.scala 869:14] - gnt_arb.io.in[0].bits <- T_1140 @[Nasti.scala 211:25] - node T_1168 = eq(roq.io.deq.valid, UInt<1>("h00")) @[Nasti.scala 220:10] - node T_1169 = or(T_1168, roq.io.deq.matches) @[Nasti.scala 220:28] - node T_1170 = or(T_1169, reset) @[Nasti.scala 220:9] - node T_1172 = eq(T_1170, UInt<1>("h00")) @[Nasti.scala 220:9] - when T_1172 : @[Nasti.scala 220:9] - printf(clk, UInt<1>(1), "Assertion failed: TL -> NASTI converter ReorderQueue: NASTI tag error\n at Nasti.scala:220 assert(!roq.io.deq.valid || roq.io.deq.matches,\n") @[Nasti.scala 220:9] - stop(clk, UInt<1>(1), 1) @[Nasti.scala 220:9] - skip @[Nasti.scala 220:9] - node T_1174 = eq(gnt_arb.io.in[0].valid, UInt<1>("h00")) @[Nasti.scala 222:10] - node T_1175 = or(T_1174, get_id_mapper.io.resp.matches) @[Nasti.scala 222:34] - node T_1176 = or(T_1175, reset) @[Nasti.scala 222:9] - node T_1178 = eq(T_1176, UInt<1>("h00")) @[Nasti.scala 222:9] - when T_1178 : @[Nasti.scala 222:9] - printf(clk, UInt<1>(1), "Assertion failed: TL -> NASTI ID Mapper: NASTI tag error\n at Nasti.scala:222 assert(!gnt_arb.io.in(0).valid || get_id_mapper.io.resp.matches,\n") @[Nasti.scala 222:9] - stop(clk, UInt<1>(1), 1) @[Nasti.scala 222:9] - skip @[Nasti.scala 222:9] - gnt_arb.io.in[1].valid <= io.nasti.b.valid @[Nasti.scala 225:26] - io.nasti.b.ready <= gnt_arb.io.in[1].ready @[Nasti.scala 226:20] - wire T_1211 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} @[Definitions.scala 863:19] - T_1211 is invalid @[Definitions.scala 863:19] - T_1211.is_builtin_type <= UInt<1>("h01") @[Definitions.scala 864:25] - T_1211.g_type <= UInt<3>("h03") @[Definitions.scala 865:16] - T_1211.client_xact_id <= put_id_mapper.io.resp.in_id @[Definitions.scala 866:24] - T_1211.manager_xact_id <= UInt<1>("h00") @[Definitions.scala 867:25] - T_1211.addr_beat <= UInt<1>("h00") @[Definitions.scala 868:19] - T_1211.data <= UInt<1>("h00") @[Definitions.scala 869:14] - gnt_arb.io.in[1].bits <- T_1211 @[Nasti.scala 227:25] - node T_1239 = eq(gnt_arb.io.in[1].valid, UInt<1>("h00")) @[Nasti.scala 234:10] - node T_1240 = or(T_1239, put_id_mapper.io.resp.matches) @[Nasti.scala 234:34] - node T_1241 = or(T_1240, reset) @[Nasti.scala 234:9] - node T_1243 = eq(T_1241, UInt<1>("h00")) @[Nasti.scala 234:9] - when T_1243 : @[Nasti.scala 234:9] - printf(clk, UInt<1>(1), "Assertion failed: NASTI tag error\n at Nasti.scala:234 assert(!gnt_arb.io.in(1).valid || put_id_mapper.io.resp.matches, \"NASTI tag error\")\n") @[Nasti.scala 234:9] - stop(clk, UInt<1>(1), 1) @[Nasti.scala 234:9] - skip @[Nasti.scala 234:9] - node T_1245 = eq(io.nasti.r.valid, UInt<1>("h00")) @[Nasti.scala 236:10] - node T_1247 = eq(io.nasti.r.bits.resp, UInt<1>("h00")) @[Nasti.scala 236:52] - node T_1248 = or(T_1245, T_1247) @[Nasti.scala 236:28] - node T_1249 = or(T_1248, reset) @[Nasti.scala 236:9] - node T_1251 = eq(T_1249, UInt<1>("h00")) @[Nasti.scala 236:9] - when T_1251 : @[Nasti.scala 236:9] - printf(clk, UInt<1>(1), "Assertion failed: NASTI read error\n at Nasti.scala:236 assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), \"NASTI read error\")\n") @[Nasti.scala 236:9] - stop(clk, UInt<1>(1), 1) @[Nasti.scala 236:9] - skip @[Nasti.scala 236:9] - node T_1253 = eq(io.nasti.b.valid, UInt<1>("h00")) @[Nasti.scala 237:10] - node T_1255 = eq(io.nasti.b.bits.resp, UInt<1>("h00")) @[Nasti.scala 237:52] - node T_1256 = or(T_1253, T_1255) @[Nasti.scala 237:28] - node T_1257 = or(T_1256, reset) @[Nasti.scala 237:9] - node T_1259 = eq(T_1257, UInt<1>("h00")) @[Nasti.scala 237:9] - when T_1259 : @[Nasti.scala 237:9] - printf(clk, UInt<1>(1), "Assertion failed: NASTI write error\n at Nasti.scala:237 assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), \"NASTI write error\")\n") @[Nasti.scala 237:9] - stop(clk, UInt<1>(1), 1) @[Nasti.scala 237:9] - skip @[Nasti.scala 237:9] - - module Queue_20 : + io.tl.grant <- gnt_arb.io.out + gnt_arb.io.in[0].valid <= io.nasti.r.valid + io.nasti.r.ready <= gnt_arb.io.in[0].ready + node T_1110 = mux(roq.io.deq.data.subblock, UInt<3>("h4"), UInt<3>("h5")) + node T_1112 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) + wire T_1140 : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1140 is invalid + T_1140.is_builtin_type <= UInt<1>("h1") + T_1140.g_type <= T_1110 + T_1140.client_xact_id <= get_id_mapper.io.resp.in_id + T_1140.manager_xact_id <= UInt<1>("h0") + T_1140.addr_beat <= T_1112 + T_1140.data <= io.nasti.r.bits.data + gnt_arb.io.in[0].bits <- T_1140 + node T_1168 = eq(roq.io.deq.valid, UInt<1>("h0")) + node T_1169 = or(T_1168, roq.io.deq.matches) + node T_1170 = or(T_1169, reset) + node T_1172 = eq(T_1170, UInt<1>("h0")) + when T_1172 : + printf(clk, UInt<1>("h1"), "Assertion failed: TL -> NASTI converter ReorderQueue: NASTI tag error\n at Nasti.scala:220 assert(!roq.io.deq.valid || roq.io.deq.matches,\n") + stop(clk, UInt<1>("h1"), 1) + node T_1174 = eq(gnt_arb.io.in[0].valid, UInt<1>("h0")) + node T_1175 = or(T_1174, get_id_mapper.io.resp.matches) + node T_1176 = or(T_1175, reset) + node T_1178 = eq(T_1176, UInt<1>("h0")) + when T_1178 : + printf(clk, UInt<1>("h1"), "Assertion failed: TL -> NASTI ID Mapper: NASTI tag error\n at Nasti.scala:222 assert(!gnt_arb.io.in(0).valid || get_id_mapper.io.resp.matches,\n") + stop(clk, UInt<1>("h1"), 1) + gnt_arb.io.in[1].valid <= io.nasti.b.valid + io.nasti.b.ready <= gnt_arb.io.in[1].ready + wire T_1211 : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1211 is invalid + T_1211.is_builtin_type <= UInt<1>("h1") + T_1211.g_type <= UInt<3>("h3") + T_1211.client_xact_id <= put_id_mapper.io.resp.in_id + T_1211.manager_xact_id <= UInt<1>("h0") + T_1211.addr_beat <= UInt<1>("h0") + T_1211.data <= UInt<1>("h0") + gnt_arb.io.in[1].bits <- T_1211 + node T_1239 = eq(gnt_arb.io.in[1].valid, UInt<1>("h0")) + node T_1240 = or(T_1239, put_id_mapper.io.resp.matches) + node T_1241 = or(T_1240, reset) + node T_1243 = eq(T_1241, UInt<1>("h0")) + when T_1243 : + printf(clk, UInt<1>("h1"), "Assertion failed: NASTI tag error\n at Nasti.scala:234 assert(!gnt_arb.io.in(1).valid || put_id_mapper.io.resp.matches, \"NASTI tag error\")\n") + stop(clk, UInt<1>("h1"), 1) + node T_1245 = eq(io.nasti.r.valid, UInt<1>("h0")) + node T_1247 = eq(io.nasti.r.bits.resp, UInt<1>("h0")) + node T_1248 = or(T_1245, T_1247) + node T_1249 = or(T_1248, reset) + node T_1251 = eq(T_1249, UInt<1>("h0")) + when T_1251 : + printf(clk, UInt<1>("h1"), "Assertion failed: NASTI read error\n at Nasti.scala:236 assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), \"NASTI read error\")\n") + stop(clk, UInt<1>("h1"), 1) + node T_1253 = eq(io.nasti.b.valid, UInt<1>("h0")) + node T_1255 = eq(io.nasti.b.bits.resp, UInt<1>("h0")) + node T_1256 = or(T_1253, T_1255) + node T_1257 = or(T_1256, reset) + node T_1259 = eq(T_1257, UInt<1>("h0")) + when T_1259 : + printf(clk, UInt<1>("h1"), "Assertion failed: NASTI write error\n at Nasti.scala:237 assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), \"NASTI write error\")\n") + stop(clk, UInt<1>("h1"), 1) + + module Queue_20 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + io is invalid - cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_122 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_122) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_123 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_122 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_122) + node full = and(ptr_match, maybe_full) + node T_123 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_123 - node T_124 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_124 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_124 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_125 = ram[UInt<1>("h00")], clk - T_125 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_139 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_139 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_141 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_141 @[Decoupled.scala 184:16] - node T_143 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_143 @[Decoupled.scala 185:16] - infer mport T_144 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_144 @[Decoupled.scala 186:15] - node T_156 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_156, 1) @[Decoupled.scala 201:32] - node T_157 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_158 = cat(T_157, ptr_diff) @[Cat.scala 20:58] - io.count <= T_158 @[Decoupled.scala 203:14] - - module Queue_22 : + when do_enq : + infer mport T_125 = ram[UInt<1>("h0")], clk + T_125 <- io.enq.bits + when do_deq : + skip + node T_139 = neq(do_enq, do_deq) + when T_139 : + maybe_full <= do_enq + node T_141 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_141 + node T_143 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_143 + infer mport T_144 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_144 + node T_156 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_156, 1) + node T_157 = and(maybe_full, ptr_match) + node T_158 = cat(T_157, ptr_diff) + io.count <= T_158 + + module Queue_22 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, count : UInt<2>} + io is invalid - cmem ram : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}[2] @[Decoupled.scala 162:16] - reg T_65 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_67 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_65, T_67) @[Decoupled.scala 167:33] - node T_70 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_70) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_71 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>} [2] + reg T_65 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_67 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_65, T_67) + node T_70 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_70) + node full = and(ptr_match, maybe_full) + node T_71 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_71 - node T_72 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_72 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_72 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_73 = ram[T_65], clk - T_73 <- io.enq.bits @[Decoupled.scala 174:24] - node T_80 = eq(T_65, UInt<1>("h01")) @[Counter.scala 20:24] - node T_82 = add(T_65, UInt<1>("h01")) @[Counter.scala 21:22] - node T_83 = tail(T_82, 1) @[Counter.scala 21:22] - T_65 <= T_83 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_85 = eq(T_67, UInt<1>("h01")) @[Counter.scala 20:24] - node T_87 = add(T_67, UInt<1>("h01")) @[Counter.scala 21:22] - node T_88 = tail(T_87, 1) @[Counter.scala 21:22] - T_67 <= T_88 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_89 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_89 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_91 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_91 @[Decoupled.scala 184:16] - node T_93 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_93 @[Decoupled.scala 185:16] + T_73 <- io.enq.bits + node T_80 = eq(T_65, UInt<1>("h1")) + node T_82 = add(T_65, UInt<1>("h1")) + node T_83 = tail(T_82, 1) + T_65 <= T_83 + when do_deq : + node T_85 = eq(T_67, UInt<1>("h1")) + node T_87 = add(T_67, UInt<1>("h1")) + node T_88 = tail(T_87, 1) + T_67 <= T_88 + node T_89 = neq(do_enq, do_deq) + when T_89 : + maybe_full <= do_enq + node T_91 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_91 + node T_93 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_93 infer mport T_94 = ram[T_67], clk - io.deq.bits <- T_94 @[Decoupled.scala 186:15] - node T_100 = sub(T_65, T_67) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_100, 1) @[Decoupled.scala 201:32] - node T_101 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_102 = cat(T_101, ptr_diff) @[Cat.scala 20:58] - io.count <= T_102 @[Decoupled.scala 203:14] - - module Queue_23 : + io.deq.bits <- T_94 + node T_100 = sub(T_65, T_67) + node ptr_diff = tail(T_100, 1) + node T_101 = and(maybe_full, ptr_match) + node T_102 = cat(T_101, ptr_diff) + io.count <= T_102 + + module Queue_23 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} + io is invalid - cmem ram : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}[2] @[Decoupled.scala 162:16] - reg T_65 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg T_67 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(T_65, T_67) @[Decoupled.scala 167:33] - node T_70 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_70) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_71 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [2] + reg T_65 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg T_67 : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(T_65, T_67) + node T_70 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_70) + node full = and(ptr_match, maybe_full) + node T_71 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_71 - node T_72 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_72 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_72 - when do_enq : @[Decoupled.scala 173:17] + when do_enq : infer mport T_73 = ram[T_65], clk - T_73 <- io.enq.bits @[Decoupled.scala 174:24] - node T_80 = eq(T_65, UInt<1>("h01")) @[Counter.scala 20:24] - node T_82 = add(T_65, UInt<1>("h01")) @[Counter.scala 21:22] - node T_83 = tail(T_82, 1) @[Counter.scala 21:22] - T_65 <= T_83 @[Counter.scala 21:13] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - node T_85 = eq(T_67, UInt<1>("h01")) @[Counter.scala 20:24] - node T_87 = add(T_67, UInt<1>("h01")) @[Counter.scala 21:22] - node T_88 = tail(T_87, 1) @[Counter.scala 21:22] - T_67 <= T_88 @[Counter.scala 21:13] - skip @[Decoupled.scala 177:17] - node T_89 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_89 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_91 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_91 @[Decoupled.scala 184:16] - node T_93 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_93 @[Decoupled.scala 185:16] + T_73 <- io.enq.bits + node T_80 = eq(T_65, UInt<1>("h1")) + node T_82 = add(T_65, UInt<1>("h1")) + node T_83 = tail(T_82, 1) + T_65 <= T_83 + when do_deq : + node T_85 = eq(T_67, UInt<1>("h1")) + node T_87 = add(T_67, UInt<1>("h1")) + node T_88 = tail(T_87, 1) + T_67 <= T_88 + node T_89 = neq(do_enq, do_deq) + when T_89 : + maybe_full <= do_enq + node T_91 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_91 + node T_93 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_93 infer mport T_94 = ram[T_67], clk - io.deq.bits <- T_94 @[Decoupled.scala 186:15] - node T_100 = sub(T_65, T_67) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_100, 1) @[Decoupled.scala 201:32] - node T_101 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_102 = cat(T_101, ptr_diff) @[Cat.scala 20:58] - io.count <= T_102 @[Decoupled.scala 203:14] - - module Queue_24 : + io.deq.bits <- T_94 + node T_100 = sub(T_65, T_67) + node ptr_diff = tail(T_100, 1) + node T_101 = and(maybe_full, ptr_match) + node T_102 = cat(T_101, ptr_diff) + io.count <= T_102 + + module Queue_24 : input clk : Clock input reset : UInt<1> - output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} - + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + io is invalid - cmem ram : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}[1] @[Decoupled.scala 162:16] - reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 167:33] - node T_50 = eq(maybe_full, UInt<1>("h00")) @[Decoupled.scala 168:28] - node empty = and(ptr_match, T_50) @[Decoupled.scala 168:25] - node full = and(ptr_match, maybe_full) @[Decoupled.scala 169:24] - node T_51 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 21:42] + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] + reg maybe_full : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) + node T_50 = eq(maybe_full, UInt<1>("h0")) + node empty = and(ptr_match, T_50) + node full = and(ptr_match, maybe_full) + node T_51 = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> do_enq is invalid do_enq <= T_51 - node T_52 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 21:42] + node T_52 = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> do_deq is invalid do_deq <= T_52 - when do_enq : @[Decoupled.scala 173:17] - infer mport T_53 = ram[UInt<1>("h00")], clk - T_53 <- io.enq.bits @[Decoupled.scala 174:24] - skip @[Decoupled.scala 173:17] - when do_deq : @[Decoupled.scala 177:17] - skip @[Decoupled.scala 177:17] - node T_59 = neq(do_enq, do_deq) @[Decoupled.scala 180:16] - when T_59 : @[Decoupled.scala 180:27] - maybe_full <= do_enq @[Decoupled.scala 181:16] - skip @[Decoupled.scala 180:27] - node T_61 = eq(empty, UInt<1>("h00")) @[Decoupled.scala 184:19] - io.deq.valid <= T_61 @[Decoupled.scala 184:16] - node T_63 = eq(full, UInt<1>("h00")) @[Decoupled.scala 185:19] - io.enq.ready <= T_63 @[Decoupled.scala 185:16] - infer mport T_64 = ram[UInt<1>("h00")], clk - io.deq.bits <- T_64 @[Decoupled.scala 186:15] - node T_68 = sub(UInt<1>("h00"), UInt<1>("h00")) @[Decoupled.scala 201:32] - node ptr_diff = tail(T_68, 1) @[Decoupled.scala 201:32] - node T_69 = and(maybe_full, ptr_match) @[Decoupled.scala 203:32] - node T_70 = cat(T_69, ptr_diff) @[Cat.scala 20:58] - io.count <= T_70 @[Decoupled.scala 203:14] - - module ExampleTop : + when do_enq : + infer mport T_53 = ram[UInt<1>("h0")], clk + T_53 <- io.enq.bits + when do_deq : + skip + node T_59 = neq(do_enq, do_deq) + when T_59 : + maybe_full <= do_enq + node T_61 = eq(empty, UInt<1>("h0")) + io.deq.valid <= T_61 + node T_63 = eq(full, UInt<1>("h0")) + io.enq.ready <= T_63 + infer mport T_64 = ram[UInt<1>("h0")], clk + io.deq.bits <- T_64 + node T_68 = sub(UInt<1>("h0"), UInt<1>("h0")) + node ptr_diff = tail(T_68, 1) + node T_69 = and(maybe_full, ptr_match) + node T_70 = cat(T_69, ptr_diff) + io.count <= T_70 + + module ExampleTop : input clk : Clock input reset : UInt<1> - output io : {flip debug : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}}, flip interrupts : UInt<1>[2], mem_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_ahb : {htrans : UInt<2>, hmastlock : UInt<1>, haddr : UInt<32>, hwrite : UInt<1>, hburst : UInt<3>, hsize : UInt<3>, hprot : UInt<4>, hwdata : UInt<64>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}[0], mem_tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], mmio_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[0], mmio_ahb : {htrans : UInt<2>, hmastlock : UInt<1>, haddr : UInt<32>, hwrite : UInt<1>, hburst : UInt<3>, hsize : UInt<3>, hprot : UInt<4>, hwdata : UInt<64>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}[0], mmio_tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], flip bus_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[0]} - + output io : { flip debug : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<34>, resp : UInt<2>}}}, flip interrupts : UInt<1>[2], mem_axi : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_ahb : { htrans : UInt<2>, hmastlock : UInt<1>, haddr : UInt<32>, hwrite : UInt<1>, hburst : UInt<3>, hsize : UInt<3>, hprot : UInt<4>, hwdata : UInt<64>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}[0], mem_tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], mmio_axi : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[0], mmio_ahb : { htrans : UInt<2>, hmastlock : UInt<1>, haddr : UInt<32>, hwrite : UInt<1>, hburst : UInt<3>, hsize : UInt<3>, hprot : UInt<4>, hwdata : UInt<64>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}[0], mmio_tl : { acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<11>, data : UInt<64>}}, flip grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr_beat : UInt<3>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}[0], flip bus_axi : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[0]} + io is invalid - inst coreplex of DefaultCoreplex @[Configs.scala 46:55] + inst coreplex of DefaultCoreplex coreplex.io is invalid coreplex.clk <= clk coreplex.reset <= reset - reg T_3641 : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) - node T_3643 = eq(T_3641, UInt<7>("h063")) @[Counter.scala 20:24] - node T_3645 = add(T_3641, UInt<1>("h01")) @[Counter.scala 21:22] - node T_3646 = tail(T_3645, 1) @[Counter.scala 21:22] - T_3641 <= T_3646 @[Counter.scala 21:13] - when T_3643 : @[Counter.scala 23:21] - T_3641 <= UInt<1>("h00") @[Counter.scala 23:29] - skip @[Counter.scala 23:21] - coreplex.io.rtcTick <= T_3643 @[Top.scala 68:23] - coreplex.io.debug <- io.debug @[Periphery.scala 110:23] - coreplex.io.interrupts[0] <= io.interrupts[0] @[Periphery.scala 139:33] - coreplex.io.interrupts[1] <= io.interrupts[1] @[Periphery.scala 139:33] - inst NastiIOTileLinkIOConverter_1 of NastiIOTileLinkIOConverter @[Periphery.scala 58:24] + reg T_3641 : UInt<7>, clk with : + reset => (reset, UInt<7>("h0")) + node T_3643 = eq(T_3641, UInt<7>("h63")) + node T_3645 = add(T_3641, UInt<1>("h1")) + node T_3646 = tail(T_3645, 1) + T_3641 <= T_3646 + when T_3643 : + T_3641 <= UInt<1>("h0") + coreplex.io.rtcTick <= T_3643 + coreplex.io.debug <- io.debug + coreplex.io.interrupts[0] <= io.interrupts[0] + coreplex.io.interrupts[1] <= io.interrupts[1] + inst NastiIOTileLinkIOConverter_1 of NastiIOTileLinkIOConverter NastiIOTileLinkIOConverter_1.io is invalid NastiIOTileLinkIOConverter_1.clk <= clk NastiIOTileLinkIOConverter_1.reset <= reset - NastiIOTileLinkIOConverter_1.io.tl <- coreplex.io.master.mem[0] @[Periphery.scala 59:18] - wire T_3810 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} @[Periphery.scala 49:20] - T_3810 is invalid @[Periphery.scala 49:20] - inst Queue_20_1 of Queue_20 @[Decoupled.scala 228:19] + NastiIOTileLinkIOConverter_1.io.tl <- coreplex.io.master.mem[0] + wire T_3810 : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} + T_3810 is invalid + inst Queue_20_1 of Queue_20 Queue_20_1.io is invalid Queue_20_1.clk <= clk Queue_20_1.reset <= reset - Queue_20_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.ar.valid @[Decoupled.scala 229:20] - Queue_20_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.ar.bits @[Decoupled.scala 230:19] - NastiIOTileLinkIOConverter_1.io.nasti.ar.ready <= Queue_20_1.io.enq.ready @[Decoupled.scala 231:15] - T_3810.ar <- Queue_20_1.io.deq @[Periphery.scala 50:14] - inst Queue_21_1 of Queue_20 @[Decoupled.scala 228:19] + Queue_20_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.ar.valid + Queue_20_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.ar.bits + NastiIOTileLinkIOConverter_1.io.nasti.ar.ready <= Queue_20_1.io.enq.ready + T_3810.ar <- Queue_20_1.io.deq + inst Queue_21_1 of Queue_20 Queue_21_1.io is invalid Queue_21_1.clk <= clk Queue_21_1.reset <= reset - Queue_21_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.aw.valid @[Decoupled.scala 229:20] - Queue_21_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.aw.bits @[Decoupled.scala 230:19] - NastiIOTileLinkIOConverter_1.io.nasti.aw.ready <= Queue_21_1.io.enq.ready @[Decoupled.scala 231:15] - T_3810.aw <- Queue_21_1.io.deq @[Periphery.scala 51:14] - inst Queue_22_1 of Queue_22 @[Decoupled.scala 228:19] + Queue_21_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.aw.valid + Queue_21_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.aw.bits + NastiIOTileLinkIOConverter_1.io.nasti.aw.ready <= Queue_21_1.io.enq.ready + T_3810.aw <- Queue_21_1.io.deq + inst Queue_22_1 of Queue_22 Queue_22_1.io is invalid Queue_22_1.clk <= clk Queue_22_1.reset <= reset - Queue_22_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.w.valid @[Decoupled.scala 229:20] - Queue_22_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.w.bits @[Decoupled.scala 230:19] - NastiIOTileLinkIOConverter_1.io.nasti.w.ready <= Queue_22_1.io.enq.ready @[Decoupled.scala 231:15] - T_3810.w <- Queue_22_1.io.deq @[Periphery.scala 52:14] - inst Queue_23_1 of Queue_23 @[Decoupled.scala 228:19] + Queue_22_1.io.enq.valid <= NastiIOTileLinkIOConverter_1.io.nasti.w.valid + Queue_22_1.io.enq.bits <- NastiIOTileLinkIOConverter_1.io.nasti.w.bits + NastiIOTileLinkIOConverter_1.io.nasti.w.ready <= Queue_22_1.io.enq.ready + T_3810.w <- Queue_22_1.io.deq + inst Queue_23_1 of Queue_23 Queue_23_1.io is invalid Queue_23_1.clk <= clk Queue_23_1.reset <= reset - Queue_23_1.io.enq.valid <= T_3810.r.valid @[Decoupled.scala 229:20] - Queue_23_1.io.enq.bits <- T_3810.r.bits @[Decoupled.scala 230:19] - T_3810.r.ready <= Queue_23_1.io.enq.ready @[Decoupled.scala 231:15] - NastiIOTileLinkIOConverter_1.io.nasti.r <- Queue_23_1.io.deq @[Periphery.scala 53:14] - inst Queue_24_1 of Queue_24 @[Decoupled.scala 228:19] + Queue_23_1.io.enq.valid <= T_3810.r.valid + Queue_23_1.io.enq.bits <- T_3810.r.bits + T_3810.r.ready <= Queue_23_1.io.enq.ready + NastiIOTileLinkIOConverter_1.io.nasti.r <- Queue_23_1.io.deq + inst Queue_24_1 of Queue_24 Queue_24_1.io is invalid Queue_24_1.clk <= clk Queue_24_1.reset <= reset - Queue_24_1.io.enq.valid <= T_3810.b.valid @[Decoupled.scala 229:20] - Queue_24_1.io.enq.bits <- T_3810.b.bits @[Decoupled.scala 230:19] - T_3810.b.ready <= Queue_24_1.io.enq.ready @[Decoupled.scala 231:15] - NastiIOTileLinkIOConverter_1.io.nasti.b <- Queue_24_1.io.deq @[Periphery.scala 54:14] - T_3810.ar.bits.cache <= UInt<4>("h03") @[Periphery.scala 168:28] - T_3810.aw.bits.cache <= UInt<4>("h03") @[Periphery.scala 169:28] - io.mem_axi[0] <- T_3810 @[Periphery.scala 170:9] - - module SimAXIMem : + Queue_24_1.io.enq.valid <= T_3810.b.valid + Queue_24_1.io.enq.bits <- T_3810.b.bits + T_3810.b.ready <= Queue_24_1.io.enq.ready + NastiIOTileLinkIOConverter_1.io.nasti.b <- Queue_24_1.io.deq + T_3810.ar.bits.cache <= UInt<4>("h3") + T_3810.aw.bits.cache <= UInt<4>("h3") + io.mem_axi[0] <- T_3810 + + module SimAXIMem : input clk : Clock input reset : UInt<1> - output io : {flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - + output io : { flip axi : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + io is invalid - reg rValid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_324 = and(io.axi.ar.ready, io.axi.ar.valid) @[Decoupled.scala 21:42] - reg ar : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}, clk - when T_324 : @[Reg.scala 29:19] - ar <- io.axi.ar.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_337 = eq(rValid, UInt<1>("h00")) @[TestHarness.scala 82:22] - io.axi.ar.ready <= T_337 @[TestHarness.scala 82:19] - node T_338 = and(io.axi.ar.ready, io.axi.ar.valid) @[Decoupled.scala 21:42] - when T_338 : @[TestHarness.scala 83:27] - rValid <= UInt<1>("h01") @[TestHarness.scala 83:36] - skip @[TestHarness.scala 83:27] - node T_340 = and(io.axi.r.ready, io.axi.r.valid) @[Decoupled.scala 21:42] - when T_340 : @[TestHarness.scala 84:26] - node T_341 = eq(ar.burst, UInt<2>("h01")) @[TestHarness.scala 85:21] - node T_342 = or(T_341, reset) @[TestHarness.scala 85:11] - node T_344 = eq(T_342, UInt<1>("h00")) @[TestHarness.scala 85:11] - when T_344 : @[TestHarness.scala 85:11] - printf(clk, UInt<1>(1), "Assertion failed\n at TestHarness.scala:85 assert(ar.burst === NastiConstants.BURST_INCR)\n") @[TestHarness.scala 85:11] - stop(clk, UInt<1>(1), 1) @[TestHarness.scala 85:11] - skip @[TestHarness.scala 85:11] - node T_346 = dshl(UInt<1>("h01"), ar.size) @[TestHarness.scala 86:35] - node T_347 = add(ar.addr, T_346) @[TestHarness.scala 86:24] - node T_348 = tail(T_347, 1) @[TestHarness.scala 86:24] - ar.addr <= T_348 @[TestHarness.scala 86:13] - node T_350 = sub(ar.len, UInt<1>("h01")) @[TestHarness.scala 87:22] - node T_351 = tail(T_350, 1) @[TestHarness.scala 87:22] - ar.len <= T_351 @[TestHarness.scala 87:12] - node T_353 = eq(ar.len, UInt<1>("h00")) @[TestHarness.scala 88:18] - when T_353 : @[TestHarness.scala 88:31] - rValid <= UInt<1>("h00") @[TestHarness.scala 88:40] - skip @[TestHarness.scala 88:31] - skip @[TestHarness.scala 84:26] - cmem mem : UInt<64>[33554432] @[TestHarness.scala 94:16] - reg wValid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - reg bValid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) - node T_358 = and(io.axi.aw.ready, io.axi.aw.valid) @[Decoupled.scala 21:42] - reg aw : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}, clk - when T_358 : @[Reg.scala 29:19] - aw <- io.axi.aw.bits @[Reg.scala 29:23] - skip @[Reg.scala 29:19] - node T_371 = eq(wValid, UInt<1>("h00")) @[TestHarness.scala 99:22] - node T_373 = eq(bValid, UInt<1>("h00")) @[TestHarness.scala 99:33] - node T_374 = and(T_371, T_373) @[TestHarness.scala 99:30] - io.axi.aw.ready <= T_374 @[TestHarness.scala 99:19] - io.axi.w.ready <= wValid @[TestHarness.scala 100:18] - node T_375 = and(io.axi.b.ready, io.axi.b.valid) @[Decoupled.scala 21:42] - when T_375 : @[TestHarness.scala 101:26] - bValid <= UInt<1>("h00") @[TestHarness.scala 101:35] - skip @[TestHarness.scala 101:26] - node T_377 = and(io.axi.aw.ready, io.axi.aw.valid) @[Decoupled.scala 21:42] - when T_377 : @[TestHarness.scala 102:27] - wValid <= UInt<1>("h01") @[TestHarness.scala 102:36] - skip @[TestHarness.scala 102:27] - node T_379 = and(io.axi.w.ready, io.axi.w.valid) @[Decoupled.scala 21:42] - when T_379 : @[TestHarness.scala 103:26] - node T_380 = eq(aw.burst, UInt<2>("h01")) @[TestHarness.scala 104:21] - node T_381 = or(T_380, reset) @[TestHarness.scala 104:11] - node T_383 = eq(T_381, UInt<1>("h00")) @[TestHarness.scala 104:11] - when T_383 : @[TestHarness.scala 104:11] - printf(clk, UInt<1>(1), "Assertion failed\n at TestHarness.scala:104 assert(aw.burst === NastiConstants.BURST_INCR)\n") @[TestHarness.scala 104:11] - stop(clk, UInt<1>(1), 1) @[TestHarness.scala 104:11] - skip @[TestHarness.scala 104:11] - node T_385 = dshl(UInt<1>("h01"), aw.size) @[TestHarness.scala 105:35] - node T_386 = add(aw.addr, T_385) @[TestHarness.scala 105:24] - node T_387 = tail(T_386, 1) @[TestHarness.scala 105:24] - aw.addr <= T_387 @[TestHarness.scala 105:13] - node T_389 = sub(aw.len, UInt<1>("h01")) @[TestHarness.scala 106:22] - node T_390 = tail(T_389, 1) @[TestHarness.scala 106:22] - aw.len <= T_390 @[TestHarness.scala 106:12] - node T_392 = eq(aw.len, UInt<1>("h00")) @[TestHarness.scala 107:18] - when T_392 : @[TestHarness.scala 107:31] - wValid <= UInt<1>("h00") @[TestHarness.scala 108:14] - bValid <= UInt<1>("h01") @[TestHarness.scala 109:14] - skip @[TestHarness.scala 107:31] - node T_395 = bits(io.axi.w.bits.strb, 0, 0) @[Bitwise.scala 13:51] - node T_396 = bits(io.axi.w.bits.strb, 1, 1) @[Bitwise.scala 13:51] - node T_397 = bits(io.axi.w.bits.strb, 2, 2) @[Bitwise.scala 13:51] - node T_398 = bits(io.axi.w.bits.strb, 3, 3) @[Bitwise.scala 13:51] - node T_399 = bits(io.axi.w.bits.strb, 4, 4) @[Bitwise.scala 13:51] - node T_400 = bits(io.axi.w.bits.strb, 5, 5) @[Bitwise.scala 13:51] - node T_401 = bits(io.axi.w.bits.strb, 6, 6) @[Bitwise.scala 13:51] - node T_402 = bits(io.axi.w.bits.strb, 7, 7) @[Bitwise.scala 13:51] - node T_403 = bits(T_395, 0, 0) @[Bitwise.scala 33:15] - node T_406 = mux(T_403, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_407 = bits(T_396, 0, 0) @[Bitwise.scala 33:15] - node T_410 = mux(T_407, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_411 = bits(T_397, 0, 0) @[Bitwise.scala 33:15] - node T_414 = mux(T_411, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_415 = bits(T_398, 0, 0) @[Bitwise.scala 33:15] - node T_418 = mux(T_415, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_419 = bits(T_399, 0, 0) @[Bitwise.scala 33:15] - node T_422 = mux(T_419, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_423 = bits(T_400, 0, 0) @[Bitwise.scala 33:15] - node T_426 = mux(T_423, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_427 = bits(T_401, 0, 0) @[Bitwise.scala 33:15] - node T_430 = mux(T_427, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_431 = bits(T_402, 0, 0) @[Bitwise.scala 33:15] - node T_434 = mux(T_431, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 33:12] - node T_435 = cat(T_410, T_406) @[Cat.scala 20:58] - node T_436 = cat(T_418, T_414) @[Cat.scala 20:58] - node T_437 = cat(T_436, T_435) @[Cat.scala 20:58] - node T_438 = cat(T_426, T_422) @[Cat.scala 20:58] - node T_439 = cat(T_434, T_430) @[Cat.scala 20:58] - node T_440 = cat(T_439, T_438) @[Cat.scala 20:58] - node T_441 = cat(T_440, T_437) @[Cat.scala 20:58] - node T_442 = and(T_441, io.axi.w.bits.data) @[TestHarness.scala 114:24] - node T_443 = not(T_441) @[TestHarness.scala 114:35] - node T_444 = shr(aw.addr, 3) @[TestHarness.scala 112:28] - node T_445 = bits(T_444, 24, 0) @[TestHarness.scala 112:58] + reg rValid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_324 = and(io.axi.ar.ready, io.axi.ar.valid) + reg ar : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}, clk with : + reset => (UInt<1>("h0"), ar) + when T_324 : + ar <- io.axi.ar.bits + node T_337 = eq(rValid, UInt<1>("h0")) + io.axi.ar.ready <= T_337 + node T_338 = and(io.axi.ar.ready, io.axi.ar.valid) + when T_338 : + rValid <= UInt<1>("h1") + node T_340 = and(io.axi.r.ready, io.axi.r.valid) + when T_340 : + node T_341 = eq(ar.burst, UInt<2>("h1")) + node T_342 = or(T_341, reset) + node T_344 = eq(T_342, UInt<1>("h0")) + when T_344 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at TestHarness.scala:85 assert(ar.burst === NastiConstants.BURST_INCR)\n") + stop(clk, UInt<1>("h1"), 1) + node T_346 = dshl(UInt<1>("h1"), ar.size) + node T_347 = add(ar.addr, T_346) + node T_348 = tail(T_347, 1) + ar.addr <= T_348 + node T_350 = sub(ar.len, UInt<1>("h1")) + node T_351 = tail(T_350, 1) + ar.len <= T_351 + node T_353 = eq(ar.len, UInt<1>("h0")) + when T_353 : + rValid <= UInt<1>("h0") + cmem mem : UInt<64> [33554432] + reg wValid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + reg bValid : UInt<1>, clk with : + reset => (reset, UInt<1>("h0")) + node T_358 = and(io.axi.aw.ready, io.axi.aw.valid) + reg aw : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}, clk with : + reset => (UInt<1>("h0"), aw) + when T_358 : + aw <- io.axi.aw.bits + node T_371 = eq(wValid, UInt<1>("h0")) + node T_373 = eq(bValid, UInt<1>("h0")) + node T_374 = and(T_371, T_373) + io.axi.aw.ready <= T_374 + io.axi.w.ready <= wValid + node T_375 = and(io.axi.b.ready, io.axi.b.valid) + when T_375 : + bValid <= UInt<1>("h0") + node T_377 = and(io.axi.aw.ready, io.axi.aw.valid) + when T_377 : + wValid <= UInt<1>("h1") + node T_379 = and(io.axi.w.ready, io.axi.w.valid) + when T_379 : + node T_380 = eq(aw.burst, UInt<2>("h1")) + node T_381 = or(T_380, reset) + node T_383 = eq(T_381, UInt<1>("h0")) + when T_383 : + printf(clk, UInt<1>("h1"), "Assertion failed\n at TestHarness.scala:104 assert(aw.burst === NastiConstants.BURST_INCR)\n") + stop(clk, UInt<1>("h1"), 1) + node T_385 = dshl(UInt<1>("h1"), aw.size) + node T_386 = add(aw.addr, T_385) + node T_387 = tail(T_386, 1) + aw.addr <= T_387 + node T_389 = sub(aw.len, UInt<1>("h1")) + node T_390 = tail(T_389, 1) + aw.len <= T_390 + node T_392 = eq(aw.len, UInt<1>("h0")) + when T_392 : + wValid <= UInt<1>("h0") + bValid <= UInt<1>("h1") + node T_395 = bits(io.axi.w.bits.strb, 0, 0) + node T_396 = bits(io.axi.w.bits.strb, 1, 1) + node T_397 = bits(io.axi.w.bits.strb, 2, 2) + node T_398 = bits(io.axi.w.bits.strb, 3, 3) + node T_399 = bits(io.axi.w.bits.strb, 4, 4) + node T_400 = bits(io.axi.w.bits.strb, 5, 5) + node T_401 = bits(io.axi.w.bits.strb, 6, 6) + node T_402 = bits(io.axi.w.bits.strb, 7, 7) + node T_403 = bits(T_395, 0, 0) + node T_406 = mux(T_403, UInt<8>("hff"), UInt<8>("h0")) + node T_407 = bits(T_396, 0, 0) + node T_410 = mux(T_407, UInt<8>("hff"), UInt<8>("h0")) + node T_411 = bits(T_397, 0, 0) + node T_414 = mux(T_411, UInt<8>("hff"), UInt<8>("h0")) + node T_415 = bits(T_398, 0, 0) + node T_418 = mux(T_415, UInt<8>("hff"), UInt<8>("h0")) + node T_419 = bits(T_399, 0, 0) + node T_422 = mux(T_419, UInt<8>("hff"), UInt<8>("h0")) + node T_423 = bits(T_400, 0, 0) + node T_426 = mux(T_423, UInt<8>("hff"), UInt<8>("h0")) + node T_427 = bits(T_401, 0, 0) + node T_430 = mux(T_427, UInt<8>("hff"), UInt<8>("h0")) + node T_431 = bits(T_402, 0, 0) + node T_434 = mux(T_431, UInt<8>("hff"), UInt<8>("h0")) + node T_435 = cat(T_410, T_406) + node T_436 = cat(T_418, T_414) + node T_437 = cat(T_436, T_435) + node T_438 = cat(T_426, T_422) + node T_439 = cat(T_434, T_430) + node T_440 = cat(T_439, T_438) + node T_441 = cat(T_440, T_437) + node T_442 = and(T_441, io.axi.w.bits.data) + node T_443 = not(T_441) + node T_444 = shr(aw.addr, 3) + node T_445 = bits(T_444, 24, 0) infer mport T_446 = mem[T_445], clk - node T_447 = and(T_443, T_446) @[TestHarness.scala 114:41] - node T_448 = or(T_442, T_447) @[TestHarness.scala 114:33] - node T_449 = shr(aw.addr, 3) @[TestHarness.scala 112:28] - node T_450 = bits(T_449, 24, 0) @[TestHarness.scala 112:58] + node T_447 = and(T_443, T_446) + node T_448 = or(T_442, T_447) + node T_449 = shr(aw.addr, 3) + node T_450 = bits(T_449, 24, 0) infer mport T_451 = mem[T_450], clk - T_451 <= T_448 @[TestHarness.scala 115:9] - skip @[TestHarness.scala 103:26] - io.axi.b.valid <= bValid @[TestHarness.scala 118:18] - io.axi.b.bits.id <= aw.id @[TestHarness.scala 119:20] - io.axi.b.bits.resp <= UInt<1>("h00") @[TestHarness.scala 120:22] - io.axi.r.valid <= rValid @[TestHarness.scala 122:18] - io.axi.r.bits.id <= ar.id @[TestHarness.scala 123:20] - node T_453 = shr(ar.addr, 3) @[TestHarness.scala 124:38] - node T_454 = bits(T_453, 24, 0) @[TestHarness.scala 124:68] + T_451 <= T_448 + io.axi.b.valid <= bValid + io.axi.b.bits.id <= aw.id + io.axi.b.bits.resp <= UInt<1>("h0") + io.axi.r.valid <= rValid + io.axi.r.bits.id <= ar.id + node T_453 = shr(ar.addr, 3) + node T_454 = bits(T_453, 24, 0) infer mport T_455 = mem[T_454], clk - io.axi.r.bits.data <= T_455 @[TestHarness.scala 124:22] - io.axi.r.bits.resp <= UInt<1>("h00") @[TestHarness.scala 125:22] - node T_458 = eq(ar.len, UInt<1>("h00")) @[TestHarness.scala 126:32] - io.axi.r.bits.last <= T_458 @[TestHarness.scala 126:22] - - extmodule SimDTM : + io.axi.r.bits.data <= T_455 + io.axi.r.bits.resp <= UInt<1>("h0") + node T_458 = eq(ar.len, UInt<1>("h0")) + io.axi.r.bits.last <= T_458 + + extmodule SimDTM : output exit : UInt<32> - output debug : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<34>, resp : UInt<2>}}} + output debug : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<5>, data : UInt<34>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<34>, resp : UInt<2>}}} input reset : UInt<1> input clk : Clock - - - module TestHarness : + defname = SimDTM + + module TestHarness : input clk : Clock input reset : UInt<1> - output io : {success : UInt<1>} - + output io : { success : UInt<1>} + io is invalid - inst dut of ExampleTop @[Top.scala 80:36] + inst dut of ExampleTop dut.io is invalid dut.clk <= clk dut.reset <= reset - dut.io.interrupts[0] <= UInt<1>("h00") @[TestHarness.scala 32:9] - dut.io.interrupts[1] <= UInt<1>("h00") @[TestHarness.scala 32:9] - inst SimAXIMem_1 of SimAXIMem @[TestHarness.scala 38:23] + dut.io.interrupts[0] <= UInt<1>("h0") + dut.io.interrupts[1] <= UInt<1>("h0") + inst SimAXIMem_1 of SimAXIMem SimAXIMem_1.io is invalid SimAXIMem_1.clk <= clk SimAXIMem_1.reset <= reset - SimAXIMem_1.io.axi.ar <- dut.io.mem_axi[0].ar @[TestHarness.scala 39:21] - SimAXIMem_1.io.axi.aw <- dut.io.mem_axi[0].aw @[TestHarness.scala 40:21] - SimAXIMem_1.io.axi.w <- dut.io.mem_axi[0].w @[TestHarness.scala 41:21] - dut.io.mem_axi[0].r <- SimAXIMem_1.io.axi.r @[TestHarness.scala 42:13] - dut.io.mem_axi[0].b <- SimAXIMem_1.io.axi.b @[TestHarness.scala 43:13] - inst SimDTM_1 of SimDTM @[TestHarness.scala 54:21] + SimAXIMem_1.io.axi.ar <- dut.io.mem_axi[0].ar + SimAXIMem_1.io.axi.aw <- dut.io.mem_axi[0].aw + SimAXIMem_1.io.axi.w <- dut.io.mem_axi[0].w + dut.io.mem_axi[0].r <- SimAXIMem_1.io.axi.r + dut.io.mem_axi[0].b <- SimAXIMem_1.io.axi.b + inst SimDTM_1 of SimDTM SimDTM_1.exit is invalid SimDTM_1.debug is invalid SimDTM_1.reset is invalid SimDTM_1.clk is invalid - SimDTM_1.clk <= clk @[TestHarness.scala 139:12] - SimDTM_1.reset <= reset @[TestHarness.scala 140:14] - dut.io.debug <- SimDTM_1.debug @[TestHarness.scala 141:11] - node T_4 = eq(SimDTM_1.exit, UInt<1>("h01")) @[TestHarness.scala 143:47] - io.success <= T_4 @[TestHarness.scala 143:15] - node T_6 = geq(SimDTM_1.exit, UInt<2>("h02")) @[TestHarness.scala 144:19] - when T_6 : @[TestHarness.scala 144:25] - node T_7 = shr(SimDTM_1.exit, 1) @[TestHarness.scala 145:59] - node T_9 = eq(reset, UInt<1>("h00")) @[TestHarness.scala 145:13] - when T_9 : @[TestHarness.scala 145:13] - printf(clk, UInt<1>(1), "*** FAILED *** (exit code = %d)\n", T_7) @[TestHarness.scala 145:13] - skip @[TestHarness.scala 145:13] - node T_11 = eq(reset, UInt<1>("h00")) @[TestHarness.scala 146:11] - when T_11 : @[TestHarness.scala 146:11] - stop(clk, UInt<1>(1), 1) @[TestHarness.scala 146:11] - skip @[TestHarness.scala 146:11] - skip @[TestHarness.scala 144:25] - + SimDTM_1.clk <= clk + SimDTM_1.reset <= reset + dut.io.debug <- SimDTM_1.debug + node T_4 = eq(SimDTM_1.exit, UInt<1>("h1")) + io.success <= T_4 + node T_6 = geq(SimDTM_1.exit, UInt<2>("h2")) + when T_6 : + node T_7 = shr(SimDTM_1.exit, 1) + node T_9 = eq(reset, UInt<1>("h0")) + when T_9 : + printf(clk, UInt<1>("h1"), "*** FAILED *** (exit code = %d)\n", T_7) + node T_11 = eq(reset, UInt<1>("h0")) + when T_11 : + stop(clk, UInt<1>("h1"), 1) diff --git a/rocket18/freechips.rocketchip.system.DefaultConfig.fir b/rocket18/freechips.rocketchip.system.DefaultConfig.fir index 06bb115..2ceca98 100644 --- a/rocket18/freechips.rocketchip.system.DefaultConfig.fir +++ b/rocket18/freechips.rocketchip.system.DefaultConfig.fir @@ -216227,8 +216227,10 @@ circuit TestHarness : tile_inputs[0].hartid <= UInt<1>("h00") @[RocketSubsystem.scala 74:17] tile_inputs[0].reset_vector <= global_reset_vector @[RocketSubsystem.scala 75:23] reg value : UInt<7>, clock with : (reset => (reset, UInt<7>("h00"))) @[Counter.scala 26:33] + wire _T_223 : UInt<1> + _T_223 is invalid when UInt<1>("h01") : @[Counter.scala 63:17] - node _T_223 = eq(value, UInt<7>("h063")) @[Counter.scala 34:24] + _T_223 <= eq(value, UInt<7>("h063")) @[Counter.scala 34:24] node _T_225 = add(value, UInt<1>("h01")) @[Counter.scala 35:22] node _T_226 = tail(_T_225, 1) @[Counter.scala 35:22] value <= _T_226 @[Counter.scala 35:13]