[NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2491-g3f8a0df Thu Jan 01 00:00:00 UTC 1970 x86_32 bootblock starting (log level: 7)... [DEBUG] CPU: Intel(R) Core(TM) Ultra 7 155H [DEBUG] CPU: ID a06a4, MeteorLake C0, ucode: 0000001c [DEBUG] CPU: AES supported, TXT supported, VT supported [INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 32768 [INFO ] Cache size = 24 MiB [DEBUG] MCH: device id 7d01 (rev 04) is MeteorLake P [DEBUG] PCH: device id 7e02 (rev 20) is MeteorLake SOC [DEBUG] IGD: device id 7d55 (rev 08) is MeteorLake-P GT2 [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1010000. [DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 7 [DEBUG] FMAP: area COREBOOT found @ 1010200 (16711168 bytes) [INFO ] CBFS: mcache @0xfef82e00 built for 17 files, used 0x3ac of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x93f700 size 0x160e8 in mcache @0xfef82e58 [INFO ] VB2:vb2_digest_init() 90344 bytes, hash algo 2, HW acceleration unsupported [INFO ] TPM LOG: clearing the log [DEBUG] FMAP: area FMAP found @ 1010000 (512 bytes) [INFO ] VB2:vb2_digest_init() 512 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `FMAP: FMAP` to PCR 2 logged [INFO ] CBFS: Found 'bootblock' @0xfe8480 size 0x7940 in mcache @0xfef83168 [INFO ] VB2:vb2_digest_init() 31040 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: bootblock` to PCR 2 logged [DEBUG] CRTM initialized. [DEBUG] TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged [DEBUG] BS: bootblock times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2491-g3f8a0df Thu Jan 01 00:00:00 UTC 1970 x86_32 romstage starting (log level: 7)... [DEBUG] pm1_sts: 8000 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00004000 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d9841038 00002204 [DEBUG] GBLRST_CAUSE: 00000440 00000004 [DEBUG] HPR_CAUSE0: 00000002 [DEBUG] prev_sleep_state 5 (S5) [DEBUG] FMAP: area COREBOOT found @ 1010200 (16711168 bytes) [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x88b000, Host base=0xf988b000, Size=0x775000 [INFO ] CBFS: Found 'fspm.bin' @0x9b5dc0 size 0xc0000 in mcache @0xfef83088 [INFO ] VB2:vb2_digest_init() 786432 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fspm.bin` to PCR 2 logged [INFO ] CBFS: Found 'fspm.bin' @0x9b5dc0 size 0xc0000 in mcache @0xfef83088 [INFO ] VB2:vb2_digest_init() 786432 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fspm.bin` to PCR 2 logged [DEBUG] FMAP: area RW_MRC_CACHE found @ 1000000 (65536 bytes) [DEBUG] soc_info: max_pcie_clock:9 [DEBUG] soc_info: max_pcie_port:12 [DEBUG] soc_info: tcss_port:4 [INFO ] SPD: module type is DDR5 [INFO ] SPD: banks 4, ranks 5, rows 12, columns 10, density 8192 Mb [INFO ] SPD: device width 4 bits, bus width 16 bits [INFO ] SPD: module size is 20480 MB (per channel) [INFO ] SPD: module type is DDR5 [INFO ] SPD: banks 4, ranks 5, rows 12, columns 10, density 8192 Mb [INFO ] SPD: device width 4 bits, bus width 16 bits [INFO ] SPD: module size is 20480 MB (per channel) [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x69fff000 254 entries. [DEBUG] IMD: root @ 0x69ffec00 62 entries. [DEBUG] External stage cache: [DEBUG] IMD: root @ 0x6fbff000 254 entries. [DEBUG] IMD: root @ 0x6fbfec00 62 entries. [DEBUG] FMAP: area RW_MRC_CACHE found @ 1000000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [INFO ] REGF update can't fit. Will empty. [DEBUG] MRC: updated 'RW_MRC_CACHE'. [ERROR] No DIMMs found [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x6f800000 0x800000 [DEBUG] Subregion 0: 0x6f800000 0x200000 [DEBUG] Subregion 1: 0x6fa00000 0x200000 [DEBUG] Subregion 2: 0x6fc00000 0x400000 [DEBUG] top_of_ram = 0x6a000000 [DEBUG] Normal boot [INFO ] CBFS: Found 'fallback/postcar' @0xab6380 size 0x8650 in mcache @0xfef83124 [INFO ] VB2:vb2_digest_init() 34384 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged [DEBUG] Loading module at 0x69a3a000 with entry 0x69a3a031. filesize: 0x8088 memsize: 0xe440 [DEBUG] Processing 354 relocs. Offset value of 0x67a3a000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2491-g3f8a0df Thu Jan 01 00:00:00 UTC 1970 x86_32 postcar starting (log level: 7)... [DEBUG] Normal boot [DEBUG] FMAP: area COREBOOT found @ 1010200 (16711168 bytes) [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x88b000, Host base=0xf988b000, Size=0x775000 [INFO ] CBFS: Found 'fallback/ramstage' @0x976d40 size 0x28875 in mcache @0x69a4d138 [INFO ] VB2:vb2_digest_init() 166005 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged [DEBUG] Loading module at 0x698c6000 with entry 0x698c6000. filesize: 0x55f38 memsize: 0x172670 [DEBUG] Processing 6025 relocs. Offset value of 0x658c6000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-2491-g3f8a0df Thu Jan 01 00:00:00 UTC 1970 x86_32 ramstage starting (log level: 7)... [WARN ] WARNING: Post-RAM FMAP access too early for cache! [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x88b000, Host base=0xf988b000, Size=0x775000 [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1010000. [DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 7 [DEBUG] Normal boot [DEBUG] FMAP: area SI_DESC found @ 0 (16384 bytes) [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [DEBUG] Update of Descriptor is not required! [INFO ] ME is HAP disabled [DEBUG] BS: BS_PRE_DEVICE entry times (exec / console): 2 / 0 ms [INFO ] Reserved BERT region base: 0x698b5000, size: 0x10000 [DEBUG] microcode: sig=0xa06a4 pf=0x80 revision=0x1c [DEBUG] FMAP: area COREBOOT found @ 1010200 (16711168 bytes) [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x955880 size 0x21400 in mcache @0x69a4d0d8 [INFO ] VB2:vb2_digest_init() 136192 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: cpu_microcode_blob.bin` to PCR 2 logged [INFO ] microcode: Update skipped, already up-to-date [INFO ] CBFS: Found 'fsps.bin' @0xa75e00 size 0x401b1 in mcache @0x69a4d2c8 [INFO ] VB2:vb2_digest_init() 262577 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: fsps.bin` to PCR 2 logged [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Setting up SMI for CPU [DEBUG] IED base = 0x6fc00000 [DEBUG] IED size = 0x00400000 [INFO ] Will perform SMM setup. [INFO ] CPU: Intel(R) Core(TM) Ultra 7 155H. [INFO ] LAPIC 0x20 in XAPIC mode. [DEBUG] CPU: APIC: 20 enabled [DEBUG] CPU: APIC: 21 enabled [DEBUG] CPU: APIC: 22 enabled [DEBUG] CPU: APIC: 23 enabled [DEBUG] CPU: APIC: 24 enabled [DEBUG] CPU: APIC: 25 enabled [DEBUG] CPU: APIC: 26 enabled [DEBUG] CPU: APIC: 27 enabled [DEBUG] CPU: APIC: 28 enabled [DEBUG] CPU: APIC: 29 enabled [DEBUG] CPU: APIC: 2a enabled [DEBUG] CPU: APIC: 2b enabled [DEBUG] CPU: APIC: 2c enabled [DEBUG] CPU: APIC: 2d enabled [DEBUG] CPU: APIC: 2e enabled [DEBUG] CPU: APIC: 2f enabled [DEBUG] CPU: APIC: 30 enabled [DEBUG] CPU: APIC: 31 enabled [DEBUG] CPU: APIC: 32 enabled [DEBUG] CPU: APIC: 33 enabled [DEBUG] CPU: APIC: 34 enabled [DEBUG] CPU: APIC: 35 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 21 APs [DEBUG] Waiting for ICR not to be busy... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x0 in XAPIC mode. [INFO ] AP: slot 1 apic_id 0, MCU rev: 0x0000001c [INFO ] LAPIC 0x40 in XAPIC mode. [INFO ] AP: slot 2 apic_id 40, MCU rev: 0x0000001c [INFO ] LAPIC 0x42 in XAPIC mode. [INFO ] AP: slot 3 apic_id 42, MCU rev: 0x0000001c [INFO ] LAPIC 0x6 in XAPIC mode. [INFO ] AP: slot 5 apic_id 6, MCU rev: 0x0000001c [INFO ] LAPIC 0x2 in XAPIC mode. [INFO ] AP: slot 6 apic_id 2, MCU rev: 0x0000001c [INFO ] LAPIC 0x4 in XAPIC mode. [INFO ] AP: slot 7 apic_id 4, MCU rev: 0x0000001c [INFO ] LAPIC 0x21 in XAPIC mode. [INFO ] AP: slot 4 apic_id 21, MCU rev: 0x0000001c [INFO ] LAPIC 0x8 in XAPIC mode. [INFO ] AP: slot 8 apic_id 8, MCU rev: 0x0000001c [INFO ] LAPIC 0xe in XAPIC mode. [INFO ] AP: slot 10 apic_id e, MCU rev: 0x0000001c [INFO ] LAPIC 0xc in XAPIC mode. [INFO ] AP: slot 11 apic_id c, MCU rev: 0x0000001c [INFO ] LAPIC 0xa in XAPIC mode. [INFO ] AP: slot 12 apic_id a, MCU rev: 0x0000001c [INFO ] LAPIC 0x18 in XAPIC mode. [INFO ] LAPIC 0x19 in XAPIC mode. [INFO ] AP: slot 13 apic_id 18, MCU rev: 0x0000001c [INFO ] AP: slot 14 apic_id 19, MCU rev: 0x0000001c [INFO ] LAPIC 0x31 in XAPIC mode. [INFO ] LAPIC 0x30 in XAPIC mode. [INFO ] AP: slot 17 apic_id 31, MCU rev: 0x0000001c [INFO ] AP: slot 16 apic_id 30, MCU rev: 0x0000001c [INFO ] LAPIC 0x29 in XAPIC mode. [INFO ] LAPIC 0x28 in XAPIC mode. [INFO ] AP: slot 15 apic_id 29, MCU rev: 0x0000001c [INFO ] AP: slot 18 apic_id 28, MCU rev: 0x0000001c [INFO ] LAPIC 0x11 in XAPIC mode. [INFO ] LAPIC 0x10 in XAPIC mode. [INFO ] AP: slot 9 apic_id 11, MCU rev: 0x0000001c [INFO ] AP: slot 19 apic_id 10, MCU rev: 0x0000001c [INFO ] LAPIC 0x38 in XAPIC mode. [INFO ] LAPIC 0x39 in XAPIC mode. [INFO ] AP: slot 20 apic_id 38, MCU rev: 0x0000001c [INFO ] AP: slot 21 apic_id 39, MCU rev: 0x0000001c [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 [DEBUG] Processing 9 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x6f80b000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x698f56b3 [DEBUG] Installing permanent SMM handler to 0x6f800000 [DEBUG] HANDLER [0x6f9fe000-0x6f9ff250] [DEBUG] CPU 0 [DEBUG] ss0 [0x6f9fdc00-0x6f9fe000] [DEBUG] stub0 [0x6f9f6000-0x6f9f61b8] [DEBUG] CPU 1 [DEBUG] ss1 [0x6f9fd800-0x6f9fdc00] [DEBUG] stub1 [0x6f9f5c00-0x6f9f5db8] [DEBUG] CPU 2 [DEBUG] ss2 [0x6f9fd400-0x6f9fd800] [DEBUG] stub2 [0x6f9f5800-0x6f9f59b8] [DEBUG] CPU 3 [DEBUG] ss3 [0x6f9fd000-0x6f9fd400] [DEBUG] stub3 [0x6f9f5400-0x6f9f55b8] [DEBUG] CPU 4 [DEBUG] ss4 [0x6f9fcc00-0x6f9fd000] [DEBUG] stub4 [0x6f9f5000-0x6f9f51b8] [DEBUG] CPU 5 [DEBUG] ss5 [0x6f9fc800-0x6f9fcc00] [DEBUG] stub5 [0x6f9f4c00-0x6f9f4db8] [DEBUG] CPU 6 [DEBUG] ss6 [0x6f9fc400-0x6f9fc800] [DEBUG] stub6 [0x6f9f4800-0x6f9f49b8] [DEBUG] CPU 7 [DEBUG] ss7 [0x6f9fc000-0x6f9fc400] [DEBUG] stub7 [0x6f9f4400-0x6f9f45b8] [DEBUG] CPU 8 [DEBUG] ss8 [0x6f9fbc00-0x6f9fc000] [DEBUG] stub8 [0x6f9f4000-0x6f9f41b8] [DEBUG] CPU 9 [DEBUG] ss9 [0x6f9fb800-0x6f9fbc00] [DEBUG] stub9 [0x6f9f3c00-0x6f9f3db8] [DEBUG] CPU 10 [DEBUG] ss10 [0x6f9fb400-0x6f9fb800] [DEBUG] stub10 [0x6f9f3800-0x6f9f39b8] [DEBUG] CPU 11 [DEBUG] ss11 [0x6f9fb000-0x6f9fb400] [DEBUG] stub11 [0x6f9f3400-0x6f9f35b8] [DEBUG] CPU 12 [DEBUG] ss12 [0x6f9fac00-0x6f9fb000] [DEBUG] stub12 [0x6f9f3000-0x6f9f31b8] [DEBUG] CPU 13 [DEBUG] ss13 [0x6f9fa800-0x6f9fac00] [DEBUG] stub13 [0x6f9f2c00-0x6f9f2db8] [DEBUG] CPU 14 [DEBUG] ss14 [0x6f9fa400-0x6f9fa800] [DEBUG] stub14 [0x6f9f2800-0x6f9f29b8] [DEBUG] CPU 15 [DEBUG] ss15 [0x6f9fa000-0x6f9fa400] [DEBUG] stub15 [0x6f9f2400-0x6f9f25b8] [DEBUG] CPU 16 [DEBUG] ss16 [0x6f9f9c00-0x6f9fa000] [DEBUG] stub16 [0x6f9f2000-0x6f9f21b8] [DEBUG] CPU 17 [DEBUG] ss17 [0x6f9f9800-0x6f9f9c00] [DEBUG] stub17 [0x6f9f1c00-0x6f9f1db8] [DEBUG] CPU 18 [DEBUG] ss18 [0x6f9f9400-0x6f9f9800] [DEBUG] stub18 [0x6f9f1800-0x6f9f19b8] [DEBUG] CPU 19 [DEBUG] ss19 [0x6f9f9000-0x6f9f9400] [DEBUG] stub19 [0x6f9f1400-0x6f9f15b8] [DEBUG] CPU 20 [DEBUG] ss20 [0x6f9f8c00-0x6f9f9000] [DEBUG] stub20 [0x6f9f1000-0x6f9f11b8] [DEBUG] CPU 21 [DEBUG] ss21 [0x6f9f8800-0x6f9f8c00] [DEBUG] stub21 [0x6f9f0c00-0x6f9f0db8] [DEBUG] stacks [0x6f800000-0x6f80b000] [DEBUG] Loading module at 0x6f9fe000 with entry 0x6f9fe06d. filesize: 0x1240 memsize: 0x1250 [DEBUG] Processing 114 relocs. Offset value of 0x6f9fe000 [DEBUG] Loading module at 0x6f9f6000 with entry 0x6f9f6000. filesize: 0x1b8 memsize: 0x1b8 [DEBUG] Processing 9 relocs. Offset value of 0x6f9f6000 [DEBUG] smm_module_setup_stub: stack_top = 0x6f80b000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000 [DEBUG] SMM Module: placing smm entry code at 6f9f5c00, cpu # 0x1 [DEBUG] SMM Module: placing smm entry code at 6f9f5800, cpu # 0x2 [DEBUG] SMM Module: placing smm entry code at 6f9f5400, cpu # 0x3 [DEBUG] SMM Module: placing smm entry code at 6f9f5000, cpu # 0x4 [DEBUG] SMM Module: placing smm entry code at 6f9f4c00, cpu # 0x5 [DEBUG] SMM Module: placing smm entry code at 6f9f4800, cpu # 0x6 [DEBUG] SMM Module: placing smm entry code at 6f9f4400, cpu # 0x7 [DEBUG] SMM Module: placing smm entry code at 6f9f4000, cpu # 0x8 [DEBUG] SMM Module: placing smm entry code at 6f9f3c00, cpu # 0x9 [DEBUG] SMM Module: placing smm entry code at 6f9f3800, cpu # 0xa [DEBUG] SMM Module: placing smm entry code at 6f9f3400, cpu # 0xb [DEBUG] SMM Module: placing smm entry code at 6f9f3000, cpu # 0xc [DEBUG] SMM Module: placing smm entry code at 6f9f2c00, cpu # 0xd [DEBUG] SMM Module: placing smm entry code at 6f9f2800, cpu # 0xe [DEBUG] SMM Module: placing smm entry code at 6f9f2400, cpu # 0xf [DEBUG] SMM Module: placing smm entry code at 6f9f2000, cpu # 0x10 [DEBUG] SMM Module: placing smm entry code at 6f9f1c00, cpu # 0x11 [DEBUG] SMM Module: placing smm entry code at 6f9f1800, cpu # 0x12 [DEBUG] SMM Module: placing smm entry code at 6f9f1400, cpu # 0x13 [DEBUG] SMM Module: placing smm entry code at 6f9f1000, cpu # 0x14 [DEBUG] SMM Module: placing smm entry code at 6f9f0c00, cpu # 0x15 [DEBUG] SMM Module: stub loaded at 6f9f6000. Will call 0x6f9fe06d [DEBUG] Clearing SMI status registers [DEBUG] SMI_STS: PM1 [DEBUG] PM1_STS: WAK TMROF [DEBUG] GPE0 STD STS: eSPI [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ee000, cpu = 0 [DEBUG] In relocation handler: CPU 0 [DEBUG] New SMBASE=0x6f9ee000 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ed000, cpu = 4 [DEBUG] In relocation handler: CPU 4 [DEBUG] New SMBASE=0x6f9ed000 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9e9400, cpu = 19 [DEBUG] In relocation handler: CPU 19 [DEBUG] New SMBASE=0x6f9e9400 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ed400, cpu = 3 [DEBUG] In relocation handler: CPU 3 [DEBUG] New SMBASE=0x6f9ed400 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ecc00, cpu = 5 [DEBUG] In relocation handler: CPU 5 [DEBUG] New SMBASE=0x6f9ecc00 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ed800, cpu = 2 [DEBUG] In relocation handler: CPU 2 [DEBUG] New SMBASE=0x6f9ed800 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ec800, cpu = 6 [DEBUG] In relocation handler: CPU 6 [DEBUG] New SMBASE=0x6f9ec800 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9eb800, cpu = 10 [DEBUG] In relocation handler: CPU 10 [DEBUG] New SMBASE=0x6f9eb800 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ea800, cpu = 14 [DEBUG] In relocation handler: CPU 14 [DEBUG] New SMBASE=0x6f9ea800 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9edc00, cpu = 1 [DEBUG] In relocation handler: CPU 1 [DEBUG] New SMBASE=0x6f9edc00 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ec000, cpu = 8 [DEBUG] In relocation handler: CPU 8 [DEBUG] New SMBASE=0x6f9ec000 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9e9800, cpu = 18 [DEBUG] In relocation handler: CPU 18 [DEBUG] New SMBASE=0x6f9e9800 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ea000, cpu = 16 [DEBUG] In relocation handler: CPU 16 [DEBUG] New SMBASE=0x6f9ea000 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9e9c00, cpu = 17 [DEBUG] In relocation handler: CPU 17 [DEBUG] New SMBASE=0x6f9e9c00 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ea400, cpu = 15 [DEBUG] In relocation handler: CPU 15 [DEBUG] New SMBASE=0x6f9ea400 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9e8c00, cpu = 21 [DEBUG] In relocation handler: CPU 21 [DEBUG] New SMBASE=0x6f9e8c00 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ec400, cpu = 7 [DEBUG] In relocation handler: CPU 7 [DEBUG] New SMBASE=0x6f9ec400 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9ebc00, cpu = 9 [DEBUG] In relocation handler: CPU 9 [DEBUG] New SMBASE=0x6f9ebc00 IEDBASE=0x6fc00000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9e9000, cpu = 20 [DEBUG] In relocation handler: CPU 20 [DEBUG] New SMBASE=0x6f9e9000 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9eb000, cpu = 12 [DEBUG] In relocation handler: CPU 12 [DEBUG] New SMBASE=0x6f9eb000 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9eac00, cpu = 13 [DEBUG] In relocation handler: CPU 13 [DEBUG] New SMBASE=0x6f9eac00 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x6f9eb400, cpu = 11 [DEBUG] In relocation handler: CPU 11 [DEBUG] New SMBASE=0x6f9eb400 IEDBASE=0x6fc00000 [DEBUG] Writing SMRR. base = 0x6f800006, mask=0xff800c00 [DEBUG] Relocation complete. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x20 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] Turbo is available but hidden [INFO ] Turbo is available and visible [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #0 initialized [INFO ] Initializing CPU #6 [INFO ] Initializing CPU #7 [INFO ] Initializing CPU #2 [INFO ] Initializing CPU #3 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #11 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #8 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #18 [INFO ] Initializing CPU #16 [INFO ] Initializing CPU #15 [INFO ] Initializing CPU #17 [DEBUG] CPU: vendor Intel device a06a4 [INFO ] Initializing CPU #12 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [INFO ] Initializing CPU #10 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #5 [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #13 [INFO ] Initializing CPU #9 [INFO ] Initializing CPU #14 [DEBUG] CPU: vendor Intel device a06a4 [INFO ] Initializing CPU #1 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #19 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #4 [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [INFO ] Initializing CPU #21 [INFO ] Initializing CPU #20 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] CPU: vendor Intel device a06a4 [DEBUG] CPU: family 06, model aa, stepping 04 [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x42 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #3 initialized [INFO ] LAPIC 0x40 switched to X2APIC mode. [INFO ] LAPIC 0x2 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #2 initialized [INFO ] LAPIC 0xe switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #6 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #10 initialized [INFO ] LAPIC 0xa switched to X2APIC mode. [INFO ] LAPIC 0x8 switched to X2APIC mode. [INFO ] LAPIC 0x30 switched to X2APIC mode. [INFO ] LAPIC 0x4 switched to X2APIC mode. [INFO ] LAPIC 0xc switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] LAPIC 0x0 switched to X2APIC mode. [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #12 initialized [INFO ] LAPIC 0x11 switched to X2APIC mode. [INFO ] LAPIC 0x6 switched to X2APIC mode. [INFO ] LAPIC 0x19 switched to X2APIC mode. [INFO ] LAPIC 0x29 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #8 initialized [INFO ] LAPIC 0x21 switched to X2APIC mode. [INFO ] LAPIC 0x39 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #7 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #11 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] LAPIC 0x18 switched to X2APIC mode. [INFO ] LAPIC 0x28 switched to X2APIC mode. [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #1 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] LAPIC 0x10 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #5 initialized [INFO ] LAPIC 0x38 switched to X2APIC mode. [INFO ] LAPIC 0x31 switched to X2APIC mode. [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #16 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #4 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #14 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #9 initialized [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #21 initialized [INFO ] microcode: Update skipped, already up-to-date [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #18 initialized [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #13 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #15 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #17 initialized [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #20 initialized [INFO ] microcode: Update skipped, already up-to-date [INFO ] CPU #19 initialized [INFO ] bsp_do_flight_plan done after 10 msecs. [DEBUG] CPU: frequency set to 4800 MHz [DEBUG] Enabling SMIs. [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 34 / 1 ms [DEBUG] Wireless is enabled [DEBUG] soc_info: max_i2c_port:6 [DEBUG] soc_info: max_gspi_port:3 [DEBUG] soc_info: max_uart_port:3 [INFO ] CBFS: Found 'vbt.bin' @0x9b56c0 size 0x4fc in mcache @0x69a4d258 [INFO ] VB2:vb2_digest_init() 1276 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 logged [INFO ] Found a VBT of 7680 bytes [DEBUG] soc_info: max_usb20_port:10 [DEBUG] soc_info: max_usb30_port:2 [DEBUG] soc_info: tcss_port:4 [DEBUG] soc_info: max_pcie_port:12 [INFO ] PCI 1.0, PIN A, using IRQ #16 [INFO ] PCI 2.2, PIN A, using IRQ #17 [INFO ] PCI 4.0, PIN A, using IRQ #16 [INFO ] PCI 5.0, PIN A, using IRQ #16 [INFO ] PCI 6.0, PIN A, using IRQ #16 [INFO ] PCI 6.1, PIN B, using IRQ #17 [INFO ] PCI 6.2, PIN C, using IRQ #18 [INFO ] PCI 7.0, PIN A, using IRQ #19 [INFO ] PCI 7.1, PIN B, using IRQ #20 [INFO ] PCI 7.2, PIN C, using IRQ #21 [INFO ] PCI 7.3, PIN D, using IRQ #22 [INFO ] PCI 8.0, PIN A, using IRQ #23 [INFO ] PCI B.0, PIN A, using IRQ #18 [INFO ] PCI D.0, PIN A, using IRQ #19 [INFO ] PCI D.1, PIN B, using IRQ #20 [INFO ] PCI 10.0, PIN A, using IRQ #21 [INFO ] PCI 10.1, PIN B, using IRQ #22 [INFO ] PCI 12.0, PIN A, using IRQ #24 [INFO ] PCI 12.6, PIN B, using IRQ #25 [INFO ] PCI 12.7, PIN C, using IRQ #23 [INFO ] PCI 14.0, PIN B, using IRQ #17 [INFO ] PCI 14.1, PIN A, using IRQ #26 [INFO ] PCI 14.3, PIN C, using IRQ #18 [INFO ] PCI 15.0, PIN A, using IRQ #27 [INFO ] PCI 15.1, PIN B, using IRQ #28 [INFO ] PCI 15.2, PIN C, using IRQ #29 [INFO ] PCI 15.3, PIN D, using IRQ #30 [INFO ] PCI 16.0, PIN A, using IRQ #19 [INFO ] PCI 16.1, PIN B, using IRQ #20 [INFO ] PCI 16.2, PIN C, using IRQ #21 [INFO ] PCI 16.3, PIN D, using IRQ #22 [INFO ] PCI 16.4, PIN A, using IRQ #19 [INFO ] PCI 16.5, PIN B, using IRQ #20 [INFO ] PCI 17.0, PIN A, using IRQ #23 [INFO ] PCI 19.0, PIN A, using IRQ #31 [INFO ] PCI 19.1, PIN B, using IRQ #32 [INFO ] PCI 19.2, PIN C, using IRQ #33 [INFO ] PCI 1C.0, PIN A, using IRQ #16 [INFO ] PCI 1C.1, PIN B, using IRQ #17 [INFO ] PCI 1C.2, PIN C, using IRQ #18 [INFO ] PCI 1C.3, PIN D, using IRQ #19 [INFO ] PCI 1C.4, PIN A, using IRQ #16 [INFO ] PCI 1C.5, PIN B, using IRQ #17 [INFO ] PCI 1C.6, PIN C, using IRQ #18 [INFO ] PCI 1C.7, PIN D, using IRQ #19 [INFO ] PCI 1E.0, PIN A, using IRQ #20 [INFO ] PCI 1E.1, PIN B, using IRQ #21 [INFO ] PCI 1E.2, PIN C, using IRQ #34 [INFO ] PCI 1E.3, PIN D, using IRQ #35 [INFO ] PCI 1F.3, PIN B, using IRQ #23 [INFO ] PCI 1F.4, PIN C, using IRQ #20 [INFO ] PCI 1F.6, PIN D, using IRQ #21 [INFO ] PCI 1F.7, PIN A, using IRQ #22 [INFO ] IRQ: Using dynamically assigned PCI IO-APIC IRQs [INFO ] FSPS returned 0 [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Detected 16 core, 22 thread CPU. [DEBUG] Display FSP Version Info HOB [DEBUG] Reference Code - CPU = d.0.b1.20 [DEBUG] uCode Version = 0.0.0.1c [DEBUG] TXT ACM version = ff.ff.ff.ffff [DEBUG] Reference Code - ME = d.0.b1.20 [DEBUG] ME Firmware Version = Consumer SKU [DEBUG] ISSE Version = FFFF.FFFF.FFFF.FFFF [DEBUG] Reference Code - PCH = d.0.b1.20 [DEBUG] PCH-CRID Status = Disabled [DEBUG] PCH-CRID Original Value = ff.ff.ff.ffff [DEBUG] PCH-CRID New Value = ff.ff.ff.ffff [DEBUG] OPROM - RST - RAID = ff.ff.ff.ffff [DEBUG] PCH Hsio Version = 4.0.0.0 [DEBUG] Reference Code - SA - System Agent = d.0.b1.20 [DEBUG] Reference Code - MRC = 1.4.2.0 [DEBUG] SA - PCIe Version = d.0.b1.20 [DEBUG] SA-CRID Status = Disabled [DEBUG] SA-CRID Original Value = 0.0.0.4 [DEBUG] SA-CRID New Value = 0.0.0.4 [DEBUG] OPROM - VBIOS = ff.ff.ff.ffff [DEBUG] IO Manageability Engine FW Version = 30.1.9.0 [DEBUG] PHY Build Version = 0.0.0.1b65 [DEBUG] Thunderbolt(TM) FW Version = 8.1.0.0 [DEBUG] System Agent Manageability Engine FW Version = ff.ff.ff.ffff [INFO ] Found PCIe Root Port #6 at PCI: 00:1c.0. [INFO ] Found PCIe Root Port #11 at PCI: 00:06.0. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #10 (originally PCI: 00:00:06.1) which was enabled in devicetree, removing and disabling. [INFO ] Remapping PCIe Root Port #11 from PCI: 00:00:06.2 to new function number 0. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:00:1c.4) which was enabled in devicetree, removing and disabling. [INFO ] Remapping PCIe Root Port #6 from PCI: 00:00:1c.5 to new function number 0. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:00:1c.7) which was enabled in devicetree, removing and disabling. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 1348 / 0 ms [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [DEBUG] PCI: 00:00:00.0 [8086/7d01] enabled [DEBUG] PCI: 00:00:02.0 [8086/7d55] enabled [DEBUG] PCI: 00:00:04.0 [8086/7d03] enabled [DEBUG] PCI: 00:00:06.0 [8086/7ecb] enabled [DEBUG] PCI: 00:00:07.0 subordinate bus PCI Express [DEBUG] PCI: 00:00:07.0 hot-plug capable [DEBUG] PCI: 00:00:07.0 [8086/7ec4] enabled [DEBUG] PCI: 00:00:08.0 [8086/7e4c] enabled [DEBUG] PCI: 00:00:0a.0 [8086/7d0d] enabled [DEBUG] PCI: 00:00:0b.0 [8086/7d1d] enabled [DEBUG] PCI: 00:00:0d.0 [8086/7ec0] enabled [DEBUG] PCI: 00:00:0d.2 [8086/7ec2] enabled [DEBUG] PCI: 00:00:13.0 [0000/0000] hidden [DEBUG] PCI: 00:00:13.2 [0000/0000] hidden [DEBUG] PCI: 00:00:13.3 [8086/7ecf] enabled [DEBUG] PCI: 00:00:14.0 [8086/7e7d] enabled [DEBUG] PCI: 00:00:14.2 [8086/7e7f] enabled [DEBUG] PCI: 00:00:14.3 [8086/7e40] enabled [DEBUG] PCI: 00:00:15.0 [8086/7e78] enabled [DEBUG] PCI: 00:00:15.1 [8086/7e79] enabled [DEBUG] PCI: 00:00:15.3 [8086/7e7b] enabled [DEBUG] me_state = 2 [DEBUG] CMOS: me_state = 4294967295 [DEBUG] ME is in HAP mode, skipping soft temp disablePCI: 00:00:16.0 [8086/7e70] enabled [DEBUG] PCI: 00:00:1c.0 [8086/7e3d] enabled [DEBUG] PCI: 00:00:1e.0 [8086/7e25] enabled [DEBUG] PCI: 00:00:1f.0 [8086/7e02] enabled [DEBUG] PCI: 00:00:1f.1 [0000/0000] hidden [DEBUG] RTC Init [WARN ] RTC: Clear requested zeroing cmos [INFO ] Set power off after power failure. [DEBUG] Disabling Deep S3 [DEBUG] Disabling Deep S3 [DEBUG] Disabling Deep S4 [DEBUG] Disabling Deep S4 [DEBUG] Disabling Deep S5 [DEBUG] Disabling Deep S5 [DEBUG] PCI: 00:00:1f.2 [0000/0000] hidden [DEBUG] PCI: 00:00:1f.3 [8086/7e28] enabled [DEBUG] PCI: 00:00:1f.4 [8086/7e22] enabled [DEBUG] PCI: 00:00:1f.5 [8086/7e23] enabled [DEBUG] PCI: 00:00:1f.6 [8086/550a] enabled [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:00:05.0 [WARN ] PCI: 00:00:07.1 [WARN ] PCI: 00:00:07.2 [WARN ] PCI: 00:00:07.3 [WARN ] PCI: 00:00:0d.1 [WARN ] PCI: 00:00:0d.3 [WARN ] PCI: 00:00:0e.0 [WARN ] PCI: 00:00:10.0 [WARN ] PCI: 00:00:10.1 [WARN ] PCI: 00:00:12.0 [WARN ] PCI: 00:00:12.6 [WARN ] PCI: 00:00:12.7 [WARN ] PCI: 00:00:13.1 [WARN ] PCI: 00:00:14.1 [WARN ] PCI: 00:00:14.5 [WARN ] PCI: 00:00:15.2 [WARN ] PCI: 00:00:15.4 [WARN ] PCI: 00:00:16.1 [WARN ] PCI: 00:00:16.4 [WARN ] PCI: 00:00:16.5 [WARN ] PCI: 00:00:17.0 [WARN ] PCI: 00:00:18.0 [WARN ] PCI: 00:00:18.1 [WARN ] PCI: 00:00:18.2 [WARN ] PCI: 00:00:19.0 [WARN ] PCI: 00:00:19.1 [WARN ] PCI: 00:00:19.2 [WARN ] PCI: 00:00:1e.1 [WARN ] PCI: 00:00:1e.2 [WARN ] PCI: 00:00:1e.3 [WARN ] PCI: 00:00:1e.4 [WARN ] PCI: 00:00:1e.5 [WARN ] PCI: 00:00:1f.7 [WARN ] PCI: Check your devicetree.cb. [DEBUG] PCI: 00:00:02.0 scanning... [DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs [DEBUG] PCI: 00:00:04.0 scanning... [DEBUG] scan_bus: bus PCI: 00:00:04.0 finished in 0 msecs [DEBUG] PCI: 00:00:06.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01 [DEBUG] PCI: 00:01:00.0 [1e4b/1602] enabled [DEBUG] GENERIC: 0.0 enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] L1 Sub-State supported from root port 6 [INFO ] L1 Sub-State Support = 0x3 [INFO ] CommonModeRestoreTime = 0x3c [INFO ] Power On Value = 0xa, Power On Scale = 0x2 [INFO ] ASPM: Enabled None [INFO ] PCI: 00:01:00.0: Enabled LTR [INFO ] PCI: 00:01:00.0: Programmed LTR max latencies [INFO ] PCI: 00:00:06.0: Setting Max_Payload_Size to 256 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:06.0 finished in 0 msecs [DEBUG] PCI: 00:00:07.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 02 [DEBUG] GENERIC: 0.0 enabled [INFO ] PCI: 00:00:07.0: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:07.0 finished in 0 msecs [DEBUG] PCI: 00:00:0d.0 scanning... [DEBUG] USB0 port 0 enabled [DEBUG] USB0 port 0 scanning... [DEBUG] USB3 port 0 enabled [DEBUG] USB3 port 1 enabled [DEBUG] USB3 port 2 disabled [DEBUG] USB3 port 3 disabled [DEBUG] USB3 port 0 scanning... [DEBUG] scan_bus: bus USB3 port 0 finished in 0 msecs [DEBUG] USB3 port 1 scanning... [DEBUG] scan_bus: bus USB3 port 1 finished in 0 msecs [DEBUG] scan_bus: bus USB0 port 0 finished in 0 msecs [DEBUG] scan_bus: bus PCI: 00:00:0d.0 finished in 0 msecs [DEBUG] PCI: 00:00:0d.2 scanning... [DEBUG] GENERIC: 0.0 enabled [DEBUG] bus: PCI: 00:00:0d.2->scan_bus: bus PCI: 00:00:0d.2 finished in 0 msecs [DEBUG] PCI: 00:00:13.0 scanning... [DEBUG] scan_bus: bus PCI: 00:00:13.0 finished in 0 msecs [DEBUG] PCI: 00:00:14.0 scanning... [DEBUG] USB0 port 0 enabled [DEBUG] USB0 port 0 scanning... [DEBUG] USB2 port 0 enabled [DEBUG] USB2 port 1 enabled [DEBUG] USB2 port 2 enabled [DEBUG] USB2 port 3 disabled [DEBUG] USB2 port 4 disabled [DEBUG] USB2 port 5 enabled [DEBUG] USB2 port 6 enabled [DEBUG] USB2 port 7 disabled [DEBUG] USB2 port 8 disabled [DEBUG] USB2 port 9 enabled [DEBUG] USB3 port 0 enabled [DEBUG] USB3 port 1 enabled [DEBUG] USB2 port 0 scanning... [DEBUG] scan_bus: bus USB2 port 0 finished in 0 msecs [DEBUG] USB2 port 1 scanning... [DEBUG] scan_bus: bus USB2 port 1 finished in 0 msecs [DEBUG] USB2 port 2 scanning... [DEBUG] scan_bus: bus USB2 port 2 finished in 0 msecs [DEBUG] USB2 port 5 scanning... [DEBUG] scan_bus: bus USB2 port 5 finished in 0 msecs [DEBUG] USB2 port 6 scanning... [DEBUG] scan_bus: bus USB2 port 6 finished in 0 msecs [DEBUG] USB2 port 9 scanning... [DEBUG] scan_bus: bus USB2 port 9 finished in 0 msecs [DEBUG] USB3 port 0 scanning... [DEBUG] scan_bus: bus USB3 port 0 finished in 0 msecs [DEBUG] USB3 port 1 scanning... [DEBUG] scan_bus: bus USB3 port 1 finished in 0 msecs [DEBUG] scan_bus: bus USB0 port 0 finished in 0 msecs [DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs [DEBUG] PCI: 00:00:14.3 scanning... [DEBUG] GENERIC: 0.0 enabled [DEBUG] scan_bus: bus PCI: 00:00:14.3 finished in 0 msecs [DEBUG] PCI: 00:00:15.0 scanning... [DEBUG] I2C: 00:15 enabled [DEBUG] I2C: 00:38 enabled [DEBUG] scan_bus: bus PCI: 00:00:15.0 finished in 0 msecs [DEBUG] PCI: 00:00:15.1 scanning... [DEBUG] scan_bus: bus PCI: 00:00:15.1 finished in 0 msecs [DEBUG] PCI: 00:00:15.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:15.3 finished in 0 msecs [DEBUG] PCI: 00:00:1c.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 2d [INFO ] BayHub LV2: Power-saving enabled [DEBUG] PCI: 00:2d:00.0 [1217/8621] enabled [INFO ] L1 Sub-State supported from root port 28 [INFO ] L1 Sub-State Support = 0xf [INFO ] CommonModeRestoreTime = 0x78 [INFO ] Power On Value = 0x5, Power On Scale = 0x1 [INFO ] ASPM: Enabled L1 [INFO ] PCI: 00:00:1c.0: Max_Payload_Size adjusted to 128 [INFO ] PCI: 00:2d:00.0: Programmed LTR max latencies [INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs [DEBUG] PCI: 00:00:1f.0 scanning... [INFO ] Found TPM 2.0 SLB9672 TT 2.0 (0x001d) by Infineon (0x15d1) [DEBUG] PNP: 0c31.0 enabled [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs [DEBUG] PCI: 00:00:1f.1 scanning... [DEBUG] scan_bus: bus PCI: 00:00:1f.1 finished in 0 msecs [DEBUG] PCI: 00:00:1f.2 scanning... [DEBUG] GENERIC: 0.0 enabled [DEBUG] GENERIC: 0.0 scanning... [DEBUG] GENERIC: 0.0 enabled [DEBUG] GENERIC: 1.0 enabled [DEBUG] scan_bus: bus GENERIC: 0.0 finished in 0 msecs [DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs [DEBUG] PCI: 00:00:1f.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs [DEBUG] PCI: 00:00:1f.4 scanning... [DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 9 msecs [DEBUG] scan_bus: bus Root Device finished in 9 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 9 / 0 ms [INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE' [DEBUG] FMAP: area RW_MRC_CACHE found @ 1000000 (65536 bytes) [INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'. [DEBUG] BM-LOCKDOWN: Enabling boot media protection scheme 'readonly' using CTRL... [INFO ] fast_spi_flash_protect: FPR 0 is enabled for range 0x00000000-0x01ffffff [INFO ] BM-LOCKDOWN: Enabled bootmedia protection [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000 [DEBUG] SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000 [DEBUG] SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000 [DEBUG] SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000 [DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 [DEBUG] SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000 [DEBUG] SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000 [DEBUG] SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000 [DEBUG] SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000 [DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfc800000, size = 0x00001000 [DEBUG] SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 [DEBUG] SA MMIO resource: DSM -> base = 0x70800000, size = 0x08000000 [DEBUG] SA MMIO resource: TSEG -> base = 0x6f800000, size = 0x00800000 [DEBUG] SA MMIO resource: GSM -> base = 0x70000000, size = 0x00800000 [INFO ] Available memory above 4GB: 96256M [INFO ] PCI: 00:00:02.0: Adjusting resource index 24: base: 0 size: 10000000 align: 28 gran: 28 limit: ffffffffffffffff [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [DEBUG] PCI: 00:00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0x3fff] mem [DEBUG] PCI: 00:00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:00:07.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] NONE 18 * [0x0 - 0x7ff] io [DEBUG] PCI: 00:00:07.0 io: size: 1000 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:07.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] NONE 10 * [0x0 - 0xc1fffff] mem [DEBUG] PCI: 00:00:07.0 mem: size: c200000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:07.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] NONE 14 * [0x0 - 0x1bffffff] prefmem [DEBUG] PCI: 00:00:07.0 prefmem: size: 1c000000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 00:2d:00.0 10 * [0x0 - 0xfff] mem [DEBUG] PCI: 00:2d:00.0 14 * [0x1000 - 0x17ff] mem [DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000068 limit 0000006f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 00000e00 limit 00000eff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 8c base 00000f00 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 90 base 00000080 limit 0000008f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 01 base 00001800 limit 000018ff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: 800, Tag: 100 [INFO ] * Base: 1900, Size: d6a0, Tag: 100 [INFO ] * Base: efc0, Size: 1040, Tag: 100 [DEBUG] PCI: 00:00:07.0 1c * [0x2000 - 0x2fff] limit: 2fff io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 6a000000 size: 0 align: 0 gran: 0 limit: dfffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 3ffffffffff [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fedc0000 limit feddffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base feda0000 limit feda0fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base feda1000 limit feda1fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base d0000000 limit dfffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed80000 limit fed83fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base feb00000 limit feb7ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed20000 limit fed7ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fec00000 limit fecfffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base fd800000 limit fe7fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base fc800000 limit fc800fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base c0000000 limit cfffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 70800000 limit 787fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 6f800000 limit 6fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 70000000 limit 707fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0e base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0f base 000c0000 limit 69ffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 10 base 6a000000 limit 7fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 11 base 100000000 limit 187fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 12 base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 13 base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:13.0 10 base 3fff0000000 limit 3ffffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:13.2 10 base fe400000 limit fe40ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1e.0 10 base fe02c000 limit fe02cfff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed) [DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base e0000000 limit e0ffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 10 base fe000000 limit fe00ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.5 00 base ff000000 limit ffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.5 01 base f8000000 limit f9ffffff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 80000000, Size: 40000000, Tag: 200 [INFO ] * Base: 1880000000, Size: 3e770000000, Tag: 200 [DEBUG] PCI: 00:00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem [DEBUG] PCI: 00:00:0b.0 10 * [0x90000000 - 0x97ffffff] limit: 97ffffff mem [DEBUG] PCI: 00:00:02.0 10 * [0x98000000 - 0x98ffffff] limit: 98ffffff mem [DEBUG] PCI: 00:00:1f.3 20 * [0x99000000 - 0x991fffff] limit: 991fffff mem [DEBUG] PCI: 00:00:07.0 24 * [0x99200000 - 0xb51fffff] limit: b51fffff prefmem [ERROR] Resource didn't fit!!! [DEBUG] PCI: 00:00:07.0 20 * size: 0xc200000 limit: ffffffff mem [DEBUG] PCI: 00:00:06.0 20 * [0xb5200000 - 0xb52fffff] limit: b52fffff mem [DEBUG] PCI: 00:00:1c.0 20 * [0xb5300000 - 0xb53fffff] limit: b53fffff mem [DEBUG] PCI: 00:00:0a.0 10 * [0xb5400000 - 0xb543ffff] limit: b543ffff mem [DEBUG] PCI: 00:00:0d.2 10 * [0xb5440000 - 0xb547ffff] limit: b547ffff mem [DEBUG] PCI: 00:00:04.0 10 * [0xb5480000 - 0xb549ffff] limit: b549ffff mem [DEBUG] PCI: 00:00:1f.6 10 * [0xb54a0000 - 0xb54bffff] limit: b54bffff mem [DEBUG] PCI: 00:00:0d.0 10 * [0xb54c0000 - 0xb54cffff] limit: b54cffff mem [DEBUG] PCI: 00:00:14.0 10 * [0xb54d0000 - 0xb54dffff] limit: b54dffff mem [DEBUG] PCI: 00:00:13.3 10 * [0xb54e0000 - 0xb54e3fff] limit: b54e3fff mem [DEBUG] PCI: 00:00:14.2 10 * [0xb54e4000 - 0xb54e7fff] limit: b54e7fff mem [DEBUG] PCI: 00:00:14.3 10 * [0xb54e8000 - 0xb54ebfff] limit: b54ebfff mem [DEBUG] PCI: 00:00:1f.3 10 * [0xb54ec000 - 0xb54effff] limit: b54effff mem [DEBUG] PCI: 00:00:08.0 10 * [0xb54f0000 - 0xb54f0fff] limit: b54f0fff mem [DEBUG] PCI: 00:00:0b.0 20 * [0xb54f1000 - 0xb54f1fff] limit: b54f1fff mem [DEBUG] PCI: 00:00:0d.2 18 * [0xb54f2000 - 0xb54f2fff] limit: b54f2fff mem [DEBUG] PCI: 00:00:13.3 18 * [0xb54f3000 - 0xb54f3fff] limit: b54f3fff mem [DEBUG] PCI: 00:00:14.2 18 * [0xb54f4000 - 0xb54f4fff] limit: b54f4fff mem [DEBUG] PCI: 00:00:15.0 10 * [0xb54f5000 - 0xb54f5fff] limit: b54f5fff mem [DEBUG] PCI: 00:00:15.1 10 * [0xb54f6000 - 0xb54f6fff] limit: b54f6fff mem [DEBUG] PCI: 00:00:15.3 10 * [0xb54f7000 - 0xb54f7fff] limit: b54f7fff mem [DEBUG] PCI: 00:00:16.0 10 * [0xb54f8000 - 0xb54f8fff] limit: b54f8fff mem [DEBUG] PCI: 00:00:1f.5 10 * [0xb54f9000 - 0xb54f9fff] limit: b54f9fff mem [DEBUG] PCI: 00:00:1f.4 10 * [0xb54fa000 - 0xb54fa0ff] limit: b54fa0ff mem [DEBUG] DOMAIN: 00000000 mem: base: 6a000000 size: 0 align: 0 gran: 0 limit: dfffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 3ffffffffff done [DEBUG] PCI: 00:01:00.0 10 * [0xb5200000 - 0xb5203fff] limit: b5203fff mem [DEBUG] NONE 18 * [0x2000 - 0x27ff] limit: 27ff io [DEBUG] NONE 14 * [0x99200000 - 0xb51fffff] limit: b51fffff prefmem [DEBUG] PCI: 00:2d:00.0 10 * [0xb5300000 - 0xb5300fff] limit: b5300fff mem [DEBUG] PCI: 00:2d:00.0 14 * [0xb5301000 - 0xb53017ff] limit: b53017ff mem [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [DEBUG] PCI: 00:00:02.0 10 <- [0x0000000098000000 - 0x0000000098ffffff] size 0x01000000 gran 0x18 mem64 [DEBUG] PCI: 00:00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64 [DEBUG] PCI: 00:00:04.0 10 <- [0x00000000b5480000 - 0x00000000b549ffff] size 0x00020000 gran 0x11 mem64 [DEBUG] PCI: 00:00:06.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:06.0 20 <- [0x00000000b5200000 - 0x00000000b52fffff] size 0x00100000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:01:00.0 10 <- [0x00000000b5200000 - 0x00000000b5203fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:07.0 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:07.0 24 <- [0x0000000099200000 - 0x00000000b51fffff] size 0x1c000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:07.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:00:08.0 10 <- [0x00000000b54f0000 - 0x00000000b54f0fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:0a.0 10 <- [0x00000000b5400000 - 0x00000000b543ffff] size 0x00040000 gran 0x12 mem64 [DEBUG] PCI: 00:00:0b.0 10 <- [0x0000000090000000 - 0x0000000097ffffff] size 0x08000000 gran 0x1b mem64 [DEBUG] PCI: 00:00:0b.0 20 <- [0x00000000b54f1000 - 0x00000000b54f1fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:0d.0 10 <- [0x00000000b54c0000 - 0x00000000b54cffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:00:0d.2 10 <- [0x00000000b5440000 - 0x00000000b547ffff] size 0x00040000 gran 0x12 mem64 [DEBUG] PCI: 00:00:0d.2 18 <- [0x00000000b54f2000 - 0x00000000b54f2fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:13.3 10 <- [0x00000000b54e0000 - 0x00000000b54e3fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:13.3 18 <- [0x00000000b54f3000 - 0x00000000b54f3fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:14.0 10 <- [0x00000000b54d0000 - 0x00000000b54dffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:00:14.2 10 <- [0x00000000b54e4000 - 0x00000000b54e7fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:14.2 18 <- [0x00000000b54f4000 - 0x00000000b54f4fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:14.3 10 <- [0x00000000b54e8000 - 0x00000000b54ebfff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:15.0 10 <- [0x00000000b54f5000 - 0x00000000b54f5fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:15.1 10 <- [0x00000000b54f6000 - 0x00000000b54f6fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:15.3 10 <- [0x00000000b54f7000 - 0x00000000b54f7fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:16.0 10 <- [0x00000000b54f8000 - 0x00000000b54f8fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio [DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem [DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000b5300000 - 0x00000000b53fffff] size 0x00100000 gran 0x14 seg 00 bumem [DEBUG] PCI: 00:2d:00.0 10 <- [0x00000000b5300000 - 0x00000000b5300fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:2d:00.0 14 <- [0x00000000b5301000 - 0x00000000b53017ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000b54ec000 - 0x00000000b54effff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:1f.3 20 <- [0x0000000099000000 - 0x00000000991fffff] size 0x00200000 gran 0x15 mem64 [DEBUG] PCI: 00:00:1f.4 10 <- [0x00000000b54fa000 - 0x00000000b54fa0ff] size 0x00000100 gran 0x08 mem64 [DEBUG] PCI: 00:00:1f.5 10 <- [0x00000000b54f9000 - 0x00000000b54f9fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:1f.6 10 <- [0x00000000b54a0000 - 0x00000000b54bffff] size 0x00020000 gran 0x11 mem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 4 / 0 ms [INFO ] coreboot skipped calling FSP notify phase: 00000020. [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 subsystem <- 8086/7d01 [DEBUG] PCI: 00:00:00.0 cmd <- 06 [DEBUG] PCI: 00:00:02.0 subsystem <- 8086/7d55 [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:04.0 subsystem <- 8086/7d03 [DEBUG] PCI: 00:00:04.0 cmd <- 02 [DEBUG] PCI: 00:00:06.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:06.0 subsystem <- 8086/7ecb [DEBUG] PCI: 00:00:06.0 cmd <- 106 [DEBUG] PCI: 00:00:07.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:07.0 cmd <- 07 [DEBUG] PCI: 00:00:08.0 subsystem <- 8086/7e4c [DEBUG] PCI: 00:00:08.0 cmd <- 06 [DEBUG] PCI: 00:00:0a.0 subsystem <- 8086/7d0d [DEBUG] PCI: 00:00:0a.0 cmd <- 02 [DEBUG] PCI: 00:00:0b.0 subsystem <- 8086/7d1d [DEBUG] PCI: 00:00:0b.0 cmd <- 02 [DEBUG] PCI: 00:00:0d.0 subsystem <- 8086/7ec0 [DEBUG] PCI: 00:00:0d.0 cmd <- 02 [DEBUG] PCI: 00:00:0d.2 subsystem <- 8086/7ec2 [DEBUG] PCI: 00:00:0d.2 cmd <- 02 [DEBUG] PCI: 00:00:13.3 subsystem <- 8086/7ecf [DEBUG] PCI: 00:00:13.3 cmd <- 02 [DEBUG] PCI: 00:00:14.0 subsystem <- 8086/7e7d [DEBUG] PCI: 00:00:14.0 cmd <- 02 [DEBUG] PCI: 00:00:14.2 subsystem <- 8086/7e7f [DEBUG] PCI: 00:00:14.2 cmd <- 02 [DEBUG] PCI: 00:00:14.3 subsystem <- 8086/7e40 [DEBUG] PCI: 00:00:14.3 cmd <- 02 [DEBUG] PCI: 00:00:15.0 subsystem <- 8086/7e78 [DEBUG] PCI: 00:00:15.0 cmd <- 02 [DEBUG] PCI: 00:00:15.1 subsystem <- 8086/7e79 [DEBUG] PCI: 00:00:15.1 cmd <- 02 [DEBUG] PCI: 00:00:15.3 subsystem <- 8086/7e7b [DEBUG] PCI: 00:00:15.3 cmd <- 02 [DEBUG] PCI: 00:00:16.0 subsystem <- 8086/7e70 [DEBUG] PCI: 00:00:16.0 cmd <- 02 [DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1c.0 subsystem <- 8086/7e3d [DEBUG] PCI: 00:00:1c.0 cmd <- 106 [DEBUG] PCI: 00:00:1e.0 subsystem <- 8086/7e25 [DEBUG] PCI: 00:00:1e.0 cmd <- 06 [DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/7e02 [DEBUG] PCI: 00:00:1f.0 cmd <- 407 [DEBUG] PCI: 00:00:1f.3 subsystem <- 1558/a763 [DEBUG] PCI: 00:00:1f.3 cmd <- 02 [DEBUG] PCI: 00:00:1f.4 subsystem <- 8086/7e22 [DEBUG] PCI: 00:00:1f.4 cmd <- 03 [DEBUG] PCI: 00:00:1f.5 subsystem <- 8086/7e23 [DEBUG] PCI: 00:00:1f.5 cmd <- 406 [DEBUG] PCI: 00:00:1f.6 subsystem <- 8086/550a [DEBUG] PCI: 00:00:1f.6 cmd <- 02 [DEBUG] PCI: 00:01:00.0 cmd <- 02 [DEBUG] PCI: 00:2d:00.0 subsystem <- 1217/8621 [DEBUG] PCI: 00:2d:00.0 cmd <- 06 [INFO ] done. [INFO ] Initializing devices... [DEBUG] PCI: 00:00:00.0 init [INFO ] CPU TDP = 28 Watts [INFO ] CPU PL1 = 35 Watts [INFO ] CPU PL2 = 64 Watts [INFO ] CPU PL4 = 120 Watts [DEBUG] Configured power limits for SA PCI ID: 0x7d01 [DEBUG] PCI: 00:00:00.0 init finished in 0 msecs [DEBUG] PCI: 00:00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1200, size: 9216000 at 0x80800000 [DEBUG] PCI: 00:00:02.0 init finished in 0 msecs [DEBUG] PCI: 00:00:06.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:06.0 init finished in 0 msecs [DEBUG] PCI: 00:00:08.0 init [DEBUG] PCI: 00:00:08.0 init finished in 0 msecs [DEBUG] PCI: 00:00:0a.0 init [DEBUG] PCI: 00:00:0a.0 init finished in 0 msecs [DEBUG] PCI: 00:00:0b.0 init [DEBUG] PCI: 00:00:0b.0 init finished in 0 msecs [DEBUG] PCI: 00:00:13.2 init [DEBUG] PCI: 00:00:13.2 init finished in 0 msecs [DEBUG] PCI: 00:00:13.3 init [DEBUG] PCI: 00:00:13.3 init finished in 0 msecs [DEBUG] PCI: 00:00:14.0 init [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs [DEBUG] PCI: 00:00:14.2 init [DEBUG] PCI: 00:00:14.2 init finished in 0 msecs [DEBUG] PCI: 00:00:15.0 init [DEBUG] I2C bus 0 version 0x3230322a [INFO ] DW I2C bus 0 at 0xb54f5000 (400 KHz) [DEBUG] PCI: 00:00:15.0 init finished in 0 msecs [DEBUG] PCI: 00:00:15.1 init [DEBUG] I2C bus 1 version 0x3230322a [INFO ] DW I2C bus 1 at 0xb54f6000 (400 KHz) [DEBUG] PCI: 00:00:15.1 init finished in 0 msecs [DEBUG] PCI: 00:00:15.3 init [DEBUG] I2C bus 3 version 0x3230322a [INFO ] DW I2C bus 3 at 0xb54f7000 (400 KHz) [DEBUG] PCI: 00:00:15.3 init finished in 0 msecs [DEBUG] PCI: 00:00:16.0 init [DEBUG] PCI: 00:00:16.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1c.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.0 init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x00 [DEBUG] IOAPIC: 120 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x20 [DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.2 init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xb54ec000 [DEBUG] azalia_audio: codec_mask = 01 [DEBUG] azalia_audio: Initializing codec #0 [DEBUG] azalia_audio: codec viddid: 10ec0245 [DEBUG] azalia_audio: verb_size: 160 [DEBUG] azalia_audio: verb loaded. [DEBUG] PCI: 00:00:1f.3 init finished in 10 msecs [DEBUG] PCI: 00:00:1f.4 init [DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs [DEBUG] PCI: 00:00:1f.6 init [DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs [DEBUG] PCI: 00:01:00.0 init [DEBUG] PCI: 00:01:00.0 init finished in 0 msecs [DEBUG] GENERIC: 0.0 init [DEBUG] GENERIC: 0.0 init finished in 0 msecs [DEBUG] GENERIC: 1.0 init [DEBUG] GENERIC: 1.0 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 11 / 0 ms [INFO ] tlcl2_send_startup: Startup return code is 0x0 [DEBUG] TPM: Write digests cached in TPM log to PCR [DEBUG] TPM: Write digest for FMAP: FMAP into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: bootblock into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/romstage into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fspm.bin into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fspm.bin into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/postcar into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fallback/ramstage into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: cpu_microcode_blob.bin into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: fsps.bin into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Write digest for CBFS: vbt.bin into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [INFO ] TPM: setup succeeded [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 56 / 0 ms [INFO ] Finalize devices... [DEBUG] PCI: 00:00:02.0 final [DEBUG] PCI: 00:00:16.0 final [DEBUG] PCI: 00:00:1f.2 final [DEBUG] PCI: 00:00:1f.4 final [DEBUG] PCI: 00:2d:00.0 final [INFO ] PCI: 00:2d:00.0: Re-programmed LTR max latencies using chip-specific quirk [DEBUG] GENERIC: 0.0 final [INFO ] added type-c port0 info to cbmem: usb2:6 usb3:1 sbu:0 data:0 [DEBUG] GENERIC: 1.0 final [INFO ] added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 [INFO ] Devices finalized [DEBUG] ME: HFSTS1 : 0x80022054 [DEBUG] ME: HFSTS2 : 0x32284100 [DEBUG] ME: HFSTS3 : 0x00000020 [DEBUG] ME: HFSTS4 : 0x00000000 [DEBUG] ME: HFSTS5 : 0x02620000 [DEBUG] ME: HFSTS6 : 0x00000000 [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO [DEBUG] ME: FW Partition Table : OK [DEBUG] ME: Bringup Loader Failure : NO [DEBUG] ME: Firmware Init Complete : NO [DEBUG] ME: Boot Options Present : NO [DEBUG] ME: Update In Progress : NO [DEBUG] ME: D0i3 Support : YES [DEBUG] ME: Low Power State Enabled : NO [DEBUG] ME: CPU Replaced : NO [DEBUG] ME: CPU Replacement Valid : YES [DEBUG] ME: Current Working State : 4 [DEBUG] ME: Current Operation State : 1 [DEBUG] ME: Current Operation Mode : 2 [DEBUG] ME: Error Code : 2 [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Enhanced Debug Mode : NO [DEBUG] ME: CPU Debug Disabled : YES [DEBUG] ME: TXT Support : YES [DEBUG] ME: Manufacturing Vars Locked : NO [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x9b0140 size 0x554d in mcache @0x69a4d22c [INFO ] VB2:vb2_digest_init() 21837 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: fallback/dsdt.aml` into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Digest of `CBFS: fallback/dsdt.aml` to PCR 2 measured [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 69815000. [DEBUG] ACPI: * FACS [DEBUG] SCI is IRQ 9, GSI 9 [DEBUG] ACPI: * FACP [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] Found 1 CPU(s) with 16/22 physical/logical core(s) each. [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PSS: 1401MHz power 28000 control 0x3000 status 0x3000 [DEBUG] PSS: 1400MHz power 28000 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 23444 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 19072 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 14900 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 10917 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 7094 control 0x400 status 0x400 [DEBUG] PCI space above 4GB MMIO is at 0x1880000000, len = 0x3e780000000 [WARN ] Unknown min d_state for PCI: 00:04.0 [WARN ] Unknown min d_state for PCI: 00:0a.0 [WARN ] Unknown min d_state for PCI: 00:0b.0 [WARN ] Unknown min d_state for PCI: 00:13.3 [WARN ] Unknown min d_state for PCI: 00:1f.4 [WARN ] Unknown min d_state for PCI: 00:04.0 [WARN ] Unknown min d_state for PCI: 00:0a.0 [WARN ] Unknown min d_state for PCI: 00:0b.0 [WARN ] Unknown min d_state for PCI: 00:13.3 [WARN ] Unknown min d_state for PCI: 00:1f.4 [INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in [INFO ] \_SB.PCI0.PMC: Intel Meteorlake at PCI: 00:00:1f.2 [INFO ] \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:00:06.0 (Intel PCIe Runtime D3) [INFO ] \_SB.PCI0.RP09: Added StorageD3Enable property [INFO ] \_SB.PCI0.TRP0: Intel USB4 PCIe Root Port at PCI: 00:00:07.0 [INFO ] USB Type-C 0 mapped to EC port 0 [WARN ] usb4_retimer_fill_ssdt: No DFP1 power GPIO for GENERIC: 0.0 [INFO ] \_SB.PCI0.TDM0.HR: Intel USB4 Retimer at GENERIC: 0.0 [INFO ] \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0 [INFO ] \_SB.PCI0.I2C0.H038: FocalTech Touchpad at I2C: 00:38 [DEBUG] PPI: Pending OS request: 0xb49a62af (0x8e419d5d) [DEBUG] PPI: OS response: CMD 0x5195c279 = 0xe7765fb0 [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0 [INFO ] \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port 1 (TBT) at USB3 port 0 [INFO ] \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port 2 at USB3 port 1 [INFO ] \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-A Left at USB2 port 0 [INFO ] \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-C Port 2 at USB2 port 1 [INFO ] \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-A Right at USB2 port 2 [INFO ] \_SB.PCI0.XHCI.RHUB.HS06: USB2 Type-C Port 1 (TBT) at USB2 port 5 [INFO ] \_SB.PCI0.XHCI.RHUB.HS07: USB2 Camera at USB2 port 6 [INFO ] \_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9 [INFO ] \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Left at USB3 port 0 [INFO ] \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Right at USB3 port 1 [INFO ] \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0 [INFO ] \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0 [DEBUG] ACPI: * SSDT [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] TPM2 log found at 0x69a4a000 [DEBUG] ACPI: * TPM2 [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] ACPI: * LPIT [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] IOAPIC: 120 interrupts [DEBUG] SCI is IRQ 9, GSI 9 [DEBUG] ACPI: * APIC [DEBUG] ACPI: added table 6/32, length now 84 [DEBUG] cmd_reg from pmc_make_ipc_cmd 1052838 in pmc_cl_discovery [INFO ] PMC crashlog feature is supported. [DEBUG] CL PMC desc table: numb of regions is 0x7 at addr 0xb54e49bc [DEBUG] CL PMC desc table: region 0x0 has size 0x400 at offset 0x9b [DEBUG] CL PMC desc table: region 0x1 has size 0x280 at offset 0xa00 [DEBUG] CL PMC desc table: region 0x2 has size 0xa at offset 0x2bb0 [DEBUG] CL PMC desc table: region 0x3 has size 0x80 at offset 0x3a00 [DEBUG] CL PMC desc table: region 0x4 has size 0x100 at offset 0x500 [DEBUG] CL PMC desc table: region 0x5 has size 0xa at offset 0x12d8 [DEBUG] CL PMC desc table: region 0x6 has size 0x6e at offset 0x1600 [DEBUG] PMC CrashLog size in discovery mode: 0x2208 [DEBUG] adjusted cpu discovery table offset: 0x1f70 [DEBUG] cpu_crashlog_discovery_table buffer count: 0x5 [DEBUG] cpu_crashlog_discovery_table buffer: 0x0 size: 0x800 offset: 0x0 [DEBUG] cpu_crashlog_discovery_table buffer: 0x1 size: 0x800 offset: 0x4000 [DEBUG] PMC crashLog size : 0x2208 [DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400 [DEBUG] Found metadata tag. PMC crashlog size adjusted to: 0x1208 [DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280 [DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa [DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80 [DEBUG] Region[0x4].Tag=0x1 offset=0x500, size=0x100 [DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa [DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e [DEBUG] Invalid data 0xdeadbeef at offset 0x1600 from addr 0xb54e0000 [DEBUG] PMC crashlog size adjusted to: 0x1050 [DEBUG] Region[0x7].Tag=0x0 offset=0x0, size=0x0 [DEBUG] m_cpu_crashLog_size : 0x4000 bytes [DEBUG] CPU crashLog present. [DEBUG] CPU crash data size: 0x4000 bytes in 0x5 region(s). [DEBUG] Invalid data 0xdeadbeef at offset 0x0 from addr 0xb5400000 [DEBUG] CPU crashlog storage_off asserted [DEBUG] CPU crashlog re_arm asserted [DEBUG] crashlog size:pmc-0x1050, cpu-0x0 [DEBUG] crashlog size:pmc-0x1050, cpu-0x0 [DEBUG] crashlog size:pmc-0x1050, cpu-0x0 [DEBUG] ACPI: * BERT [DEBUG] ACPI: added table 7/32, length now 92 [DEBUG] current = 698204e0 [DEBUG] ACPI: * DMAR [DEBUG] soc_fill_dmar - gfxvtbar:0xfc800000 0xfc800001 [DEBUG] ACPI: added table 8/32, length now 100 [DEBUG] ACPI: added table 9/32, length now 108 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 10/32, length now 116 [INFO ] ACPI: done. [DEBUG] ACPI tables: 46656 bytes. [DEBUG] smbios_write_tables: 6980d000 [DEBUG] EC firmware version: 2024-07-17_4ae73b9 [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [INFO ] GENERIC: 0.0 (WIFI Device) [DEBUG] SMBIOS tables: 869 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 65b [DEBUG] Writing coreboot table at 0x69839000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-000000006980cfff: RAM [DEBUG] 4. 000000006980d000-00000000698c5fff: CONFIGURATION TABLES [DEBUG] 5. 00000000698c6000-0000000069a38fff: RAMSTAGE [DEBUG] 6. 0000000069a39000-0000000069ffffff: CONFIGURATION TABLES [DEBUG] 7. 000000006a000000-000000007fffffff: RESERVED [DEBUG] 8. 00000000c0000000-00000000e0ffffff: RESERVED [DEBUG] 9. 00000000f8000000-00000000f9ffffff: RESERVED [DEBUG] 10. 00000000fc800000-00000000fc800fff: RESERVED [DEBUG] 11. 00000000fd800000-00000000fe7fffff: RESERVED [DEBUG] 12. 00000000feb00000-00000000feb7ffff: RESERVED [DEBUG] 13. 00000000fec00000-00000000fecfffff: RESERVED [DEBUG] 14. 00000000fed20000-00000000fed83fff: RESERVED [DEBUG] 15. 00000000feda0000-00000000feda1fff: RESERVED [DEBUG] 16. 00000000fedc0000-00000000feddffff: RESERVED [DEBUG] 17. 00000000ff000000-00000000ffffffff: RESERVED [DEBUG] 18. 0000000100000000-000000187fffffff: RAM [DEBUG] 19. 000003fff0000000-000003ffffffffff: RESERVED [INFO ] Setting up bootsplash in 1920x1200@32 [INFO ] CBFS: Found 'bootsplash.jpg' @0x9a0e00 size 0xf317 in mcache @0x69a4d204 [INFO ] VB2:vb2_digest_init() 62231 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: bootsplash.jpg` into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Digest of `CBFS: bootsplash.jpg` to PCR 2 measured [DEBUG] Bootsplash image resolution: 1024x768 [INFO ] Bootsplash loaded [DEBUG] Wrote coreboot table at: 0x69839000, 0x58c bytes, checksum 7d45 [DEBUG] coreboot table: 1444 bytes. [DEBUG] IMD ROOT 0. 0x69fff000 0x00001000 [DEBUG] IMD SMALL 1. 0x69ffe000 0x00001000 [DEBUG] FSP MEMORY 2. 0x69c4e000 0x003b0000 [DEBUG] CONSOLE 3. 0x69a4e000 0x00200000 [DEBUG] RO MCACHE 4. 0x69a4d000 0x000003ac [DEBUG] TIME STAMP 5. 0x69a4c000 0x00000910 [DEBUG] TPM2 TCGLOG 6. 0x69a4a000 0x000013d8 [DEBUG] MEM INFO 7. 0x69a49000 0x00000f48 [DEBUG] AFTER CAR 8. 0x69a39000 0x00010000 [DEBUG] RAMSTAGE 9. 0x698c5000 0x00174000 [DEBUG] ACPI BERT 10. 0x698b5000 0x00010000 [DEBUG] REFCODE 11. 0x69855000 0x00060000 [DEBUG] SMM BACKUP 12. 0x69845000 0x00010000 [DEBUG] IGD OPREGION13. 0x69841000 0x00003c51 [DEBUG] COREBOOT 14. 0x69839000 0x00008000 [DEBUG] ACPI 15. 0x69815000 0x00024000 [DEBUG] SMBIOS 16. 0x6980d000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x69ffec00 0x00000400 [DEBUG] FSP RUNTIME 1. 0x69ffebe0 0x00000004 [DEBUG] FMAP 2. 0x69ffea80 0x0000015e [DEBUG] POWER STATE 3. 0x69ffea20 0x00000044 [DEBUG] MRC VERSION 4. 0x69ffea00 0x00000004 [DEBUG] ROMSTAGE 5. 0x69ffe9e0 0x00000004 [DEBUG] ROMSTG STCK 6. 0x69ffe920 0x000000a8 [DEBUG] ACPI GNVS 7. 0x69ffe8e0 0x00000040 [DEBUG] TYPE_C INFO 8. 0x69ffe8c0 0x0000000c [DEBUG] TPM PPI 9. 0x69ffe760 0x0000015a [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 411 / 1 ms [INFO ] LAPIC 0x20 in X2APIC mode. [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x0000000069ffffff size 0x69f40000 type 6 [DEBUG] 0x000000006a000000 - 0x000000007fffffff size 0x16000000 type 0 [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1 [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0 [DEBUG] 0x0000000100000000 - 0x000000187fffffff size 0x1780000000 type 6 [DEBUG] 0x000003fff0000000 - 0x000003ffffffffff size 0x10000000 type 0 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x20: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x20 setup mtrr for CPU physical address size: 46 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 8/11. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x000000006a000000 mask 0x00003ffffe000000 type 0 [DEBUG] MTRR: 1 base 0x000000006c000000 mask 0x00003ffffc000000 type 0 [DEBUG] MTRR: 2 base 0x0000000070000000 mask 0x00003ffff0000000 type 0 [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x00003ffff0000000 type 1 [DEBUG] MTRR: 4 base 0x0000000090000000 mask 0x00003ffff0000000 type 0 [DEBUG] MTRR: 5 base 0x00000000a0000000 mask 0x00003fffe0000000 type 0 [DEBUG] MTRR: 6 base 0x00000000c0000000 mask 0x00003fffc0000000 type 0 [DEBUG] MTRR: 7 base 0x000003fff0000000 mask 0x00003ffff0000000 type 0 [INFO ] LAPIC 0xa in X2APIC mode. [INFO ] LAPIC 0x4 in X2APIC mode. [INFO ] LAPIC 0x42 in X2APIC mode. [INFO ] LAPIC 0x0 in X2APIC mode. [INFO ] LAPIC 0x40 in X2APIC mode. [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x259 0x0000000000000000 [INFO ] LAPIC 0x8 in X2APIC mode. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x268 0x0606060606060606 [INFO ] LAPIC 0x11 in X2APIC mode. [INFO ] LAPIC 0x30 in X2APIC mode. [INFO ] LAPIC 0x10 in X2APIC mode. [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x250 0x0606060606060606 [INFO ] LAPIC 0x21 in X2APIC mode. [INFO ] LAPIC 0xe in X2APIC mode. [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x258 0x0606060606060606 [INFO ] LAPIC 0x19 in X2APIC mode. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26e 0x0606060606060606 [INFO ] LAPIC 0xc in X2APIC mode. [INFO ] LAPIC 0x6 in X2APIC mode. [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x40: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x258 0x0606060606060606 [INFO ] LAPIC 0x29 in X2APIC mode. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x40 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x42: MTRR: Fixed MSR 0x26f 0x0606060606060606 [INFO ] LAPIC 0x28 in X2APIC mode. [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x259 0x0000000000000000 [INFO ] LAPIC 0x31 in X2APIC mode. [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x268 0x0606060606060606 [INFO ] LAPIC 0x18 in X2APIC mode. [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x42 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x21: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x8: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x258 0x0606060606060606 [INFO ] LAPIC 0x38 in X2APIC mode. [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x4 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x30: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x11: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x8 setup mtrr for CPU physical address size: 46 bits [INFO ] LAPIC 0x2 in X2APIC mode. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x6 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0xe: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x19: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0xa: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xe setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x21 setup mtrr for CPU physical address size: 46 bits [INFO ] LAPIC 0x39 in X2APIC mode. [DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0xc: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xa setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x28: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0xc setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x38: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x39: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x28 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x29: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x19 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x18: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x30 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x11 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x10: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x18 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x39 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x38 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x10 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x31: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x29 setup mtrr for CPU physical address size: 46 bits [DEBUG] apic_id 0x31 setup mtrr for CPU physical address size: 46 bits [DEBUG] MTRR: TEMPORARY Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x0000000069ffffff size 0x69f40000 type 6 [DEBUG] 0x000000006a000000 - 0x00000000feffffff size 0x95000000 type 0 [DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5 [DEBUG] 0x0000000100000000 - 0x000000187fffffff size 0x1780000000 type 6 [DEBUG] 0x000003fff0000000 - 0x000003ffffffffff size 0x10000000 type 0 [DEBUG] MTRR: Removing WRCOMB type. WB/UC MTRR counts: 12/11 > 10. [DEBUG] MTRR: default type WB/UC MTRR counts: 12/11. [DEBUG] MTRR: UC selected as default type. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x00003fffc0000000 type 6 [DEBUG] MTRR: 1 base 0x0000000040000000 mask 0x00003fffe0000000 type 6 [DEBUG] MTRR: 2 base 0x0000000060000000 mask 0x00003ffff8000000 type 6 [DEBUG] MTRR: 3 base 0x0000000068000000 mask 0x00003ffffe000000 type 6 [DEBUG] MTRR: 4 base 0x00000000ff000000 mask 0x00003fffff000000 type 5 [DEBUG] MTRR: 5 base 0x0000000100000000 mask 0x00003fff00000000 type 6 [DEBUG] MTRR: 6 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 [DEBUG] MTRR: 7 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 [DEBUG] MTRR: 8 base 0x0000000800000000 mask 0x00003ff800000000 type 6 [DEBUG] MTRR: 9 base 0x0000001000000000 mask 0x00003ff800000000 type 6 [ERROR] Not enough MTRRs available! MTRR index is 10 with 10 MTRRs in total. [WARN ] Not enough MTRRs: 11 vs 10 [WARN ] Unable to insert temporary MTRR range: 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5 [DEBUG] MTRR: TEMPORARY Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x0000000069ffffff size 0x69f40000 type 6 [DEBUG] 0x000000006a000000 - 0x00000000f97fffff size 0x8f800000 type 0 [DEBUG] 0x00000000f9800000 - 0x00000000f9ffffff size 0x00800000 type 5 [DEBUG] 0x00000000fa000000 - 0x00000000feffffff size 0x05000000 type 0 [DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5 [DEBUG] 0x0000000100000000 - 0x000000187fffffff size 0x1780000000 type 6 [DEBUG] 0x000003fff0000000 - 0x000003ffffffffff size 0x10000000 type 0 [DEBUG] MTRR: Removing WRCOMB type. WB/UC MTRR counts: 15/12 > 10. [DEBUG] MTRR: default type WB/UC MTRR counts: 15/12. [DEBUG] MTRR: UC selected as default type. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x00003fffc0000000 type 6 [DEBUG] MTRR: 1 base 0x0000000040000000 mask 0x00003fffe0000000 type 6 [DEBUG] MTRR: 2 base 0x0000000060000000 mask 0x00003ffff8000000 type 6 [DEBUG] MTRR: 3 base 0x0000000068000000 mask 0x00003ffffe000000 type 6 [DEBUG] MTRR: 4 base 0x00000000f9800000 mask 0x00003fffff800000 type 5 [DEBUG] MTRR: 5 base 0x00000000ff000000 mask 0x00003fffff000000 type 5 [DEBUG] MTRR: 6 base 0x0000000100000000 mask 0x00003fff00000000 type 6 [DEBUG] MTRR: 7 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 [DEBUG] MTRR: 8 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 [DEBUG] MTRR: 9 base 0x0000000800000000 mask 0x00003ff800000000 type 6 [ERROR] Not enough MTRRs available! MTRR index is 10 with 10 MTRRs in total. [ERROR] Not enough MTRRs available! MTRR index is 11 with 10 MTRRs in total. [WARN ] Not enough MTRRs: 12 vs 10 [WARN ] Unable to insert temporary MTRR range: 0x00000000f9800000 - 0x00000000f9ffffff size 0x00800000 type 5 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 2 / 0 ms [INFO ] CBFS: Found 'fallback/payload' @0x80 size 0x93f61f in mcache @0x69a4d02c [INFO ] VB2:vb2_digest_init() 9696799 bytes, hash algo 2, HW acceleration unsupported [DEBUG] TPM: Extending digest for `CBFS: fallback/payload` into PCR 2 [INFO ] tlcl2_extend: response is 0x0 [DEBUG] TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured [DEBUG] Checking segment from ROM address 0xff0102ac [DEBUG] Checking segment from ROM address 0xff0102c8 [DEBUG] Checking segment from ROM address 0xff0102e4 [DEBUG] Checking segment from ROM address 0xff010300 [DEBUG] Checking segment from ROM address 0xff01031c [DEBUG] Checking segment from ROM address 0xff010338 [DEBUG] Loading segment from ROM address 0xff0102ac [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x00090000 memsize 0x1000 srcaddr 0xff010354 filesize 0x1000 [DEBUG] Loading Segment: addr: 0x00090000 memsz: 0x0000000000001000 filesz: 0x0000000000001000 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff0102c8 [DEBUG] code (compression=0) [DEBUG] New segment dstaddr 0x01000000 memsize 0x302400 srcaddr 0xff011354 filesize 0x302400 [DEBUG] Loading Segment: addr: 0x01000000 memsz: 0x0000000000302400 filesz: 0x0000000000302400 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff0102e4 [DEBUG] code (compression=0) [DEBUG] New segment dstaddr 0x00040000 memsize 0x171 srcaddr 0xff313754 filesize 0x171 [DEBUG] Loading Segment: addr: 0x00040000 memsz: 0x0000000000000171 filesz: 0x0000000000000171 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff010300 [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x00091000 memsize 0x6 srcaddr 0xff3138c5 filesize 0x6 [DEBUG] Loading Segment: addr: 0x00091000 memsz: 0x0000000000000006 filesz: 0x0000000000000006 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff01031c [DEBUG] data (compression=0) [DEBUG] New segment dstaddr 0x04000000 memsize 0x63c000 srcaddr 0xff3138cb filesize 0x63c000 [DEBUG] Loading Segment: addr: 0x04000000 memsz: 0x000000000063c000 filesz: 0x000000000063c000 [DEBUG] it's not compressed! [DEBUG] Loading segment from ROM address 0xff010338 [DEBUG] Entry Point 0x00040000 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 29442 / 0 ms [INFO ] coreboot skipped calling FSP notify phase: 00000040. [INFO ] coreboot skipped calling FSP notify phase: 000000f0. [INFO ] coreboot TPM 2.0 measurements: [INFO ] PCR-2 fc8b189b7018e442718c488d53dc3263c02a9dc60f48470da55e3d18fcdb00c7 SHA256 [FMAP: FMAP] [INFO ] PCR-2 d3105ffaa5242ba3cc29f3dc42cff49fbd5e0547e5395063a09487c966ee8f9b SHA256 [CBFS: bootblock] [INFO ] PCR-2 3a44a5396c520dcce5aa4fb8cd5cc8e342ea960d00594669b796902ced3d9c2a SHA256 [CBFS: fallback/romstage] [INFO ] PCR-2 4caa43d3340b2d83ee451346f964682bd960c242c0d083e30204c7ac51cd7c4f SHA256 [CBFS: fspm.bin] [INFO ] PCR-2 4caa43d3340b2d83ee451346f964682bd960c242c0d083e30204c7ac51cd7c4f SHA256 [CBFS: fspm.bin] [INFO ] PCR-2 639782b69e001920ed536deb69ce6d1843006e5fdb544b35696f5f4ed275d530 SHA256 [CBFS: fallback/postcar] [INFO ] PCR-2 a8baea0174e25660c9ff969f047e2c428c9ba0d4ea4661621a6982408eae6fbc SHA256 [CBFS: fallback/ramstage] [INFO ] PCR-2 36cc5efefd2ac01a25ce3b9ce73875441578749b4ce6ae02f3d370b0efccc199 SHA256 [CBFS: cpu_microcode_blob.bin] [INFO ] PCR-2 bf837755c5a5b44c6858dce685d013a0ee5a21b5265ccc727c066b1618ada664 SHA256 [CBFS: fsps.bin] [INFO ] PCR-2 5af716b41653caaa99f824a56c789305d97ca1fa8b1c73d2bb56145a3f20ae65 SHA256 [CBFS: vbt.bin] [INFO ] PCR-2 66136c5a2be9491c9e37fc6828cc3a0ad4f72e2a81f3396396aa1c4b5d3e3e88 SHA256 [CBFS: fallback/dsdt.aml] [INFO ] PCR-2 e122f99af7d07e6b988571cc05b39674806133c00e563df3a6bc9c195e391700 SHA256 [CBFS: bootsplash.jpg] [INFO ] PCR-2 1739580e2b62661c6aecbf2f8d8e4650fd5650415d5ad17faa2e553adba1309d SHA256 [CBFS: fallback/payload] [INFO ] HECI: coreboot in recovery mode; found CSE in expected Debug Mode state, skipping EOP [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 1 / 0 ms [DEBUG] mp_park_aps done after 0 msecs. [DEBUG] Jumping to boot code at 0x00040000(0x69839000)