From b9948fdc1020df72806e9c19fe7a5929e8b31a7c Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Mon, 29 Jan 2024 22:18:38 -0800 Subject: [PATCH] =?UTF-8?q?>=20generate=20verilog=20=E8=96=9B=E7=AB=8B?= =?UTF-8?q?=E4=BC=9F=20Linux=20tianyi-virtual-machine=206.5.0-15-generic?= =?UTF-8?q?=20#15~22.04.1-Ubuntu=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Jan=201?= =?UTF-8?q?2=2018:54:30=20UTC=202=20x86=5F64=20x86=5F64=20x86=5F64=20GNU/L?= =?UTF-8?q?inux=20=2022:18:38=20up=20=201:43,=20=201=20user,=20=20load=20a?= =?UTF-8?q?verage:=201.08,=201.00,=200.86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/playground/src/Top_Module.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/npc/playground/src/Top_Module.scala b/npc/playground/src/Top_Module.scala index 8833350c1c..b071f6f253 100644 --- a/npc/playground/src/Top_Module.scala +++ b/npc/playground/src/Top_Module.scala @@ -5,11 +5,15 @@ import chisel3._ */ class NVboard_IOs extends Bundle{ val ledr=Output(Vec(16,Bool())) + + def loadDefault():Unit={ + ledr:=0.U.asTypeOf(io.ledr) + } } class Top_Module extends Module { val io=IO(new NVboard_IOs) - io.ledr:=0.U.asTypeOf(io.ledr) + io.loadDefault() io.ledr(0):=true.B io.ledr(1):=false.B