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nobugCPU.map.rpt
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Analysis & Synthesis report for nobugCPU
Tue Jul 06 18:52:34 2021
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. User-Specified and Inferred Latches
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jul 06 18:52:34 2021 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; nobugCPU ;
; Top-level Entity Name ; nobugCPU ;
; Family ; MAX7000S ;
; Total macrocells ; 41 ;
; Total pins ; 44 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; nobugCPU ; nobugCPU ;
; Family name ; MAX7000S ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Auto ; Auto ;
; Ignore SOFT Buffers ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+----------------------------------------------------------------------------+-----------------+---------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; nobugCPU.vhd ; yes ; User VHDL File ; C:/Users/Administrator/Desktop/nobugCPU/nobugCPU.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 41 ;
; Total registers ; 3 ;
; I/O pins ; 44 ;
; Shareable expanders ; 1 ;
; Parallel expanders ; 10 ;
; Maximum fan-out node ; SW[1] ;
; Maximum fan-out ; 40 ;
; Total fan-out ; 422 ;
; Average fan-out ; 4.91 ;
+----------------------+----------------------+
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |nobugCPU ; 41 ; 44 ; |nobugCPU ; work ;
+----------------------------+------------+------+---------------------+--------------+
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; INT ; INT ; yes ;
; Number of user-specified and inferred latches = 1 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Tue Jul 06 18:52:33 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nobugCPU -c nobugCPU
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Found 2 design units, including 1 entities, in source file nobugcpu.vhd
Info: Found design unit 1: nobugCPU-arch
Info: Found entity 1: nobugCPU
Info: Elaborating entity "nobugCPU" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at nobugCPU.vhd(134): inferring latch(es) for signal or variable "INT", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "INT" at nobugCPU.vhd(134)
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clear signal driven by pin "CLR" to global clear signal
Info: Promoted clock signal driven by pin "T3" to global clock signal
Info: Implemented 86 device resources after synthesis - the final resource count might be different
Info: Implemented 16 input pins
Info: Implemented 28 output pins
Info: Implemented 41 macrocells
Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 216 megabytes
Info: Processing ended: Tue Jul 06 18:52:34 2021
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01