diff --git a/nobugCPU-behave.vhd b/nobugCPU-behave.vhd new file mode 100644 index 0000000..9777d36 --- /dev/null +++ b/nobugCPU-behave.vhd @@ -0,0 +1,292 @@ +-- -------------------------------------------------------------------- +-- 本文件名 nobugCPU-behave +-- -------------------------------------------------------------------- +-- 描述 +-- 第四个任务：自选题目三 +-- 数据流描述版本及行为描述版本双版本的基础附加功能实现 +-- -------------------------------------------------------------------- +-- 版本日期 v1.0 2021.7.6 +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 库引用 +-- -------------------------------------------------------------------- +-- library 库名; +-- use 库名,库中程序包,程序包中的项; +-- -------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 实体声明 +-- -------------------------------------------------------------------- +---- 输入in std_logic +-- CLR #CLR +-- Z,C 状态寄存器 +-- -------------------------------------------------------------------- +---- 输入in std_logic_vector +-- IR 指令高四位 +-- SW 操作模式 +-- W 三个节拍 +-- -------------------------------------------------------------------- +---- 输出out std_logic +-- SELCTL, R0~3选择 +-- DRW, R0~3控制 +-- LPC, PCINC, PCADD, PC 控制 +-- LAR, ARINC, AR 控制 +-- STOP, 停机控制 +-- LIR, IR 控制 +-- LDZ, LDC, 状态控制 +-- CIN, M, 运算控制 +-- MEMW, 内存控制 +-- ABUS, SBUS, MBUS, 总线控制 +-- SHORT, LONG, 拍数控制 +-- -------------------------------------------------------------------- +---- 输出out std_logic_vector +-- S 选择ALU、 +-- SEL 选择R和MUX +-- -------------------------------------------------------------------- +entity nobugCPU is + port ( + CLR, + C, Z , + T3, QD: in std_logic; + IR: in std_logic_vector(7 downto 4); + SW , W: in std_logic_vector(3 downto 1); + + SELCTL, + DRW, + LPC, PCINC, PCADD, + LAR, ARINC, + LIR, + LDZ, LDC, + CIN, M, + MEMW, + ABUS, SBUS, MBUS, + STOP, + SHORT, LONG: out std_logic; + S, SEL: out std_logic_vector(3 downto 0) + ); +end nobugCPU; +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 工程体 +-- -------------------------------------------------------------------- +-- 结构体描述方式 +-- 行为描述 behave 使用功能描述，以进程为主 +-- -------------------------------------------------------------------- +---- 结构体的声明 +architecture behave of nobugCPU is +---- 中间信号的声明 + signal ST0, SST0 : std_logic; +begin +-- -------------------------------------------------------------------- +---- 结构体描述语句 +-- -------------------------------------------------------------------- + process (SW, IR, W(1), W(2), W(3), T3 ,CLR, C, Z, ST0, SST0) + begin +-- -------------------------------------------------------------------- +-- 初始化控制信号 + SELCTL <= '0'; + DRW <= '0'; + LPC <= '0'; + PCINC <= '0'; + PCADD <= '0'; + LIR <= '0'; + LAR <= '0'; + ARINC <= '0'; + LDZ <= '0'; + LDC <= '0'; + ABUS <= '0'; + SBUS <= '0'; + MBUS <= '0'; + CIN <= '0'; + M <= '0'; + MEMW <= '0'; + STOP <= '0'; + SHORT <= '0'; + LONG <= '0'; + SST0 <= '0'; + + S <= "0000"; + SEL <= "0000"; + +-- -------------------------------------------------------------------- +-- ST0 状态 + if (clr = '0') then + ST0 <= '0'; + else + if (T3'event and T3 = '0') and SST0 = '1' then + ST0 <= '1'; + end if; + + case SW is +-- -------------------------------------------------------------------- + -- WRITE_MEM + when "001" => + SBUS <= W(1); + STOP <= W(1); + SHORT <= W(1); + SELCTL <= W(1); + SST0 <= W(1); + + LAR <= W(1) and (not ST0); + ARINC <= W(1) and ST0; + MEMW <= W(1) and ST0; +-- -------------------------------------------------------------------- + -- READ_MEM + when "010" => + STOP <= W(1); + SHORT <= W(1); + SELCTL <= W(1); + SST0 <= W(1); + + SBUS <= W(1) and (not ST0); + LAR <= W(1) and (not ST0); + MBUS <= W(1) and ST0; + ARINC <= W(1) and ST0; +-- -------------------------------------------------------------------- + -- READ_REG + when "011" => + SELCTL <= W(1) or W(2); + STOP <= W(1) or W(2); + + SEL(0) <= W(1) or W(2); + SEL(1) <= W(2); + SEL(2) <= '0'; + SEL(3) <= W(2); +-- -------------------------------------------------------------------- + -- WRITE_REG + when "100" => + SELCTL <= W(1) or W(2); + SBUS <= W(1) or W(2); + STOP <= W(1) or W(2); + SST0 <= W(2); + DRW <= W(1) or W(2); + + SEL(3) <= (ST0 and W(1)) or (ST0 and W(2)); + SEL(2) <= W(2); + SEL(1) <= ((not ST0) and W(1)) or (ST0 and W(2)); + SEL(0) <= W(1); + +-- -------------------------------------------------------------------- + -- INS_FETCH + when "000" => +-------------------------------------------------------------------- + -- 用户置入PC的值指定程序初始位置 + if ST0 = '0' then + LPC <= W(1); + SBUS <= W(1); + SST0 <= W(1); + SHORT <= W(1); + STOP <= W(1); + SELCTL <= W(1); +-------------------------------------------------------------------- + -- 执行程序 + else -- ST0='1' + LIR <= W(1); + PCINC <= W(1); + case IR is + when "0001" => -- ADD + S <= W(2) & '0' & '0' & W(2); + CIN <= W(2); + ABUS <= W(2); + DRW <= W(2); + LDZ <= W(2); + LDC <= W(2); + when "0010" => -- SUB + S <= '0' & W(2) & W(2) & '0'; + ABUS <= W(2); + DRW <= W(2); + LDZ <= W(2); + LDC <= W(2); + when "0011" => -- AND + M <= W(2); + S <= W(2) & '0' & W(2) & W(2); + ABUS <= W(2); + DRW <= W(2); + LDZ <= W(2); + when "0100" => -- INC + S <= '0' & '0' & '0' & '0'; + ABUS <= W(2); + DRW <= W(2); + LDZ <= W(2); + LDC <= W(2); + when "0101" => -- LD + M <= W(2); + S <= W(2) & '0' & W(2) & '0' ; + ABUS <= W(2); + LAR <= W(2); + LONG <= W(2); + + DRW <= W(3); + MBUS <= W(3); + when "0110" => -- ST + -- W2 和 W3 的 S 不同 + M <= W(2) or W(3); + S <= ( W(2) or W(3)) & W(2) & ( W(2) or W(3)) & W(2); + ABUS <= W(2) or W(3); + LAR <= W(2); + LONG <= W(2); + + MEMW <= W(3); + when "0111" => -- JC + PCADD <= W(2) and C; + when "1000" => -- JZ + PCADD <= W(2) and Z; + when "1001" => -- JMP + M <= W(2); + S <= W(2) & W(2) & W(2) & W(2); + ABUS <= W(2); + LPC <= W(2); + when "1110" => -- STP + STOP <= W(2); +-- -------------------------扩展功能----------------------------------- + --输出 + when "1010" => -- out + M <= W(2); + S <= W(2) & '0' & W(2) & '0'; + ABUS <= W(2); + --或 + when "1011" => -- or + M <= W(2); + S <= W(2) & W(2) & W(2) & '0'; + ABUS <= W(2); + DRW <= W(2); + LDZ <= W(2); + --比较-- + when "1100" => -- cmp + S <= '0' & W(2) & W(2) & '0'; + ABUS <= W(2); + LDZ <= W(2); + LDC <= W(2); + --移动-- + when "1101" => -- mov + M <= W(2); + S <= W(2) & '0' & W(2) & '0'; + ABUS <= W(2); + DRW <= W(2); + when others => null; -- IR + end case; -- IR + + end if; -- ST0='1' + + when others => null;--SW="000" + end case; -- SW + + end if; -- clr='1' + + end process; +end architecture behave; +-- -------------------------------------------------------------------- + + diff --git a/nobugCPU-behave.vhdl b/nobugCPU-behave.vhdl deleted file mode 100755 index 34eb681..0000000 --- a/nobugCPU-behave.vhdl +++ /dev/null @@ -1,268 +0,0 @@ --- -------------------------------------------------------------------- --- 库引用 --- library 库名; --- use 库名,库中程序包,程序包中的项; --- -------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_signed.all; --- -------------------------------------------------------------------- - - - --- -------------------------------------------------------------------- --- 实体声明 --- -------------------------------------------------------------------- ----- 输入in std_logic --- CLR #CLR --- Z,C 状态寄存器 --- -------------------------------------------------------------------- ----- 输入in std_logic_vector --- IR 指令高四位 --- SW 操作模式 --- W 三个节拍 --- -------------------------------------------------------------------- ----- 输出out std_logic --- SELCTL, R0~3选择 --- DRW, R0~3控制 --- LPC, PCINC, PCADD, PC 控制 --- LAR, ARINC, AR 控制 --- STOP, 停机控制 --- LIR, IR 控制 --- LDZ, LDC, 状态控制 --- CIN, M, 运算控制 --- MEMW, 内存控制 --- ABUS, SBUS, MBUS, 总线控制 --- SHORT, LONG, 拍数控制 --- -------------------------------------------------------------------- ----- 输出out std_logic_vector --- S 选择ALU、 --- SEL 选择R和MUX --- -------------------------------------------------------------------- -entity nobugCPU is - port ( - CLR, - C, Z , - T3, QD: in std_logic; - IR: in std_logic_vector(7 downto 4); - SW , W: in std_logic_vector(3 downto 1); - - SELCTL, - DRW, - LPC, PCINC, PCADD, - LAR, ARINC, - LIR, - LDZ, LDC, - CIN, M, - MEMW, - ABUS, SBUS, MBUS, - STOP, - SHORT, LONG: out std_logic; - S, SEL: out std_logic_vector(3 downto 0) - ); -end nobugCPU; --- -------------------------------------------------------------------- - - - --- -------------------------------------------------------------------- --- 工程体 --- -------------------------------------------------------------------- --- 结构体描述方式 --- 行为描述 behave 进程 --- -------------------------------------------------------------------- ----- 结构体的声明 -architecture behave of nobugCPU is ----- 中间信号的声明 - signal ST0, SST0 : std_logic; -begin ----- 结构体描述语句 - process (SW, IR, W(1), W(2), W(3), T3 ,CLR, C, Z, ST0, SST0) - begin - SELCTL <= '0'; - DRW <= '0'; - LPC <= '0'; - PCINC <= '0'; - PCADD <= '0'; - LIR <= '0'; - LAR <= '0'; - ARINC <= '0'; - LDZ <= '0'; - LDC <= '0'; - ABUS <= '0'; - SBUS <= '0'; - MBUS <= '0'; - CIN <= '0'; - M <= '0'; - MEMW <= '0'; - STOP <= '0'; - SHORT <= '0'; - LONG <= '0'; - SST0 <= '0'; - - S <= "0000"; - SEL <= "0000"; - - - if (clr = '0') then - ST0 <= '0'; - else - if (T3'event and T3 = '0') and SST0 = '1' then - ST0 <= '1'; - end if; - - case SW is - -- WRITE_MEM - when "001" => - SBUS <= W(1); - STOP <= W(1); - SHORT <= W(1); - SELCTL <= W(1); - SST0 <= W(1); - - LAR <= W(1) and (not ST0); - ARINC <= W(1) and ST0; - MEMW <= W(1) and ST0; - -- READ_MEM - when "010" => - STOP <= W(1); - SHORT <= W(1); - SELCTL <= W(1); - SST0 <= W(1); - - SBUS <= W(1) and (not ST0); - LAR <= W(1) and (not ST0); - MBUS <= W(1) and ST0; - ARINC <= W(1) and ST0; - -- READ_REG - when "011" => - SELCTL <= W(1) or W(2); - STOP <= W(1) or W(2); - - SEL(0) <= W(1) or W(2); - SEL(1) <= W(2); - SEL(2) <= '0'; - SEL(3) <= W(2); - -- WRITE_REG - when "100" => - SELCTL <= W(1) or W(2); - SBUS <= W(1) or W(2); - STOP <= W(1) or W(2); - SST0 <= W(2); - DRW <= W(1) or W(2); - - SEL(3) <= (ST0 and W(1)) or (ST0 and W(2)); - SEL(2) <= W(2); - SEL(1) <= ((not ST0) and W(1)) or (ST0 and W(2)); - SEL(0) <= W(1); - - -- INS_FETCH - when "000" => - if ST0 = '0' then - LPC <= W(1); -- 用户指定程序初始位置，为了可以置入PC的值 - SBUS <= W(1); - SST0 <= W(1); - SHORT <= W(1); - STOP <= W(1); - SELCTL <= W(1); - else -- ST0='1' - LIR <= W(1); - PCINC <= W(1); - case IR is - when "0001" => -- ADD - S <= W(2) & '0' & '0' & W(2); - CIN <= W(2); - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - LDC <= W(2); - when "0010" => -- SUB - S <= '0' & W(2) & W(2) & '0'; - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - LDC <= W(2); - when "0011" => -- AND - M <= W(2); - S <= W(2) & '0' & W(2) & W(2); - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - when "0100" => -- INC - S <= '0' & '0' & '0' & '0'; - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - LDC <= W(2); - when "0101" => -- LD - M <= W(2); - S <= W(2) & '0' & W(2) & '0' ; - ABUS <= W(2); - LAR <= W(2); - LONG <= W(2); - - DRW <= W(3); - MBUS <= W(3); - when "0110" => --ST - -- W2 和 W3 的 S 不同 - M <= W(2) or W(3); - S <= ( W(2) or W(3)) & W(2) & ( W(2) or W(3)) & W(2); - ABUS <= W(2) or W(3); - LAR <= W(2); - LONG <= W(2); - - MEMW <= W(3); - when "0111" => --JC - PCADD <= W(2) and C; - when "1000" => --JZ - PCADD <= W(2) and Z; - when "1001" => --JMP - M <= W(2); - S <= W(2) & W(2) & W(2) & W(2); - ABUS <= W(2); - LPC <= W(2); - when "1110" => --STP - STOP <= W(2); --- -------------------------扩展功能----------------------------------- - --输出 - when "1010" => -- out - M <= W(2); - S <= W(2) & '0' & W(2) & '0'; - ABUS <= W(2); - --或 - when "1011" => -- or - M <= W(2); - S <= W(2) & W(2) & W(2) & '0'; - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - --比较-- - when "1100" => -- cmp - M <= '0'; - S <= '0' & W(2) & W(2) & '0'; - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - --移动-- - when "1101" => -- mov - M <= W(2); - S <= W(2) & '0' & W(2) & '0'; - ABUS <= W(2); - DRW <= W(2); - LDZ <= W(2); - when others => null; -- IR - end case; -- IR - - end if; -- ST0='1' - - when others => null;--SW="000" - end case; -- SW - - end if; -- clr='1' - - end process; -end architecture behave; --- -------------------------------------------------------------------- - - diff --git a/nobugCPU-interrupt.vhd b/nobugCPU-interrupt.vhd new file mode 100644 index 0000000..a60e699 --- /dev/null +++ b/nobugCPU-interrupt.vhd @@ -0,0 +1,247 @@ +-- -------------------------------------------------------------------- +-- 本文件名 nobugCPU-pipe +-- -------------------------------------------------------------------- +-- 描述 +-- 第三个任务：自选题目二 +-- 在必选题目基础上，设计实现带有中断功能的硬布线控制器。 +-- -------------------------------------------------------------------- +-- 版本日期 v1.0 2021.7.4 +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 库引用 +-- -------------------------------------------------------------------- +-- library 库名; +-- use 库名,库中程序包,程序包中的项; +-- -------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +-- -------------------------------------------------------------------- + + + + +-- -------------------------------------------------------------------- +-- 实体声明 +-- -------------------------------------------------------------------- +-- port(端口名 : 端口模式 数据类型); +-- 输入模式in : 操作模式，指令 +-- 输出模式out : 控制各个部件信号 +-- -------------------------------------------------------------------- +---- 输入in std_logic +-- CLR #CLR +-- Z,C 状态寄存器 +-- -------------------------------------------------------------------- +---- 输入in std_logic_vector +-- IR 指令高四位 +-- SW 操作模式 +-- W 三个节拍 +-- -------------------------------------------------------------------- +---- 输出out std_logic +-- SELCTL, R0~3选择 +-- DRW, R0~3控制 +-- LPC, PCINC, PCADD, PC 控制 +-- LAR, ARINC, AR 控制 +-- STOP, 停机控制 +-- LIR, IR 控制 +-- LDZ, LDC, 状态控制 +-- CIN, M, 运算控制 +-- MEMW, 内存控制 +-- ABUS, SBUS, MBUS, 总线控制 +-- SHORT, LONG, 拍数控制 +-- -------------------------------------------------------------------- +---- 输出out std_logic_vector +-- S 选择ALU、 +-- SEL 选择R和MUX +-- -------------------------------------------------------------------- +entity nobugCPU is + port( + CLR, T3, C, Z, PULSE, MF: in std_logic; + IR: in std_logic_vector(7 downto 4); + SW, W: in std_logic_vector(3 downto 1); + + SELCTL, + DRW, + LPC, PCINC, PCADD, + LAR, ARINC, + LIR, + LDZ, LDC, + CIN, M, + MEMW, + ABUS, SBUS, MBUS, + STOP, + SHORT, LONG: out std_logic; + S, SEL: out std_logic_vector(3 downto 0); + + AAAA: out std_logic + ); +end nobugCPU; +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 工程体 +-- -------------------------------------------------------------------- +-- 结构体描述方式 +-- 数据流描述 dataflow 使用布尔代数式描述，以门信号赋值操作为主 +-- -------------------------------------------------------------------- +---- 结构体的声明 +architecture arch of nobugCPU is +---- 中间信号的声明 + signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; + signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; + signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; + signal IRET, INT, INTEN, INTDI, EN_INT, ST1: std_logic; +begin +-- -------------------------------------------------------------------- +---- 结构体描述语句 +-- -------------------------------------------------------------------- +-- 操作模式 + WRITE_REG <= '1' when SW = "100" else '0'; + READ_REG <= '1' when SW = "011" else '0'; + INS_FETCH <= '1' when SW = "000" and ST1 = '0' else '0'; + READ_MEM <= '1' when SW = "010" else '0'; + WRITE_MEM <= '1' when SW = "001" else '0'; + +-- -------------------------------------------------------------------- +-- 操作码 + ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; + SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; + AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; + INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; + LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; + ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; + JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; + JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; + JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; + STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; + + NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; + OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; + OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; + CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; + MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; + + IRET <= '1' when IR = "1111" and INS_FETCH = '1' and ST0 = '1' else '0'; + +-- -------------------------------------------------------------------- +-- ST0 状态 + process(CLR, T3, W) + begin + if (CLR = '0') then + ST0 <= '0'; + elsif (T3'event and T3 = '0') then + if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(1) = '1'))) then + ST0 <= '1'; + elsif (ST0 = '1' and (WRITE_REG = '1' and W(2) = '1')) then + ST0 <= '0'; + end if; + end if; + end process; + +-- -------------------------------------------------------------------- +-- ST1 中断状态中标记 + process(CLR, T3, W, INT) + begin + if (CLR = '0') then + ST1 <= '0'; + elsif (T3'event and T3 = '0') then + if (ST1 = '0' and INT = '1' and + (((NOP = '1' or ADD = '1' or SUB = '1' or AND_I = '1' or INC = '1' or JC = '1' or JZ = '1' or JMP = '1' or OUT_I = '1' or + OR_I = '1' or CMP = '1' or MOV = '1' or STP = '1' or IRET = '1')and W(2) = '1') + or ((ST = '1' or LD = '1') and W(3) = '1'))) then + ST1 <= '1'; + elsif (ST1 = '1' and INT = '0' and W(2) = '1') then + ST1 <= '0'; + end if; + end if; + end process; + +-- -------------------------------------------------------------------- +-- 控制信号合成 + SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)) or (ST1 and W(2)); + + SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); + SEL(2) <= (WRITE_REG and W(2)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); + SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)) or (IRET and W(3)); + SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))) or (IRET and W(3)); + + SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT) or (IRET and W(3)); + + DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV or (JMP and EN_INT)) and W(2)) or (LD and W(3)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); + + STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(2)) or (ST1 and W(1)) or (INS_FETCH and not ST0 and W(1)) or (IRET and W(2)); + + LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(2)); + + SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)); + + MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(3)); + + ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; + + MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(3)); + + PCINC <= INS_FETCH and W(1) and ST0; + LIR <= INS_FETCH and W(1) and ST0; + + CIN <= ADD and W(2); + + ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (INS_FETCH and W(1) and ST0 and EN_INT) or (IRET and W(3)); + + LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(2); + LDC <= (ADD or SUB or INC or CMP) and W(2); + + M <= ((AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (IRET and W(3)); + + S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (IRET and W(3)); + --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); + S(2) <= ((SUB or ST) and W(2)) or ((OR_I or CMP) and W(2)); + --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); + S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I or CMP) and W(2)) or (IRET and W(3)); + --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); + S(0) <= (ADD or AND_I or ST) and W(2); + + LPC <= (JMP and W(2)) or (INS_FETCH and not ST0 and W(1)) or (ST1 and W(2)) or (IRET and W(3)); + + LONG <= (ST or LD or IRET) and W(2); + + PCADD <= ((C and JC) or (Z and JZ)) and W(2); + +-- -------------------------------------------------------------------- +-- EN_INT 允许响应中断标记 + process (CLR, INTEN, INTDI, EN_INT, MF) + begin + if CLR = '0' then + EN_INT <= '1'; + elsif MF'event and MF = '1' then + EN_INT <= INTEN or (EN_INT and not INTDI); + end if; + end process; + +-- INT 中断信号 + process (CLR, EN_INT, PULSE) + begin + if CLR = '0' then + INT <= '0'; + end if; + if PULSE = '1' then + INT <= EN_INT; + end if; + if EN_INT = '0' then + INT <= '0'; + end if; + end process; + + INTDI <= ST1 and W(1); + + INTEN <= IRET and W(1); + + AAAA <= EN_INT; + +end architecture arch; +-- -------------------------------------------------------------------- diff --git a/nobugCPU-nopipe.vhd b/nobugCPU-nopipe.vhd old mode 100755 new mode 100644 index 31c00dd..5321306 --- a/nobugCPU-nopipe.vhd +++ b/nobugCPU-nopipe.vhd @@ -1,102 +1,189 @@ +-- -------------------------------------------------------------------- +-- 本文件名 nobugCPU-nopipe +-- -------------------------------------------------------------------- +-- 描述 +-- 第一个任务：必选题目 +-- 基础功能： +-- 按照给定数据格式、指令系统和数据通路，根据所提供的器件要求， +-- 自行设计一个基于硬布线控制器的顺序模型处理机。 +-- 附加功能： +-- 在原指令基础上扩指至少三条。 +-- 允许用户在程序开始时指定PC指针的值。 +-- -------------------------------------------------------------------- +-- 版本日期 v1.0 2021.7.3 +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 库引用 +-- -------------------------------------------------------------------- +-- library 库名; +-- use 库名,库中程序包,程序包中的项; +-- -------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; - +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 实体声明 +-- -------------------------------------------------------------------- +---- 输入in std_logic +-- CLR #CLR +-- Z,C 状态寄存器 +-- -------------------------------------------------------------------- +---- 输入in std_logic_vector +-- IR 指令高四位 +-- SW 操作模式 +-- W 三个节拍 +-- -------------------------------------------------------------------- +---- 输出out std_logic +-- SELCTL, R0~3选择 +-- DRW, R0~3控制 +-- LPC, PCINC, PCADD, PC 控制 +-- LAR, ARINC, AR 控制 +-- STOP, 停机控制 +-- LIR, IR 控制 +-- LDZ, LDC, 状态控制 +-- CIN, M, 运算控制 +-- MEMW, 内存控制 +-- ABUS, SBUS, MBUS, 总线控制 +-- SHORT, LONG, 拍数控制 +-- -------------------------------------------------------------------- +---- 输出out std_logic_vector +-- S 选择ALU、 +-- SEL 选择R和MUX +-- -------------------------------------------------------------------- entity nobugCPU is - port( - CLR, T3, C, Z: in std_logic; - IR: in std_logic_vector(7 downto 4); - SW, W: in std_logic_vector(3 downto 1); - DRW, PCINC, LPC, LAR, PCADD, ARINC, SELCTL, MEMW, STOP, LIR, LDZ, LDC, CIN, M, ABUS, SBUS, MBUS, SHORT, LONG: out std_logic; - S, SEL: out std_logic_vector(3 downto 0) - ); + port( + CLR, T3, C, Z: in std_logic; + IR: in std_logic_vector(7 downto 4); + SW, W: in std_logic_vector(3 downto 1); + + SELCTL, + DRW, + LPC, PCINC, PCADD, + LAR, ARINC, + LIR, + LDZ, LDC, + CIN, M, + MEMW, + ABUS, SBUS, MBUS, + STOP, + SHORT, LONG: out std_logic; + S, SEL: out std_logic_vector(3 downto 0) + ); end nobugCPU; +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 工程体 +-- -------------------------------------------------------------------- +-- 结构体描述方式 +-- 数据流描述 dataflow 使用布尔代数式描述，以门信号赋值操作为主 +-- -------------------------------------------------------------------- +---- 结构体的声明 architecture arch of nobugCPU is - signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; - signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; - signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; +---- 中间信号的声明 + signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; + signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; + signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; begin - WRITE_REG <= '1' when SW = "100" else '0'; - READ_REG <= '1' when SW = "011" else '0'; - INS_FETCH <= '1' when SW = "000" else '0'; - READ_MEM <= '1' when SW = "010" else '0'; - WRITE_MEM <= '1' when SW = "001" else '0'; +---- 结构体描述语句 +-- 操作模式 + WRITE_REG <= '1' when SW = "100" else '0'; + READ_REG <= '1' when SW = "011" else '0'; + INS_FETCH <= '1' when SW = "000" else '0'; + READ_MEM <= '1' when SW = "010" else '0'; + WRITE_MEM <= '1' when SW = "001" else '0'; - ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; - SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; - AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; - INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; - LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; - ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; - JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; - JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; - JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; - STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; +-- 操作码 + ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; + SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; + AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; + INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; + LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; + ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; + JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; + JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; + JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; + STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; - NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; - OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; - OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; - CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; - MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; + NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; + OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; + OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; + CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; + MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; - process(CLR, T3, W) - begin - if (CLR = '0') then - ST0 <= '0'; - elsif (T3'event and T3 = '0') then - if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(1) = '1'))) then - ST0 <= '1'; - end if; - end if; - end process; +-- ST0 状态 + process(CLR, T3, W) + begin + if (CLR = '0') then + ST0 <= '0'; + elsif (T3'event and T3 = '0') then + if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(1) = '1'))) then + ST0 <= '1'; + elsif (ST0 = '1' and (WRITE_REG = '1' and W(2) = '1')) then + ST0 <= '0'; + end if; + end if; + end process; - SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)); +-- 控制信号合成 + SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)); - SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)); - SEL(2) <= (WRITE_REG and W(2)); - SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)); - SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))); + SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)); + SEL(2) <= (WRITE_REG and W(2)); + SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)); + SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))); - SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)); + SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)); - DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV) and W(2)) or (LD and W(3)); + DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV) and W(2)) or (LD and W(3)); - STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(2)) or (INS_FETCH and not ST0 and W(1)); + STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(2)) or (INS_FETCH and not ST0 and W(1)); - LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(2)); + LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(2)); - SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)); + SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)); - MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(3)); + MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(3)); - ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; + ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; - MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(3)); + MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(3)); - PCINC <= INS_FETCH and W(1) and ST0; - LIR <= INS_FETCH and W(1) and ST0; + PCINC <= INS_FETCH and W(1) and ST0; + LIR <= INS_FETCH and W(1) and ST0; - CIN <= ADD and W(2); + CIN <= ADD and W(2); - ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); + ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); - LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(2); - LDC <= (ADD or SUB or INC or CMP) and W(2); + LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(2); + LDC <= (ADD or SUB or INC or CMP) and W(2); - M <= ((AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); + M <= ((AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); - S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); - --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); - S(2) <= ((SUB or ST or JMP) and W(2)) or ((OR_I or CMP) and W(2)); - --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); - S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I or CMP) and W(2)); - --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); - S(0) <= (ADD or AND_I or ST or JMP) and W(2); + S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)); + --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); + S(2) <= ((SUB or ST or JMP) and W(2)) or ((OR_I or CMP) and W(2)); + --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); + S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I or CMP) and W(2)); + --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); + S(0) <= (ADD or AND_I or ST or JMP) and W(2); - LPC <= (JMP and W(2)) or (INS_FETCH and not ST0 and W(1)); + LPC <= (JMP and W(2)) or (INS_FETCH and not ST0 and W(1)); - LONG <= (ST or LD) and W(2); + LONG <= (ST or LD) and W(2); - PCADD <= ((C and JC) or (Z and JZ)) and W(2); + PCADD <= ((C and JC) or (Z and JZ)) and W(2); end architecture arch; +-- -------------------------------------------------------------------- + diff --git a/nobugCPU-pipe.vhd b/nobugCPU-pipe.vhd old mode 100755 new mode 100644 index 0f96ec0..63f591d --- a/nobugCPU-pipe.vhd +++ b/nobugCPU-pipe.vhd @@ -1,107 +1,204 @@ +-- -------------------------------------------------------------------- +-- 本文件名 nobugCPU-pipe +-- -------------------------------------------------------------------- +-- 描述 +-- 第二个任务：自选题目一 +-- 在必选题目基础上，完成流水硬连线控制器的设计根据设计方案， +-- 在TEC-8上进行组装、调试运行 。 +-- -------------------------------------------------------------------- +-- 版本日期 v1.0 2021.7.4 +-- -------------------------------------------------------------------- + + + +-- -------------------------------------------------------------------- +-- 库引用 +-- -------------------------------------------------------------------- +-- library 库名; +-- use 库名,库中程序包,程序包中的项; +-- -------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; - +-- -------------------------------------------------------------------- + + + + +-- -------------------------------------------------------------------- +-- 实体声明 +-- -------------------------------------------------------------------- +-- port(端口名 : 端口模式 数据类型); +-- 输入模式in : 操作模式，指令 +-- 输出模式out : 控制各个部件信号 +-- -------------------------------------------------------------------- +---- 输入in std_logic +-- CLR #CLR +-- Z,C 状态寄存器 +-- -------------------------------------------------------------------- +---- 输入in std_logic_vector +-- IR 指令高四位 +-- SW 操作模式 +-- W 三个节拍 +-- -------------------------------------------------------------------- +---- 输出out std_logic +-- SELCTL, R0~3选择 +-- DRW, R0~3控制 +-- LPC, PCINC, PCADD, PC 控制 +-- LAR, ARINC, AR 控制 +-- STOP, 停机控制 +-- LIR, IR 控制 +-- LDZ, LDC, 状态控制 +-- CIN, M, 运算控制 +-- MEMW, 内存控制 +-- ABUS, SBUS, MBUS, 总线控制 +-- SHORT, LONG, 拍数控制 +-- -------------------------------------------------------------------- +---- 输出out std_logic_vector +-- S 选择ALU、 +-- SEL 选择R和MUX +-- -------------------------------------------------------------------- entity nobugCPU is - port( - CLR, T3, C, Z: in std_logic; - IR: in std_logic_vector(7 downto 4); - SW, W: in std_logic_vector(3 downto 1); - DRW, PCINC, LPC, LAR, PCADD, ARINC, SELCTL, MEMW, STOP, LIR, LDZ, LDC, CIN, M, ABUS, SBUS, MBUS, SHORT, LONG: out std_logic; - S, SEL: out std_logic_vector(3 downto 0) - ); + port( + CLR, T3, C, Z: in std_logic; + IR: in std_logic_vector(7 downto 4); + SW, W: in std_logic_vector(3 downto 1); + + SELCTL, + DRW, + LPC, PCINC, PCADD, + LAR, ARINC, + LIR, + LDZ, LDC, + CIN, M, + MEMW, + ABUS, SBUS, MBUS, + STOP, + SHORT, LONG: out std_logic; + S, SEL: out std_logic_vector(3 downto 0) + ); end nobugCPU; +-- -------------------------------------------------------------------- -architecture arch of nobugCPU is - signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; - signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; - signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; -begin - WRITE_REG <= '1' when SW = "100" else '0'; - READ_REG <= '1' when SW = "011" else '0'; - INS_FETCH <= '1' when SW = "000" else '0'; - READ_MEM <= '1' when SW = "010" else '0'; - WRITE_MEM <= '1' when SW = "001" else '0'; - - ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; - SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; - AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; - INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; - LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; - ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; - JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; - JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; - JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; - STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; - - NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; - OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; - OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; - CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; - MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; - - process(CLR, T3, W) - begin - if (CLR = '0') then - ST0 <= '0'; - elsif (T3'event and T3 = '0') then - if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(2) = '1'))) then - ST0 <= '1'; - end if; - end if; - end process; - - process(T3, W) - begin - if (T3'event and T3 = '1') then - PCINC <= (INS_FETCH and not ST0 and W(2)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)) or ((LD or ST or (JC and C) or (JZ and Z) or JMP) and W(2)); - LIR <= (INS_FETCH and not ST0 and W(2)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)) or ((LD or ST or (JC and C) or (JZ and Z) or JMP) and W(2)); - end if; - end process; - - SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)); - - SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)); - SEL(2) <= (WRITE_REG and W(2)); - SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)); - SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))); - - SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)); - - DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV) and W(1)) or (LD and W(2)); - STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(1)) or (INS_FETCH and not ST0 and W(1)); - LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(1)); - SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)); - MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(2)); - ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; - - MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(2)); - - CIN <= ADD and W(1); - - ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); - - LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(1); - LDC <= (ADD or SUB or INC or CMP) and W(1); - - M <= ((AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); - - S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); - --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); - S(2) <= ((SUB or ST or JMP) and W(1)) or ((OR_I or CMP) and W(1)); - --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); - S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I or CMP) and W(1)); - --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); - S(0) <= (ADD or AND_I or ST or JMP) and W(1); - - LPC <= (JMP and W(1)) or (INS_FETCH and not ST0 and W(1)); - - LONG <= '0'; - - PCADD <= ((C and JC) or (Z and JZ)) and W(1); +-- -------------------------------------------------------------------- +-- 工程体 +-- -------------------------------------------------------------------- +-- 结构体描述方式 +-- 数据流描述 dataflow 使用布尔代数式描述，以门信号赋值操作为主 +-- -------------------------------------------------------------------- +---- 结构体的声明 +architecture arch of nobugCPU is +---- 中间信号的声明 + signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; + signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; + signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; +begin +-- -------------------------------------------------------------------- +---- 结构体描述语句 +-- -------------------------------------------------------------------- +-- 操作模式 + WRITE_REG <= '1' when SW = "100" else '0'; + READ_REG <= '1' when SW = "011" else '0'; + INS_FETCH <= '1' when SW = "000" else '0'; + READ_MEM <= '1' when SW = "010" else '0'; + WRITE_MEM <= '1' when SW = "001" else '0'; + +-- -------------------------------------------------------------------- +-- 操作码 + ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; + SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; + AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; + INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; + LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; + ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; + JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; + JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; + JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; + STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; + + NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; + OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; + OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; + CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; + MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; + +-- -------------------------------------------------------------------- +-- ST0 状态 + process(CLR, T3, W) + begin + if (CLR = '0') then + ST0 <= '0'; + elsif (T3'event and T3 = '0') then + if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(2) = '1'))) then + ST0 <= '1'; + elsif (ST0 = '1' and (WRITE_REG = '1' and W(2) = '1')) then + ST0 <= '0'; + end if; + end if; + end process; + +-- -------------------------------------------------------------------- +-- PCINC LIR， T3上升执行 + process(T3, W) + begin + if (T3'event and T3 = '1') then + PCINC <= (INS_FETCH and not ST0 and W(2)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)) or ((LD or ST or (JC and C) or (JZ and Z) or JMP) and W(2)); + LIR <= (INS_FETCH and not ST0 and W(2)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)) or ((LD or ST or (JC and C) or (JZ and Z) or JMP) and W(2)); + end if; + end process; + + +-- -------------------------------------------------------------------- +-- 控制信号合成 + SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)); + + SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)); + SEL(2) <= (WRITE_REG and W(2)); + SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)); + SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))); + + SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)); + + DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV) and W(1)) or (LD and W(2)); + + STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(1)) or (INS_FETCH and not ST0 and W(1)); + + LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(1)); + + SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or ((NOP or ADD or SUB or AND_I or INC or (JC and not C) or (JZ and not Z) or OUT_I or OR_I or CMP or MOV) and W(1)); + + MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(2)); + + ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; + + MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(2)); + + CIN <= ADD and W(1); + + ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); + + LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(1); + LDC <= (ADD or SUB or INC or CMP) and W(1); + + M <= ((AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); + + S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I) and W(1)); + --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); + S(2) <= ((SUB or ST or JMP) and W(1)) or ((OR_I or CMP) and W(1)); + --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); + S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(1)) or (ST and W(2)) or ((OR_I or MOV or OUT_I or CMP) and W(1)); + --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); + S(0) <= (ADD or AND_I or ST or JMP) and W(1); + + LPC <= (JMP and W(1)) or (INS_FETCH and not ST0 and W(1)); + + LONG <= '0'; + + PCADD <= ((C and JC) or (Z and JZ)) and W(1); end architecture arch; +-- -------------------------------------------------------------------- diff --git a/nobugCPU.vhd b/nobugCPU.vhd deleted file mode 100755 index 9f3aec2..0000000 --- a/nobugCPU.vhd +++ /dev/null @@ -1,153 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity nobugCPU is - port( - CLR, T3, C, Z, PULSE, MF: in std_logic; - IR: in std_logic_vector(7 downto 4); - SW, W: in std_logic_vector(3 downto 1); - DRW, PCINC, LPC, LAR, PCADD, ARINC, SELCTL, MEMW, STOP, LIR, LDZ, LDC, CIN, M, ABUS, SBUS, MBUS, SHORT, LONG: out std_logic; - S, SEL: out std_logic_vector(3 downto 0); - AAAA: out std_logic - ); -end nobugCPU; - -architecture arch of nobugCPU is - signal WRITE_REG, READ_REG, INS_FETCH, WRITE_MEM, READ_MEM, ST0: std_logic; - signal ADD, SUB, AND_I, INC, LD, ST, JC, JZ, JMP, STP: std_logic; - signal NOP, OUT_I, OR_I, CMP, MOV: std_logic; - signal IRET, INT, INTEN, INTDI, EN_INT, ST1: std_logic; -begin - WRITE_REG <= '1' when SW = "100" else '0'; - READ_REG <= '1' when SW = "011" else '0'; - INS_FETCH <= '1' when SW = "000" and ST1 = '0' else '0'; - READ_MEM <= '1' when SW = "010" else '0'; - WRITE_MEM <= '1' when SW = "001" else '0'; - - ADD <= '1' when IR = "0001" and INS_FETCH = '1' and ST0 = '1' else '0'; - SUB <= '1' when IR = "0010" and INS_FETCH = '1' and ST0 = '1' else '0'; - AND_I <= '1' when IR = "0011" and INS_FETCH = '1' and ST0 = '1' else '0'; - INC <= '1' when IR = "0100" and INS_FETCH = '1' and ST0 = '1' else '0'; - LD <= '1' when IR = "0101" and INS_FETCH = '1' and ST0 = '1' else '0'; - ST <= '1' when IR = "0110" and INS_FETCH = '1' and ST0 = '1' else '0'; - JC <= '1' when IR = "0111" and INS_FETCH = '1' and ST0 = '1' else '0'; - JZ <= '1' when IR = "1000" and INS_FETCH = '1' and ST0 = '1' else '0'; - JMP <= '1' when IR = "1001" and INS_FETCH = '1' and ST0 = '1' else '0'; - STP <= '1' when IR = "1110" and INS_FETCH = '1' and ST0 = '1' else '0'; - - NOP <= '1' when IR = "0000" and INS_FETCH = '1' and ST0 = '1' else '0'; - OUT_I <= '1' when IR = "1010" and INS_FETCH = '1' and ST0 = '1' else '0'; - OR_I <= '1' when IR = "1011" and INS_FETCH = '1' and ST0 = '1' else '0'; - CMP <= '1' when IR = "1100" and INS_FETCH = '1' and ST0 = '1' else '0'; - MOV <= '1' when IR = "1101" and INS_FETCH = '1' and ST0 = '1' else '0'; - - IRET <= '1' when IR = "1111" and INS_FETCH = '1' and ST0 = '1' else '0'; - - process(CLR, T3, W) - begin - if (CLR = '0') then - ST0 <= '0'; - elsif (T3'event and T3 = '0') then - if (ST0 = '0' and ((WRITE_REG = '1' and W(2) = '1') or (READ_MEM = '1' and W(1) = '1') or (WRITE_MEM = '1' and W(1) = '1') or (INS_FETCH = '1' and W(1) = '1'))) then - ST0 <= '1'; - elsif (ST0 = '1' and (WRITE_REG = '1' and W(2) = '1')) then - ST0 <= '0'; - end if; - end if; - end process; - - process(CLR, T3, W, INT) - begin - if (CLR = '0') then - ST1 <= '0'; - elsif (T3'event and T3 = '0') then - if (ST1 = '0' and INT = '1' and - (((NOP = '1' or ADD = '1' or SUB = '1' or AND_I = '1' or INC = '1' or JC = '1' or JZ = '1' or JMP = '1' or OUT_I = '1' or - OR_I = '1' or CMP = '1' or MOV = '1' or STP = '1' or IRET = '1')and W(2) = '1') - or ((ST = '1' or LD = '1') and W(3) = '1'))) then - ST1 <= '1'; - elsif (ST1 = '1' and INT = '0' and W(2) = '1') then - ST1 <= '0'; - end if; - end if; - end process; - - SBUS <= ((WRITE_REG or (READ_MEM and not ST0) or WRITE_MEM or (INS_FETCH and not ST0)) and W(1)) or (WRITE_REG and W(2)) or (ST1 and W(2)); - - SEL(3) <= (WRITE_REG and (W(1) or W(2)) and ST0) or (READ_REG and W(2)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); - SEL(2) <= (WRITE_REG and W(2)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); - SEL(1) <= (WRITE_REG and ((W(1) and not ST0) or (W(2) and ST0))) or (READ_REG and W(2)) or (IRET and W(3)); - SEL(0) <= (WRITE_REG and W(1)) or (READ_REG and (W(1) or W(2))) or (IRET and W(3)); - - SELCTL <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT) or (IRET and W(3)); - - DRW <= (WRITE_REG and (W(1) or W(2))) or ((ADD or SUB or AND_I or INC or OR_I or MOV or (JMP and EN_INT)) and W(2)) or (LD and W(3)) or (INS_FETCH and not ST0 and W(1)) or (INS_FETCH and W(1) and ST0 and EN_INT); - - STOP <= ((WRITE_REG or READ_REG) and (W(1) or W(2))) or ((READ_MEM or WRITE_MEM) and W(1)) or (STP and W(2)) or (ST1 and W(1)) or (INS_FETCH and not ST0 and W(1)) or (IRET and W(2)); - - LAR <= ((READ_MEM or WRITE_MEM) and W(1) and not ST0) or ((ST or LD) and W(2)); - - SHORT <= ((READ_MEM or WRITE_MEM) and W(1)) or (INS_FETCH and not ST0 and W(1)); - - MBUS <= (READ_MEM and W(1) and ST0) or (LD and W(3)); - - ARINC <= (WRITE_MEM or READ_MEM) and W(1) and ST0; - - MEMW <= (WRITE_MEM and W(1) and ST0) or (ST and W(3)); - - PCINC <= INS_FETCH and W(1) and ST0; - LIR <= INS_FETCH and W(1) and ST0; - - CIN <= ADD and W(2); - - ABUS <= ((ADD or SUB or AND_I or INC or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (INS_FETCH and W(1) and ST0 and EN_INT) or (IRET and W(3)); - - LDZ <= (ADD or SUB or AND_I or INC or OR_I or CMP) and W(2); - LDC <= (ADD or SUB or INC or CMP) and W(2); - - M <= ((AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (IRET and W(3)); - - S(3) <= ((ADD or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I) and W(2)) or (IRET and W(3)); - --S(3) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and ADD) or (W(2) and AND_I) or (W(2) and LD); - S(2) <= ((SUB or ST) and W(2)) or ((OR_I or CMP) and W(2)); - --S(2) <= (W(2) and (ST or JMP)) or (W(2) and SUB); - S(1) <= ((SUB or AND_I or LD or ST or JMP) and W(2)) or (ST and W(3)) or ((OR_I or MOV or OUT_I or CMP) and W(2)) or (IRET and W(3)); - --S(1) <= ((W(2) or W(3)) and ST) or (W(2) and JMP) or (W(2) and SUB) or (W(2) and AND_I) or (W(2) and LD); - S(0) <= (ADD or AND_I or ST) and W(2); - - LPC <= (JMP and W(2)) or (INS_FETCH and not ST0 and W(1)) or (ST1 and W(2)) or (IRET and W(3)); - - LONG <= (ST or LD or IRET) and W(2); - - PCADD <= ((C and JC) or (Z and JZ)) and W(2); - - process (CLR, INTEN, INTDI, EN_INT, MF) - begin - if CLR = '0' then - EN_INT <= '1'; - elsif MF'event and MF = '1' then - EN_INT <= INTEN or (EN_INT and not INTDI); - end if; - end process; - - process (CLR, EN_INT, PULSE) - begin - if CLR = '0' then - INT <= '0'; - end if; - if PULSE = '1' then - INT <= EN_INT; - end if; - if EN_INT = '0' then - INT <= '0'; - end if; - end process; - - INTDI <= ST1 and W(1); - - INTEN <= IRET and W(1); - - AAAA <= EN_INT; - -end architecture arch;