From f6e2cb9b84c9ea54e56f7e1490070838800db06e Mon Sep 17 00:00:00 2001 From: Jay Vasanth Date: Fri, 30 Sep 2022 17:12:39 -0400 Subject: [PATCH] drivers: uart: microchip: add support for mec15xx update uart mchp xec driver to support mec15xx and add pinctrl support for mec15xx uart Signed-off-by: Jay Vasanth --- .../mec1501modular_assy6885.dts | 2 + .../mec15xxevb_assy6853.dts | 2 + drivers/serial/uart_mchp_xec.c | 66 +++++++++++++++---- dts/arm/microchip/mec1501hsz.dtsi | 18 +++-- 4 files changed, 71 insertions(+), 17 deletions(-) diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts index 872cc8657035..33f6dc06d300 100644 --- a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts +++ b/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts @@ -52,6 +52,8 @@ &uart1 { status = "okay"; current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; }; &adc0 { diff --git a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index d7a67f353ab1..1ac1439bdc52 100644 --- a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -80,6 +80,8 @@ &uart2 { status = "okay"; current-speed = <115200>; + pinctrl-0 = <&uart2_tx_gpio146 &uart2_rx_gpio145>; + pinctrl-names = "default"; }; &adc0 { diff --git a/drivers/serial/uart_mchp_xec.c b/drivers/serial/uart_mchp_xec.c index 8a7b74eea8f7..bc7859aad443 100644 --- a/drivers/serial/uart_mchp_xec.c +++ b/drivers/serial/uart_mchp_xec.c @@ -24,16 +24,15 @@ #include #include #include +#ifdef CONFIG_SOC_SERIES_MEC172X #include #include +#endif #include #include #include #include -BUILD_ASSERT(IS_ENABLED(CONFIG_SOC_SERIES_MEC172X), - "XEC UART driver only support MEC172x at this time"); - /* Clock source is 1.8432 MHz derived from PLL 48 MHz */ #define XEC_UART_CLK_SRC_1P8M 0 /* Clock source is PLL 48 MHz output */ @@ -195,6 +194,56 @@ struct uart_xec_dev_data { static const struct uart_driver_api uart_xec_driver_api; +#ifdef CONFIG_SOC_SERIES_MEC172X + +static void uart_clr_slp_en(const struct device *dev) +{ + struct uart_xec_device_config const *dev_cfg = dev->config; + + z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, dev_cfg->pcr_bitpos, 0); +} + +static inline void uart_xec_girq_clr(const struct device *dev) +{ + struct uart_xec_device_config const *dev_cfg = dev->config; + + mchp_soc_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos); +} + +static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn) +{ + mchp_xec_ecia_girq_src_en(girq_idx, girq_posn); +} + +#else + +static void uart_clr_slp_en(const struct device *dev) +{ + struct uart_xec_device_config const *dev_cfg = dev->config; + + if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART0_POS) { + mchp_pcr_periph_slp_ctrl(PCR_UART0, 0); + } else if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART1_POS) { + mchp_pcr_periph_slp_ctrl(PCR_UART1, 0); + } else { + mchp_pcr_periph_slp_ctrl(PCR_UART2, 0); + } +} + +static inline void uart_xec_girq_clr(const struct device *dev) +{ + struct uart_xec_device_config const *dev_cfg = dev->config; + + MCHP_GIRQ_SRC(dev_cfg->girq_id) = BIT(dev_cfg->girq_pos); +} + +static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn) +{ + MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn); +} + +#endif + static void set_baud_rate(const struct device *dev, uint32_t baud_rate) { const struct uart_xec_device_config * const dev_cfg = dev->config; @@ -363,11 +412,7 @@ static int uart_xec_init(const struct device *dev) struct uart_xec_dev_data *dev_data = dev->data; int ret; - ret = z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, - dev_cfg->pcr_bitpos, 0); - if (ret != 0) { - return ret; - } + uart_clr_slp_en(dev); ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); if (ret != 0) { @@ -750,7 +795,6 @@ static void uart_xec_irq_callback_set(const struct device *dev, */ static void uart_xec_isr(const struct device *dev) { - const struct uart_xec_device_config * const dev_cfg = dev->config; struct uart_xec_dev_data * const dev_data = dev->data; if (dev_data->cb) { @@ -758,7 +802,7 @@ static void uart_xec_isr(const struct device *dev) } /* clear ECIA GIRQ R/W1C status bit after UART status cleared */ - mchp_xec_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos); + uart_xec_girq_clr(dev); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -862,7 +906,7 @@ static const struct uart_driver_api uart_xec_driver_api = { uart_xec_isr, DEVICE_DT_INST_GET(n), \ 0); \ irq_enable(DT_INST_IRQN(n)); \ - mchp_xec_ecia_girq_src_en(DT_INST_PROP_BY_IDX(n, girqs, 0), \ + uart_xec_girq_en(DT_INST_PROP_BY_IDX(n, girqs, 0), \ DT_INST_PROP_BY_IDX(n, girqs, 1)); \ } #else diff --git a/dts/arm/microchip/mec1501hsz.dtsi b/dts/arm/microchip/mec1501hsz.dtsi index 85d02eb49455..16e6e63194ec 100644 --- a/dts/arm/microchip/mec1501hsz.dtsi +++ b/dts/arm/microchip/mec1501hsz.dtsi @@ -162,30 +162,36 @@ pcrs = <1 9>; }; uart0: uart@400f2400 { - compatible = "ns16550"; + compatible = "microchip,xec-uart"; reg = <0x400f2400 0x400>; interrupts = <40 0>; clock-frequency = <1843200>; current-speed = <38400>; - reg-shift = <0>; + girqs = <15 0>; + pcrs = <2 1>; + ldn = <9>; status = "disabled"; }; uart1: uart@400f2800 { - compatible = "ns16550"; + compatible = "microchip,xec-uart"; reg = <0x400f2800 0x400>; interrupts = <41 0>; clock-frequency = <1843200>; current-speed = <38400>; - reg-shift = <0>; + girqs = <15 1>; + pcrs = <2 2>; + ldn = <10>; status = "disabled"; }; uart2: uart@400f2c00 { - compatible = "ns16550"; + compatible = "microchip,xec-uart"; reg = <0x400f2c00 0x400>; interrupts = <44 0>; clock-frequency = <1843200>; current-speed = <38400>; - reg-shift = <0>; + girqs = <15 4>; + pcrs = <2 28>; + ldn = <11>; status = "disabled"; };