How to configure CS for LPSPI peripheral on NXP MIMXRT106x

[asteriskSF]

zephyr 3.5.0
mimxrt1062 evkb

I soldered resistor to enable the arduino_spi interface.
I added my spi peripheral into the dts:

pinmux_lpspi1: pinmux_lpspi1 {
	group0 {
		pinmux = <&iomuxc_gpio_sd_b0_01_lpspi1_pcs0>,
			<&iomuxc_gpio_sd_b0_00_lpspi1_sck>,
			<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
			<&iomuxc_gpio_sd_b0_02_lpspi1_sdo>;
		drive-strength = "r0-6";
		slew-rate = "slow";
		nxp,speed = "100-mhz";
	};
};

arduino_spi: &lpspi1 {
	status = "okay";
	/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
	dmas = <&edma0 0 13>, <&edma0 1 14>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&pinmux_lpspi1>;
	pinctrl-names = "default";
	/* TODO ?? cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; */
	bgt60tr13c: bgt60tr13c@0 {
		compatible = "infineon,bgt60tr13c";
		spi-max-frequency = <50000000>;
		status = "okay";
		reg = <0>;
     	irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
     	reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
	};
};

During testing I find:

• CS is not toggling..
• SCK is running at 16 MHz not the 50MHz specified

I found a zephyr issue indicating the built-in PCS handling is buggy: #16544

Considering the recommended workaround is to use GPIO CS.

1. How should I set the pinctrl PCS pin in pinmux_lpspi?
2. Do I need an independent pin ctrl for the GPIO to select the iomux as a gpio instead of PCS?
3. Any examples available of using the lpspi in zephyr?
4. What is the maximum bit rate I can expect?
5. Does the DMA mode work?

[asteriskSF]

I have a bit more data on the SPI clock speed. It turns out the default config from zephyr sets the LPSPI peripheral to run off USB1 PLL PFD0 (which is configured for 251 MHz) divided by 8. Because it was running below 32 MHz it was unable to generate a clock faster than 16 MHz.

I modified soc_rt10xx.c in the zephyr to configure PFD1 as 480*18/29 and then divided by 3 to achieve ~100 MHz.

This requires modifying settings in an SDK file. Is there a clean way I can override these settings?

[mariopaja]

@asteriskSF

What I ended up doing on RT1064 to test out the SPI with W5500 ethernet module was commenting out <&iomuxc_gpio_sd_b0_01_lpspi1_pcs0>, and then using cs-gpios = <&gpioX X GPIO_ACTIVE_LOW>.

In this way I was able to make it work. with W5500. However, this did not work out with LAN865x.

Could you send me the modified soc_rt10xx.c?

[asteriskSF]

I have been able to get the cs-gpios to work with an I/O that wasn't in the pin configuration. I'll try your suggestion of commenting the PCS pin.

The way pinctrl and muxing is implemented seems to me a complete mystery. I found "modules/hal/nxp/dts/nxp/nxp_imx/rt/mimxrt1062dvl6b-pinctrl.dtsi but not really sure how it all works beyond there. When I made the cs-gpios for the lpspi1 pcs I referenced the pinctrl to determine it should be either gpio3 io13 or gpio8 io13. I suppose that is explained somewhere in the reference manual.

        /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 {
                pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>;
                gpr = <0x400ac070 0xd 0x0>;
        };
        /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 {
                pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>;
                gpr = <0x400ac070 0xd 0x1>;
        };

I put this in my board pinctrl

	cs-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;

But maybe I should be doing something like this:

cs-gpios = <&iomuxc_gpio_sd_b0_01_gpio3_io13>;

BTW, the changes to soc_rt10xx.c were:

#ifdef CONFIG_SPI_MCUX_LPSPI
	CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 29U); /* Set PFD1 to 480*18/29 */
	CLOCK_SetMux(kCLOCK_LpspiMux, 0); /* Set SPI source to USB1 PFD1 */
	CLOCK_SetDiv(kCLOCK_LpspiDiv, 2); /* Set SPI divider to divide 1 */
#endif

its a shame NXP doesn't provide enumerations for the CLOCK_SetMux register values, I hate having "magic numbers" in the code, or maybe they do and I haven't found them yet!

[asteriskSF]

Well referencing the iomuxc in the cs-gpios didn't work. I got this error:

devicetree error: <Node /soc/iomuxc@401f8000/IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 in 'D:/aaa/radar/zephyr/misc/empty_file.c'> lacks #gpio-cells

[asteriskSF]

Also so far I haven't been able to get the SPI to operate at full bus speed. I tried the DMA operation, but there are gaps between every byte of the transfer. The Zephyr drivers seem to need some work to drive at the full data rate.

[asteriskSF]

@mmahadevan108 I noticed you have worked on the driver files. @DerekSnell not sure if you can advise, but you have been helpful on my other questions. :)
Should PCS work for LPSI on MIMXRX1062?
Any tips on how to achieve higher data rates on SPI when using DMA?

[asteriskSF]

I noticed this comment in the fsl_lpspi_edma.c code:

/*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/
LPSPI_SetFifoWatermarks(base, 0U, 0U);

Wondering if this assumption was true with spi running at 16MHz, but might not be true after boosting the speed to 50 MHz?
Will adjusting these settings help?

[ofirshe]

I'm encountering the same issue as I described here #77999.
Any suggestions on how to resolve it ?