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Add MAX32660EVSYS
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- Add SDK files (updated to match mbed system)
- Implement mbed API files
- Update mbed related configuration (CMakefiles, .json files...)
- Add gcc and arm related files (linker, scatter, startup...)
- Tested with ARM and GCC_ARM toolchain
- GreenTea tests have been executed

Signed-off-by: Sadik.Ozer <[email protected]>
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Sadik.Ozer authored and Sadik.Ozer committed Sep 30, 2021
1 parent 4cfbea4 commit 9c029bf
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1 change: 1 addition & 0 deletions targets/TARGET_Maxim/CMakeLists.txt
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add_subdirectory(TARGET_MAX32620C EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL)

add_library(mbed-maxim INTERFACE)

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110 changes: 110 additions & 0 deletions targets/TARGET_Maxim/TARGET_MAX32660/CMakeLists.txt
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# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0

add_subdirectory(TARGET_MAX32660EVSYS EXCLUDE_FROM_ALL)
add_subdirectory(device EXCLUDE_FROM_ALL)

add_library(mbed-max32660 INTERFACE)


set(MXM_PARTNUMBER MAX32660)
set(MXM_SOURCE_DIR ./Libraries/PeriphDrivers/Source)
set(MXM_PERIPH_DRIVER_DIR ./Libraries/PeriphDrivers)
set(MXM_CMSIS_DIR ./Libraries/CMSIS/Device/Maxim)

target_include_directories(mbed-max32660
INTERFACE
.

${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER}
${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include

${MXM_SOURCE_DIR}/DMA
${MXM_SOURCE_DIR}/LP
${MXM_SOURCE_DIR}/FLC
${MXM_SOURCE_DIR}/GPIO
${MXM_SOURCE_DIR}/I2C
${MXM_SOURCE_DIR}/ICC
${MXM_SOURCE_DIR}/RTC
${MXM_SOURCE_DIR}/SPI
${MXM_SOURCE_DIR}/SPIMSS
${MXM_SOURCE_DIR}/TMR
${MXM_SOURCE_DIR}/UART
${MXM_SOURCE_DIR}/WDT
)

target_sources(mbed-max32660
INTERFACE
PeripheralPins.c
gpio_api.c
gpio_irq_api.c
i2c_api.c
pinmap.c
port_api.c
rtc_api.c
serial_api.c
sleep.c
spi_api.c
us_ticker.c
lp_ticker.c
flash_api.c

${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32660.c

${MXM_SOURCE_DIR}/SYS/mxc_assert.c
${MXM_SOURCE_DIR}/SYS/mxc_delay.c
${MXM_SOURCE_DIR}/SYS/mxc_lock.c
${MXM_SOURCE_DIR}/SYS/pins_me11.c
${MXM_SOURCE_DIR}/SYS/sys_me11.c
${MXM_SOURCE_DIR}/SYS/nvic_table.c

${MXM_SOURCE_DIR}/DMA/dma_me11.c
${MXM_SOURCE_DIR}/DMA/dma_reva.c

${MXM_SOURCE_DIR}/LP/lp_me11.c

${MXM_SOURCE_DIR}/FLC/flc_common.c
${MXM_SOURCE_DIR}/FLC/flc_me11.c
${MXM_SOURCE_DIR}/FLC/flc_reva.c

${MXM_SOURCE_DIR}/GPIO/gpio_common.c
${MXM_SOURCE_DIR}/GPIO/gpio_me11.c
${MXM_SOURCE_DIR}/GPIO/gpio_reva.c

${MXM_SOURCE_DIR}/I2C/i2c_me11.c
${MXM_SOURCE_DIR}/I2C/i2c_reva.c

${MXM_SOURCE_DIR}/SPIMSS/spimss_me11.c
${MXM_SOURCE_DIR}/SPIMSS/spimss_reva.c
${MXM_SOURCE_DIR}/SPIMSS/i2s_me11.c
${MXM_SOURCE_DIR}/SPIMSS/i2s_reva.c

${MXM_SOURCE_DIR}/ICC/icc_common.c
${MXM_SOURCE_DIR}/ICC/icc_me11.c
${MXM_SOURCE_DIR}/ICC/icc_reva.c

${MXM_SOURCE_DIR}/RTC/rtc_me11.c
${MXM_SOURCE_DIR}/RTC/rtc_reva.c

${MXM_SOURCE_DIR}/SPI/spi_me11.c
${MXM_SOURCE_DIR}/SPI/spi_reva.c

${MXM_SOURCE_DIR}/TMR/tmr_common.c
${MXM_SOURCE_DIR}/TMR/tmr_me11.c
${MXM_SOURCE_DIR}/TMR/tmr_reva.c

${MXM_SOURCE_DIR}/UART/uart_common.c
${MXM_SOURCE_DIR}/UART/uart_me11.c
${MXM_SOURCE_DIR}/UART/uart_reva.c

${MXM_SOURCE_DIR}/WDT/wdt_common.c
${MXM_SOURCE_DIR}/WDT/wdt_me11.c
${MXM_SOURCE_DIR}/WDT/wdt_reva.c
)

target_link_libraries(mbed-max32660
INTERFACE
mbed-maxim
)


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/**
* @file fcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
*/

/* ****************************************************************************
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */

#ifndef _FCR_REGS_H_
#define _FCR_REGS_H_

/* **** Includes **** */
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

#if defined (__ICCARM__)
#pragma system_include
#endif

#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif

/// @endcond

/* **** Definitions **** */

/**
* @ingroup fcr
* @defgroup fcr_registers FCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
* @details Function Control.
*/

/**
* @ingroup fcr_registers
* Structure type to access the FCR Registers.
*/
typedef struct {
__IO uint32_t reg0; /**< <tt>\b 0x00:</tt> FCR REG0 Register */
} mxc_fcr_regs_t;

/* Register offsets for module FCR */
/**
* @ingroup fcr_registers
* @defgroup FCR_Register_Offsets Register Offsets
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
* @{
*/
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
/**@} end of group fcr_registers */

/**
* @ingroup fcr_registers
* @defgroup FCR_REG0 FCR_REG0
* @brief Register 0.
* @{
*/
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */

#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */

#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */

#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */

/**@} end of group FCR_REG0_Register */

#ifdef __cplusplus
}
#endif

#endif /* _FCR_REGS_H_ */
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