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Added extra HSE Values for STM32G431xB #15385

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merged 3 commits into from
Mar 8, 2023
Merged

Added extra HSE Values for STM32G431xB #15385

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7c87d7c
removed HSE speed limitation for STM32G431RB
cooleo2 Feb 26, 2023
7fcec27
Added HSE range validation for STM32g431xB
cooleo2 Mar 2, 2023
ac8204c
added support for 4, 8 and 16MHz
cooleo2 Mar 4, 2023
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11 changes: 10 additions & 1 deletion targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };

#if HSE_VALUE != 24000000
#if HSE_VALUE != 4000000 && HSE_VALUE != 8000000 && HSE_VALUE != 16000000 && HSE_VALUE != 24000000
#error Unsupported externall clock value, check HSE_VALUE define
#endif

Expand All @@ -100,7 +100,16 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#if HSE_VALUE == 4000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
#elif HSE_VALUE == 8000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
#elif HSE_VALUE == 16000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
#elif HSE_VALUE == 24000000
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6;
#endif

//! 170MHz as a core frequency for FDCAN is not suitable for many frequencies,
//! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz
//! should be standard.
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