soc/intel/cmn/blk/cse/cse.c: ensure resources are allocated <4G

Without this patch, if RESOURCE_ALLOCATION_TOP_DOWN is enabled and coreboot is compiled for IA32, the HECI device becomes inaccessible after resource allocation. Signed-off-by: Michał Kopeć <[email protected]>
Dasharo · Jan 16, 2025 · 5a313c7 · 5a313c7
1 parent c4edf10
commit 5a313c7
Showing 1 changed file with 16 additions and 1 deletion.
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
@@ -1599,9 +1599,24 @@ static void cse_final(struct device *dev)
 		cse_final_end_of_firmware();
 }
 
+#if ENV_RAMSTAGE
+static void heci_read_resources(struct device *dev)
+{
+	/* Read standard PCI resources. */
+	pci_dev_read_resources(dev);
+
+	if (ENV_X86_32) {
+		/* Put resource below 4G to ensure coreboot can access it */
+		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		res->limit = 0xffffffff;
+		res->flags &= ~IORESOURCE_ABOVE_4G;
+	}
+}
+#endif
+
 struct device_operations cse_ops = {
 	.set_resources		= pci_dev_set_resources,
-	.read_resources		= pci_dev_read_resources,
+	.read_resources		= heci_read_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= pci_dev_init,
 	.ops_pci		= &pci_dev_ops_pci,