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Merge pull request #3695 from Sonicadvance1/fix_3686
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Revert "OpcodeDispatcher: optimize logical flags"
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@alyssarosenzweig
alyssarosenzweig authored Jun 14, 2024
2 parents b17a2e9 + 9c62c41 commit 9aa82ec
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Showing 9 changed files with 264 additions and 199 deletions.
11 changes: 4 additions & 7 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -511,13 +511,10 @@ void OpDispatchBuilder::CalculateFlags_Logical(uint8_t SrcSize, Ref Res, Ref Src
// Undefined
_InvalidateFlags(1 << X86State::RFLAG_AF_RAW_LOC);

if (SrcSize >= 4) {
HandleNZ00Write();
CalculatePF(_AndWithFlags(IR::SizeToOpSize(SrcSize), Res, Res));
} else {
SetNZ_ZeroCV(SrcSize, Res);
CalculatePF(Res);
}
CalculatePF(Res);

// SF/ZF/CF/OF
SetNZ_ZeroCV(SrcSize, Res);
}

void OpDispatchBuilder::CalculateFlags_ShiftLeftImmediate(uint8_t SrcSize, Ref UnmaskedRes, Ref Src1, uint64_t Shift) {
Expand Down
56 changes: 28 additions & 28 deletions unittests/InstructionCountCI/Atomics.json
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Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w20, w20, w5",
"ands w26, w20, w20"
"orr w26, w20, w5",
"tst w26, w26"
]
},
"lock adc byte [rax], cl": {
Expand Down Expand Up @@ -290,8 +290,8 @@
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w20, w20, w5",
"ands w26, w20, w20"
"eor w26, w20, w5",
"tst w26, w26"
]
},
"lock add qword [rax], rcx": {
Expand Down Expand Up @@ -537,8 +537,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x100",
"ands w26, w20, w20"
"orr w26, w20, #0x100",
"tst w26, w26"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
Expand All @@ -547,8 +547,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w20, w21, w20",
"ands w26, w20, w20"
"orr w26, w21, w20",
"tst w26, w26"
]
},
"lock or qword [rax], 0x100": {
Expand All @@ -557,8 +557,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x100",
"ands x26, x20, x20"
"orr x26, x20, #0x100",
"tst x26, x26"
]
},
"lock or qword [rax], -2147483647": {
Expand All @@ -567,8 +567,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0xffffffff80000001",
"ands x26, x20, x20"
"orr x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock or word [rax], 1": {
Expand All @@ -587,8 +587,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x1",
"ands w26, w20, w20"
"orr w26, w20, #0x1",
"tst w26, w26"
]
},
"lock or qword [rax], 1": {
Expand All @@ -597,8 +597,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x1",
"ands x26, x20, x20"
"orr x26, x20, #0x1",
"tst x26, x26"
]
},
"lock adc byte [rax], 1": {
Expand Down Expand Up @@ -1326,8 +1326,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x100",
"ands w26, w20, w20"
"eor w26, w20, #0x100",
"tst w26, w26"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
Expand All @@ -1336,8 +1336,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w21, [x4]",
"eor w20, w21, w20",
"ands w26, w20, w20"
"eor w26, w21, w20",
"tst w26, w26"
]
},
"lock xor qword [rax], 0x100": {
Expand All @@ -1346,8 +1346,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x100",
"ands x26, x20, x20"
"eor x26, x20, #0x100",
"tst x26, x26"
]
},
"lock xor qword [rax], -2147483647": {
Expand All @@ -1356,8 +1356,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0xffffffff80000001",
"ands x26, x20, x20"
"eor x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock xor word [rax], 1": {
Expand All @@ -1376,8 +1376,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x1",
"ands w26, w20, w20"
"eor w26, w20, #0x1",
"tst w26, w26"
]
},
"lock xor qword [rax], 1": {
Expand All @@ -1386,8 +1386,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x1",
"ands x26, x20, x20"
"eor x26, x20, #0x1",
"tst x26, x26"
]
},
"lock dec byte [rax]": {
Expand Down
56 changes: 28 additions & 28 deletions unittests/InstructionCountCI/FlagM/Atomics.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,8 +65,8 @@
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w20, w20, w5",
"ands w26, w20, w20"
"orr w26, w20, w5",
"tst w26, w26"
]
},
"lock adc byte [rax], cl": {
Expand Down Expand Up @@ -269,8 +269,8 @@
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w20, w20, w5",
"ands w26, w20, w20"
"eor w26, w20, w5",
"tst w26, w26"
]
},
"lock add qword [rax], rcx": {
Expand Down Expand Up @@ -486,8 +486,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x100",
"ands w26, w20, w20"
"orr w26, w20, #0x100",
"tst w26, w26"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
Expand All @@ -496,8 +496,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w20, w21, w20",
"ands w26, w20, w20"
"orr w26, w21, w20",
"tst w26, w26"
]
},
"lock or qword [rax], 0x100": {
Expand All @@ -506,8 +506,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x100",
"ands x26, x20, x20"
"orr x26, x20, #0x100",
"tst x26, x26"
]
},
"lock or qword [rax], -2147483647": {
Expand All @@ -516,8 +516,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0xffffffff80000001",
"ands x26, x20, x20"
"orr x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock or word [rax], 1": {
Expand All @@ -536,8 +536,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x1",
"ands w26, w20, w20"
"orr w26, w20, #0x1",
"tst w26, w26"
]
},
"lock or qword [rax], 1": {
Expand All @@ -546,8 +546,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x1",
"ands x26, x20, x20"
"orr x26, x20, #0x1",
"tst x26, x26"
]
},
"lock adc byte [rax], 1": {
Expand Down Expand Up @@ -1199,8 +1199,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x100",
"ands w26, w20, w20"
"eor w26, w20, #0x100",
"tst w26, w26"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
Expand All @@ -1209,8 +1209,8 @@
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w21, [x4]",
"eor w20, w21, w20",
"ands w26, w20, w20"
"eor w26, w21, w20",
"tst w26, w26"
]
},
"lock xor qword [rax], 0x100": {
Expand All @@ -1219,8 +1219,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x100",
"ands x26, x20, x20"
"eor x26, x20, #0x100",
"tst x26, x26"
]
},
"lock xor qword [rax], -2147483647": {
Expand All @@ -1229,8 +1229,8 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0xffffffff80000001",
"ands x26, x20, x20"
"eor x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock xor word [rax], 1": {
Expand All @@ -1249,8 +1249,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x1",
"ands w26, w20, w20"
"eor w26, w20, #0x1",
"tst w26, w26"
]
},
"lock xor qword [rax], 1": {
Expand All @@ -1259,8 +1259,8 @@
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x1",
"ands x26, x20, x20"
"eor x26, x20, #0x1",
"tst x26, x26"
]
},
"lock dec byte [rax]": {
Expand Down
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