Update patch with sxtw case

FEX-Emu · Feb 20, 2024 · ee23b55 · ee23b55
1 parent c63f61a
commit ee23b55
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Showing 3 changed files with 31 additions and 16 deletions.
diff --git a/FEXCore/Source/Interface/IR/PassManager.cpp b/FEXCore/Source/Interface/IR/PassManager.cpp
@@ -80,7 +80,8 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool Inli
 
     InsertPass(CreateDeadStoreElimination(ctx->HostFeatures.SupportsAVX));
     InsertPass(CreatePassDeadCodeElimination());
-    InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
+    InsertPass(CreateConstProp(
+        InlineConstants, ctx->HostFeatures.SupportsTSOImm9, Is64BitMode()));
 
     InsertPass(CreateDeadFlagCalculationEliminination());
 
@@ -121,5 +122,4 @@ bool PassManager::Run(IREmitter *IREmit) {
 
   return Changed;
 }
-
 }
diff --git a/FEXCore/Source/Interface/IR/Passes.h b/FEXCore/Source/Interface/IR/Passes.h
@@ -16,15 +16,17 @@ class Pass;
 class RegisterAllocationPass;
 class RegisterAllocationData;
 
-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateInlineCallOptimization(const FEXCore::CPUIDEmu* CPUID);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
-fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
-                                                                                  bool SupportsAVX);
+fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass>
+CreateRegisterAllocationPass(FEXCore::IR::Pass *CompactionPass,
+                             bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();
 
 namespace Validation {

diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
@@ -91,6 +91,7 @@ static bool IsTSOImm9(uint64_t imm) {
 }
 
 static std::tuple<MemOffsetType, uint8_t, OrderedNode*, OrderedNode*> MemExtendedAddressing(IREmitter *IREmit, uint8_t AccessSize,  IROp_Header* AddressHeader) {
+  LOGMAN_THROW_A_FMT(AddressHeader->Op == OP_ADD, "Invalid address Op");
   auto Src0Header = IREmit->GetOpHeader(AddressHeader->Args[0]);
   if (Src0Header->Size == 8) {
     //Try to optimize: Base + MUL(Offset, Scale)
@@ -141,7 +142,13 @@ static std::tuple<MemOffsetType, uint8_t, OrderedNode*, OrderedNode*> MemExtende
   }
 
   // no match anywhere, just add
-  return { MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[0]), IREmit->UnwrapNode(AddressHeader->Args[1]) };
+  auto Arg0 = IREmit->UnwrapNode(AddressHeader->Args[0]);
+  auto Arg1 = IREmit->UnwrapNode(AddressHeader->Args[1]);
+  if (Src0Header->Size == 8) {
+    return {MEM_OFFSET_SXTX, 1, Arg0, Arg1};
+  } else {
+    return {MEM_OFFSET_SXTW, 1, Arg0, Arg1};
+  }
 }
 
 static OrderedNodeWrapper RemoveUselessMasking(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t mask) {
@@ -184,9 +191,10 @@ static bool IsBfeAlreadyDone(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t
 
 class ConstProp final : public FEXCore::IR::Pass {
 public:
-  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9)
-    : InlineConstants(DoInlineConstants)
-    , SupportsTSOImm9 {SupportsTSOImm9} { }
+  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9,
+                     bool Is64BitMode)
+      : InlineConstants(DoInlineConstants), SupportsTSOImm9{SupportsTSOImm9},
+        Is64BitMode(Is64BitMode) {}
 
   bool Run(IREmitter *IREmit) override;
 
@@ -219,6 +227,7 @@ class ConstProp final : public FEXCore::IR::Pass {
     return Result.first->second;
   }
   bool SupportsTSOImm9{};
+  bool Is64BitMode;
   // This is a heuristic to limit constant pool live ranges to reduce RA interference pressure.
   // If the range is unbounded then RA interference pressure seems to increase to the point
   // that long blocks of constant usage can slow to a crawl.
@@ -526,12 +535,14 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
 
       if (AddressHeader->Op == OP_ADD &&
-          (AddressHeader->Size == 8 || AddressHeader->Size == 4)) {
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
+        auto [OffsetType, OffsetScale, Arg0, Arg1] =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
 
         Op->OffsetType = OffsetType;
         Op->OffsetScale = OffsetScale;
-        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0); // Addr
+        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0);   // Addr
         IREmit->ReplaceNodeArgument(CodeNode, Op->Offset_Index, Arg1); // Offset
 
         Changed = true;
@@ -544,7 +555,8 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
 
       if (AddressHeader->Op == OP_ADD &&
-          (AddressHeader->Size == 8 || AddressHeader->Size == 4)) {
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
         auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
 
         Op->OffsetType = OffsetType;
@@ -1295,8 +1307,9 @@ bool ConstProp::Run(IREmitter *IREmit) {
   return Changed;
 }
 
-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9) {
-  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode) {
+  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9,
+                                       Is64BitMode);
 }
-
 }