4.9-1.0.x-imx merge latest changes from rel_imx_4.9.x_1.0.0_ga

Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt

@@ -0,0 +1,38 @@
+Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over
+rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver
+needed to get/set gpio status from M4 side by rpmsg.
+
+Required properties:
+- compatible : Should be "fsl,imx-rpmsg-gpio".
+- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1.
+- gpio-controller : Mark the device node as a gpio controller.
+- #gpio-cells : Should be two. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+      0 = active high
+      1 = active low
+
+Note: Each GPIO port should have an alias correctly numbered in "aliases"
+node.
+
+Examples:
+
+aliases {
+	gpio4 = &rpmsg_gpio0;
+	gpio5 = &rpmsg_gpio1;
+};
+
+rpmsg_gpio0: rpmsg-gpio0 {
+	compatible = "fsl,imx-rpmsg-gpio";
+	port_idx = <0>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	status = "okay";
+};
+
+rpmsg_gpio1: rpmsg-gpio1 {
+	compatible = "fsl,imx-rpmsg-gpio";
+	port_idx = <1>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	status = "okay";
+};

arch/arm/boot/dts/imx7ulp-evk.dts

@@ -16,6 +16,11 @@
 	model = "NXP i.MX7ULP EVK";
 	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
 
+	aliases {
+		gpio4 = &rpmsg_gpio0;
+		gpio5 = &rpmsg_gpio1;
+	};
+
 	chosen {
 		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
 		stdout-path = &lpuart4;
@@ -166,6 +171,22 @@
 		status = "okay";
 	};
 
+	rpmsg_gpio0: rpmsg-gpio0 {
+		compatible = "fsl,imx-rpmsg-gpio";
+		port_idx = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "okay";
+	};
+
+	rpmsg_gpio1: rpmsg-gpio1 {
+		compatible = "fsl,imx-rpmsg-gpio";
+		port_idx = <1>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "okay";
+	};
+
 	rpmsg_keys: rpmsg-keys {
 		compatible = "fsl,rpmsg-keys";
 
@@ -484,15 +505,11 @@
 &rpmsg{
 	/*
 	 * 64K for one rpmsg instance, default using 2 rpmsg instances:
-	 * --0x9FF00000~0x9FF0FFFF: pingpong
-	 * --0x9FF10000~0x9FF1FFFF: pmic
-	 * --0x9FF20000~0x9FF2FFFF: pm
-	 * --0x9FF30000~0x9FF3FFFF: audio
-	 * --0x9FF40000~0x9FF4FFFF: virtual tty
-	 * --0x9FF50000~0x9FF5FFFF: keys
+	 * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio
+	 * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty
 	 */
-	vdev-nums = <6>;
-	reg = <0x9FF00000 0x60000>;
+	vdev-nums = <2>;
+	reg = <0x9FF00000 0x20000>;
 	status = "okay";
 };
 

arch/arm/configs/imx_v7_defconfig

@@ -198,6 +198,7 @@ CONFIG_SPI_IMX=y
 CONFIG_SPI_FSL_LPSPI=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_IMX_RPMSG=y
 CONFIG_GPIO_MAX732X=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_74X164=y

arch/arm/mach-imx/anatop.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -145,7 +146,7 @@ void imx_anatop_pre_suspend(void)
 		return;
 	}
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_anatop_disable_pu(true);
 
 	if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
@@ -175,7 +176,7 @@ void imx_anatop_post_resume(void)
 		return;
 	}
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_anatop_disable_pu(false);
 
 	if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
@@ -209,6 +210,7 @@ void __init imx_init_revision_from_anatop(void)
 	unsigned int revision;
 	u32 digprog;
 	u16 offset = ANADIG_DIGPROG;
+	u16 major_part, minor_part;
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
 	anatop_base = of_iomap(np, 0);
@@ -220,45 +222,25 @@ void __init imx_init_revision_from_anatop(void)
 	digprog = readl_relaxed(anatop_base + offset);
 	iounmap(anatop_base);
 
-	switch (digprog & 0xff) {
-	case 0:
-		/*
-		 * For i.MX6QP, most of the code for i.MX6Q can be resued,
-		 * so internally, we identify it as i.MX6Q Rev 2.0
-		 */
-		if (digprog >> 8 & 0x01)
-			revision = IMX_CHIP_REVISION_2_0;
-		else
-			revision = IMX_CHIP_REVISION_1_0;
-		break;
-	case 1:
-		revision = IMX_CHIP_REVISION_1_1;
-		break;
-	case 2:
-		revision = IMX_CHIP_REVISION_1_2;
-		break;
-	case 3:
-		revision = IMX_CHIP_REVISION_1_3;
-		break;
-	case 4:
-		revision = IMX_CHIP_REVISION_1_4;
-		break;
-	case 5:
-		/*
-		 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
-		 * as 'D' in Part Number last character.
-		 */
-		revision = IMX_CHIP_REVISION_1_5;
-		break;
-	default:
+	/*
+	 * On i.MX7D digprog value match linux version format, so
+	 * it needn't map again and we can use register value directly.
+	 */
+	if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
+		revision = digprog & 0xff;
+	} else {
 		/*
-		 * Fail back to return raw register value instead of 0xff.
-		 * It will be easy to know version information in SOC if it
-		 * can't be recognized by known version. And some chip's (i.MX7D)
-		 * digprog value match linux version format, so it needn't map
-		 * again and we can use register value directly.
+		 * MAJOR: [15:8], the major silicon revison;
+		 * MINOR: [7: 0], the minor silicon revison;
+		 *
+		 * please refer to the i.MX RM for the detailed
+		 * silicon revison bit define.
+		 * format the major part and minor part to match the
+		 * linux kernel soc version format.
 		 */
-		revision = digprog & 0xff;
+		major_part = (digprog >> 8) & 0xf;
+		minor_part = digprog & 0xf;
+		revision = ((major_part + 1) << 4) | minor_part;
 	}
 
 	mxc_set_cpu_type(digprog >> 16 & 0xff);

arch/arm/mach-imx/cpu.c

@@ -126,7 +126,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6SX";
 		break;
 	case MXC_CPU_IMX6Q:
-		if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 			soc_id = "i.MX6QP";
 		else
 			soc_id = "i.MX6Q";

arch/arm/mach-imx/gpc.c

@@ -1,6 +1,7 @@
 /*
  * Copyright 2011-2016 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -231,7 +232,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 	int i;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
 
 	/* power down the mega-fast power domain */
@@ -254,7 +255,7 @@ void imx_gpc_post_resume(void)
 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 	int i;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		_imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
 
 	/* Keep ARM core powered on for other low-power modes */
@@ -648,7 +649,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
 	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 
 	if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() &&
-		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		return 0;
 
 	_imx6q_pm_pu_power_off(genpd);
@@ -693,7 +694,7 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
 	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 	int ret;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0
 		&& &imx6q_pu_domain == pu) {
 		if (!pu_on)
 			pu_on = true;
@@ -856,7 +857,7 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
 
 	is_off = IS_ENABLED(CONFIG_PM);
 	if (is_off && !(cpu_is_imx6q() &&
-		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)) {
+		imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)) {
 		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
 	} else {
 		/*

arch/arm/mach-imx/mach-imx6q.c

@@ -1,6 +1,7 @@
 /*
  * Copyright 2011-2015 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -310,15 +311,15 @@ static inline void imx6q_enet_init(void)
 	imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp");
 	imx6q_enet_phy_init();
 	imx6q_1588_init();
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx6q_enet_clk_sel();
 }
 
 static void __init imx6q_init_machine(void)
 {
 	struct device *parent;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
 	else
 		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",

drivers/clk/imx/clk-imx6q.c

@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -662,7 +663,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 	clk[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 
-	if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
+	if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
 		clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
 		clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
 	} else {
@@ -990,7 +991,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
 		imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
 	} else if (clk_on_imx6q()) {
-		if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
+		if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
 			clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]);
 			imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 720000000);
 			clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
@@ -1087,7 +1088,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	 * for i.MX6QP with speeding grading set to 1.2GHz,
 	 * VPU should run at 396MHz.
 	 */
-	if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
+	if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 		WARN_ON(!np);
 

drivers/gpio/Kconfig

@@ -442,6 +442,12 @@ config GPIO_VF610
 	help
 	  Say yes here to support Vybrid vf610 GPIOs.
 
+config GPIO_IMX_RPMSG
+	bool "NXP i.MX7ULP RPMSG GPIO support"
+	depends on ARCH_MXC && RPMSG && GPIOLIB
+	help
+	  This driver support i.MX7ULP RPMSG virtual GPIOs.
+
 config GPIO_VR41XX
 	tristate "NEC VR4100 series General-purpose I/O Uint support"
 	depends on CPU_VR41XX

drivers/gpio/Makefile

@@ -124,6 +124,7 @@ obj-$(CONFIG_GPIO_TZ1090)	+= gpio-tz1090.o
 obj-$(CONFIG_GPIO_TZ1090_PDC)	+= gpio-tz1090-pdc.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VF610)	+= gpio-vf610.o
+obj-$(CONFIG_GPIO_IMX_RPMSG)	+= gpio-imx-rpmsg.o
 obj-$(CONFIG_GPIO_VIPERBOARD)	+= gpio-viperboard.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o