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Possible fix to BRAM uint0_t size issue... #201

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Paulo-D2000
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Just rounding up the result from log2

"Rounding" 0 to 1 by adding extra 1...
Possible fix to uint0_t RAM function
@@ -1756,7 +1756,7 @@ def GET_MEM_H_LOGIC_LOOKUP(parser_state):
dim = dims[i]
addr_t = (
"uint"
+ str(int(math.ceil(math.log(dim, 2))))
+ str(int(math.ceil(math.log(dim, 2)))+1) #round up by 1
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@JulianKemmerer JulianKemmerer Jul 2, 2024

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Reasonable, but I prefer to keep the width exact as needed

For ex. you need two address bits to address four things
but the round up by one makes it 3 bits for dim=4

hmm maybe just need a simple 'its uint1 unless >1 then do math as is'

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There is another place this math occurs at for sizing muxes in this same file

sel_width = int(math.ceil(math.log(n, 2)))

mind changing there too?

And searching repo I found one more place

"uint" + str(int(math.ceil(math.log(first_dim, 2)))) + "_t"

could maybe make a common helper func in https://github.com/JulianKemmerer/PipelineC/blob/master/src/utilities.py
but not critical

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