Verilog Testbench Output

Verilog Testbench Output

Ordt can generate a simple verilog testbench for verifying basic operations of generated register logic. The testbench contains the register logic and a bfm to drive the primary leaf or parallel decoder interface. Testbench generation using ring or serial8 primary decoder interface types and ability to drive transactions on a secondary decoder interface are not supported currently. Test commands are added as ordt parameters to drive the bench.

Note: this page reflects code in version 170724.01

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Testbench generation example

The rdl input file below with inline parameters includes 2 registers - the first contains a rollover counter and a saturating counter, and the second contains an indication of the rollover counter overflow. The simple set of test sequences verify the values of the counters as well as the overflow.

	// verilog testbench example
	//
	// parameter defines for this example
	<PARMS>
	output systemverilog {
	    root_decoder_interface = parallel      // parallel | leaf | serial8 | ring8 | ring16 | ring32
	    nack_partial_writes = true     // issue nack for writes of size less than target
	}
	output bench {
		add_test_command = "read 32 0x0 0x0"  // verify counter init value
		add_test_command = "read 32 0x4 0x0"  // verify no overflow
		// turn on increment inputs
		add_test_command = "statement #1 h2l_counts_reg_sat_cnt_incr=1'b1;" 
		add_test_command = "statement h2l_counts_reg_rollover_cnt_incr=1'b1;"
		add_test_command = "wait 10"
		add_test_command = "statement #1 h2l_counts_reg_sat_cnt_incr=1'b0;" 
		add_test_command = "statement h2l_counts_reg_rollover_cnt_incr=1'b0;"
		// verify correct counts and no overflow
		add_test_command = "read 32 0x0 0x000a000a"  // verify counter value
		add_test_command = "read 32 0x4 0x0"  // verify no overflow
		// turn on increment inputs
		add_test_command = "statement #1 h2l_counts_reg_sat_cnt_incr=1'b1;" 
		add_test_command = "statement h2l_counts_reg_rollover_cnt_incr=1'b1;"
		add_test_command = "wait 32"
		add_test_command = "statement #1 h2l_counts_reg_sat_cnt_incr=1'b0;" 
		add_test_command = "statement h2l_counts_reg_rollover_cnt_incr=1'b0;"
		// verify correct counts and overflow
		add_test_command = "read 32 0x0 0x000a001f"  // verify counter value
		add_test_command = "read 32 0x4 0x1"  // verify overflow
	}
	</PARMS>
	
	addrmap {
	    reg  {       
	        field { sw=rw; hw=na; counter; incrsaturate; } sat_cnt[4:0]=5'h0;  // 5b saturating counter
	        field { sw=rw; hw=na; counter; overflow; } rollover_cnt[20:16]=5'h0;  // 5b rollover counter
	    } counts_reg;
	    reg  {       
	        field { sw=rw; hw=na; } detect=1'b0;  // set to 1 if overflow
	    } overflow_reg;
	    overflow_reg.detect->hwset=counts_reg.rollover_cnt->overflow;  // overflow detect 
	} foo_map;

Bench and register logic is generated via...

 ordt -vbench bench.v -verilog regs.v vbench_example.rdl

Compile and run of the code (using Icarus in this case) results in...

    $ iverilog bench.v regs.v
    $ vvp a.out
     << Starting the Simulation >>
    VCD info: dumpfile test.vcd opened for output.
     15: Applying reset...
     45: Releasing reset...
    56: initiating  1 word read to address 0000000000...
      ack = 1
      nack = 0
      read data = 00000000
      read compare OK - expected 00000000
    96: initiating  1 word read to address 0000000004...
      ack = 1
      nack = 0
      read data = 00000000
      read compare OK - expected 00000000
    236: initiating  1 word read to address 0000000000...
      ack = 1
      nack = 0
      read data = 000a000a
      read compare OK - expected 000a000a
    276: initiating  1 word read to address 0000000004...
      ack = 1
      nack = 0
      read data = 00000000
      read compare OK - expected 00000000
    636: initiating  1 word read to address 0000000000...
      ack = 1
      nack = 0
      read data = 000a001f
      read compare OK - expected 000a001f
    676: initiating  1 word read to address 0000000004...
      ack = 1
      nack = 0
      read data = 00000001
      read compare OK - expected 00000001