GitHub - Kalclavia/ARMv8-Single-Cycle-Processor: Project to create a single-cycle processor in Verilog based on the ArmV8 ISA.

Kalclavia / ARMv8-Single-Cycle-Processor Public

Project to create a single-cycle processor in Verilog based on the ArmV8 ISA.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.v		ALU.v
DataMemory.v		DataMemory.v
InstructionMemory.v		InstructionMemory.v
MOVZ Test Assembly Code.txt		MOVZ Test Assembly Code.txt
NextPClogic.v		NextPClogic.v
Opcodes Table.xlsx		Opcodes Table.xlsx
RegisterFile.v		RegisterFile.v
SignExtender.v		SignExtender.v
SingleCycleControl.v		SingleCycleControl.v
SingleCycleProc.v		SingleCycleProc.v
SingleCycleProcTest.v		SingleCycleProcTest.v