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Fix lerdge script. #18771

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merged 1 commit into from
Jul 25, 2020
Merged

Fix lerdge script. #18771

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13 changes: 0 additions & 13 deletions buildroot/share/PlatformIO/scripts/copy_marlin_variant_to_framework.py
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Original file line number Diff line number Diff line change
Expand Up @@ -15,19 +15,6 @@ def copytree(src, dst, symlinks=False, ignore=None):
platform = env.PioPlatform()
board = env.BoardConfig()
variant = board.get("build.variant")
variant_dir = ' +<buildroot/share/PlatformIO/variants/' + variant + '>';
src_filter = env.get("SRC_FILTER")
print("Starting SRC Filter:", env.get("SRC_FILTER"))
src_filter_value = src_filter[0];

src_filter_value = src_filter_value + variant_dir
src_filter[0] = src_filter_value;
env["SRC_FILTER"] = src_filter

print("Modified SRC Filter:", env.get("SRC_FILTER"))

cxx_flags = env['CXXFLAGS']
print("CXXFLAGS", cxx_flags)

FRAMEWORK_DIR = platform.get_package_dir("framework-arduinoststm32")
assert os.path.isdir(FRAMEWORK_DIR)
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2 changes: 1 addition & 1 deletion platformio.ini
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Expand Up @@ -846,7 +846,7 @@ extra_scripts = ${common.extra_scripts}
build_flags = ${common_stm32.build_flags}
-DSTM32F4 -DSTM32F4xx -DTARGET_STM32F4
-DDISABLE_GENERIC_SERIALUSB -DARDUINO_ARCH_STM32 -DARDUINO_LERDGE
-DTRANSFER_CLOCK_DIV=8
-DTRANSFER_CLOCK_DIV=8 -DHAL_SRAM_MODULE_ENABLED
build_unflags = ${common_stm32.build_unflags} -DUSBCON -DUSBD_USE_CDC -DUSBD_VID=0x0483

#
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