apb-verification-uvm

This project focuses on the Verification of Advanced Peripheral Bus (APB) protocol using the Universal Verification Methodology (UVM).

APB Block Diagram

APB Interface Signals

Signal Name	Direction	Width	Description
PCLK	Input	1-bit	Clock signal
PRESETn	Input	1-bit	Active-low reset signal
PADDR	Input	32-bit	Address signal
PSELx	Input	1-bit	Select signal for the slave device
PENABLE	Input	1-bit	Indicates second and subsequent cycles of an APB transfer
PWRITE	Input	1-bit	Indicates an APB write access when HIGH and an APB read access when LOW
PWDATA	Input	32-bit	Data to be written to the selected address
PREADY	Output	1-bit	Indicates the slave is ready to complete the data transfer
PRDATA	Output	32-bit	Data read from the selected address
PSLVERR	Output	1-bit	Indicates a slave error

UVM Testbench Architecture

Coverage Results

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• Code Coverage :
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