Merge pull request #185 from OpenXiangShan/align-scheduler

Align scheduler

configs/common/CacheConfig.py

@@ -212,6 +212,9 @@ def config_cache(options, system):
                         system.cpu[i].add_pf_downstream(dcache.prefetcher)
                     if options.ideal_cache:
                         dcache.prefetcher.stream_pf_ahead = False
+                    if options.l1d_use_xsstride:
+                        dcache.prefetcher.enable_berti = False
+                        dcache.prefetcher.enable_sstride = True
 
             if options.ideal_cache:
                 icache.response_latency = 0

configs/common/Options.py

@@ -283,7 +283,9 @@ def addCommonOptions(parser, configure_xiangshan=False):
     parser.add_argument("--list-hwp-types",
                         action=ListHWP, nargs=0,
                         help="List available hardware prefetcher types")
-
+    parser.add_argument("--l1d-use-xsstride", action="store_true", default=False,
+                        help="""
+                        Enable SPP component for L1 data prefetcher""")
     parser.add_argument("--l1d-enable-spp", action="store_true", default=False,
                         help="""
                         Enable SPP component for L1 data prefetcher""")

configs/common/cores/arm/O3_ARM_v7a.py

@@ -123,8 +123,6 @@ class O3_ARM_v7a_3(ArmO3CPU):
     renameWidth = 3
     renameToIEWDelay = 1
     issueToExecuteDelay = 1
-    dispatchWidth = 6
-    issueWidth = 8
     wbWidth = 8
     fuPool = O3_ARM_v7a_FUP()
     iewToCommitDelay = 1

configs/common/cores/arm/ex5_big.py

@@ -123,8 +123,6 @@ class ex5_big(ArmO3CPU):
     renameWidth = 3
     renameToIEWDelay = 1
     issueToExecuteDelay = 1
-    dispatchWidth = 6
-    issueWidth = 8
     wbWidth = 8
     fuPool = ex5_big_FUP()
     iewToCommitDelay = 1

configs/example/kmh.py

@@ -0,0 +1,67 @@
+import argparse
+import sys
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+from m5.util.fdthelper import *
+
+addToPath('../')
+
+from ruby import Ruby
+
+from common.FSConfig import *
+from common.SysPaths import *
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common import XSConfig
+from common.Caches import *
+from common import Options
+from example.xiangshan import *
+
+if __name__ == '__m5_main__':
+
+    # Add args
+    parser = argparse.ArgumentParser()
+    Options.addCommonOptions(parser, configure_xiangshan=True)
+    Options.addXiangshanFSOptions(parser)
+
+    # Add the ruby specific and protocol specific args
+    if '--ruby' in sys.argv:
+        Ruby.define_options(parser)
+
+    args = parser.parse_args()
+
+    args.xiangshan_system = True
+    args.enable_difftest = True
+    args.enable_riscv_vector = True
+
+    args.l2_hwp_type = "WorkerPrefetcher"
+    args.pht_pf_level = 2
+    args.l1d_use_xsstride = True
+
+
+    assert not args.external_memory_system
+
+    test_mem_mode = 'timing'
+
+    # override cpu class and clock
+    if args.xiangshan_ecore:
+        FutureClass = None
+        args.cpu_clock = '2.4GHz'
+    else:
+        FutureClass = None
+
+    # Match the memories with the CPUs, based on the options for the test system
+    TestMemClass = Simulation.setMemClass(args)
+
+    test_sys = build_test_system(args.num_cpus, args)
+
+    root = Root(full_system=True, system=test_sys)
+
+    Simulation.run_vanilla(args, root, test_sys, FutureClass)

configs/example/xiangshan.py

@@ -23,12 +23,20 @@
 from common.Caches import *
 from common import Options
 
-def build_test_system(np):
+def build_test_system(np, args):
     assert buildEnv['TARGET_ISA'] == "riscv"
+
+    # override cpu class and clock
+    if args.xiangshan_ecore:
+        TestCPUClass = XiangshanECore
+        args.cpu_clock = '2.4GHz'
+    else:
+        TestCPUClass = XiangshanCore
+
     ruby = False
     if hasattr(args, 'ruby') and args.ruby:
         ruby = True
-    test_sys = makeBareMetalXiangshanSystem(test_mem_mode, SysConfig(mem=args.mem_size), None, np=np, ruby=ruby)
+    test_sys = makeBareMetalXiangshanSystem('timing', SysConfig(mem=args.mem_size), None, np=np, ruby=ruby)
     test_sys.num_cpus = np
 
     test_sys.xiangshan_system = True
@@ -255,39 +263,35 @@ def build_test_system(np):
 
     return test_sys
 
-# Add args
-parser = argparse.ArgumentParser()
-Options.addCommonOptions(parser, configure_xiangshan=True)
-Options.addXiangshanFSOptions(parser)
+if __name__ == '__m5_main__':
+    # Add args
+    parser = argparse.ArgumentParser()
+    Options.addCommonOptions(parser, configure_xiangshan=True)
+    Options.addXiangshanFSOptions(parser)
 
-# Add the ruby specific and protocol specific args
-if '--ruby' in sys.argv:
-    Ruby.define_options(parser)
+    # Add the ruby specific and protocol specific args
+    if '--ruby' in sys.argv:
+        Ruby.define_options(parser)
 
-args = parser.parse_args()
+    args = parser.parse_args()
 
-args.xiangshan_system = True
-args.enable_difftest = True
-args.enable_riscv_vector = True
-
-assert not args.external_memory_system
+    if args.xiangshan_ecore:
+        FutureClass = None
+        args.cpu_clock = '2.4GHz'
+    else:
+        FutureClass = None
 
-test_mem_mode = 'timing'
+    args.xiangshan_system = True
+    args.enable_difftest = True
+    args.enable_riscv_vector = True
 
-# override cpu class and clock
-if args.xiangshan_ecore:
-    TestCPUClass = XiangshanECore
-    FutureClass = None
-    args.cpu_clock = '2.4GHz'
-else:
-    TestCPUClass = XiangshanCore
-    FutureClass = None
+    assert not args.external_memory_system
 
-# Match the memories with the CPUs, based on the options for the test system
-TestMemClass = Simulation.setMemClass(args)
+    # Match the memories with the CPUs, based on the options for the test system
+    TestMemClass = Simulation.setMemClass(args)
 
-test_sys = build_test_system(args.num_cpus)
+    test_sys = build_test_system(args.num_cpus, args)
 
-root = Root(full_system=True, system=test_sys)
+    root = Root(full_system=True, system=test_sys)
 
-Simulation.run_vanilla(args, root, test_sys, FutureClass)
+    Simulation.run_vanilla(args, root, test_sys, FutureClass)

src/arch/riscv/RiscvCPU.py

@@ -56,16 +56,12 @@ class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
     mmu = RiscvMMU()
 
 class XiangshanCore(RiscvO3CPU):
-    fuPool = XSCoreFUPool()
+    pass
 
 class XiangshanECore(XiangshanCore):
-    fuPool = XSECoreFUPool()
-
     fetchWidth = 8
     decodeWidth = 4
     renameWidth = 4
-    dispatchWidth = 4
-    issueWidth = 6
     wbWidth = 6
 
     numROBEntries = 150
@@ -79,13 +75,9 @@ class XiangshanECore(XiangshanCore):
     numPhysRMiscRegs = 40
 
 class XiangshanECore2Read(XiangshanCore):
-    fuPool = XSECore2ReadFUPool()
-
     fetchWidth = 8
     decodeWidth = 4
     renameWidth = 4
-    dispatchWidth = 4
-    issueWidth = 6
     wbWidth = 6
 
     numROBEntries = 150

src/cpu/FuncUnit.py

@@ -94,5 +94,5 @@ class FUDesc(SimObject):
     cxx_header = "cpu/func_unit.hh"
     cxx_class = 'gem5::FUDesc'
 
-    count = Param.Int("number of these FU's available")
+    count = Param.Int(0, "number of these FU's available (deprecated)")
     opList = VectorParam.OpDesc("operation classes for this FU type")

src/cpu/o3/BaseO3CPU.py

@@ -132,18 +132,16 @@ def support_take_over(cls):
                "Issue/Execute/Writeback delay")
     executeToWriteBackDelay = Param.Cycles(1, "Execute to issue delay")
 
-    dispatchWidth = Param.Unsigned(6, "Dispatch width")
-    issueWidth = Param.Unsigned(8, "Issue width")
-    wbWidth = Param.Unsigned(8, "Writeback width")
-    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
+    dispWidth = Param.Unsigned(6, "Each DispQue dispatch width")
+    wbWidth = Param.Unsigned(20, "Writeback width")
 
     iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
                "delay")
     renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
-    commitWidth = Param.Unsigned(6, "Commit width")
+    commitWidth = Param.Unsigned(8, "Commit width")
 
-    squashWidth = Param.Unsigned(6, "Squash width with rollback rob walk")
-    replayWidth = Param.Unsigned(6, "Squash width with redo rob walk")
+    squashWidth = Param.Unsigned(8, "Squash width with rollback rob walk")
+    replayWidth = Param.Unsigned(8, "Squash width with redo rob walk")
     ConstSquashCycle = Param.Unsigned(1, "Squash width with redo rob walk")
     robWalkPolicy = Param.ROBWalkPolicy('Replay', "Squash with a specific policy")
 
@@ -179,7 +177,7 @@ def support_take_over(cls):
 
     numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
 
-    numPhysIntRegs = Param.Unsigned(192,
+    numPhysIntRegs = Param.Unsigned(224,
             "Number of physical integer registers")
     numPhysFloatRegs = Param.Unsigned(192, "Number of physical floating point "
                                       "registers")
@@ -192,7 +190,7 @@ def support_take_over(cls):
     numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")
     numPhysRMiscRegs = Param.Unsigned(40, "Number of physical renameable misc registers")
 
-    numDQEntries = Param.Unsigned(16, "Number of entries in the dispQue")
+    numDQEntries = Param.Unsigned(18, "Number of entries in the dispQue")
     numROBEntries = Param.Unsigned(256, "Number of reorder buffer entries")
 
     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")