cpu-o3: add some comments for backend

No features have been modified, just enhanced readability.

Change-Id: I51f67ea4801c7c25707839ef1185a559adc8d3cb

src/cpu/o3/iew.cc

@@ -1219,6 +1219,7 @@ IEW::dispatchInstFromDispQue(ThreadID tid)
                 DPRINTF(IEW, "[tid:%i] Dispatch: Memory instruction "
                         "encountered, adding to LSQ.\n", tid);
 
+                // allocate entry in store queue
                 ldstQueue.insertStore(inst);
 
                 // AMOs need to be set as "canCommit()"
@@ -1231,8 +1232,7 @@ IEW::dispatchInstFromDispQue(ThreadID tid)
                 DPRINTF(IEW, "[tid:%i] Dispatch: Memory instruction "
                         "encountered, adding to LSQ.\n", tid);
 
-                // Reserve a spot in the load store queue for this
-                // memory access.
+                // allocate entry in load queue
                 ldstQueue.insertLoad(inst);
 
                 add_to_iq = true;
@@ -1241,6 +1241,7 @@ IEW::dispatchInstFromDispQue(ThreadID tid)
                 DPRINTF(IEW, "[tid:%i] Dispatch: Memory instruction "
                         "encountered, adding to LSQ.\n", tid);
 
+                // allocate entry in store queue
                 ldstQueue.insertStore(inst);
 
                 if (inst->isStoreConditional()) {
@@ -1533,7 +1534,8 @@ IEW::executeInsts()
         // scheduler is used.  Currently the scheduler schedules the oldest
         // instruction first, so the branch resolution order will be correct.
         if (!(inst->isLoad() || inst->isStore())) {
-            // Load/Store will call this in `lsq_unit.cc` after execution
+            // because Load/Store become pipeline execution ,Load/Store will
+            // call this in `lsq_unit.cc` after execution
             SquashCheckAfterExe(inst);
         }
     }
@@ -1717,6 +1719,8 @@ IEW::tick()
             !fromCommit->commitInfo[tid].squash &&
             !fromCommit->commitInfo[tid].robSquashing) {
 
+            // Marks some of the entries in the store queue as canWB and
+            // they will be moved to the store buffer when appropriate.
             ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
 
             ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);

src/cpu/o3/iew.hh

@@ -133,6 +133,7 @@ class IEW
 
   private:
 
+    /** The dispatch queue capacity */
     std::vector<uint32_t> dqSize;
 
     /** Overall stage status. */
@@ -253,11 +254,17 @@ class IEW
     /** Returns if the LSQ has any stores to writeback. */
     bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 
+    /** Just set the relevant flag in lsq and at the appropriate
+     * time, lsq will attempt to write the data in the store buffer
+     * back to the cache. returns true if there is no data in either
+     * the store queue or the store buffer to write back to.
+     */
     bool flushAllStores(ThreadID tid) { return ldstQueue.flushAllStores(tid); }
 
     /** Check if we need to squash after a load/store/branch is executed. */
     void SquashCheckAfterExe(DynInstPtr inst);
 
+    /** notify the mem_dep_unit */
     void notifyExecuted(const DynInstPtr &inst) { instQueue.notifyExecuted(inst); }
 
     /**
@@ -559,6 +566,7 @@ class IEW
         statistics::Vector dispatchStallReason;
     } iewStats;
 
+    /** The width that can be dispatched to the scheduler per cycle. */
     std::vector<StallReason> dispatchStalls;
 
     StallReason blockReason{NoStall};

src/cpu/o3/issue_queue.cc

@@ -382,6 +382,8 @@ IssueQue::selectInst()
     selectQ.clear();
     for (int pi = 0; pi < outports; pi++) {
         auto readyQ = readyQs[pi];
+
+        // move the cancel inst in the readyQ
         while (!readyQ->empty()) {
             auto top = readyQ->top();
             if (!top->canceled()) {
@@ -390,6 +392,7 @@ IssueQue::selectInst()
             top->clearInReadyQ();
             readyQ->pop();
         }
+
         if (!readyQ->empty()) {
             auto inst = readyQ->top();
             if (portBusy[pi] & (1llu << scheduler->getCorrectedOpLat(inst))) {
@@ -533,6 +536,12 @@ IssueQue::insert(const DynInstPtr& inst)
         assert(inst->readyToIssue());
     }
 
+
+    /** For memory-related instructions, memory dependency prediction is
+     * used to determine whether they can be out of order execution.
+     * -- pass the dependency check: instruction can be schedule.
+     * -- failed in dependency check: schedule in the store address be computered.
+     */
     if (inst->isMemRef()) {
         // insert and check memDep
         scheduler->memDepUnit[inst->threadNumber].insert(inst);

src/cpu/o3/issue_queue.hh

@@ -165,6 +165,7 @@ class IssueQue : public SimObject
     void insertNonSpec(const DynInstPtr& inst);
 
     void markMemDepDone(const DynInstPtr& inst);
+    /** move the mem inst to readyQ, and try it again. */
     void retryMem(const DynInstPtr& inst);
     bool idle();
 

src/cpu/o3/lsq.cc

@@ -1042,6 +1042,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
     }
 
     /* This is the place were instructions get the effAddr. */
+    /* Only atomic types can attempt to send requests to the cache at this stage.*/
     if (inst->isAtomic() && request->isTranslationComplete()) {
         if (request->isMemAccessRequired()) {
             inst->effAddr = request->getVaddr();

src/cpu/o3/lsq_unit.cc

@@ -1104,7 +1104,7 @@ LSQUnit::loadPipeS1(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
     Fault load_fault = inst->getFault();
     LSQRequest* request = inst->savedRequest;
 
-    // Cache access
+    // normal inst cache access
     if (request && request->isTranslationComplete()) {
         if (request->isMemAccessRequired()) {
             inst->effAddr = request->getVaddr();

src/cpu/o3/lsq_unit.hh

@@ -544,6 +544,12 @@ class LSQUnit
     /** Process instructions in each load pipeline stages. */
     void executeLoadPipeSx();
 
+    /**
+     * - stage0: normal inst access TLB, atomic access TLB and try send to cache.
+     * - stage1: normal inst try send to cache.
+     * - stage2: Analyze the flag and try to send the inst to commit.
+     * - stage3: now just return fault and do nothing.
+     */
     Fault loadPipeS0(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
     Fault loadPipeS1(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
     Fault loadPipeS2(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
@@ -552,6 +558,10 @@ class LSQUnit
     /** Process instructions in each store pipeline stages. */
     void executeStorePipeSx();
 
+    /**
+     * - stage0: access TLB
+     * - stage1: save data to store queue, check load violations, set memDepViolator
+     */
     Fault storePipeS0(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
     Fault storePipeS1(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
     Fault emptyStorePipeSx(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag, uint64_t stage);