mem: l2 cache use drrip replacement (#304)

Change-Id: I3b208d4796352cfb3b6519865d1f789aa111ff7c
OpenXiangShan · Feb 27, 2025 · a72aeb7 · a72aeb7
1 parent 8e0eada
commit a72aeb7
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diff --git a/configs/common/Caches.py b/configs/common/Caches.py
@@ -103,6 +103,8 @@ class L2Cache(Cache):
     # recvTimingResp serviceMSHR latency
     response_latency = 0
 
+    replacement_policy = DRRIPRP(constituency_size = 64, team_size = 8)
+
     cache_level = 2
     enable_wayprediction = False
 

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
@@ -814,7 +814,7 @@ Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)
                     .missLatency[tgt_pkt->req->requestorId()] +=
                     completion_time - target.recvTime;
                 stats.cmdStats(tgt_pkt)
-                    .missLatencyDist.sample((completion_time - target.recvTime)/500);
+                    .missLatencyDist.sample(ticksToCycles(completion_time - target.recvTime));
 
                 if (tgt_pkt->cmd == MemCmd::LockedRMWReadReq) {
                     // We're going to leave a target in the MSHR until the