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cpu: Fix topdown duplicate statistics load_stall and store_stall #283

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cpu: Fix topdown duplicate statistics load_stall and store_stall #283

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8 changes: 5 additions & 3 deletions src/cpu/o3/cpu.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -499,9 +499,11 @@ CPU::CPUStats::CPUStats(CPU *cpu)

Scheduler* scheduler = cpu->iew.getScheduler();
const auto &stats = scheduler->getStats();
// coreBound = (EXEC_STALL_CYCLE - MEMSTALL_ANYLOAD - MEMSTALL_STORE)/CPU_CYCLE
coreBound = (stats.exec_stall_cycle - stats.memstall_any_load - stats.memstall_any_store) / cpu->baseStats.numCycles;
memoryBound = (stats.memstall_any_load + stats.memstall_any_store) / cpu->baseStats.numCycles;
// coreBound = (EXEC_STALL_CYCLE - MEMSTALL_ANYLOAD - MEMSTALL_STORE + MENSTALL_BOTH_LOAD_STALL)/CPU_CYCLE
coreBound = (stats.exec_stall_cycle - stats.memstall_any_load - stats.memstall_any_store
+ stats.menstall_both_load_stall) / cpu->baseStats.numCycles;
memoryBound = (stats.memstall_any_load + stats.memstall_any_store
- stats.menstall_both_load_stall) / cpu->baseStats.numCycles;
l1Bound = (stats.memstall_any_load - stats.memstall_l1miss) / cpu->baseStats.numCycles;
l2Bound = (stats.memstall_l1miss - stats.memstall_l2miss) / cpu->baseStats.numCycles;
l3Bound = (stats.memstall_l2miss - stats.memstall_l3miss) / cpu->baseStats.numCycles;
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13 changes: 11 additions & 2 deletions src/cpu/o3/issue_queue.cc
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Expand Up @@ -784,17 +784,26 @@ Scheduler::issueAndSelect()
for (auto it : issueQues) {
it->issueToFu();
}
bool mentall_store = false, menstall_load = false;

if (instsToFu.size() < intel_fewops) {
stats.exec_stall_cycle++;
if (lsq->anyStoreNotExecute()) stats.memstall_any_store++;
if (lsq->anyStoreNotExecute()) {
stats.memstall_any_store++;
mentall_store = true;
}
}
if (instsToFu.size() == 0) {
int misslevel = lsq->anyInflightLoadsNotComplete();
if (misslevel != 0) stats.memstall_any_load++;
if (misslevel != 0) {
stats.memstall_any_load++;
menstall_load = true;
}
if ((misslevel & ((1<<1) - 1)) == ((1<<1) - 1)) stats.memstall_l1miss++;
if ((misslevel & ((1<<2) - 1)) == ((1<<2) - 1)) stats.memstall_l2miss++;
if ((misslevel & ((1<<3) - 1)) == ((1<<3) - 1)) stats.memstall_l3miss++;
}
stats.menstall_both_load_stall += (menstall_load && mentall_store);

// must wait for all insts was issued
for (auto it : issueQues) {
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1 change: 1 addition & 0 deletions src/cpu/o3/issue_queue.hh
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Expand Up @@ -222,6 +222,7 @@ class Scheduler : public SimObject
statistics::Scalar memstall_l1miss;
statistics::Scalar memstall_l2miss;
statistics::Scalar memstall_l3miss;
statistics::Scalar menstall_both_load_stall;
} stats;

struct disp_policy
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