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cpu-o3: align fcvt, fmv's latency #287

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Feb 18, 2025
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cpu-o3: align fcvt, fmv's latency #287

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12 changes: 6 additions & 6 deletions src/arch/riscv/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -2133,15 +2133,15 @@ decode QUADRANT default Unknown::unknown() {
if ((Rd&0x80000000) != 0) {
Rd |= (0xFFFFFFFFULL << 32);
}
}}, FloatCvtOp);
}}, FloatMvOp);
0x1: fclass_s({{
Rd = f32_classify(f32(freg(Fs1_bits)));
}}, FloatMiscOp);
}
0x71: decode ROUND_MODE {
0x0: fmv_x_d({{
Rd = freg(Fs1_bits).v;
}}, FloatCvtOp);
}}, FloatMvOp);
0x1: fclass_d({{
Rd = f64_classify(f64(freg(Fs1_bits)));
}}, FloatMiscOp);
Expand All @@ -2152,7 +2152,7 @@ decode QUADRANT default Unknown::unknown() {
if ((Rd&0x8000) != 0) {
Rd |= (0xFFFFFFFFFFFFULL << 16);
}
}}, FloatCvtOp);
}}, FloatMvOp);
0x1: fclass_h({{
Rd = f16_classify(f16(freg(Fs1_bits)));
}}, FloatMiscOp);
Expand All @@ -2163,19 +2163,19 @@ decode QUADRANT default Unknown::unknown() {
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
}}, FloatMvOp);
0x79: fmv_d_x({{
freg_t fd;
fd = freg(f64(Rs1));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
}}, FloatMvOp);
0x7a: fmv_h_x({{
freg_t fd;
fd = freg(f16(Rs1_uh));
Fd_bits = fd.v;
}}, FloatCvtOp);
}}, FloatMvOp);
}
}

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6 changes: 3 additions & 3 deletions src/cpu/FuncUnit.py
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Expand Up @@ -40,9 +40,9 @@
from m5.params import *

class OpClass(Enum):
vals = ['No_OpClass', 'IntAlu', 'IntBr', 'IntMult', 'IntDiv', 'FloatAdd',
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv',
'FloatMisc', 'FloatSqrt',
vals = ['No_OpClass', 'IntAlu', 'IntBr', 'IntMult', 'IntDiv',
'FloatAdd', 'FloatMult', 'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
'FloatCmp', 'FloatCvt', 'FloatMv','FloatMisc',
'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu',
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3 changes: 2 additions & 1 deletion src/cpu/o3/FuncUnitConfig.py
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Expand Up @@ -87,7 +87,8 @@ class FP_ALU(FUDesc):
OpDesc(opClass='FloatMult', opLat=4)]

class FP_MISC(FUDesc):
opList = [ OpDesc(opClass='FloatCvt', opLat=3)]
opList = [ OpDesc(opClass='FloatCvt', opLat=5), # float -> int 5 cycles, int -> float 7 cycle
OpDesc(opClass='FloatMv', opLat=5)]

class FP_MAC(FUDesc):
opList = [ OpDesc(opClass='FMAAcc', opLat=2),
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7 changes: 6 additions & 1 deletion src/cpu/o3/issue_queue.cc
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Expand Up @@ -1097,13 +1097,18 @@ Scheduler::bypassWriteback(const DynInstPtr& inst)
uint32_t
Scheduler::getOpLatency(const DynInstPtr& inst)
{
if (inst->opClass() == FloatCvtOp) [[unlikely]] {
if (inst->destRegIdx(0).isFloatReg()) {
return 2 + opExecTimeTable[inst->opClass()];
}
}
return opExecTimeTable[inst->opClass()];
}

uint32_t
Scheduler::getCorrectedOpLat(const DynInstPtr& inst)
{
uint32_t oplat = opExecTimeTable[inst->opClass()];
uint32_t oplat = getOpLatency(inst);
oplat += inst->isLoad() ? 2 : 0;
return oplat;
}
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1 change: 1 addition & 0 deletions src/cpu/op_class.hh
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Expand Up @@ -60,6 +60,7 @@ static const OpClass IntDivOp = enums::IntDiv;
static const OpClass FloatAddOp = enums::FloatAdd;
static const OpClass FloatCmpOp = enums::FloatCmp;
static const OpClass FloatCvtOp = enums::FloatCvt;
static const OpClass FloatMvOp = enums::FloatMv;
static const OpClass FloatMultOp = enums::FloatMult;
static const OpClass FloatMultAccOp = enums::FloatMultAcc;
static const OpClass FloatDivOp = enums::FloatDiv;
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