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mem: l2 cache use drrip replacement #304

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merged 1 commit into from
Feb 27, 2025
Merged

mem: l2 cache use drrip replacement #304

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2 changes: 2 additions & 0 deletions configs/common/Caches.py
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,8 @@ class L2Cache(Cache):
# recvTimingResp serviceMSHR latency
response_latency = 0

replacement_policy = DRRIPRP(constituency_size = 64, team_size = 8)

cache_level = 2
enable_wayprediction = False

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2 changes: 1 addition & 1 deletion src/mem/cache/cache.cc
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Expand Up @@ -814,7 +814,7 @@ Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)
.missLatency[tgt_pkt->req->requestorId()] +=
completion_time - target.recvTime;
stats.cmdStats(tgt_pkt)
.missLatencyDist.sample((completion_time - target.recvTime)/500);
.missLatencyDist.sample(ticksToCycles(completion_time - target.recvTime));

if (tgt_pkt->cmd == MemCmd::LockedRMWReadReq) {
// We're going to leave a target in the MSHR until the
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