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Spi flash samples #7

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Jun 26, 2020
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17 changes: 13 additions & 4 deletions boards/arm/quick_feather/quick_feather.dts
100644 → 100755
Original file line number Diff line number Diff line change
Expand Up @@ -132,8 +132,8 @@
* 0x0001ffff (sectors 16-31) is reserved for use
* by the application.
*/
storage_partition: partition@10000 {
label = "storage";
metadata_partition: partition@10000 {
label = "metadata";
reg = <0x00010000 0x00010000>;
};

Expand All @@ -145,9 +145,18 @@
label = "image-1";
reg = <0x00040000 0x00020000>;
};
scratch_partition: partition@60000 {
label = "image-scratch";
slot2_partition: partition@60000 {
label = "image-2";
reg = <0x00060000 0x00020000>;
};
slot3_partition: partition@80000 {
label = "image-3";
reg = <0x00080000 0x00020000>;
};
storage_partition: partition@100000 {
label = "storage";
reg = <0x00100000 0x00010000>;
};

};
};
2 changes: 0 additions & 2 deletions samples/drivers/spi_flash/src/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -68,8 +68,6 @@ void main(void)
printf("Flash write failed! %d\n", rc);
return;
}
// Sleep for a while
k_sleep(100); //in ms

memset(buf, 0, len);
rc = flash_read(flash_dev, FLASH_TEST_REGION_OFFSET, buf, len);
Expand Down
5 changes: 5 additions & 0 deletions soc/arm/quicklogic_eos_s3/soc.c
Original file line number Diff line number Diff line change
Expand Up @@ -150,6 +150,11 @@ static void eos_s3_cru_init(void)
/* Set divider for domain C11 to ~ 5.12MHz */
CRU->CLK_CTRL_D_0 = (CLK_CTRL_CLK_DIVIDER_ENABLE |
CLK_CTRL_CLK_DIVIDER_RATIO_12);

/* Set C02 clock to default value,
* if any prev app such as boot loader changes it will be set back
*/
CRU->CLK_CTRL_B_0 = 0x204;
}

#ifdef CONFIG_SOC_EOS_S3_FPGA
Expand Down