Merge pull request #15718 from bergzand/pr/rv32i/fe310_rv32i_refactor

riscv_common: Refactor common fe310 code to riscv_common
RIOT-OS · Feb 8, 2021 · 50cf93c · 50cf93c
2 parents 83fbde1 + 19bb182
commit 50cf93c
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Showing 53 changed files with 481 additions and 282 deletions.
diff --git a/boards/hifive1b/include/periph_conf.h b/boards/hifive1b/include/periph_conf.h
@@ -21,6 +21,8 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+#include "kernel_defines.h"
+#include "macros/units.h"
 #include "periph_cpu.h"
 #include "clk_conf.h"
 

diff --git a/cpu/fe310/Kconfig b/cpu/fe310/Kconfig
@@ -5,31 +5,15 @@
 # directory for more details.
 #
 
-config CPU_ARCH_RISCV
-    bool
-    select HAS_ARCH_RISCV
-    select HAS_NEWLIB
-    select HAS_PICOLIBC if '$(RIOT_CI_BUILD)' != '1'
-    select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
-
-config CPU_CORE_RV32M
-    bool
-    select CPU_ARCH_RISCV
-    select HAS_ARCH_32BIT
-
 config CPU_FAM_FE310
     bool
-    select CPU_CORE_RV32M
+    select CPU_CORE_RV32I
     select HAS_CPU_FE310
     select HAS_PERIPH_CPUID
     select HAS_PERIPH_GPIO
     select HAS_PERIPH_GPIO_IRQ
-    select HAS_PERIPH_PLIC
     select HAS_PERIPH_PM
     select HAS_PERIPH_WDT
-    select HAS_CPP
-    select HAS_LIBSTDCPP
-    select HAS_SSP
 
 config CPU_MODEL_FE310_G000
     bool
@@ -39,24 +23,12 @@ config CPU_MODEL_FE310_G002
     bool
     select CPU_FAM_FE310
 
-## Definition of specific features
-config HAS_ARCH_RISCV
-    bool
-    help
-        Indicates that the current CPU has a RISC-V.
-
 ## Definition of specific features
 config HAS_CPU_FE310
     bool
     help
         Indicates that a 'fe310' cpu is being used.
 
-config CPU_ARCH
-    default "risc-v" if CPU_ARCH_RISCV
-
-config CPU_CORE
-    default "rv32m" if CPU_CORE_RV32M
-
 config CPU_FAM
     default "fe310" if CPU_FAM_FE310
 
@@ -68,3 +40,5 @@ config CPU
     default "fe310" if CPU_FAM_FE310
 
 rsource "Kconfig.clk"
+
+source "$(RIOTCPU)/riscv_common/Kconfig"
diff --git a/cpu/fe310/Makefile b/cpu/fe310/Makefile
@@ -2,6 +2,6 @@
 MODULE = cpu
 
 # add a list of subdirectories, that should also be built
-DIRS = periph vendor
+DIRS = $(RIOTCPU)/riscv_common periph vendor
 
 include $(RIOTBASE)/Makefile.base
diff --git a/cpu/fe310/Makefile.dep b/cpu/fe310/Makefile.dep
@@ -5,16 +5,17 @@ ifneq (,$(filter newlib,$(USEMODULE)))
   USEMODULE += newlib_syscalls_default
 endif
 
-USEMODULE += sifive_drivers_fe310
-
 USEMODULE += periph
-USEMODULE += periph_pm
+USEMODULE += sifive_drivers_fe310
 
 FEATURES_REQUIRED += periph_plic
 
 ifneq (,$(filter periph_rtc,$(USEMODULE)))
   FEATURES_REQUIRED += periph_rtt
 endif
 
-# Make calls to malloc and friends thread-safe
-USEMODULE += malloc_thread_safe
+ifneq (,$(filter periph_timer,$(USEMODULE)))
+  FEATURES_REQUIRED += periph_coretimer
+endif
+
+include $(RIOTCPU)/riscv_common/Makefile.dep
diff --git a/cpu/fe310/Makefile.features b/cpu/fe310/Makefile.features
@@ -1,16 +1,6 @@
-FEATURES_PROVIDED += arch_32bit
-FEATURES_PROVIDED += arch_riscv
-FEATURES_PROVIDED += cpp
-FEATURES_PROVIDED += libstdcpp
-FEATURES_PROVIDED += newlib
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
-FEATURES_PROVIDED += periph_plic
 FEATURES_PROVIDED += periph_pm
 FEATURES_PROVIDED += periph_wdt
-FEATURES_PROVIDED += ssp
 
-# RISC-V toolchain on CI does not work properly with picolibc yet
-ifeq (,$(RIOT_CI_BUILD))
-  FEATURES_PROVIDED += picolibc
-endif
+include $(RIOTCPU)/riscv_common/Makefile.features
diff --git a/cpu/fe310/Makefile.include b/cpu/fe310/Makefile.include
@@ -11,24 +11,4 @@ else ifeq ($(CPU_MODEL), fe310_g002)
   ROM_LEN ?= 0x0006a120
 endif
 
-# All variables must be defined in the CPU configuration when using the common
-# `ldscripts/fe310.ld`
-ifneq (,$(ROM_START_ADDR)$(RAM_START_ADDR)$(ROM_LEN)$(RAM_LEN))
-  $(if $(ROM_START_ADDR),,$(error ROM_START_ADDR is not defined))
-  $(if $(RAM_START_ADDR),,$(error RAM_START_ADDR is not defined))
-  $(if $(ROM_LEN),,$(error ROM_LEN is not defined))
-  $(if $(RAM_LEN),,$(error RAM_LEN is not defined))
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_rom_start_addr=$(ROM_START_ADDR)
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_start_addr=$(RAM_START_ADDR)
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_rom_length=$(ROM_LEN)
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_length=$(RAM_LEN)
-endif
-
-ifneq (,$(ITIM_START_ADDR))
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_itim_start_addr=$(ITIM_START_ADDR)
-  LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_itim_length=$(ITIM_LEN)
-endif
-
-LINKER_SCRIPT ?= fe310.ld
-
-include $(RIOTMAKE)/arch/riscv.inc.mk
+include $(RIOTCPU)/riscv_common/Makefile.include
diff --git a/cpu/fe310/clock.c b/cpu/fe310/clock.c
@@ -26,7 +26,7 @@
 static uint32_t _cpu_frequency = 0;
 #endif
 
-void clock_init(void)
+void fe310_clock_init(void)
 {
     /* Ensure that we aren't running off the PLL before we mess with it. */
     if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {

diff --git a/cpu/fe310/cpu.c b/cpu/fe310/cpu.c
@@ -21,8 +21,7 @@
 #include "periph/init.h"
 #include "periph_conf.h"
 
-#include "vendor/encoding.h"
-#include "vendor/plic_driver.h"
+#include "vendor/riscv_csr.h"
 
 #include "stdio_uart.h"
 
@@ -95,7 +94,7 @@ void flash_init(void)
 void cpu_init(void)
 {
     /* Initialize clock */
-    clock_init();
+    fe310_clock_init();
 
 #if USE_CLOCK_HFROSC_PLL
     /* Initialize flash memory, only when using the PLL: in this
@@ -104,14 +103,8 @@ void cpu_init(void)
     flash_init();
 #endif
 
-    /* Enable FPU if present */
-    if (read_csr(misa) & (1 << ('F' - 'A'))) {
-        write_csr(mstatus, MSTATUS_FS); /* allow FPU instructions without trapping */
-        write_csr(fcsr, 0);             /* initialize rounding mode, undefined at reset */
-    }
-
-    /* Initialize IRQs */
-    irq_init();
+    /* Common RISC-V initialization */
+    riscv_init();
 
     /* Initialize stdio */
     stdio_init();

diff --git a/cpu/fe310/doc.txt b/cpu/fe310/doc.txt
@@ -0,0 +1,9 @@
+/**
+ * @defgroup        cpu_fe310 SiFive fe310
+ * @ingroup         cpu
+ * @brief           SiFive fe310 RISC-V MCU specific implementation.
+ *
+ * This module contains SiFive fe310 specific code and definition.
+ *
+ * @see cpu_riscv_common
+ */
diff --git a/cpu/fe310/include/clk_conf.h b/cpu/fe310/include/clk_conf.h
@@ -20,6 +20,7 @@
 #define CLK_CONF_H
 
 #include "macros/units.h"
+#include "kernel_defines.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/cpu/fe310/include/cpu.h b/cpu/fe310/include/cpu.h
diff --git a/cpu/fe310/include/cpu_conf.h b/cpu/fe310/include/cpu_conf.h
@@ -19,34 +19,22 @@
 #ifndef CPU_CONF_H
 #define CPU_CONF_H
 
-/**
- * @name Configuration of default stack sizes
- * @{
- */
-#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
-#define THREAD_EXTRA_STACKSIZE_PRINTF   (256)
-#endif
-#ifndef THREAD_STACKSIZE_DEFAULT
-#define THREAD_STACKSIZE_DEFAULT        (1024)
-#endif
-#ifndef THREAD_STACKSIZE_IDLE
-#define THREAD_STACKSIZE_IDLE           (256)
+#include "cpu_conf_common.h"
+#include "vendor/platform.h"
+
+#ifdef __cplusplus
+extern "C" {
 #endif
-/** @} */
 
 /**
- * @brief   Declare the heap_stats function as available
+ * @brief Base address of the CLINT
  */
-#define HAVE_HEAP_STATS
+#define CLINT_BASE_ADDR     (CLINT_CTRL_ADDR)
 
 /**
- * @brief   This arch uses the inlined irq API.
+ * @brief Base address of the PLIC peripheral
  */
-#define IRQ_API_INLINED     (1)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
+#define PLIC_BASE_ADDR      (PLIC_CTRL_ADDR)
 
 #ifdef __cplusplus
 }