fixup! fixup! fixup! riscv_common: Refactor common fe310 code to risc…

…v_common
RIOT-OS · Feb 4, 2021 · 55a4760 · 55a4760
1 parent 2fd20b6
commit 55a4760
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Showing 5 changed files with 9 additions and 2 deletions.
diff --git a/cpu/fe310/Kconfig b/cpu/fe310/Kconfig
@@ -12,6 +12,7 @@ config CPU_FAM_FE310
     select HAS_PERIPH_CPUID
     select HAS_PERIPH_GPIO
     select HAS_PERIPH_GPIO_IRQ
+    select HAS_PERIPH_PM
     select HAS_PERIPH_WDT
 
 config CPU_MODEL_FE310_G000
@@ -39,3 +40,5 @@ config CPU
     default "fe310" if CPU_FAM_FE310
 
 rsource "Kconfig.clk"
+
+source "$(RIOTCPU)/riscv_common/Kconfig"
diff --git a/cpu/fe310/Makefile.features b/cpu/fe310/Makefile.features
@@ -1,5 +1,6 @@
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
+FEATURES_PROVIDED += periph_pm
 FEATURES_PROVIDED += periph_wdt
 
 include $(RIOTCPU)/riscv_common/Makefile.features
diff --git a/cpu/riscv_common/Kconfig b/cpu/riscv_common/Kconfig
@@ -12,7 +12,6 @@ config CPU_ARCH_RISCV
     select HAS_NEWLIB
     select HAS_PERIPH_CORETIMER
     select HAS_PERIPH_PLIC
-    select HAS_PERIPH_PM
     select HAS_PICOLIBC if '$(RIOT_CI_BUILD)' != '1'
     select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
     select HAS_SSP

diff --git a/cpu/riscv_common/Makefile.features b/cpu/riscv_common/Makefile.features
@@ -5,7 +5,6 @@ FEATURES_PROVIDED += libstdcpp
 FEATURES_PROVIDED += newlib
 FEATURES_PROVIDED += periph_coretimer
 FEATURES_PROVIDED += periph_plic
-FEATURES_PROVIDED += periph_pm
 FEATURES_PROVIDED += ssp
 
 # RISC-V toolchain on CI does not work properly with picolibc yet

diff --git a/kconfigs/Kconfig.features b/kconfigs/Kconfig.features
@@ -94,6 +94,11 @@ config HAS_PERIPH_CAN
     help
         Indicates that a CAN peripheral is present.
 
+config HAS_PERIPH_CORETIMER
+    bool
+    help
+        Indicates that the CLINT timer can be used as timer peripheral
+
 config HAS_PERIPH_CPUID
     bool
     help