Merge #19077

19077: cpu/esp32: configurable linker scripts r=benpicco a=gschorcht

### Contribution description

This PR provides configurable linker scripts for ESP32x SoCs.

Using the vendor `memory.ld.in` file and a `sections.ld.in` file instead of the static versions of these files, from which the actual used `memory.ld` and  `sections.ld` are generated using the C preprocessor, allows to use the configuration in `sdkconfig.h` as well as Kconfig to define a custom memory layout. For example, it is no longer necessary to maintain different `memory.ld` files for the ESP32 BLE module, since the memory layout is now defined from the values of the configuration.

Note for the review: The `memory.ld.in` files are now simply copies of the manufacturer's `memory.ld.in` files. However, it is not possible to use the vendor's `memory.ld.in` files directly, because they have to be extended further on, e.g. for the `periph_flashpage` implementation.

This PR is prerequisite for the `periph_flashpage` support in PR #19079.

### Testing procedure

Green CI.

### Issues/PRs references

Prerequisite for PR #19079

Co-authored-by: Gunar Schorcht <[email protected]>

Makefile.include

@@ -731,7 +731,7 @@ else
 link: ..compiler-check ..build-message $(BASELIBS) $(ARCHIVES) ..module-check
 endif # RIOTNOLINK
 
-$(ELFFILE): $(BASELIBS) $(ARCHIVES)
+$(ELFFILE): $(BASELIBS) $(ARCHIVES) $(LD_SCRIPTS)
 	$(Q)$(_LINK) -o $@
 
 .PHONY: $(APPLICATION_MODULE).module

cpu/esp32/Makefile.include

@@ -168,12 +168,8 @@ endif
 
 LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/
 
-ifneq (,$(filter esp32_sdk_lib_bt_esp32,$(USEPKG)))
-  LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/memory_bt.ld
-else
-  LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/memory.ld
-endif
-LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/sections.ld
+LINKFLAGS += -T$(BINDIR)/memory.ld
+LINKFLAGS += -T$(BINDIR)/sections.ld
 
 LINKFLAGS += -T$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/ld/$(CPU_FAM).peripherals.ld
 LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.api.ld
@@ -251,4 +247,14 @@ ifneq (,$(filter esp_jtag,$(USEMODULE)))
   OPENOCD_DBG_EXTRA_CMD += -c 'reset halt'
 endif
 
+LD_SCRIPTS += $(BINDIR)/memory.ld $(BINDIR)/sections.ld
+
+$(BINDIR)/memory.ld: $(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/memory.ld.in \
+                     $(BINDIR)/riotbuild/riotbuild.h pkg-prepare
+	$(Q)$(CC) -DLD_FILE_GEN $(INCLUDES) -include '$(BINDIR)/riotbuild/riotbuild.h' \
+				-I$(RIOTCPU)/$(CPU)/ld -P -x c -E $< -o $@
+$(BINDIR)/sections.ld: $(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/sections.ld.in \
+                       $(BINDIR)/riotbuild/riotbuild.h pkg-prepare
+	$(Q)$(CC) -DLD_FILE_GEN -include '$(BINDIR)/riotbuild/riotbuild.h' -C -P -x c -E $< -o $@
+
 $(BOOTLOADER_BIN):

cpu/esp32/include/sdkconfig.h

@@ -27,7 +27,7 @@
  * header. To avoid having to patch all these files, `stdlib.h` is included
  * in this header file, which in turn is included by every ESP-IDF file.
  */
-#ifndef __ASSEMBLER__
+#if !defined(__ASSEMBLER__) && !defined(LD_FILE_GEN)
 #include <stdlib.h>
 #endif
 

cpu/esp32/ld/esp32/memory.ld → cpu/esp32/ld/esp32/memory.ld.in

@@ -19,41 +19,57 @@
    Please use preprocessor features sparingly! Restrict
    to simple macros with numeric values, and/or #if/#endif blocks.
 */
-/*
- * Automatically generated file. DO NOT EDIT.
- * Espressif IoT Development Framework (ESP-IDF) Configuration Header
- */
+#include "sdkconfig.h"
+#include "ld.common"
 
-/* List of deprecated options */
-/*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* CPU instruction prefetch padding size for flash mmap scenario */
-_esp_flash_mmap_prefetch_pad_size = 16;
-/* CPU instruction prefetch padding size for memory protection scenario */
-_esp_memprot_prefetch_pad_size = 0;
-/* Memory alignment size for PMS */
-_esp_memprot_align_size = 0;
 /* If BT is not built at all */
+#ifndef CONFIG_BTDM_RESERVE_DRAM
+#define CONFIG_BTDM_RESERVE_DRAM 0
+#endif
+
+#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
+#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
+#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
+#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
+#else
+#define ESP_BOOTLOADER_RESERVE_RTC 0
+#endif
+
+#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
+
+ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
+          "Fixed static ram data does not fit.")
+
+#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE
+
+#else
+#define DRAM0_0_SEG_LEN 0x2c200
+#endif
+
 MEMORY
 {
   /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
   of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
   are connected to the data port of the CPU and eg allow bytewise access. */
+
   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
-  iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Even though the segment name is iram, it is actually mapped to flash
   */
-  iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20
+  iram0_2_seg (RX) :                 org = 0x400D0020, len = 0x330000-0x20
+
   /*
     (0x20 offset above is a convenience for the app binary image generation.
     Flash cache has 64KB pages. The .bin file which is flashed to the chip
     has a 0x18 byte file header, and each segment has a 0x08 byte segment
     header. Setting this offset makes it simple to meet the flash cache MMU's
     constraint that (paddr % 64KB == vaddr % 64KB).)
   */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
 
      Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -63,41 +79,73 @@ MEMORY
      in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
      additional static memory temporarily cannot be used.
   */
-  dram0_0_seg (RW) : org = 0x3FFB0000 + 0,
-                                     len = 0x2c200 - 0
+  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BTDM_RESERVE_DRAM,
+                                     len = DRAM0_0_SEG_LEN - CONFIG_BTDM_RESERVE_DRAM
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
-  drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
+  drom0_0_seg (R) :                  org = 0x3F400020, len = 0x400000-0x20
+
   /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
   /* RTC fast memory (executable). Persists over deep sleep.
    */
-  rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - 0
+  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000
+
   /* RTC fast memory (same block as above), viewed from data bus */
-  rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - 0
+  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
+
   /* RTC slow memory (data accessible). Persists over deep sleep.
 
      Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
-  rtc_slow_seg(RW) : org = 0x50000000 + 0,
-                                     len = 0x2000 - 0
+  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
+                                     len = 0x2000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
+
   /* external memory */
-  extern_ram_seg(RWX) : org = 0x3F800000,
+  extern_ram_seg(RWX)  :             org = 0x3F800000,
                                      len = 0x400000
 }
+
+#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
+/* static data ends at defined address */
+_static_data_end = 0x3FFB0000 + DRAM0_0_SEG_LEN;
+#else
 _static_data_end = _bss_end;
+#endif
+
 /* Heap ends at top of dram0_0_seg */
-_heap_end = 0x40000000 - 0x0;
+_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
+
 _data_seg_org = ORIGIN(rtc_data_seg);
+
 /* The lines below define location alias for .rtc.data section based on Kconfig option.
    When the option is not defined then use slow memory segment
    else the data will be placed in fast memory segment */
+#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
 REGION_ALIAS("rtc_data_location", rtc_slow_seg );
+#else
+REGION_ALIAS("rtc_data_location", rtc_data_seg );
+#endif
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   REGION_ALIAS("default_code_seg", iram0_2_seg);
+#else
+  REGION_ALIAS("default_code_seg", iram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+#else
+  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
 /**
  *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
  *  also be first in the segment.
  */
-/* TODO
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   ASSERT(_rodata_start == ORIGIN(default_rodata_seg),
          ".flash.appdesc section must be placed at the beginning of the rodata segment.")
-*/
+#endif

cpu/esp32/ld/esp32/sections.ld → cpu/esp32/ld/esp32/sections.ld.in

@@ -18,6 +18,7 @@ SECTIONS
   .rtc.text :
   {
     . = ALIGN(4);
+    _rtc_text_start = ABSOLUTE(.);
 
     *(.rtc.literal .rtc.text .rtc.text.*)
 
@@ -452,6 +453,19 @@ SECTIONS
   . = 0x40000000;
   _eheap3 = ABSOLUTE(.);
 
+  .flash.appdesc : ALIGN(0x10)
+  {
+    _rodata_start = ABSOLUTE(.);
+
+    *(.rodata_desc .rodata_desc.*)               /* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! */
+    *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
+
+    /* Create an empty gap within this section. Thanks to this, the end of this
+     * section will match .flah.rodata's begin address. Thus, both sections
+     * will be merged when creating the final bin image. */
+    . = ALIGN(ALIGNOF(.flash.rodata));
+  } >default_rodata_seg
+
   _rodata_start = ABSOLUTE(.);
   .flash.rodata : ALIGN(0x10)
   {