fixup! fixup! fixup! riscv_common: Refactor common fe310 code to risc…

…v_common
RIOT-OS · Jan 15, 2021 · b045327 · b045327
1 parent 390dd43
commit b045327
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Showing 20 changed files with 70 additions and 1,371 deletions.
diff --git a/cpu/fe310/Makefile.dep b/cpu/fe310/Makefile.dep
@@ -13,3 +13,5 @@ FEATURES_REQUIRED += periph_plic
 ifneq (,$(filter periph_rtc,$(USEMODULE)))
   FEATURES_REQUIRED += periph_rtt
 endif
+
+include $(RIOTCPU)/riscv_common/Makefile.dep
diff --git a/cpu/fe310/cpu.c b/cpu/fe310/cpu.c
@@ -22,8 +22,7 @@
 #include "periph/init.h"
 #include "periph_conf.h"
 
-#include "vendor/encoding.h"
-#include "vendor/plic_driver.h"
+#include "vendor/riscv_csr.h"
 
 #include "stdio_uart.h"
 

diff --git a/cpu/fe310/include/cpu_conf.h b/cpu/fe310/include/cpu_conf.h
@@ -26,6 +26,8 @@
 extern "C" {
 #endif
 
+#define CLINT_BASE_ADDR     (CLINT_CTRL_ADDR)
+
 #ifdef __cplusplus
 }
 #endif
-Original file line number
+Diff line change
@@ Expand Up / @@ -26,6 +26,8 @@ @@
     extern "C" {
     #endif
+    #define CLINT_BASE_ADDR     (CLINT_CTRL_ADDR)
     #ifdef __cplusplus
     }
     #endif
@@ Expand Down @@