cpu/esp32: disable warnings in ESP-IDF for gcc 12.2

RIOT-OS · Apr 4, 2023 · d27423d · d27423d
1 parent 9ef732b
commit d27423d
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Showing 3 changed files with 16 additions and 0 deletions.
diff --git a/cpu/esp32/bootloader/Makefile b/cpu/esp32/bootloader/Makefile
@@ -164,6 +164,10 @@ INCLUDES = \
 # CONFIG_ESPTOOLPY_FLASHFREQ_* and CONFIG_FLASHMODE_*
 CFLAGS = -include '$(RIOTBUILD_CONFIG_HEADER_C)' \
 
+# TODO: required to be able to compile with GCC 12.1, remove them after upgrade to ESP-IDF 5.1
+CFLAGS += -Wno-error=format=
+CFLAGS += -Wno-format
+
 ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
   INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
   CFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV

diff --git a/cpu/esp32/esp-idf/esp_idf_cflags.mk b/cpu/esp32/esp-idf/esp_idf_cflags.mk
@@ -34,6 +34,14 @@ CFLAGS += -Wno-enum-compare
 # those are false positives.
 CFLAGS += -Wno-cast-align
 
+# TODO: required to be able to compile with GCC 12.1, remove them after upgrade to ESP-IDF 5.1
+CFLAGS += -Wno-attributes
+CFLAGS += -Wno-enum-conversion
+CFLAGS += -Wno-error=format=
+CFLAGS += -Wno-format
+CFLAGS += -Wno-use-after-free
+CFLAGS += -Wno-incompatible-pointer-types
+
 # additional CFLAGS required for RISC-V architecture
 ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
   INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include

diff --git a/cpu/esp32/esp-idf/nvs_flash/Makefile b/cpu/esp32/esp-idf/nvs_flash/Makefile
@@ -30,6 +30,10 @@ include ../esp_idf.mk
 # those are false positives.
 CFLAGS += -Wno-cast-align
 
+# TODO: required to be able to compile with GCC 12.1, remove them after upgrade to ESP-IDF 5.1
+CFLAGS += -Wno-error=format=
+CFLAGS += -Wno-format
+
 # additional CFLAGS required for RISC-V architecture
 ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
   CFLAGS += -Wno-error=format=