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cpu/stm32f0: define isr within macros
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@aabadie
aabadie committed Mar 10, 2017
1 parent 6cfa9b7 commit ea9edca
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65 changes: 65 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f030r8_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f030r8
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F030R8_ISR_H
#define STM32F030R8_ISR_H

#if defined(CPU_MODEL_STM32F030R8)

#define STM32F030R8_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) (0UL), /* reserved */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) (0UL), /* reserved */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) isr_tim6_dac, /* timer 6 and digital to analog converter */ \
(void*) isr_tim7, /* timer 7 */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) isr_tim15, /* timer 15 */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) isr_i2c2, /* I2C 2 */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) (0UL), /* reserved */ \
(void*) (0UL), /* reserved */ \
(void*) (0UL) /* reserved */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F030R8_ISR_H */
65 changes: 65 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f031k6_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f031k6
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F031K6_ISR_H
#define STM32F031K6_ISR_H

#if defined(CPU_MODEL_STM32F031K6)

#define STM32F031K6_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) isr_pvd, /* power control */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) isr_tim2, /* timer 2 */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) isr_tim6_dac, /* timer 6 and digital to analog converter */ \
(void*) isr_tim7, /* timer 7 */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) isr_tim15, /* timer 15 */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) isr_i2c2, /* I2C 2 */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) isr_usart3_8, /* USART 3 to 8 */ \
(void*) isr_cec, /* consumer electronics control */ \
(void*) (0UL) /* reserved */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F031K6_ISR_H */
65 changes: 65 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f042k6_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f042k6
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F042K6_ISR_H
#define STM32F042K6_ISR_H

#if defined(CPU_MODEL_STM32F042K6)

#define STM32F042K6_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) isr_pvd, /* power control */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) isr_tim2, /* timer 2 */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) (0UL), /* reserved */ \
(void*) (0UL), /* reserved */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) (0UL), /* reserved */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) (0UL), /* reserved */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) (0UL), /* reserved */ \
(void*) isr_cec, /* consumer electronics control */ \
(void*) (0UL) /* reserved */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F042K6_ISR_H */
66 changes: 66 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f051r8_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f051r8
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F051R8_ISR_H
#define STM32F051R8_ISR_H

#if defined(CPU_MODEL_STM32F051R8)

#define STM32F051R8_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) isr_pvd, /* power control */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) isr_tim2, /* timer 2 */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) isr_tim6_dac, /* timer 6 and digital to analog converter */ \
(void*) isr_tim7, /* timer 7 */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) isr_tim15, /* timer 15 */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) isr_i2c2, /* I2C 2 */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) (0UL), /* reserved */ \
(void*) isr_usart3_8, /* USART 3 to 8 */ \
(void*) isr_cec, /* consumer electronics control */ \
(void*) isr_usb /* USB */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F051R8_ISR_H */
65 changes: 65 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f070rb_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f070rb
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F070RB_ISR_H
#define STM32F070RB_ISR_H

#if defined(CPU_MODEL_STM32F070RB)

#define STM32F070RB_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) (0UL), /* reserved */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) (0UL), /* reserved */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) isr_tim6_dac, /* timer 6 and digital to analog converter */ \
(void*) (0UL), /* reserved */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) isr_tim15, /* timer 15 */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) isr_i2c2, /* I2C 2 */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) isr_usart3_4, /* USART 3 and 4 */ \
(void*) (0UL), /* reserved */ \
(void*) isr_usb /* USB */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F070RB_ISR_H */
65 changes: 65 additions & 0 deletions cpu/stm32f0/include/vectors/stm32f072rb_isr.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup cpu_stm32f0
* @{
*
* @file
* @brief Interrupt vector definitions for stm32f072rb
*
* @author Alexandre Abadie <[email protected]>
*
* @}
*/

#ifndef STM32F072RB_ISR_H
#define STM32F072RB_ISR_H

#if defined(CPU_MODEL_STM32F072RB)

#define STM32F072RB_VECTORS \
(void*) isr_wwdg, /* windowed watchdog */ \
(void*) isr_pvd, /* power control */ \
(void*) isr_rtc, /* real time clock */ \
(void*) isr_flash, /* flash memory controller */ \
(void*) isr_rcc, /* reset and clock control */ \
(void*) isr_exti, /* external interrupt lines 0 and 1 */ \
(void*) isr_exti, /* external interrupt lines 2 and 3 */ \
(void*) isr_exti, /* external interrupt lines 4 to 15 */ \
(void*) isr_ts, /* touch sensing input*/ \
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ \
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/ \
(void*) isr_dma1_ch4_5, /* direct memory access controller 1, channel 4 and 5*/ \
(void*) isr_adc1_comp, /* analog digital converter */ \
(void*) isr_tim1_brk_up_trg_com, /* timer 1 break, update, trigger and communication */ \
(void*) isr_tim1_cc, /* timer 1 capture compare */ \
(void*) isr_tim2, /* timer 2 */ \
(void*) isr_tim3, /* timer 3 */ \
(void*) isr_tim6_dac, /* timer 6 and digital to analog converter */ \
(void*) isr_tim7, /* timer 7 */ \
(void*) isr_tim14, /* timer 14 */ \
(void*) isr_tim15, /* timer 15 */ \
(void*) isr_tim16, /* timer 16 */ \
(void*) isr_tim17, /* timer 17 */ \
(void*) isr_i2c1, /* I2C 1 */ \
(void*) isr_i2c2, /* I2C 2 */ \
(void*) isr_spi1, /* SPI 1 */ \
(void*) isr_spi2, /* SPI 2 */ \
(void*) isr_usart1, /* USART 1 */ \
(void*) isr_usart2, /* USART 2 */ \
(void*) isr_usart3_4, /* USART 3 and 4 */ \
(void*) isr_cec, /* consumer electronics control */ \
(void*) isr_usb /* USB */
#endif

#ifdef __cplusplus
extern "C" {}
#endif

#endif /* STM32F072RB_ISR_H */
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