Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

cpu/samd21: Enable continuous read bit for periph_rtt #17403

Open
wants to merge 4 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 24 additions & 4 deletions cpu/sam0_common/periph/rtc_rtt.c
Original file line number Diff line number Diff line change
Expand Up @@ -122,12 +122,29 @@ static void _wait_syncbusy(void)
}
}

__attribute__((unused)) static void _enable_continuous_read(void)
{
#ifdef RTC_READREQ_RCONT
/* Re-enable Continuous Read as this bit is cleared by hardware
when we write in a write synchronized register */
RTC->MODE0.READREQ.bit.RCONT = 1;
RTC->MODE0.READREQ.bit.RREQ = 1;
_wait_syncbusy();
#endif
}

#if defined(MODULE_PERIPH_RTC) || defined(MODULE_PERIPH_RTT)
static void _read_req(void)
{
#ifdef RTC_READREQ_RREQ
RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ;
#if defined (RTC_READREQ_RREQ)
if (RTC->MODE0.READREQ.bit.RCONT) {
return;
}
else {
_enable_continuous_read();
}
#endif

_wait_syncbusy();
}
#endif
Expand Down Expand Up @@ -175,6 +192,7 @@ static inline void _rtt_reset(void)
{
#ifdef RTC_MODE0_CTRL_SWRST
RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_SWRST;
_wait_syncbusy();
while (RTC->MODE0.CTRL.bit.SWRST) {}
#else
RTC->MODE0.CTRLA.reg = RTC_MODE2_CTRLA_SWRST;
Expand Down Expand Up @@ -405,6 +423,7 @@ void rtt_init(void)
| RTC_MODE0_PRESCALER;
#endif
_wait_syncbusy();
_enable_continuous_read();

/* initially clear flag */
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0
Expand Down Expand Up @@ -709,6 +728,7 @@ void rtt_set_counter(uint32_t count)
{
RTC->MODE0.COUNT.reg = count;
_wait_syncbusy();
_enable_continuous_read();
}

uint32_t rtt_get_alarm(void)
Expand Down Expand Up @@ -743,9 +763,9 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)

/* set COMP register */
RTC->MODE0.COMP[0].reg = alarm;
_wait_syncbusy();

/* enable compare interrupt and clear flag */
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
/* enable compare interrupt */
RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;

/* block power mode if callback function is present */
Expand Down
1 change: 0 additions & 1 deletion cpu/samd21/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@ config CPU_COMMON_SAMD21
select CPU_CORE_CORTEX_M0PLUS
select HAS_CPU_SAMD21
select HAS_PERIPH_GPIO_FAST_READ
select MODULE_ZTIMER_NO_PERIPH_RTT if TEST_KCONFIG && MODULE_ZTIMER

config CPU_FAM_SAMD10
bool
Expand Down
5 changes: 2 additions & 3 deletions sys/ztimer/Makefile.dep
Original file line number Diff line number Diff line change
Expand Up @@ -73,11 +73,10 @@ endif
# NOTE: select the module here and not in the CPU so that order of inclusion
# does not have periph_rtt selected earlier that it should be while at the same
# time avoiding the module 'ztimer-no_periph_rtt' being included unecesarily.
# The samd21 rtt busy loops for 180us every time an alarm is set or
# The fe310 rtt busy loops for a long period every time an alarm is set or
# the counter is read, this propagates and leads to timing errors
# on ztimer_msec that are higher than > +-1msec.
# The same goes for the fe310 rtt.
ifneq (,$(filter samd21 fe310,$(CPU)))
ifneq (,$(filter fe310,$(CPU)))
USEMODULE += ztimer_no_periph_rtt
endif

Expand Down
8 changes: 0 additions & 8 deletions tests/periph_pm/Makefile.board.dep

This file was deleted.