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periph/spi: add support for printing and testing SPI clock rate (2nd) #18374

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periph/spi: add support for printing and testing SPI clock rate (2nd) #18374

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4da153d
periph/spi: printing and testing SPI clock rates
hugueslarrive Aug 12, 2021
3776278
kinetis/dist/calc_spi_scalers: removed from buildtest
hugueslarrive Sep 13, 2021
1dd8750
kinetis/doc: update SPI driver section
hugueslarrive Sep 13, 2021
1252a5e
checks/static-tests: remove trailing whitespaces
hugueslarrive Sep 13, 2021
9096819
tests/periph_spi: remove HAS_ARBITRARY_BUS_SPEED conditions
hugueslarrive Sep 13, 2021
66fefb6
boards/frdm-k22f: cleanup (fixes static-tests warnings)
hugueslarrive Sep 15, 2021
93b125f
kinetis/periph/spi: bugfix, enhancements and comments
hugueslarrive Sep 16, 2021
773c312
qn908x/periph/spi: some cleanup
hugueslarrive Sep 16, 2021
30149be
sam0_common/periph/spi: fix a small mistake
hugueslarrive Sep 16, 2021
d18cb3f
tests/periph_spi: remove a newline
hugueslarrive Sep 16, 2021
8087906
cpu/native/spi: dummy implementation
hugueslarrive Sep 17, 2021
371a9ac
sys/arduino: adapted to the new SPI API
hugueslarrive Sep 18, 2021
8ac0aac
drivers/soft_spi: adapted to match the new SPI API
hugueslarrive Sep 18, 2021
2e58849
tests/driver_nrf24l01p_lowlevel: adapted to the new SPI API
hugueslarrive Sep 19, 2021
8a8d198
pkg/*: adapted to the new SPI API
hugueslarrive Sep 19, 2021
4683b34
fixup! pkg/*: adapted to the new SPI API
hugueslarrive Sep 20, 2021
0d674ee
fixup! drivers/soft_spi: adapted to match the new SPI API
hugueslarrive Sep 20, 2021
f6da085
cpu/atxmega: removes a forgotten function
hugueslarrive Sep 23, 2021
efbc04e
Update cpu/atxmega/periph/spi.c
hugueslarrive Sep 23, 2021
f627aba
cpu/esp32: implementation of spi_get_clk and spi_get_freq
gschorcht Jul 27, 2022
d760711
cleanup murdock errors
MrKevinWeiss Jul 28, 2022
a0cbc16
noch mal
MrKevinWeiss Jul 28, 2022
36b1b11
cpu/nrf51/spi: clamp lower val
MrKevinWeiss Aug 3, 2022
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4 changes: 0 additions & 4 deletions .github/workflows/tools-buildtest.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -63,10 +63,6 @@ jobs:
uses: aabadie/riot-action@v1
with:
cmd: make -C cpu/stm32/dist/clk_conf
- name: Build kinetis calc_spi_scalers
uses: aabadie/riot-action@v1
with:
cmd: make -C cpu/kinetis/dist/calc_spi_scalers
- name: Build fixdep tool
uses: aabadie/riot-action@v1
with:
Expand Down
44 changes: 0 additions & 44 deletions boards/common/kw41z/include/periph_conf_common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -122,50 +122,6 @@ static const uart_conf_t uart_config[] = {
#define LPUART_0_SRC 3
/** @} */

/**
* @name SPI clock configuration
*
* Clock configuration values based on the configured 16Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) | /* -> 100000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | /* -> 400000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
)
};
/** @} */

/**
* @name Random Number Generator configuration
* @{
Expand Down
103 changes: 48 additions & 55 deletions boards/frdm-k22f/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -141,22 +141,54 @@ static const uart_conf_t uart_config[] = {
*/
static const adc_conf_t adc_config[] = {
/* dev, pin, channel */
[ 0] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0, .avg = ADC_AVG_MAX }, /* ADC0_DP0 */
[ 1] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19, .avg = ADC_AVG_MAX }, /* ADC0_DM0 */
[ 2] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0, .avg = ADC_AVG_MAX }, /* ADC1_DP0 */
[ 3] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19, .avg = ADC_AVG_MAX }, /* ADC1_DM0 */
[ 4] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* PTB0 (Arduino A0) */
[ 5] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* PTB1 (Arduino A1) */
[ 6] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* PTC1 (Arduino A2) */
[ 7] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4, .avg = ADC_AVG_MAX }, /* PTC2 (Arduino A3) */
[0] = { /* ADC0_DP0 */
.dev = ADC0, .pin = GPIO_UNDEF,
.chan = 0, .avg = ADC_AVG_MAX
},
[1] = { /* ADC0_DM0 */
.dev = ADC0, .pin = GPIO_UNDEF,
.chan = 19, .avg = ADC_AVG_MAX
},
[2] = { /* ADC1_DP0 */
.dev = ADC1, .pin = GPIO_UNDEF,
.chan = 0, .avg = ADC_AVG_MAX
},
[3] = { /* ADC1_DM0 */
.dev = ADC1, .pin = GPIO_UNDEF,
.chan = 19, .avg = ADC_AVG_MAX
},
[4] = { /* PTB0 (Arduino A0) */
.dev = ADC0, .pin = GPIO_PIN(PORT_B, 0),
.chan = 8, .avg = ADC_AVG_MAX
},
[5] = { /* PTB1 (Arduino A1) */
.dev = ADC0, .pin = GPIO_PIN(PORT_B, 1),
.chan = 9, .avg = ADC_AVG_MAX
},
[6] = { /* PTC1 (Arduino A2) */
.dev = ADC0, .pin = GPIO_PIN(PORT_C, 1),
.chan = 15, .avg = ADC_AVG_MAX
},
[7] = { /* PTC2 (Arduino A3) */
.dev = ADC0, .pin = GPIO_PIN(PORT_C, 2),
.chan = 4, .avg = ADC_AVG_MAX
},
/* internal: temperature sensor */
/* The temperature sensor has a very high output impedance, it must not be
* sampled using hardware averaging, or the sampled values will be garbage */
[ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 26, .avg = ADC_AVG_NONE },
/* The temperature sensor has a very high output impedance, it must
* not be sampled using hardware averaging, or the sampled values
* will be garbage */
[8] = {
.dev = ADC0, .pin = GPIO_UNDEF,
.chan = 26, .avg = ADC_AVG_NONE
},
/* internal: band gap */
/* Note: the band gap buffer uses a bit of current and is turned off by default,
* Set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading or the input will be floating */
[ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 27, .avg = ADC_AVG_MAX },
/* Note: the band gap buffer uses a bit of current and is turned off
* by default, set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading
* or the input will be floating */
[9] = {
.dev = ADC0, .pin = GPIO_UNDEF,
.chan = 27, .avg = ADC_AVG_MAX
},
};

#define ADC_NUMOF ARRAY_SIZE(adc_config)
Expand Down Expand Up @@ -191,47 +223,8 @@ static const pwm_conf_t pwm_config[] = {

/**
* @name SPI configuration
*
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};

* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
Expand Down
43 changes: 2 additions & 41 deletions boards/frdm-k64f/include/periph_conf.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -188,47 +188,8 @@ static const pwm_conf_t pwm_config[] = {

/**
* @name SPI configuration
*
* Clock configuration values based on the configured 30Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
)
};

* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
Expand Down
39 changes: 0 additions & 39 deletions boards/mulle/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -260,47 +260,8 @@ static const pwm_conf_t pwm_config[] = {

/**
* @name SPI configuration
*
* Clock configuration values based on the configured 47988736Hz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};

static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
Expand Down
39 changes: 0 additions & 39 deletions boards/openlabs-kw41z-mini/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -266,47 +266,8 @@ static const pwm_conf_t pwm_config[] = {

/**
* @name SPI configuration
*
* Clock configuration values based on the configured 16Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) | /* -> 100000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | /* -> 400000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
)
};

static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
Expand Down
39 changes: 0 additions & 39 deletions boards/pba-d-01-kw2x/include/periph_conf.h
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -174,47 +174,8 @@ static const pwm_conf_t pwm_config[] = {

/**
* @name SPI device configuration
*
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};

static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
Expand Down
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