cpu/rpx0xx/cmsis: Update vendor header files

boards/rpi-pico/include/board.h

@@ -34,9 +34,9 @@ extern "C" {
  * @{
  */
 #define LED0_PIN        GPIO_PIN(0, 25)
-#define LED0_ON         do {SIO->GPIO_OUT_SET.reg = 1UL << 25;} while (0)
-#define LED0_OFF        do {SIO->GPIO_OUT_CLR.reg = 1UL << 25;} while (0)
-#define LED0_TOGGLE     do {SIO->GPIO_OUT_XOR.reg = 1UL << 25;} while (0)
+#define LED0_ON         do {SIO->GPIO_OUT_SET = 1UL << 25;} while (0)
+#define LED0_OFF        do {SIO->GPIO_OUT_CLR = 1UL << 25;} while (0)
+#define LED0_TOGGLE     do {SIO->GPIO_OUT_XOR = 1UL << 25;} while (0)
 #define LED0_NAME       "LED(Green)"
 /** @} */
 

cpu/rpx0xx/clock.c

@@ -29,25 +29,25 @@
 
 static void _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_Enum source)
 {
-    io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos,
+    io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos,
                               CLOCKS_CLK_SYS_CTRL_SRC_Msk);
 }
 
 static void _clk_sys_set_aux_source(CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum source)
 {
-    io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos,
+    io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos,
                               CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk);
 }
 
 static void _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_Enum source)
 {
-    io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_SRC_Pos,
+    io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_SRC_Pos,
                               CLOCKS_CLK_REF_CTRL_SRC_Msk);
 }
 
 static void _clk_ref_set_aux_source(CLOCKS_CLK_REF_CTRL_AUXSRC_Enum source)
 {
-    io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos,
+    io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos,
                               CLOCKS_CLK_REF_CTRL_AUXSRC_Msk);
 }
 
@@ -66,7 +66,7 @@ void clock_sys_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CT
     /* switch the glitchless mux to clk_ref */
     _clk_sys_set_source(source);
     /* apply divider */
-    CLOCKS->CLK_SYS_DIV.reg = div;
+    CLOCKS->CLK_SYS_DIV = div;
     /* poll SELECTED until the switch is completed */
     while (!(CLOCKS->CLK_SYS_SELECTED & (1U << source))) { }
 }
@@ -83,7 +83,7 @@ void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out,
     /* change the auxiliary mux */
     _clk_sys_set_aux_source(aux);
     /* apply divider */
-    CLOCKS->CLK_SYS_DIV.reg = div;
+    CLOCKS->CLK_SYS_DIV = div;
     /* switch the glitchless mux to clk_sys_aux */
     _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux);
     /* poll SELECTED until the switch is completed */
@@ -98,7 +98,7 @@ void clock_ref_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CT
     /* switch the glitchless mux to clock source */
     _clk_ref_set_source(source);
     /* apply divider */
-    CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk;
+    CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk;
     /* poll SELECTED until the switch is completed */
     while (!(CLOCKS->CLK_REF_SELECTED & (1U << source))) { }
 }
@@ -115,7 +115,7 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out,
     /* change the auxiliary mux */
     _clk_ref_set_aux_source(aux);
     /* apply divider */
-    CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk;
+    CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk;
     /* switch the glitchless mux to clk_ref_aux */
     _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_clksrc_clk_ref_aux);
     /* poll SELECTED until the switch is completed */
@@ -124,56 +124,56 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out,
 
 void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux)
 {
-    io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos));
-    io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL.reg, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos,
+    io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos));
+    io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos,
                               CLOCKS_CLK_PERI_CTRL_AUXSRC_Msk);
-    io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos));
+    io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos));
 }
 
 void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux)
 {
     assert(f_out <= f_in);
     uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out;
-    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos);
-    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL.reg, aux);
-    CLOCKS->CLK_GPOUT0_DIV.reg = div;
-    io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos);
-    io_reg_atomic_set(&PADS_BANK0->GPIO21.reg, 1U << PADS_BANK0_GPIO21_IE_Pos);
+    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos);
+    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL, aux);
+    CLOCKS->CLK_GPOUT0_DIV = div;
+    io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos);
+    io_reg_atomic_set(&PADS_BANK0->GPIO21, 1U << PADS_BANK0_GPIO21_IE_Pos);
     gpio_set_function_select(21, FUNCTION_SELECT_CLOCK);
 }
 
 void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum aux)
 {
     assert(f_out <= f_in);
     uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out;
-    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos);
-    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL.reg, aux);
-    CLOCKS->CLK_GPOUT1_DIV.reg = div;
-    io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos);
-    io_reg_atomic_set(&PADS_BANK0->GPIO23.reg, 1U << PADS_BANK0_GPIO23_IE_Pos);
+    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos);
+    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL, aux);
+    CLOCKS->CLK_GPOUT1_DIV = div;
+    io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos);
+    io_reg_atomic_set(&PADS_BANK0->GPIO23, 1U << PADS_BANK0_GPIO23_IE_Pos);
     gpio_set_function_select(23, FUNCTION_SELECT_CLOCK);
 }
 
 void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum aux)
 {
     assert(f_out <= f_in);
     uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out;
-    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos);
-    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL.reg, aux);
-    CLOCKS->CLK_GPOUT2_DIV.reg = div;
-    io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos);
-    io_reg_atomic_set(&PADS_BANK0->GPIO24.reg, 1U << PADS_BANK0_GPIO24_IE_Pos);
+    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos);
+    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL, aux);
+    CLOCKS->CLK_GPOUT2_DIV = div;
+    io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos);
+    io_reg_atomic_set(&PADS_BANK0->GPIO24, 1U << PADS_BANK0_GPIO24_IE_Pos);
     gpio_set_function_select(24, FUNCTION_SELECT_CLOCK);
 }
 
 void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux)
 {
     assert(f_out <= f_in);
     uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out;
-    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos);
-    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL.reg, aux);
-    CLOCKS->CLK_GPOUT3_DIV.reg = div;
-    io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos);
-    io_reg_atomic_set(&PADS_BANK0->GPIO25.reg, 1U << PADS_BANK0_GPIO25_IE_Pos);
+    io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos);
+    _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL, aux);
+    CLOCKS->CLK_GPOUT3_DIV = div;
+    io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos);
+    io_reg_atomic_set(&PADS_BANK0->GPIO25, 1U << PADS_BANK0_GPIO25_IE_Pos);
     gpio_set_function_select(25, FUNCTION_SELECT_CLOCK);
 }

cpu/rpx0xx/include/io_reg.h

@@ -121,7 +121,7 @@ static inline void io_reg_atomic_clear(volatile uint32_t *reg, uint32_t mask)
  *
  * Example use:
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.c}
- * io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos,
+ * io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos,
  *                           CLOCKS_CLK_SYS_CTRL_SRC_Msk);
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */

cpu/rpx0xx/include/periph_cpu.h

@@ -487,7 +487,7 @@ static inline void gpio_reset_all_config(uint8_t pin)
  */
 static inline void periph_reset(uint32_t components)
 {
-    io_reg_atomic_set(&RESETS->RESET.reg, components);
+    io_reg_atomic_set(&RESETS->RESET, components);
 }
 
 /**
@@ -498,8 +498,8 @@ static inline void periph_reset(uint32_t components)
  */
 static inline void periph_reset_done(uint32_t components)
 {
-    io_reg_atomic_clear(&RESETS->RESET.reg, components);
-    while ((~RESETS->RESET_DONE.reg) & components) { }
+    io_reg_atomic_clear(&RESETS->RESET, components);
+    while ((~RESETS->RESET_DONE) & components) { }
 }
 
 /**

cpu/rpx0xx/periph/gpio.c

@@ -42,8 +42,8 @@ static void *_args[GPIO_PIN_NUMOF];
 int gpio_init(gpio_t pin, gpio_mode_t mode)
 {
     assert(pin < GPIO_PIN_NUMOF);
-    SIO->GPIO_OE_CLR.reg = 1LU << pin;
-    SIO->GPIO_OUT_CLR.reg = 1LU << pin;
+    SIO->GPIO_OE_CLR = 1LU << pin;
+    SIO->GPIO_OUT_CLR = 1LU << pin;
 
     switch (mode) {
     case GPIO_IN:
@@ -98,7 +98,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
             gpio_set_pad_config(pin, pad_config);
             gpio_set_io_config(pin, io_config);
         }
-        SIO->GPIO_OE_SET.reg = 1LU << pin;
+        SIO->GPIO_OE_SET = 1LU << pin;
         break;
     default:
         return -ENOTSUP;
@@ -108,27 +108,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
 
 int gpio_read(gpio_t pin)
 {
-    if (SIO->GPIO_OE.reg & (1LU << pin)) {
+    if (SIO->GPIO_OE & (1LU << pin)) {
         /* pin is output: */
-        return SIO->GPIO_OUT.reg & (1LU << pin);
+        return SIO->GPIO_OUT & (1LU << pin);
     }
     /* pin is input: */
-    return SIO->GPIO_IN.reg & (1LU << pin);
+    return SIO->GPIO_IN & (1LU << pin);
 }
 
 void gpio_set(gpio_t pin)
 {
-    SIO->GPIO_OUT_SET.reg = 1LU << pin;
+    SIO->GPIO_OUT_SET = 1LU << pin;
 }
 
 void gpio_clear(gpio_t pin)
 {
-    SIO->GPIO_OUT_CLR.reg = 1LU << pin;
+    SIO->GPIO_OUT_CLR = 1LU << pin;
 }
 
 void gpio_toggle(gpio_t pin)
 {
-    SIO->GPIO_OUT_XOR.reg = 1LU << pin;
+    SIO->GPIO_OUT_XOR = 1LU << pin;
 }
 
 void gpio_write(gpio_t pin, int value)
@@ -144,8 +144,8 @@ void gpio_write(gpio_t pin, int value)
 #ifdef MODULE_PERIPH_GPIO_IRQ
 static void _irq_enable(gpio_t pin, unsigned flank)
 {
-    volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0.reg;
-    volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg;
+    volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0;
+    volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0;
     /* There are 4 bits to control IRQs per pin, hence the configuration is split across multiple
      * I/O registers. The following calculates the position the four bits matching the given pin,
      * where idx refers to the I/O register and shift_amount to the position in the I/O register.
@@ -201,15 +201,15 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb
 void isr_io_bank0(void)
 {
     unsigned offset = 0;
-    volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0.reg;
-    volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg;
+    volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0;
+    volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0;
 
     DEBUG("[rp0x00] GPIO IRQ mask:      %08x, %08x, %08x, %08x\n",
-          (unsigned)IO_BANK0->PROC0_INTE0.reg, (unsigned)IO_BANK0->PROC0_INTE1.reg,
-          (unsigned)IO_BANK0->PROC0_INTE2.reg, (unsigned)IO_BANK0->PROC0_INTE3.reg);
+          (unsigned)IO_BANK0->PROC0_INTE0, (unsigned)IO_BANK0->PROC0_INTE1,
+          (unsigned)IO_BANK0->PROC0_INTE2, (unsigned)IO_BANK0->PROC0_INTE3);
     DEBUG("[rp0x00] GPIO IRQ status:    %08x, %08x, %08x, %08x\n",
-          (unsigned)IO_BANK0->PROC0_INTS0.reg, (unsigned)IO_BANK0->PROC0_INTS1.reg,
-          (unsigned)IO_BANK0->PROC0_INTS2.reg, (unsigned)IO_BANK0->PROC0_INTS3.reg);
+          (unsigned)IO_BANK0->PROC0_INTS0, (unsigned)IO_BANK0->PROC0_INTS1,
+          (unsigned)IO_BANK0->PROC0_INTS2, (unsigned)IO_BANK0->PROC0_INTS3);
 
     /* There are four IRQ status bits per pin, so there is info for 8 pins per I/O register.
      * We will iterate over all IRQ status I/O registers in the outer loop, and over all 8 pins

cpu/rpx0xx/periph/timer.c

@@ -88,14 +88,14 @@ static inline void _irq_enable(tim_t dev)
 {
     for (uint8_t i = 0; i < timer_config[dev].ch_numof; i++) {
         NVIC_EnableIRQ(timer_config[dev].ch[i].irqn);
-        io_reg_atomic_set(&DEV(dev)->INTE.reg, (1U << i));
+        io_reg_atomic_set(&DEV(dev)->INTE, (1U << i));
     }
 }
 
 static void _isr(tim_t dev, int channel)
 {
     /* clear latched interrupt */
-    io_reg_atomic_clear(&DEV(dev)->INTR.reg, 1U << channel);
+    io_reg_atomic_clear(&DEV(dev)->INTR, 1U << channel);
 
     if (_timer_is_periodic(dev, channel)) {
         if (_timer_reset_on_match(dev, channel)) {
@@ -118,15 +118,16 @@ int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg)
     }
     /* The timer must run at 1000000 Hz (µs precision)
        because the number of cycles per µs is shared with the watchdog.
-       The reference clock (clk_ref) is divided by WATCHDOG->TICK.bits.CYCLES
+       The reference clock (clk_ref) is divided by
+       (WATCHDOG->TICK & WATCHDOC_TICK_CYCLES_Mask)
        to generate µs ticks.
      */
     assert(freq == US_PER_SEC); (void)freq;
     _timer_ctx_cb[dev] = cb;
     _timer_ctx_arg[dev] = arg;
     periph_reset(RESETS_RESET_timer_Msk);
     periph_reset_done(RESETS_RESET_timer_Msk);
-    io_reg_write_dont_corrupt(&WATCHDOG->TICK.reg,
+    io_reg_write_dont_corrupt(&WATCHDOG->TICK,
                               (CLOCK_XOSC / MHZ(1)) << WATCHDOG_TICK_CYCLES_Pos,
                               WATCHDOG_TICK_CYCLES_Msk);
     _irq_enable(dev);
@@ -205,7 +206,7 @@ int timer_clear(tim_t dev, int channel)
         return -EINVAL;
     }
     /* ARMED bits are write clear */
-    io_reg_atomic_set(&DEV(dev)->ARMED.reg, (1 << channel));
+    io_reg_atomic_set(&DEV(dev)->ARMED, (1 << channel));
     unsigned state = irq_disable();
     _timer_disable_periodic(dev, channel);
     irq_restore(state);
@@ -223,13 +224,13 @@ unsigned int timer_read(tim_t dev)
 void timer_start(tim_t dev)
 {
     assert(dev < TIMER_NUMOF);
-    io_reg_atomic_clear(&DEV(dev)->PAUSE.reg, (1 << TIMER_PAUSE_PAUSE_Pos));
+    io_reg_atomic_clear(&DEV(dev)->PAUSE, (1 << TIMER_PAUSE_PAUSE_Pos));
 }
 
 void timer_stop(tim_t dev)
 {
     assert(dev < TIMER_NUMOF);
-    io_reg_atomic_set(&DEV(dev)->PAUSE.reg, (1 << TIMER_PAUSE_PAUSE_Pos));
+    io_reg_atomic_set(&DEV(dev)->PAUSE, (1 << TIMER_PAUSE_PAUSE_Pos));
 }
 
 /* timer 0 IRQ0 */

cpu/rpx0xx/periph/uart.c

@@ -48,7 +48,7 @@ static uint32_t uartcr;
 void _irq_enable(uart_t uart)
 {
     UART0_Type *dev = uart_config[uart].dev;
-    dev->UARTIMSC.reg = UART0_UARTIMSC_RXIM_Msk;
+    dev->UARTIMSC = UART0_UARTIMSC_RXIM_Msk;
     NVIC_EnableIRQ(uart_config[uart].irqn);
 }
 
@@ -72,8 +72,8 @@ void _set_symbolrate(uart_t uart, uint32_t baud)
         baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
     }
 
-    dev->UARTIBRD.reg = baud_ibrd;
-    dev->UARTFBRD.reg = baud_fbrd;
+    dev->UARTIBRD = baud_ibrd;
+    dev->UARTFBRD = baud_fbrd;
 }
 
 int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity,
@@ -82,7 +82,7 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity
     assert((unsigned)uart < UART_NUMOF);
     UART0_Type *dev = uart_config[uart].dev;
 
-    io_reg_atomic_clear(&dev->UARTCR.reg,
+    io_reg_atomic_clear(&dev->UARTCR,
                         UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk);
 
     /* Beware of strange hardware bug: If the configuration bitmask is prepared in register and
@@ -91,26 +91,26 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity
      * next char send out. If the configuration is updated in multiple bus accesses, it will apply
      * directly to the next char. So: Double check e.g. with tests/periph_uart_mode after touching
      * the initialization code here */
-    dev->UARTLCR_H.reg = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos;
+    dev->UARTLCR_H = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos;
 
     if (stop_bits == UART_STOP_BITS_2) {
-        io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_STP2_Msk);
+        io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_STP2_Msk);
     }
 
     switch (uart_parity) {
     case UART_PARITY_NONE:
         break;
     case UART_PARITY_EVEN:
-        io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+        io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
         break;
     case UART_PARITY_ODD:
-        io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_PEN_Msk);
+        io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
         break;
     default:
         return UART_NOMODE;
     }
 
-    io_reg_atomic_set(&dev->UARTCR.reg,
+    io_reg_atomic_set(&dev->UARTCR,
                       UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk);
 
     return UART_OK;
@@ -148,7 +148,7 @@ void uart_deinit_pins(uart_t uart)
 {
     assert((unsigned)uart < UART_NUMOF);
     gpio_reset_all_config(uart_config[uart].tx_pin);
-    SIO->GPIO_OE_CLR.reg = 1LU << uart_config[uart].tx_pin;
+    SIO->GPIO_OE_CLR = 1LU << uart_config[uart].tx_pin;
     if (ctx[uart].rx_cb) {
         gpio_reset_all_config(uart_config[uart].rx_pin);
     }
@@ -167,10 +167,10 @@ void uart_poweron(uart_t uart)
     _poweron(uart);
     UART0_Type *dev = uart_config[uart].dev;
     /* restore configuration registers */
-    dev->UARTIBRD.reg = uartibrd;
-    dev->UARTFBRD.reg = uartfbrd;
-    dev->UARTLCR_H.reg = uartlcr_h;
-    dev->UARTCR.reg = uartcr;
+    dev->UARTIBRD = uartibrd;
+    dev->UARTFBRD = uartfbrd;
+    dev->UARTLCR_H = uartlcr_h;
+    dev->UARTCR = uartcr;
     /* restore IRQs, if needed */
     if (ctx[uart].rx_cb != NULL) {
         _irq_enable(uart);
@@ -183,10 +183,10 @@ void uart_poweroff(uart_t uart)
     assert((unsigned)uart < UART_NUMOF);
     UART0_Type *dev = uart_config[uart].dev;
     /* backup configuration registers */
-    uartibrd = dev->UARTIBRD.reg;
-    uartfbrd = dev->UARTFBRD.reg;
-    uartlcr_h = dev->UARTLCR_H.reg;
-    uartcr = dev->UARTCR.reg;
+    uartibrd = dev->UARTIBRD;
+    uartfbrd = dev->UARTFBRD;
+    uartlcr_h = dev->UARTLCR_H;
+    uartcr = dev->UARTCR;
     /* disconnect GPIOs and power off peripheral */
     uart_deinit_pins(uart);
     periph_reset((uart) ? RESETS_RESET_uart1_Msk : RESETS_RESET_uart0_Msk);
@@ -217,10 +217,10 @@ int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg)
     if (rx_cb != NULL) {
         _irq_enable(uart);
         /* clear any pending data and IRQ to avoid receiving a garbage char */
-        uint32_t status = dev->UARTRIS.reg;
-        dev->UARTICR.reg = status;
-        (void)dev->UARTDR.reg;
-        io_reg_atomic_set(&dev->UARTCR.reg, UART0_UARTCR_RXE_Msk);
+        uint32_t status = dev->UARTRIS;
+        dev->UARTICR = status;
+        (void)dev->UARTDR;
+        io_reg_atomic_set(&dev->UARTCR, UART0_UARTCR_RXE_Msk);
     }
 
     return UART_OK;
@@ -232,8 +232,8 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
     UART0_Type *dev = uart_config[uart].dev;
 
     for (size_t i = 0; i < len; i++) {
-        dev->UARTDR.reg = data[i];
-        while (!(dev->UARTRIS.reg & UART0_UARTRIS_TXRIS_Msk)) { }
+        dev->UARTDR = data[i];
+        while (!(dev->UARTRIS & UART0_UARTRIS_TXRIS_Msk)) { }
     }
 }
 
@@ -253,11 +253,11 @@ void isr_handler(uint8_t num)
 {
     UART0_Type *dev = uart_config[num].dev;
 
-    uint32_t status = dev->UARTMIS.reg;
-    dev->UARTICR.reg = status;
+    uint32_t status = dev->UARTMIS;
+    dev->UARTICR = status;
 
     if (status & UART0_UARTMIS_RXMIS_Msk) {
-        uint32_t data = dev->UARTDR.reg;
+        uint32_t data = dev->UARTDR;
         if (data & (UART0_UARTDR_BE_Msk | UART0_UARTDR_PE_Msk | UART0_UARTDR_FE_Msk)) {
             DEBUG_PUTS("[rpx0xx] uart RX error (parity, break, or framing error");
         }

cpu/rpx0xx/pll.c

@@ -44,22 +44,22 @@ static void _pll_start(PLL_SYS_Type *pll, uint8_t ref_div,
     assert(post_div_2 <= PLL_POSTDIV_MAX);
 
     /* program reference clock divider */
-    io_reg_write_dont_corrupt(&pll->CS.reg, ref_div << PLL_SYS_CS_REFDIV_Pos,
+    io_reg_write_dont_corrupt(&pll->CS, ref_div << PLL_SYS_CS_REFDIV_Pos,
                               PLL_SYS_CS_REFDIV_Msk);
     /* program feedback divider */
-    io_reg_write_dont_corrupt(&pll->FBDIV_INT.reg,
+    io_reg_write_dont_corrupt(&pll->FBDIV_INT,
                               vco_feedback_scale << PLL_SYS_FBDIV_INT_FBDIV_INT_Pos,
                               PLL_SYS_FBDIV_INT_FBDIV_INT_Msk);
     /* turn on the main power */
-    io_reg_atomic_clear(&pll->PWR.reg, (1U << PLL_SYS_PWR_VCOPD_Pos)
+    io_reg_atomic_clear(&pll->PWR, (1U << PLL_SYS_PWR_VCOPD_Pos)
                                      | (1U << PLL_SYS_PWR_DSMPD_Pos)
                                      | (1U << PLL_SYS_PWR_PD_Pos));
     /* wait for VCO to lock (i.e. keep its output stable) */
-    while (!pll->CS.bit.LOCK) { }
+    while (!(pll->CS & PLL_SYS_CS_LOCK_Msk)) { }
     /* set up post divisors and turn them on */
-    pll->PRIM.reg = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos)
+    pll->PRIM = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos)
                   | (post_div_2 << PLL_SYS_PRIM_POSTDIV2_Pos);
-    io_reg_atomic_clear(&pll->PWR.reg, 1U << PLL_SYS_PWR_POSTDIVPD_Pos);
+    io_reg_atomic_clear(&pll->PWR, 1U << PLL_SYS_PWR_POSTDIVPD_Pos);
 }
 
 /**
@@ -72,7 +72,7 @@ static void _pll_stop(PLL_SYS_Type *pll)
                  | (1U << PLL_SYS_PWR_POSTDIVPD_Pos)
                  | (1U << PLL_SYS_PWR_DSMPD_Pos)
                  | (1U << PLL_SYS_PWR_PD_Pos);
-    io_reg_atomic_set(&pll->PWR.reg, reg);
+    io_reg_atomic_set(&pll->PWR, reg);
 }
 
 void pll_start_sys(uint8_t ref_div,

cpu/rpx0xx/rosc.c

@@ -31,19 +31,19 @@
 void rosc_start(void)
 {
     /* set drive strengths to default 0 */
-    io_reg_atomic_clear(&ROSC->FREQA.reg, ROSC_FREQA_PASSWD_Msk);
-    io_reg_atomic_clear(&ROSC->FREQB.reg, ROSC_FREQB_PASSWD_Msk);
+    io_reg_atomic_clear(&ROSC->FREQA, ROSC_FREQA_PASSWD_Msk);
+    io_reg_atomic_clear(&ROSC->FREQB, ROSC_FREQB_PASSWD_Msk);
     /* apply settings with magic value 0x9696 */
     const uint32_t magic = 0x9696U;
-    io_reg_write_dont_corrupt(&ROSC->FREQA.reg, magic << ROSC_FREQA_PASSWD_Pos,
+    io_reg_write_dont_corrupt(&ROSC->FREQA, magic << ROSC_FREQA_PASSWD_Pos,
                               ROSC_FREQA_PASSWD_Msk);
-    io_reg_write_dont_corrupt(&ROSC->FREQB.reg, magic << ROSC_FREQB_PASSWD_Pos,
+    io_reg_write_dont_corrupt(&ROSC->FREQB, magic << ROSC_FREQB_PASSWD_Pos,
                               ROSC_FREQB_PASSWD_Msk);
 
     /* default divider is 16 */
-    io_reg_write_dont_corrupt(&ROSC->DIV.reg, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk);
-    io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos);
-    while (!ROSC->STATUS.bit.STABLE) { }
+    io_reg_write_dont_corrupt(&ROSC->DIV, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk);
+    io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos);
+    while (!(ROSC->STATUS & ROSC_STATUS_STABLE_Msk)) { }
 }
 
 /**
@@ -53,5 +53,5 @@ void rosc_start(void)
  */
 void rosc_stop(void)
 {
-    io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos);
+    io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos);
 }

cpu/rpx0xx/xosc.c

@@ -34,15 +34,15 @@ void xosc_start(uint32_t f_ref)
 {
     assert(f_ref == MHZ(12));
     uint32_t delay = _xosc_conf_sartup_delay(f_ref, 1);
-    io_reg_write_dont_corrupt(&XOSC->STARTUP.reg, delay << XOSC_STARTUP_DELAY_Pos,
+    io_reg_write_dont_corrupt(&XOSC->STARTUP, delay << XOSC_STARTUP_DELAY_Pos,
                               XOSC_STARTUP_DELAY_Msk);
-    io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos,
+    io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos,
                               XOSC_CTRL_ENABLE_Msk);
-    while (!XOSC->STATUS.bit.STABLE) { }
+    while (!(XOSC->STATUS & XOSC_STATUS_STABLE_Msk)) { }
 }
 
 void xosc_stop(void)
 {
-    io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos,
+    io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos,
                               XOSC_CTRL_ENABLE_Msk);
 }