cpu/stm32/periph_spi: only perform DMA transfer above threshold

[benpicco]

Contribution description

Same as for sam0, only perform DMA transfer if there are more than CONFIG_SPI_DMA_THRESHOLD_BYTES to transfer to avoid a net slowdown for single byte transfers due to DMA setup overhead.

Testing procedure

Issues/PRs references

[MrKevinWeiss]

It looks good but I ran out of time to test. I will do that tomorrow...

[MrKevinWeiss]

BOARD=nucleo-f413zh make flash term -C tests/periph/spi_dma

master (10MHz)

init 0 0 4 0 0
2024-01-04 10:24:17,644 # init 0 0 4 0 0
2024-01-04 10:24:17,651 # Trying to initialize SPI_DEV(0): mode: 0, clk: 4, cs_port: 0, cs_pin: 0
2024-01-04 10:24:17,659 # (if below the program crashes with a failed assertion, then it means the configuration is not supported)
2024-01-04 10:24:17,660 # Success.
bench 0
2024-01-04 10:24:19,329 # bench
2024-01-04 10:24:19,335 # ### Running some benchmarks, all values in [us] ###
2024-01-04 10:24:19,338 # ### Test                              Transfer time   user time
2024-01-04 10:24:19,339 # 
2024-01-04 10:24:19,349 #  1 - write 1000 times 1 byte:                 8621    8623
2024-01-04 10:24:19,365 #  2 - write 1000 times 2 byte:                 12277   7923
2024-01-04 10:24:19,504 #  3 - write 1000 times 100 byte:               135440  6762
2024-01-04 10:24:19,527 #  4 - write 1000 times 1 byte to register:     17098   17100
2024-01-04 10:24:19,552 #  5 - write 1000 times 2 byte to register:     20977   16639
2024-01-04 10:24:19,701 #  6 - write 1000 times 100 byte to register:   144218  15579
2024-01-04 10:24:19,717 #  7 - read 1000 times 2 byte:                  12196   7802
2024-01-04 10:24:19,857 #  8 - read 1000 times 100 byte:                135361  6642
2024-01-04 10:24:19,882 #  9 - read 1000 times 2 byte from register:    20878   16599
2024-01-04 10:24:20,031 # 10 - read 1000 times 100 byte from register:  144157  15519
2024-01-04 10:24:20,047 # 11 - transfer 1000 times 2 byte:              12217   7883
2024-01-04 10:24:20,187 # 12 - transfer 1000 times 100 byte:            135341  6662
2024-01-04 10:24:20,213 # 13 - transfer 1000 times 2 byte to register:  20897   16599
2024-01-04 10:24:20,362 # 14 - transfer 1000 times 100 byte to register:144178  15540
2024-01-04 10:24:20,374 # 15 - acquire/release 1000 times:              7681    7683
2024-01-04 10:24:21,376 # -- - SUM:                                     971537  173555
2024-01-04 10:24:21,377 # 
2024-01-04 10:24:21,379 # ### All runs complete ###

pr (10MHz)

init 0 0 4 0 0
2024-01-04 10:23:04,054 # init 0 0 4 0 0
2024-01-04 10:23:04,060 # Trying to initialize SPI_DEV(0): mode: 0, clk: 4, cs_port: 0, cs_pin: 0
2024-01-04 10:23:04,070 # (if below the program crashes with a failed assertion, then it means the configuration is not supported)
2024-01-04 10:23:04,071 # Success.
bench
2024-01-04 10:23:08,667 # bench
2024-01-04 10:23:08,672 # ### Running some benchmarks, all values in [us] ###
2024-01-04 10:23:08,674 # ### Test                              Transfer time   user time
2024-01-04 10:23:08,675 # 
2024-01-04 10:23:08,681 #  1 - write 1000 times 1 byte:                 3341    3343
2024-01-04 10:23:08,689 #  2 - write 1000 times 2 byte:                 4290    4292
2024-01-04 10:23:08,829 #  3 - write 1000 times 100 byte:               135380  6682
2024-01-04 10:23:08,840 #  4 - write 1000 times 1 byte to register:     6391    6392
2024-01-04 10:23:08,852 #  5 - write 1000 times 2 byte to register:     7381    7383
2024-01-04 10:23:08,995 #  6 - write 1000 times 100 byte to register:   138641  9962
2024-01-04 10:23:09,004 #  7 - read 1000 times 2 byte:                  4551    4553
2024-01-04 10:23:09,143 #  8 - read 1000 times 100 byte:                135361  6642
2024-01-04 10:23:09,155 #  9 - read 1000 times 2 byte from register:    7651    7653
2024-01-04 10:23:09,299 # 10 - read 1000 times 100 byte from register:  138641  10002
2024-01-04 10:23:09,307 # 11 - transfer 1000 times 2 byte:              4651    4652
2024-01-04 10:23:09,447 # 12 - transfer 1000 times 100 byte:            135381  6603
2024-01-04 10:23:09,459 # 13 - transfer 1000 times 2 byte to register:  7741    7743
2024-01-04 10:23:09,604 # 14 - transfer 1000 times 100 byte to register:138600  10002
2024-01-04 10:23:09,615 # 15 - acquire/release 1000 times:              7681    7682
2024-01-04 10:23:10,618 # -- - SUM:                                     875682  103586
2024-01-04 10:23:10,618 # 
2024-01-04 10:23:10,621 # ### All runs complete ###

[MrKevinWeiss]

ACK.

Eventually we can tune for different clocks but the this does what is intended and makes sense for 10MHz at least.

[riot-ci]

Murdock results

✔️ PASSED

753fae6 cpu/stm32/periph_spi: only perform DMA transfer above threshold

Success	Failures	Total	Runtime
8101	0	8101	11m:20s

Artifacts

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