[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue

Cherry-pick llvm#109439 Change-Id: I555ef6c0a2ffe806aa40c0e0c639fdb12c45c27c
ROCm · Oct 22, 2024 · 14e4fe2 · 14e4fe2
1 parent 42cfb9f
commit 14e4fe2
Showing 1 changed file with 4 additions and 5 deletions.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8936,12 +8936,11 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
     IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
   }
 
-  uint16_t Opc = MI.getOpcode();
-  // FIXME: Copies inserted in the block prolog for live-range split should also
-  // be included.
+  uint16_t Opcode = MI.getOpcode();
   return IsNullOrVectorRegister &&
-         (isSpillOpcode(Opc) || (!MI.isTerminator() && Opc != AMDGPU::COPY &&
-                                 MI.modifiesRegister(AMDGPU::EXEC, &RI)));
+         (isSGPRSpill(Opcode) ||
+          (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
+           MI.modifiesRegister(AMDGPU::EXEC, &RI)));
 }
 
 MachineInstrBuilder