Perf counters

README.md

@@ -49,6 +49,7 @@
     - [YamlPlugin](#yamlplugin)
     - [FpuPlugin](#fpuplugin)
     - [AesPlugin](#aesplugin)
+    - [CounterPlugin](#counterplugin)
 
 
 
@@ -1319,3 +1320,21 @@ It was also ported on libressl via the following patch :
 <https://github.com/SpinalHDL/buildroot-spinal-saxon/blob/main/patches/libressl/0000-vexriscv-aes.patch>
 
 Speed up of 4 was observed in libressl running in linux. <https://github.com/SpinalHDL/SaxonSoc/pull/53#issuecomment-730133020>
+
+#### CounterPlugin
+
+Provides performance-counter and time CSRs.
+
+Here is how to provide a custom event condition (which can then be configured by code):
+In setup phase
+```scala
+val ctrSrv = pipeline.service(classOf[CounterService])
+ctrSrv.createEvent(eventId)
+```
+In build phase
+```scala
+val ctrSrv = pipeline.service(classOf[CounterService])
+ctrSrv.getCondition(eventId) := boolCond
+```
+eventId is BigInt, but only events between 0 and 2 ** XLEN (excluding boundaries) can be selected by cpu.
+The configured counter counts clockcycles with boolCond asserted.

src/main/scala/vexriscv/Riscv.scala

@@ -216,6 +216,10 @@ object Riscv{
     def MCYCLEH   = 0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
     def MINSTRETH = 0xB82 // MRW Upper 32 bits of minstret, RV32I only.
     val MCOUNTEREN  = 0x306
+    val MCOUNTER  = 0xB03 // MRW Base address for mhpmcounterX.
+    val MCOUNTERH = 0xB83 // MRW Base address for mhpmcounterXh, RV32I only.
+    val MCOUNTINHIBIT = 0x320
+    val MEVENT    = 0x323 // MRW Base address for mhpmeventX.
 
     val SSTATUS     = 0x100
     val SIE         = 0x104
@@ -234,6 +238,8 @@ object Riscv{
     def UTIMEH   = 0xC81
     def UINSTRET  = 0xC02 // UR Machine instructions-retired counter.
     def UINSTRETH = 0xC82 // UR Upper 32 bits of minstret, RV32I only.
+    val UCOUNTER  = 0xC03 // UR Base address for hpmcounter.
+    val UCOUNTERH = 0xC83 // UR Base address for hpmcounterXh, RV32I only.
 
     val FFLAGS = 0x1
     val FRM = 0x2

src/main/scala/vexriscv/Services.scala

@@ -49,6 +49,8 @@ trait PrivilegeService{
   def isUser() : Bool
   def isSupervisor() : Bool
   def isMachine() : Bool
+  def hasUser() : Boolean
+  def hasSupervisor() : Boolean
   def forceMachine() : Unit
 
   def encodeBits() : Bits = {
@@ -70,6 +72,8 @@ case class PrivilegeServiceDefault() extends PrivilegeService{
   override def isUser(): Bool = False
   override def isSupervisor(): Bool = False
   override def isMachine(): Bool = True
+  override def hasUser(): Boolean = false
+  override def hasSupervisor(): Boolean = false
   override def forceMachine(): Unit = {}
 }
 
@@ -143,4 +147,4 @@ class CacheReport {
 
 class DebugReport {
   @BeanProperty var hardwareBreakpointCount = 0
-}
+}

src/main/scala/vexriscv/demo/Briey.scala

@@ -146,12 +146,8 @@ object BrieyConfig{
             mscratchGen    = false,
             mcauseAccess   = CsrAccess.READ_ONLY,
             mbadaddrAccess = CsrAccess.READ_ONLY,
-            mcycleAccess   = CsrAccess.NONE,
-            minstretAccess = CsrAccess.NONE,
             ecallGen       = false,
-            wfiGenAsWait         = false,
-            ucycleAccess   = CsrAccess.NONE,
-            uinstretAccess = CsrAccess.NONE
+            wfiGenAsWait         = false
           )
         ),
         new YamlPlugin("cpu0.yaml")

src/main/scala/vexriscv/demo/GenFull.scala

@@ -80,6 +80,7 @@ object GenFull extends App{
         earlyBranch = false,
         catchAddressMisaligned = true
       ),
+      new CounterPlugin(CounterPluginConfig()),
       new YamlPlugin("cpu0.yaml")
     )
   )

src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala

@@ -122,12 +122,8 @@ object VexRiscvAhbLite3{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala

@@ -120,12 +120,8 @@ object VexRiscvAvalonForSim{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala

@@ -117,12 +117,8 @@ object VexRiscvAvalonWithIntegratedJtag{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

src/main/scala/vexriscv/demo/VexRiscvAxi4LinuxPlicClint.scala

@@ -96,7 +96,20 @@ object VexRiscvAxi4LinuxPlicClint{
             earlyBranch = false,
             catchAddressMisaligned = true
           ),
-          new CsrPlugin(CsrPluginConfig.openSbi(mhartid = 0, misa = Riscv.misaToInt(s"ima")).copy(utimeAccess = CsrAccess.READ_ONLY)),
+          new CsrPlugin(CsrPluginConfig.openSbi(mhartid = 0, misa = Riscv.misaToInt(s"ima"))),
+          new CounterPlugin(CounterPluginConfig(
+            NumOfCounters       = 0,
+            mcycleAccess        = CsrAccess.NONE,
+            ucycleAccess        = CsrAccess.NONE,
+            minstretAccess      = CsrAccess.NONE,
+            uinstretAccess      = CsrAccess.NONE,
+            mcounterenAccess    = CsrAccess.NONE,
+            scounterenAccess    = CsrAccess.NONE,
+            mcounterAccess      = CsrAccess.NONE,
+            ucounterAccess      = CsrAccess.NONE,
+            meventAccess        = CsrAccess.NONE,
+            mcountinhibitAccess = CsrAccess.NONE
+          )),
           new YamlPlugin("cpu0.yaml")
         )
       )
@@ -152,7 +165,9 @@ object VexRiscvAxi4LinuxPlicClint{
             plugin.softwareInterrupt  setAsDirectionLess() := cpu.clintCtrl.io.softwareInterrupt(0)
             plugin.externalInterrupt  setAsDirectionLess() := cpu.plicCtrl.io.targets(0)
             plugin.externalInterruptS setAsDirectionLess() := cpu.plicCtrl.io.targets(1)
-            plugin.utime              setAsDirectionLess() := cpu.clintCtrl.io.time
+          }
+          case plugin: CounterPlugin => {
+            plugin.time              setAsDirectionLess() := cpu.clintCtrl.io.time
           }
           case _ =>
         }

src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala

@@ -118,12 +118,8 @@ object VexRiscvAxi4WithIntegratedJtag{
               mscratchGen    = false,
               mcauseAccess   = CsrAccess.READ_ONLY,
               mbadaddrAccess = CsrAccess.READ_ONLY,
-              mcycleAccess   = CsrAccess.NONE,
-              minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
-              wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE,
-              uinstretAccess = CsrAccess.NONE
+              wfiGenAsWait         = false
             )
           ),
           new YamlPlugin("cpu0.yaml")

src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala

@@ -150,7 +150,7 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
     plic.addTarget(core.cpu.externalSupervisorInterrupt)
     List(clint.logic, core.cpu.logic).produce {
       for (plugin <- core.cpu.config.plugins) plugin match {
-        case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
+        case plugin: CounterPlugin if plugin.time != null => plugin.time := clint.logic.io.time
         case _ =>
       }
     }
@@ -204,15 +204,11 @@ object VexRiscvSmpClusterGen {
 
     val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}")
     val csrConfig = if(withSupervisor){
-      var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug)
+      var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(withPrivilegedDebug = privilegedDebug)
       if(csrFull){
        c = c.copy(
          mcauseAccess   = CsrAccess.READ_WRITE,
-         mbadaddrAccess = CsrAccess.READ_WRITE,
-         ucycleAccess   = CsrAccess.READ_ONLY,
-         uinstretAccess = CsrAccess.READ_ONLY,
-         mcycleAccess   = CsrAccess.READ_WRITE,
-         minstretAccess = CsrAccess.READ_WRITE
+         mbadaddrAccess = CsrAccess.READ_WRITE
        )
       }
       c
@@ -232,13 +228,10 @@ object VexRiscvSmpClusterGen {
         mscratchGen    = forceMscratch,
         mcauseAccess   = CsrAccess.READ_ONLY,
         mbadaddrAccess = CsrAccess.READ_ONLY,
-        mcycleAccess   = CsrAccess.NONE,
-        minstretAccess = CsrAccess.NONE,
         ecallGen       = true,
         ebreakGen      = true,
         wfiGenAsWait   = false,
         wfiGenAsNop    = true,
-        ucycleAccess   = CsrAccess.NONE,
         withPrivilegedDebug = privilegedDebug
       )
     }
@@ -358,6 +351,19 @@ object VexRiscvSmpClusterGen {
           catchAddressMisaligned = true,
           fenceiGenAsAJump = false
         ),
+        new CounterPlugin(if(csrFull) CounterPluginConfig() else CounterPluginConfig(
+          NumOfCounters       = 0,
+          mcycleAccess        = CsrAccess.NONE,
+          ucycleAccess        = CsrAccess.NONE,
+          minstretAccess      = CsrAccess.NONE,
+          uinstretAccess      = CsrAccess.NONE,
+          mcounterenAccess    = CsrAccess.NONE,
+          scounterenAccess    = CsrAccess.NONE,
+          mcounterAccess      = CsrAccess.NONE,
+          ucounterAccess      = CsrAccess.NONE,
+          meventAccess        = CsrAccess.NONE,
+          mcountinhibitAccess = CsrAccess.NONE
+        )),
         new YamlPlugin(s"cpu$hartId.yaml")
       )
     )