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Correct way of evaluating logic circuit #15

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RenatoGeh opened this issue Jun 1, 2020 · 5 comments · Fixed by #16
Closed

Correct way of evaluating logic circuit #15

RenatoGeh opened this issue Jun 1, 2020 · 5 comments · Fixed by #16
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@RenatoGeh
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Hi,

I am attempting to evaluate a Logical\DeltaNode, in the following way:

# I'm creating an XData as a BitArray{2}, where m is the number of variables.
X = LogicCircuits.XData(BitArray{2}(undef, 1, m))
# Then, given a circuit C.
p = C(X)

However, this outputs the following error.

ERROR: LoadError: TypeError: in typeassert, expected Array{BitArray{1},1}, got BitArray{1}
Stacktrace:
 [1] (::LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}})(::FalseNode) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:29
 [2] foldup_rec at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:153 [inlined]
 [3] (::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}})(::FalseNode) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:150
 [4] (::LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}})(::⋀Node, ::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:264
 [5] (::LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}})(::⋀Node, ::Function) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:30
 [6] foldup_rec at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:151 [inlined]
 [7] (::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}})(::⋀Node) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:150
 [8] (::LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}})(::⋁Node, ::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:280
 [9] (::LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}})(::⋁Node, ::Function) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:30
 [10] foldup_rec at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:151 [inlined]
 [11] (::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}})(::⋁Node) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:150
 [12] (::LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}})(::⋀Node, ::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:264
 [13] (::LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}})(::⋀Node, ::Function) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:30
 [14] foldup_rec at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:151 [inlined]
 [15] (::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}})(::⋀Node) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:150
 [16] (::LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}})(::⋁Node, ::LogicCircuits.Utils.var"#callback#17"{true,Array{BitArray{1},1},LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}},LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:280
 [17] (::LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}})(::⋁Node, ::Function) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:30
 [18] foldup_rec(::⋁Node, ::LogicCircuits.Logical.var"#f_leaf#7"{Array{BitArray{1},1},LogicCircuits.Logical.var"#f_con#100"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#f_lit#99"{PlainXData{Bool,BitArray{2}}}}, ::LogicCircuits.Logical.var"#f_inner#8"{Array{BitArray{1},1},LogicCircuits.Logical.var"#fa#101"{PlainXData{Bool,BitArray{2}}},LogicCircuits.Logical.var"#fo#102"{PlainXData{Bool,BitArray{2}}}}, ::Type{Array{BitArray{1},1}}, ::Val{true}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:151
 [19] foldup_rec(::⋁Node, ::Function, ::Function, ::Type{Array{BitArray{1},1}}) at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:145
 [20] foldup at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Utils/Graphs.jl:138 [inlined]
 [21] foldup at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/CircuitTraversal.jl:31 [inlined]
 [22] evaluate at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:284 [inlined]
 [23] ΔNode at /home/renatogeh/.julia/packages/LogicCircuits/5odQU/src/Logical/Queries.jl:248 [inlined]

What exactly am I doing wrong here? Even the minimal example below with a simple circuit outputs the same error.

using LogicCircuits
α = LogicCircuits.⋁Node([LogicCircuits.⋀Node([LogicCircuits.LiteralNode(1), LogicCircuits.TrueNode()]), LogicCircuits.⋀Node([LogicCircuits.LiteralNode(-1), LogicCircuits.FalseNode()])])
X = LogicCircuits.XData(BitArray{2}(undef, 1, 2))
α(X)

Thank you,
Renato

@RenatoGeh
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Ok, so doing some digging, I found out that if I replace the constant nodes with literals, it works fine. Does evaluate not work with constant nodes?

@guyvdbroeck
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Thanks for the report. It's very likely that I implemented this without support for constants. Of course you can always propagate away the constants, but I will implement the general case of evaluation anyway.

@guyvdbroeck guyvdbroeck self-assigned this Jun 1, 2020
@RenatoGeh
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Thanks! While I'm at it, I'm a bit confused with the many inference methods implemented. What exactly are the differences between UpFlow and DownFlow? And how do they differ from simple evaluation? Again, thank you all for being so quick on the PRs and issues.

RenatoGeh added a commit to RenatoGeh/LogicCircuits.jl that referenced this issue Jun 2, 2020
khosravipasha pushed a commit that referenced this issue Jun 2, 2020
@khosravipasha
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khosravipasha commented Jun 2, 2020

@RenatoGeh Thanks for the fix.

We are aware these are a bit confusing and planning to fix and document them for our v0.2 release (probably early summer). Some of these data-strcutures might be gone in the future. But as of now, UpFlow Circuit are circuits in parallel with the original circuit to allocate cached results when we are doing upward passes in a given circuit. Any algorithm that uses upward pass uses a UpFlow Circuit (for example evaluate and marginal_likelihood). We also have algorithms that need to do a downward pass in addition to a upward pass, in those cases a DownFlow circuit is allocated to cache intermediary results.

The distinction has been mostly for historical and sometimes performance reasons, when we get the chance we are planning to simply the code. We are also experimenting with different implementations. for example, we also have recursive version of the algorithms without expclit allocation of flow circuit. We are currently buidling a benchmark and based on that will decide which implementations to keep (or which ones to set as default so end-users don't have to worry about which method to use).

@RenatoGeh
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I see. Thank you for answering. :)

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