Updated some config options to be read as uint16_t not uint8_t to all…

…ow for a wider param space (#229)

src/include/simeng/pipeline/LoadStoreQueue.hh

@@ -34,9 +34,11 @@ class LoadStoreQueue {
       unsigned int maxCombinedSpace, MemoryInterface& memory,
       span<PipelineBuffer<std::shared_ptr<Instruction>>> completionSlots,
       std::function<void(span<Register>, span<RegisterValue>)> forwardOperands,
-      bool exclusive = false, uint8_t loadBandwidth = UINT8_MAX,
-      uint8_t storeBandwidth = UINT8_MAX, uint8_t permittedRequests = UINT8_MAX,
-      uint8_t permittedLoads = UINT8_MAX, uint8_t permittedStores = UINT8_MAX);
+      bool exclusive = false, uint16_t loadBandwidth = UINT16_MAX,
+      uint16_t storeBandwidth = UINT16_MAX,
+      uint16_t permittedRequests = UINT16_MAX,
+      uint16_t permittedLoads = UINT16_MAX,
+      uint16_t permittedStores = UINT16_MAX);
 
   /** Constructs a split load/store queue model, simulating discrete queues for
    * load and store instructions, supplying completion slots for loads and an
@@ -46,9 +48,11 @@ class LoadStoreQueue {
       MemoryInterface& memory,
       span<PipelineBuffer<std::shared_ptr<Instruction>>> completionSlots,
       std::function<void(span<Register>, span<RegisterValue>)> forwardOperands,
-      bool exclusive = false, uint8_t loadBandwidth = UINT8_MAX,
-      uint8_t storeBandwidth = UINT8_MAX, uint8_t permittedRequests = UINT8_MAX,
-      uint8_t permittedLoads = UINT8_MAX, uint8_t permittedStores = UINT8_MAX);
+      bool exclusive = false, uint16_t loadBandwidth = UINT16_MAX,
+      uint16_t storeBandwidth = UINT16_MAX,
+      uint16_t permittedRequests = UINT16_MAX,
+      uint16_t permittedLoads = UINT16_MAX,
+      uint16_t permittedStores = UINT16_MAX);
 
   /** Retrieve the available space for load uops. For combined queue this is the
    * total remaining space. */
@@ -173,16 +177,16 @@ class LoadStoreQueue {
   bool exclusive_;
 
   /** The amount of data readable from the L1D cache per cycle. */
-  uint64_t loadBandwidth_;
+  uint16_t loadBandwidth_;
 
   /** The amount of data writable to the L1D cache per cycle. */
-  uint64_t storeBandwidth_;
+  uint16_t storeBandwidth_;
 
   /** The combined limit of loads and store requests permitted per cycle. */
-  uint8_t totalLimit_;
+  uint16_t totalLimit_;
 
   /** The number of loads and stores permitted per cycle. */
-  std::array<uint8_t, 2> reqLimits_;
+  std::array<uint16_t, 2> reqLimits_;
 };
 
 }  // namespace pipeline

src/lib/ModelConfig.cc

@@ -91,8 +91,8 @@ void ModelConfig::validate() {
   // Branch-Predictor
   root = "Branch-Predictor";
   subFields = {"BTB-bitlength"};
-  nodeChecker<uint8_t>(configFile_[root][subFields[0]], subFields[0],
-                       std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger);
+  nodeChecker<uint16_t>(configFile_[root][subFields[0]], subFields[0],
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger);
   subFields.clear();
 
   // L1-Cache
@@ -110,20 +110,20 @@ void ModelConfig::validate() {
   nodeChecker<bool>(configFile_[root][subFields[1]], subFields[1],
                     std::vector<bool>{true, false}, ExpectedValue::Bool, false);
   nodeChecker<uint16_t>(configFile_[root][subFields[2]], subFields[2],
-                        std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger,
-                        UINT8_MAX);
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger,
+                        UINT16_MAX);
   nodeChecker<uint16_t>(configFile_[root][subFields[3]], subFields[3],
-                        std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger,
-                        UINT8_MAX);
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger,
+                        UINT16_MAX);
   nodeChecker<uint16_t>(configFile_[root][subFields[4]], subFields[4],
-                        std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger,
-                        UINT8_MAX);
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger,
+                        UINT16_MAX);
   nodeChecker<uint16_t>(configFile_[root][subFields[5]], subFields[5],
-                        std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger,
-                        UINT8_MAX);
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger,
+                        UINT16_MAX);
   nodeChecker<uint16_t>(configFile_[root][subFields[6]], subFields[6],
-                        std::make_pair(1, UINT8_MAX), ExpectedValue::UInteger,
-                        UINT8_MAX);
+                        std::make_pair(1, UINT16_MAX), ExpectedValue::UInteger,
+                        UINT16_MAX);
   subFields.clear();
 
   // Ports

src/lib/models/outoforder/Core.cc

@@ -60,16 +60,16 @@ Core::Core(MemoryInterface& instructionMemory, MemoryInterface& dataMemory,
             dispatchIssueUnit_.forwardOperands(regs, values);
           },
           config["L1-Cache"]["Exclusive"].as<bool>(),
-          config["L1-Cache"]["Load-Bandwidth"].as<uint8_t>(),
-          config["L1-Cache"]["Store-Bandwidth"].as<uint8_t>(),
-          config["L1-Cache"]["Permitted-Requests-Per-Cycle"].as<uint8_t>(),
-          config["L1-Cache"]["Permitted-Loads-Per-Cycle"].as<uint8_t>(),
-          config["L1-Cache"]["Permitted-Stores-Per-Cycle"].as<uint8_t>()),
+          config["L1-Cache"]["Load-Bandwidth"].as<uint16_t>(),
+          config["L1-Cache"]["Store-Bandwidth"].as<uint16_t>(),
+          config["L1-Cache"]["Permitted-Requests-Per-Cycle"].as<uint16_t>(),
+          config["L1-Cache"]["Permitted-Loads-Per-Cycle"].as<uint16_t>(),
+          config["L1-Cache"]["Permitted-Stores-Per-Cycle"].as<uint16_t>()),
       reorderBuffer_(config["Queue-Sizes"]["ROB"].as<unsigned int>(),
                      registerAliasTable_, loadStoreQueue_,
                      [this](auto instruction) { raiseException(instruction); }),
       fetchUnit_(fetchToDecodeBuffer_, instructionMemory, processMemorySize,
-                 entryPoint, config["Core"]["Fetch-Block-Size"].as<uint8_t>(),
+                 entryPoint, config["Core"]["Fetch-Block-Size"].as<uint16_t>(),
                  isa, branchPredictor),
       decodeUnit_(fetchToDecodeBuffer_, decodeToRenameBuffer_, branchPredictor),
       renameUnit_(decodeToRenameBuffer_, renameToDispatchBuffer_,

src/lib/pipeline/LoadStoreQueue.cc

@@ -19,8 +19,9 @@ LoadStoreQueue::LoadStoreQueue(
     unsigned int maxCombinedSpace, MemoryInterface& memory,
     span<PipelineBuffer<std::shared_ptr<Instruction>>> completionSlots,
     std::function<void(span<Register>, span<RegisterValue>)> forwardOperands,
-    bool exclusive, uint8_t loadBandwidth, uint8_t storeBandwidth,
-    uint8_t permittedRequests, uint8_t permittedLoads, uint8_t permittedStores)
+    bool exclusive, uint16_t loadBandwidth, uint16_t storeBandwidth,
+    uint16_t permittedRequests, uint16_t permittedLoads,
+    uint16_t permittedStores)
     : completionSlots_(completionSlots),
       forwardOperands_(forwardOperands),
       maxCombinedSpace_(maxCombinedSpace),
@@ -38,8 +39,9 @@ LoadStoreQueue::LoadStoreQueue(
     MemoryInterface& memory,
     span<PipelineBuffer<std::shared_ptr<Instruction>>> completionSlots,
     std::function<void(span<Register>, span<RegisterValue>)> forwardOperands,
-    bool exclusive, uint8_t loadBandwidth, uint8_t storeBandwidth,
-    uint8_t permittedRequests, uint8_t permittedLoads, uint8_t permittedStores)
+    bool exclusive, uint16_t loadBandwidth, uint16_t storeBandwidth,
+    uint16_t permittedRequests, uint16_t permittedLoads,
+    uint16_t permittedStores)
     : completionSlots_(completionSlots),
       forwardOperands_(forwardOperands),
       maxLoadQueueSpace_(maxLoadQueueSpace),
@@ -374,7 +376,7 @@ void LoadStoreQueue::tick() {
   // Send memory requests adhering to set bandwidth and number of permitted
   // requests per cycle
   // Index 0: loads, index 1: stores
-  std::array<uint8_t, 2> reqCounts = {0, 0};
+  std::array<uint16_t, 2> reqCounts = {0, 0};
   std::array<uint64_t, 2> dataTransfered = {0, 0};
   std::array<bool, 2> exceededLimits = {false, false};
   auto itLoad = requestLoadQueue_.begin();

src/tools/simeng/main.cc

@@ -222,7 +222,7 @@ int main(int argc, char** argv) {
       std::make_unique<simeng::arch::aarch64::Architecture>(kernel, config);
 
   auto predictor = simeng::BTBPredictor(
-      config["Branch-Predictor"]["BTB-bitlength"].as<uint8_t>());
+      config["Branch-Predictor"]["BTB-bitlength"].as<uint16_t>());
   auto config_ports = config["Ports"];
   std::vector<std::vector<uint16_t>> portArrangement(config_ports.size());
   // Extract number of ports