Micro op and fusion #220
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Micro op and fusion #220
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…Architecture class
…r the extraction of uops from the MacroOp vector which are then passed into the output buffer as if they are standard Instructions
…ops split from a macro-op to retired once all uops are committable
… constructor. Minor naming convention corrections and added an arbitrary micro-op index value for implementation defined use
…e data identifiers
… getExecutionInfo a public function so it can be used by the micro decoder on newly created micro-operations. Also removed SVE instruction identifier and load/store instruction split flag as both are going to be unused.
…ions from new internal uop buffer. Also duplicated decode unit's internal uop buffer behaviour in emulation core so that it may support multiple micro-operations.
…ve bug whereby the 'front' of the queue would change position when inspecting the state of micro-operations.
…rations flow through the pipeline by providing the data to be stored as an execution rather than a getter at the point of retirement.
…Added execute and address generation logic for ldr 64-bit pre-offset micro-operations.
…helper functions. Also added support for 64-bit immediate post-index load micro-operation.
…low for differing execution flow between store micro-operations.
…operations in the emulation and inorder cores.
…nstruction splitting. Will remove comments before a PR.
…s elements. Also furthered support for LDR/LDP/STR/STP variants in microDecoder.
…support for load and store variants that have differenlty sized destination elements.
…nstrution_decode. Additionally, resolved invalid RAW dependency between LDP unsigned imm uops.
…Works with both micro and macro operations now
…ll addresses are processed before the entry is removed from the request queue.
… correct retired stat from inorder core
…ite access to memory operand
…nt under the LDP micro-op RAW dependency check
…ommitted seperately
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This PR is primarily concerned with the introduction of micro-operations/instruction splitting. Key developments are: