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AArch64 Instruction support & minor bug fixes #273
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…the mbind syscall.
… index) NEON instructions with tests.
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#rerun tests |
…f SME src/dest operands.
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One small comment about a misspelling but looks good otherwise
The instructions in ROB are sorted by their insnID, hence we can use binary search to efficiently find them.
This avoids having to make a new vector for every tick of DispatchIssueUnit
Replace std::vector with std::list as it supports O(1) deletion.
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One comment about the TODO. The rest looks good
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A few comments for points of discussion
As well as some AArch64 instruction support, the following fixes and optimisations are implemented : - Added example SME core (A64FX with in-core SME support) - Fixes MIPS calculation in CoreWrapper.cc - Fixed store instruction group allocation logic for non-SVE instructions - Corrected SME instruction group allocation in - Reassign LdAddr iterator after erasing element in LSQ load conflict logic (originally in PR Reassign iterator after erasing element in std::vector #272) - Moved optinisations of PR Minor optimizations #274 into this PR : - Refactored the ReorderBuffer::commitMicroOps method by using binary search to find the list of uops with the same instruction id. This improves the complexity from O(n) to O(logn) - Changed the DispatchIssueUnit::tick method to use a dynamic array instead of initializing a vector for each method call. This eliminates ~ 14m memory allocations for stream-triad. - Replaced std::vector to std::list in LoadStoreQueue::startLoad as it provides O(1) deletion compared to O(n) (worst-case). - Removed the explicit copy constructor from the AArch64 Instruction class - Changed MatrixRow-Count config option to Matrix-Count - Makes it easier for the user to understand how many physcial ZA registers they are defining - Hides the internal ZA implementation, again making it easier for users to understand and use
As well as some AArch64 instruction support, the following fixes are implemented :
ReorderBuffer::commitMicroOps
method by using binary search to find the list of uops with the same instruction id. This improves the complexity from O(n) to O(logn)DispatchIssueUnit::tick
method to use a dynamic array instead of initializing a vector for each method call. This eliminates ~ 14m memory allocations for stream-triad.std::vector
tostd::list
inLoadStoreQueue::startLoad
as it provides O(1) deletion compared to O(n) (worst-case).MatrixRow-Count
config option toMatrix-Count