Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

AArch64 Instruction support & minor bug fixes #273

Merged
merged 23 commits into from
Jan 30, 2023
Merged

Conversation

FinnWilkinson
Copy link
Contributor

@FinnWilkinson FinnWilkinson commented Nov 16, 2022

As well as some AArch64 instruction support, the following fixes are implemented :

  • Added example SME core (A64FX with in-core SME support)
  • Fixes MIPS calculation in CoreWrapper.cc
  • Fixed store instruction group allocation logic for non-SVE instructions
  • Corrected SME instruction group allocation in
  • Reassign LdAddr iterator after erasing element in LSQ load conflict logic (originally in PR Reassign iterator after erasing element in std::vector #272)
  • Moved optinisations of PR Minor optimizations #274 into this PR :
    • Refactored the ReorderBuffer::commitMicroOps method by using binary search to find the list of uops with the same instruction id. This improves the complexity from O(n) to O(logn)
    • Changed the DispatchIssueUnit::tick method to use a dynamic array instead of initializing a vector for each method call. This eliminates ~ 14m memory allocations for stream-triad.
    • Replaced std::vector to std::list in LoadStoreQueue::startLoad as it provides O(1) deletion compared to O(n) (worst-case).
  • Removed the explicit copy constructor from the AArch64 Instruction class
  • Changed MatrixRow-Count config option to Matrix-Count
    • Makes it easier for the user to understand how many physcial ZA registers they are defining
    • Hides the internal ZA implementation, again making it easier for users to understand and use

@FinnWilkinson FinnWilkinson added bug Something isn't working enhancement New feature or request labels Nov 16, 2022
@FinnWilkinson FinnWilkinson self-assigned this Nov 16, 2022
@FinnWilkinson
Copy link
Contributor Author

#rerun tests

Copy link
Contributor

@jj16791 jj16791 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

One small comment about a misspelling but looks good otherwise

src/lib/arch/aarch64/Instruction_decode.cc Outdated Show resolved Hide resolved
The instructions in ROB are sorted by their insnID, hence we can use binary search to efficiently find them.
This avoids having to make a new vector for every tick of DispatchIssueUnit
Replace std::vector with std::list as it supports O(1) deletion.
Copy link
Contributor

@dANW34V3R dANW34V3R left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

One comment about the TODO. The rest looks good

src/lib/arch/aarch64/Instruction_execute.cc Show resolved Hide resolved
Copy link
Contributor

@jj16791 jj16791 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

A few comments for points of discussion

src/include/simeng/pipeline/DispatchIssueUnit.hh Outdated Show resolved Hide resolved
src/lib/pipeline/LoadStoreQueue.cc Outdated Show resolved Hide resolved
src/include/simeng/pipeline/ReorderBuffer.hh Show resolved Hide resolved
@FinnWilkinson FinnWilkinson merged commit bfac331 into dev Jan 30, 2023
jj16791 pushed a commit that referenced this pull request May 19, 2023
As well as some AArch64 instruction support, the following fixes and optimisations are implemented :

- Added example SME core (A64FX with in-core SME support)
- Fixes MIPS calculation in CoreWrapper.cc
- Fixed store instruction group allocation logic for non-SVE instructions
- Corrected SME instruction group allocation in
- Reassign LdAddr iterator after erasing element in LSQ load conflict logic (originally in PR Reassign iterator after erasing element in std::vector #272)
- Moved optinisations of PR Minor optimizations #274 into this PR :
- Refactored the ReorderBuffer::commitMicroOps method by using binary search to find the list of uops with the same instruction id. This improves the complexity from O(n) to O(logn)
- Changed the DispatchIssueUnit::tick method to use a dynamic array instead of initializing a vector for each method call. This eliminates ~ 14m memory allocations for stream-triad.
- Replaced std::vector to std::list in LoadStoreQueue::startLoad as it provides O(1) deletion compared to O(n) (worst-case).
- Removed the explicit copy constructor from the AArch64 Instruction class
- Changed MatrixRow-Count config option to Matrix-Count
- Makes it easier for the user to understand how many physcial ZA registers they are defining
- Hides the internal ZA implementation, again making it easier for users to understand and use
@FinnWilkinson FinnWilkinson deleted the RIKEN-code-support branch June 8, 2023 10:06
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working enhancement New feature or request
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants