In-order Early Halting Fix

[dANW34V3R]

This pull request adds:

• Correct tagging of RISC-V multiply and divide instructions
• Renaming of knownTarget_ to knownOffset_ and fixing the RISC-V assignment to this variable

This pull request fixes:

• With the specific sequence of instructions: branch, multi-cycle instruction, branch, the in-order core would sometimes incorrectly halt.

  This would only happen in the case that each branch instruction set knownTarget_ to a value outside the valid range defined by the program size. This is due to incorrectly setting the variable as the instruction's own address had not been initialised and so was some garbage value different on each run.

  This caused a halt because the first mispredicted branch causes a bubble when the fetch unit halts not knowing what to fetch next. Once executed, a multicycle instruction is fetched and flows normally through the pipeline. This is immediately followed by another branch which mispredicts in the same way. This puts the pipeline in the state: write-back unit and completion slots empty due to bubble caused by first branch, execute unit stalled while multicycle instruction executes, front end buffers stalled waiting on the execute unit and fetch unit halted due to second branch mispredict.

  The condition for the in-order core to halt was: the fetch unit has halted and the heads of the buffers are empty - in the above state this appears to be the case as, when stalled, the buffers do not swap the head and tail. Therefore, even after being decoded, the second branch is stuck in the tail of the decode to execute buffer and so it appears empty. The completion slots are empty due to the bubble from the first branch and the fetch to decode buffer is empty due to the bubble created by the second branch. The fetch unit has halted as the second branch has predicted outside the valid range. As all conditions are true, the in-order pipeline halts and the simulation ends.

  A test has been created to force this state and fails sometimes before the fix is implemented.

  To fix this, the halting condition is updated so that the head or tail of the buffer is checked depending on whether it is stalled or not and the execute unit is checked to see if there is an instruction currently executing. The test now always passes.