Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update AArch64 Contiguous NEON/SVE Loads #330

Merged
merged 2 commits into from
Jul 14, 2023
Merged

Update AArch64 Contiguous NEON/SVE Loads #330

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
2772ba0
Updated all Arch64 single structure vector/sve loads to extract their…
FinnWilkinson Jul 13, 2023
bb4e117
Updated Instruction_Address entries for those loads altered in prior …
Jul 14, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/include/simeng/MemoryInterface.hh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ struct MemoryAccessTarget {
/** The address to access. */
uint64_t address;
/** The number of bytes to access at `address`. */
uint8_t size;
uint16_t size;
rahahahat marked this conversation as resolved.
Show resolved Hide resolved

/** Check for equality of two access targets. */
bool operator==(const MemoryAccessTarget& other) const {
Expand Down
2 changes: 2 additions & 0 deletions src/include/simeng/arch/aarch64/Instruction.hh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -453,6 +453,8 @@ class Instruction : public simeng::Instruction {

void setMemoryAddresses(std::vector<MemoryAccessTarget>&& addresses);

void setMemoryAddresses(MemoryAccessTarget address);
rahahahat marked this conversation as resolved.
Show resolved Hide resolved

/** The memory addresses this instruction accesses, as a vector of {offset,
* width} pairs. */
std::vector<MemoryAccessTarget> memoryAddresses;
Expand Down
6 changes: 6 additions & 0 deletions src/lib/arch/aarch64/Instruction.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,12 @@ void Instruction::setMemoryAddresses(
memoryAddresses = std::move(addresses);
}

void Instruction::setMemoryAddresses(MemoryAccessTarget address) {
dataPending_ = 1;
memoryData.resize(1);
memoryAddresses.push_back(address);
}

span<const MemoryAccessTarget> Instruction::getGeneratedAddresses() const {
return {memoryAddresses.data(), memoryAddresses.size()};
}
Expand Down
165 changes: 19 additions & 146 deletions src/lib/arch/aarch64/Instruction_address.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -66,23 +66,11 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
// [<xn|sp>{, xm, LSL #2}]
// SME
const uint16_t partition_num = VL_bits / 32;
const uint64_t* pg =
operands[partition_num + 1].getAsVector<uint64_t>();
const uint64_t n = operands[partition_num + 2].get<uint64_t>();
uint64_t m = 0;
if (metadata.operands[2].mem.index)
m = operands[partition_num + 3].get<uint64_t>() << 2;

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 16) * 4);
if (pg[i / 16] & shifted_active) {
addresses.push_back({(n + m) + (i * 4), 4});
}
}
setMemoryAddresses(std::move(addresses));
setMemoryAddresses({(n + m), static_cast<uint16_t>(VL_bits / 8)});
break;
}
case Opcode::AArch64_LD1i32: { // ld1 {vt.s}[index], [xn]
Expand Down Expand Up @@ -110,41 +98,15 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
break;
}
case Opcode::AArch64_LD1RQ_D_IMM: { // ld1rqd {zd.d}, pg/z, [xn{, #imm}]
const uint64_t* p = operands[0].getAsVector<uint64_t>();

uint64_t addr =
operands[1].get<uint64_t>() + metadata.operands[2].mem.disp;

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(2);

for (int i = 0; i < 2; i++) {
uint64_t shifted_active = 1ull << ((i % 8) * 8);
if (p[i / 8] & shifted_active) {
addresses.push_back({addr, 8});
}
addr += 8;
}
setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(16)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1RQ_W_IMM: { // ld1rqw {zd.s}, pg/z, [xn{, #imm}]
const uint64_t* p = operands[0].getAsVector<uint64_t>();

uint64_t addr =
operands[1].get<uint64_t>() + metadata.operands[2].mem.disp;

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(4);

for (int i = 0; i < 4; i++) {
uint64_t shifted_active = 1ull << ((i % 16) * 4);
if (p[i / 16] & shifted_active) {
addresses.push_back({addr, 4});
}
addr += 4;
}
setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(16)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1RW_IMM: { // ld1rw {zt.s}, pg/z, [xn, #imm]
Expand Down Expand Up @@ -243,133 +205,58 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
break;
}
case Opcode::AArch64_LD1B: { // ld1b {zt.b}, pg/z, [xn, xm]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 8;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset = operands[2].get<uint64_t>();

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << (i % 64);
if (p[i / 64] & shifted_active) {
addresses.push_back({base + (offset + i), 1});
}
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({base + offset, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1D: { // ld1d {zt.d}, pg/z, [xn, xm, lsl #3]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 64;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset = operands[2].get<uint64_t>();
const uint64_t addr = base + (offset * 8);

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 8) * 8);
if (p[i / 8] & shifted_active) {
addresses.push_back({base + ((offset + i) * 8), 8});
}
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1D_IMM_REAL: { // ld1d {zt.d}, pg/z, [xn{, #imm,
// mul vl}]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 64;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset =
static_cast<uint64_t>(metadata.operands[2].mem.disp);
const uint64_t addr = base + (offset * partition_num * 8);

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

uint64_t addr = base + (offset * partition_num * 8);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 8) * 8);
if (p[i / 8] & shifted_active) {
addresses.push_back({addr, 8});
}
addr += 8;
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1H: { // ld1h {zt.h}, pg/z, [xn, xm, lsl #1]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 16;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset = operands[2].get<uint64_t>();
const uint64_t addr = base + (offset * 2);

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 32) * 2);
if (p[i / 32] & shifted_active) {
addresses.push_back({base + ((offset + i) * 2), 2});
}
}

setMemoryAddresses(addresses);
setMemoryAddresses({addr, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1W: { // ld1w {zt.s}, pg/z, [xn, xm, lsl #2]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 32;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset = operands[2].get<uint64_t>();
const uint64_t addr = base + (offset * 4);

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 16) * 4);
if (p[i / 16] & shifted_active) {
addresses.push_back({base + ((offset + i) * 4), 4});
}
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD1W_IMM_REAL: { // ld1w {zt.s}, pg/z, [xn{, #imm,
// mul vl}]
const uint64_t* p = operands[0].getAsVector<uint64_t>();
const uint16_t partition_num = VL_bits / 32;

const uint64_t base = operands[1].get<uint64_t>();
const uint64_t offset =
static_cast<uint64_t>(metadata.operands[2].mem.disp);
const uint64_t addr = base + (offset * partition_num * 4);

std::vector<MemoryAccessTarget> addresses;
addresses.reserve(partition_num);

uint64_t addr = base + (offset * partition_num * 4);

for (int i = 0; i < partition_num; i++) {
uint64_t shifted_active = 1ull << ((i % 16) * 4);
if (p[i / 16] & shifted_active) {
addresses.push_back({addr, 4});
}
addr += 4;
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, static_cast<uint16_t>(VL_bits / 8)});
rahahahat marked this conversation as resolved.
Show resolved Hide resolved
break;
}
case Opcode::AArch64_LD2D: { // ld2d {zt1.d, zt2.d}, pg/z, [xn|sp, xm,
Expand Down Expand Up @@ -668,34 +555,20 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
const uint64_t offset =
static_cast<uint64_t>(metadata.operands[1].mem.disp);

std::vector<MemoryAccessTarget> addresses(partition_num);

uint64_t addr = base + (offset * partition_num);

for (int i = 0; i < partition_num; i++) {
addresses[i] = {addr, 1};
addr += 1;
}

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, partition_num});
break;
}
case Opcode::AArch64_LDR_ZXI: { // ldr zt, [xn{, #imm, mul vl}]
const uint16_t partition_num = VL_bits / 8;

const uint64_t base = operands[0].get<uint64_t>();
const uint64_t offset =
static_cast<uint64_t>(metadata.operands[1].mem.disp);

std::vector<MemoryAccessTarget> addresses(partition_num);

uint64_t addr = base + (offset * partition_num);
for (int i = 0; i < partition_num; i++) {
addresses[i] = {addr, 1};
addr += 1;
}
const int64_t offset =
static_cast<int64_t>(metadata.operands[1].mem.disp);
const uint64_t addr = base + (offset * partition_num);

setMemoryAddresses(std::move(addresses));
setMemoryAddresses({addr, partition_num});
break;
}
case Opcode::AArch64_LDNPSi: { // ldnp st1, st2, [xn, #imm]
Expand Down
Loading