lint and style

examples/verilog/uart/run.py

@@ -12,17 +12,13 @@
 usage on a typical module.
 """
 
-from os.path import join, dirname
+from pathlib import Path
 from vunit.verilog import VUnit
 
-vu = VUnit.from_argv()
+SRC_PATH = Path(__file__).parent / "src"
 
-src_path = join(dirname(__file__), "src")
+VU = VUnit.from_argv()
+VU.add_library("uart_lib").add_source_files(SRC_PATH / "*.sv")
+VU.add_library("tb_uart_lib").add_source_files(SRC_PATH / "test" / "*.sv")
 
-uart_lib = vu.add_library("uart_lib")
-uart_lib.add_source_files(join(src_path, "*.sv"))
-
-tb_uart_lib = vu.add_library("tb_uart_lib")
-tb_uart_lib.add_source_files(join(src_path, "test", "*.sv"))
-
-vu.main()
+VU.main()

examples/verilog/user_guide/run.py

@@ -12,13 +12,12 @@
 the :ref:`User Guide <user_guide>`.
 """
 
-from os.path import join, dirname
+from pathlib import Path
 from vunit.verilog import VUnit
 
-root = dirname(__file__)
+ROOT = Path(__file__).parent
 
-vu = VUnit.from_argv()
-lib = vu.add_library("lib")
-lib.add_source_files(join(root, "*.sv"))
+VU = VUnit.from_argv()
+VU.add_library("lib").add_source_files(ROOT / "*.sv")
 
-vu.main()
+VU.main()

examples/verilog/verilog_ams/run.py

@@ -4,16 +4,16 @@
 #
 # Copyright (c) 2014-2020, Lars Asplund [email protected]
 
-from os.path import join, dirname
+from pathlib import Path
 from vunit.verilog import VUnit
 
-root = dirname(__file__)
+ROOT = Path(__file__).parent
 
-vu = VUnit.from_argv()
-lib = vu.add_library("lib")
-lib.add_source_files(join(root, "*.sv"))
-lib.add_source_files(join(root, "*.vams")).set_compile_option(
+VU = VUnit.from_argv()
+LIB = VU.add_library("lib")
+LIB.add_source_files(ROOT / "*.sv")
+LIB.add_source_files(ROOT / "*.vams").set_compile_option(
     "modelsim.vlog_flags", ["-ams"]
 )
 
-vu.main()
+VU.main()

examples/vhdl/array/run.py

@@ -16,16 +16,16 @@
 from pathlib import Path
 from vunit import VUnit
 
-vu = VUnit.from_argv()
-vu.add_osvvm()
+VU = VUnit.from_argv()
+VU.add_osvvm()
 
-src_path = Path(__file__).parent / "src"
+SRC_PATH = Path(__file__).parent / "src"
 
-vu.add_library("lib").add_source_files(
-    [src_path / "*.vhd", src_path / "test" / "*.vhd"]
+VU.add_library("lib").add_source_files(
+    [SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"]
 )
 
-vu.set_compile_option("ghdl.flags", ["-frelaxed"])
-vu.set_sim_option("ghdl.elab_flags", ["-frelaxed"])
+VU.set_compile_option("ghdl.flags", ["-frelaxed"])
+VU.set_sim_option("ghdl.elab_flags", ["-frelaxed"])
 
-vu.main()
+VU.main()

examples/vhdl/array_axis_vcs/run.py

@@ -19,13 +19,13 @@
 from pathlib import Path
 from vunit import VUnit
 
-vu = VUnit.from_argv()
-vu.add_verification_components()
+VU = VUnit.from_argv()
+VU.add_verification_components()
 
-src_path = Path(__file__).parent / "src"
+SRC_PATH = Path(__file__).parent / "src"
 
-vu.add_library("lib").add_source_files([src_path / "*.vhd", src_path / "**" / "*.vhd"])
+VU.add_library("lib").add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "**" / "*.vhd"])
 
 # vu.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
 
-vu.main()
+VU.main()

examples/vhdl/axi_dma/run.py

@@ -18,14 +18,14 @@
 from pathlib import Path
 from vunit import VUnit
 
-vu = VUnit.from_argv()
-vu.add_osvvm()
-vu.add_verification_components()
+VU = VUnit.from_argv()
+VU.add_osvvm()
+VU.add_verification_components()
 
-src_path = Path(__file__).parent / "src"
+SRC_PATH = Path(__file__).parent / "src"
 
-vu.add_library("axi_dma_lib").add_source_files(
-    [src_path / "*.vhd", src_path / "test" / "*.vhd"]
+VU.add_library("axi_dma_lib").add_source_files(
+    [SRC_PATH / "*.vhd", SRC_PATH / "test" / "*.vhd"]
 )
 
-vu.main()
+VU.main()

examples/vhdl/check/run.py

@@ -14,10 +14,10 @@
 from pathlib import Path
 from vunit import VUnit
 
-vu = VUnit.from_argv()
+VU = VUnit.from_argv()
 
 # Enable location preprocessing but exclude all but check_false to make the example less bloated
-vu.enable_location_preprocessing(
+VU.enable_location_preprocessing(
     exclude_subprograms=[
         "debug",
         "info",
@@ -36,8 +36,8 @@
     ]
 )
 
-vu.enable_check_preprocessing()
+VU.enable_check_preprocessing()
 
-vu.add_library("lib").add_source_files(Path(__file__).parent / "tb_example.vhd")
+VU.add_library("lib").add_source_files(Path(__file__).parent / "tb_example.vhd")
 
-vu.main()
+VU.main()

examples/vhdl/com/run.py

@@ -16,14 +16,14 @@
 from pathlib import Path
 from vunit import VUnit
 
-vu = VUnit.from_argv()
-vu.add_com()
-vu.add_verification_components()
-vu.add_osvvm()
+VU = VUnit.from_argv()
+VU.add_com()
+VU.add_verification_components()
+VU.add_osvvm()
 
-root = Path(__file__).parent
+ROOT = Path(__file__).parent
 
-vu.add_library("lib").add_source_files(root / "src" / "*.vhd")
-vu.add_library("tb_lib").add_source_files(root / "test" / "*.vhd")
+VU.add_library("lib").add_source_files(ROOT / "src" / "*.vhd")
+VU.add_library("tb_lib").add_source_files(ROOT / "test" / "*.vhd")
 
-vu.main()
+VU.main()

examples/vhdl/composite_generics/run.py

@@ -19,17 +19,27 @@ def encode(tb_cfg):
     return ", ".join(["%s:%s" % (key, str(tb_cfg[key])) for key in tb_cfg])
 
 
-vu = VUnit.from_argv()
-
-tb_lib = vu.add_library("tb_lib")
-tb_lib.add_source_files(Path(__file__).parent / "test" / "*.vhd")
-
-test_1 = tb_lib.test_bench("tb_composite_generics").test("Test 1")
-
-vga_tb_cfg = dict(image_width=640, image_height=480, dump_debug_data=False)
-test_1.add_config(name="VGA", generics=dict(encoded_tb_cfg=encode(vga_tb_cfg)))
-
-tiny_tb_cfg = dict(image_width=4, image_height=3, dump_debug_data=True)
-test_1.add_config(name="tiny", generics=dict(encoded_tb_cfg=encode(tiny_tb_cfg)))
-
-vu.main()
+VU = VUnit.from_argv()
+
+TB_LIB = VU.add_library("tb_lib")
+TB_LIB.add_source_files(Path(__file__).parent / "test" / "*.vhd")
+
+TEST = TB_LIB.test_bench("tb_composite_generics").test("Test 1")
+
+TEST.add_config(
+    name="VGA",
+    generics=dict(
+        encoded_tb_cfg=encode(
+            dict(image_width=640, image_height=480, dump_debug_data=False)
+        )
+    ),
+)
+
+TEST.add_config(
+    name="tiny",
+    generics=dict(
+        encoded_tb_cfg=encode(dict(image_width=4, image_height=3, dump_debug_data=True))
+    ),
+)
+
+VU.main()

examples/vhdl/coverage/run.py

@@ -12,15 +12,15 @@ def post_run(results):
     results.merge_coverage(file_name="coverage_data")
 
 
-vu = VUnit.from_argv()
+VU = VUnit.from_argv()
 
-lib = vu.add_library("lib")
-lib.add_source_files(Path(__file__).parent / "*.vhd")
+LIB = VU.add_library("lib")
+LIB.add_source_files(Path(__file__).parent / "*.vhd")
 
-lib.set_compile_option("rivierapro.vcom_flags", ["-coverage", "bs"])
-lib.set_compile_option("rivierapro.vlog_flags", ["-coverage", "bs"])
-lib.set_compile_option("modelsim.vcom_flags", ["+cover=bs"])
-lib.set_compile_option("modelsim.vlog_flags", ["+cover=bs"])
-lib.set_sim_option("enable_coverage", True)
+LIB.set_compile_option("rivierapro.vcom_flags", ["-coverage", "bs"])
+LIB.set_compile_option("rivierapro.vlog_flags", ["-coverage", "bs"])
+LIB.set_compile_option("modelsim.vcom_flags", ["+cover=bs"])
+LIB.set_compile_option("modelsim.vlog_flags", ["+cover=bs"])
+LIB.set_sim_option("enable_coverage", True)
 
-vu.main(post_run=post_run)
+VU.main(post_run=post_run)

examples/vhdl/docker_runall.sh

@@ -1,6 +1,6 @@
 #!/bin/sh
 
-cd $(dirname $0)
+cd $(dirname "$0")
 
 docker run --rm -t \
   -v /$(pwd)/../..://work \

examples/vhdl/external_buffer/cp.py

@@ -4,24 +4,25 @@
 #
 # Copyright (c) 2014-2020, Lars Asplund [email protected]
 
-from vunit import VUnit
 from subprocess import check_call
+from shutil import which
 from pathlib import Path
+from vunit import VUnit
 
-src_path = Path(__file__).parent / "src"
+SRC_PATH = Path(__file__).parent / "src"
 
-c_obj = src_path / "cp.o"
+C_OBJ = SRC_PATH / "cp.o"
 # Compile C application to an object
-check_call(["gcc", "-fPIC", "-c", str(src_path / "cp.c"), "-o", str(c_obj)])
+check_call([which("gcc"), "-fPIC", "-c", str(SRC_PATH / "cp.c"), "-o", str(C_OBJ)])
 
 # Enable the external feature for strings
-vu = VUnit.from_argv(vhdl_standard="2008", compile_builtins=False)
-vu.add_builtins({"string": True})
+VU = VUnit.from_argv(vhdl_standard="2008", compile_builtins=False)
+VU.add_builtins({"string": True})
 
-lib = vu.add_library("lib")
-lib.add_source_files(str(src_path / "tb_extcp_*.vhd"))
+LIB = VU.add_library("lib")
+LIB.add_source_files(SRC_PATH / "tb_extcp_*.vhd")
 
 # Add the C object to the elaboration of GHDL
-vu.set_sim_option("ghdl.elab_flags", ["-Wl," + str(c_obj)])
+VU.set_sim_option("ghdl.elab_flags", ["-Wl," + str(C_OBJ)])
 
-vu.main()
+VU.main()

examples/vhdl/external_buffer/run.py

@@ -25,51 +25,52 @@
 simulation.
 """
 
-from vunit import VUnit, ROOT
 from subprocess import check_call
+from shutil import which
 from pathlib import Path
+from vunit import VUnit, ROOT
 
-src_path = Path(__file__).parent / "src"
-ext_srcs = Path(ROOT) / "vunit" / "vhdl" / "data_types" / "src" / "external" / "ghdl"
+SRC_PATH = Path(__file__).parent / "src"
+EXT_SRCS = Path(ROOT) / "vunit" / "vhdl" / "data_types" / "src" / "external" / "ghdl"
 
 # Compile C applications to an objects
-c_iobj = src_path / "imain.o"
-c_bobj = src_path / "bmain.o"
+C_IOBJ = SRC_PATH / "imain.o"
+C_BOBJ = SRC_PATH / "bmain.o"
 
-for val in [["int32_t", c_iobj], ["uint8_t", c_bobj]]:
+for val in [["int32_t", C_IOBJ], ["uint8_t", C_BOBJ]]:
     check_call(
         [
-            "gcc",
+            which("gcc"),
             "-fPIC",
             "-DTYPE=" + val[0],
             "-I",
-            ext_srcs,
+            EXT_SRCS,
             "-c",
-            src_path / "main.c",
+            SRC_PATH / "main.c",
             "-o",
             val[1],
         ]
     )
 
 # Enable the external feature for strings/byte_vectors and integer_vectors
-vu = VUnit.from_argv(vhdl_standard="2008", compile_builtins=False)
-vu.add_builtins({"string": True, "integer": True})
+VU = VUnit.from_argv(vhdl_standard="2008", compile_builtins=False)
+VU.add_builtins({"string": True, "integer": True})
 
-lib = vu.add_library("lib")
-lib.add_source_files(src_path / "tb_ext_*.vhd")
+LIB = VU.add_library("lib")
+LIB.add_source_files(SRC_PATH / "tb_ext_*.vhd")
 
 # Add the C object to the elaboration of GHDL
-for tb in lib.get_test_benches(pattern="*tb_ext*", allow_empty=False):
+for tb in LIB.get_test_benches(pattern="*tb_ext*", allow_empty=False):
     tb.set_sim_option(
         "ghdl.elab_flags",
-        ["-Wl," + str(c_bobj), "-Wl,-Wl,--version-script=" + str(ext_srcs / "grt.ver")],
+        ["-Wl," + str(C_BOBJ), "-Wl,-Wl,--version-script=" + str(EXT_SRCS / "grt.ver")],
         overwrite=True,
     )
-for tb in lib.get_test_benches(pattern="*tb_ext*_integer*", allow_empty=False):
+for tb in LIB.get_test_benches(pattern="*tb_ext*_integer*", allow_empty=False):
     tb.set_sim_option(
         "ghdl.elab_flags",
-        ["-Wl," + str(c_iobj), "-Wl,-Wl,--version-script=" + str(ext_srcs / "grt.ver")],
+        ["-Wl," + str(C_IOBJ), "-Wl,-Wl,--version-script=" + str(EXT_SRCS / "grt.ver")],
         overwrite=True,
     )
 
-vu.main()
+VU.main()

examples/vhdl/external_buffer/src/cp.c

@@ -18,26 +18,24 @@ NOTE: This file is expected to be used along with tb_extcp_byte_vector.vhd or tb
 
 extern int ghdl_main (int argc, char **argv);
 
-uint8_t *D[1];
+uint8_t *D[2];
 const uint32_t length = 10;
 
 // Check procedure, to be executed when GHDL exits.
 // The simulation is expected to copy the first 1/3 elements to positions [1/3, 2/3),
 // while incrementing each value by one, and then copy elements from [1/3, 2/3) to
 // [2/3, 3/3), while incrementing each value by two.
 static void exit_handler(void) {
-  int i, j, z, k;
-  uint8_t expected, got;
-  k = 0;
-
-  for(i=0; i<length; i++) {
+  uint i;
+  for ( i=0; i<length ; i++ ) {
+    int8_t expected, got;
     expected = D[0][i];
     got = D[1][i];
     if (expected != got) {
-      printf("check error %d: %d %d\n", i, expected, got);
+      printf("check error %u: %d %d\n", i, expected, got);
       exit(1);
     }
-    printf("%d: %d\n", i, got);
+    printf("%u: %d\n", i, got);
   }
 
   free(D[0]);