Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add libraries to vsim for Riviera-PRO #1087

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 8 additions & 0 deletions vunit/sim_if/rivierapro.py
Original file line number Diff line number Diff line change
Expand Up @@ -177,6 +177,10 @@ def compile_vhdl_file_command(self, source_file):
"""
Returns the command to compile a VHDL file
"""
libraries = []
for library in self._libraries:
if library.name not in ["simprims_ver", "unifast_ver", "unimacro_ver", "unisims_ver"]:
libraries += ["-L", library.name]

return (
[
Expand All @@ -185,6 +189,7 @@ def compile_vhdl_file_command(self, source_file):
"-j",
str(Path(self._sim_cfg_file_name).parent),
]
+ libraries
+ source_file.compile_options.get("rivierapro.vcom_flags", [])
+ [
self._std_str(source_file.get_vhdl_standard()),
Expand Down Expand Up @@ -310,6 +315,9 @@ def _create_load_function(

vsim_flags += ["-lib", config.library_name]

for library in self._libraries:
vsim_flags += ["-L", library.name]

if config.vhdl_configuration_name is None:
# Add the the testbench top-level unit last as coverage is
# only collected for the top-level unit specified last
Expand Down
Loading