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Apply floor truncation on Digitizer output by default. #225

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80 changes: 42 additions & 38 deletions gen/inc/WireCellGen/Digitizer.h
Original file line number Diff line number Diff line change
Expand Up @@ -15,42 +15,46 @@
#include "WireCellAux/Logger.h"
#include <deque>

namespace WireCell {

namespace Gen {

class Digitizer : public Aux::Logger,
public IFrameFilter, public IConfigurable {
public:
Digitizer(const std::string& anode_tn = "AnodePlane",
int resolution = 12, // bits of resolution
double gain = -1.0, // input gain
std::vector<double> fullscale = {0.0, 2.0 * units::volt},
std::vector<double> baselines = {900 * units::mV, 900 * units::mV, 200 * units::mV});
virtual ~Digitizer();

virtual void configure(const WireCell::Configuration& config);
virtual WireCell::Configuration default_configuration() const;

// Voltage frame goes in, ADC frame comes out.
virtual bool operator()(const input_pointer& inframe, output_pointer& outframe);

// implementation method. Return a "floating point ADC"
// value for the given voltage assumed to have been lifted
// to the baseline.
double digitize(double voltage);

private:
IAnodePlane::pointer m_anode;
std::string m_anode_tn;
int m_resolution;
double m_gain;
std::vector<double> m_fullscale, m_baselines;
std::string m_frame_tag;
size_t m_count{0};
bool m_round{false}; // apply round to FP ADC values
};

} // namespace Gen
} // namespace WireCell
namespace WireCell::Gen {


class Digitizer : public Aux::Logger,
public IFrameFilter, public IConfigurable {
public:
Digitizer();
virtual ~Digitizer();

virtual void configure(const WireCell::Configuration& config);
virtual WireCell::Configuration default_configuration() const;

// Voltage frame goes in, ADC frame comes out.
virtual bool operator()(const input_pointer& inframe, output_pointer& outframe);

// implementation method. Return a "floating point ADC"
// value for the given voltage assumed to have been lifted
// to the baseline.
double digitize(double voltage);

private:
/// Config: "anode" - type/name of an IAnodePlane
IAnodePlane::pointer m_anode;

/// Config: "resolution" - number of ADC bits
int m_resolution{12};

/// Config: "gain" - relative input gain
double m_gain{1.0};

/// Config: "fullscale" - two element array of min/max ADC range in units of Voltage
std::vector<double> m_fullscale{0.0, 2.0 * units::volt};
/// Config: "baselines" - three element array giving nominal baseline of each plane in units of Voltage
std::vector<double> m_baselines{900 * units::mV, 900 * units::mV, 200 * units::mV};
/// Config: "frame_tag" - string, if given, a frame tag to apply to produced frames.
std::string m_frame_tag{""};
size_t m_count{0};
/// Config: "round" - bool. If bool true, round to nearest integer. Else floor (default).
bool m_round{false}; // apply round to FP ADC values
};

} // namespace WireCell::Gen
#endif
19 changes: 5 additions & 14 deletions gen/src/Digitizer.cxx
Original file line number Diff line number Diff line change
Expand Up @@ -19,17 +19,8 @@ using namespace WireCell;
using WireCell::Aux::SimpleTrace;
using WireCell::Aux::SimpleFrame;

Gen::Digitizer::Digitizer(const std::string& anode,
int resolution, double gain,
std::vector<double> fullscale,
std::vector<double> baselines)
Gen::Digitizer::Digitizer()
: Aux::Logger("Digitizer", "gen")
, m_anode_tn(anode)
, m_resolution(resolution)
, m_gain(gain)
, m_fullscale(fullscale)
, m_baselines(baselines)
, m_frame_tag("")
{
}

Expand All @@ -38,7 +29,7 @@ Gen::Digitizer::~Digitizer() {}
WireCell::Configuration Gen::Digitizer::default_configuration() const
{
Configuration cfg;
put(cfg, "anode", m_anode_tn);
put(cfg, "anode", "AnodePlane");

put(cfg, "resolution", m_resolution);
put(cfg, "gain", m_gain);
Expand All @@ -61,8 +52,8 @@ WireCell::Configuration Gen::Digitizer::default_configuration() const

void Gen::Digitizer::configure(const Configuration& cfg)
{
m_anode_tn = get<string>(cfg, "anode", m_anode_tn);
m_anode = Factory::find_tn<IAnodePlane>(m_anode_tn);
auto anode_tn = get<string>(cfg, "anode", "AnodePlane");
m_anode = Factory::find_tn<IAnodePlane>(anode_tn);

m_resolution = get(cfg, "resolution", m_resolution);
m_gain = get(cfg, "gain", m_gain);
Expand Down Expand Up @@ -98,7 +89,7 @@ double Gen::Digitizer::digitize(double voltage)
if (m_round) {
return round(fp_adc);
}
return fp_adc;
return floor(fp_adc);
}

bool Gen::Digitizer::operator()(const input_pointer& vframe, output_pointer& adcframe)
Expand Down
1 change: 1 addition & 0 deletions img/test/test-wct-uboone-img.bats
Original file line number Diff line number Diff line change
Expand Up @@ -133,6 +133,7 @@ function do_blobs () {
local dfile="cluster_6501_graph.json"
[[ -s "$dfile" ]]

echo $moo validate -t wirecell.cluster.Cluster -s "$sfile" "$dfile"
run $moo validate -t wirecell.cluster.Cluster -s "$sfile" "$dfile"
echo "$output"
[[ "$status" -eq 0 ]]
Expand Down
17 changes: 1 addition & 16 deletions img/test/test-wct-uboone-img.jsonnet
Original file line number Diff line number Diff line change
Expand Up @@ -235,20 +235,6 @@ local dumpframes = pg.pnode({
name: 'dumpframe',
}, nin=1, nout=0);

local magdecon = pg.pnode({
type: 'MagnifySink',
name: 'magdecon',
data: {
output_filename: "mag.root",
root_file_mode: 'UPDATE',
frames: ['gauss', 'wiener', 'gauss_error'],
cmmtree: [['bad','bad']],
summaries: ['gauss', 'wiener', 'gauss_error'],
trace_has_tag: true,
anode: wc.tn(anodes[0]),
},
}, nin=1, nout=1, uses=[anodes[0]]);

local waveform_map = {
type: 'WaveformMap',
name: 'wfm',
Expand Down Expand Up @@ -381,7 +367,6 @@ local graph = pg.pipeline([
cmm_mod, // CMM modification
frame_masking, // apply CMM
charge_err, // calculate charge error
// magdecon, // magnify out
// dumpframes,
imgpipe,
pg.fan.fanout("ClusterFanout", [img.dump(outpat%fmt, fmt) for fmt in std.split(formats, ',')], "")
Expand All @@ -398,7 +383,7 @@ local app = {
local cmdline = {
type: "wire-cell",
data: {
plugins: ["WireCellGen", "WireCellPgraph", "WireCellSio", "WireCellSigProc", "WireCellRoot", "WireCellImg"],
plugins: ["WireCellGen", "WireCellPgraph", "WireCellSio", "WireCellSigProc", "WireCellImg"],
apps: ["Pgrapher"]
}
};
Expand Down
2 changes: 1 addition & 1 deletion test/test/test-pdsp-simsn-nfsp.jsonnet
Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ local sio_sink(output, tags=[]) = pg.pnode({

local sio_tap(output, tags=[]) = pg.fan.tap('FrameFanout', sio_sink(output, tags), wc.basename(output));

local plugins = [ "WireCellSio", "WireCellGen", "WireCellSigProc","WireCellApps", "WireCellPgraph", "WireCellTbb", "WireCellRoot"];
local plugins = [ "WireCellSio", "WireCellGen", "WireCellSigProc","WireCellApps", "WireCellPgraph", "WireCellTbb"];

function(input="input.npz",
vltoutput="frames-vlt.npz", adcoutput="frames-adc.npz",
Expand Down