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added extra whitespace
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Signed-off-by: Hayden Cook <[email protected]>
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@haydenc-amd
haydenc-amd committed Aug 31, 2023
1 parent 3bc0732 commit 0742f06
Showing 1 changed file with 17 additions and 17 deletions.
34 changes: 17 additions & 17 deletions src/com/xilinx/rapidwright/design/DesignTools.java
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Original file line number Diff line number Diff line change
Expand Up @@ -1509,7 +1509,7 @@ public static void makeBlackBox(Design d, String hierarchicalCellName) {
* Preserves other parts of the net if used by other sinks in the site if an
* input. For the unrouting to be successful, this method depends on the site
* routing to be consistent.
*
*
* @param cell The cell of the pin
* @param logicalPinName The logical pin name source or sink to have routing
* removed.
Expand Down Expand Up @@ -1587,9 +1587,9 @@ public static List<SitePinInst> unrouteCellPinSiteRouting(Cell cell, String logi
}
} else {
// site routing terminates here or is invalid
}
}
}

} else if (otherCell != cell && otherCell.getLogicalPinMapping(pin.getName()) != null) {
// Don't search farther, we don't need to unroute anything else
if (pin.isInput() && belPin.isInput()) {
Expand Down Expand Up @@ -1673,7 +1673,7 @@ public static List<SitePinInst> unrouteCellPinSiteRouting(Cell cell, String logi
* cells and nets insides of a cell instance. Method (2) is more likely to have
* complications. This also unroutes both GND and VCC nets to avoid
* implementation issues by Vivado in subsequent place and route runs.
*
*
* @param d The current design
* @param hierarchicalCell The hierarchical cell to become a black box.
*/
Expand Down Expand Up @@ -1857,7 +1857,7 @@ public static void makeBlackBox(Design d, EDIFHierCellInst hierarchicalCell) {
/**
* Helper method for makeBlackBox(). When cutting out nets that used to be
* source'd from something inside a black box, the net names need to be updated.
*
*
* @param d The current design
* @param currNet Current net that requires a name change
* @param newSource The source net (probably a pin on the black box)
Expand Down Expand Up @@ -3639,7 +3639,7 @@ public static boolean isNetDrivenByHierPort(Net net) {
* Locks the logical netlist of the design using the DONT_TOUCH property. This
* strives to be as close as possible to what Vivado's 'lock_design -level
* netlist' does to lock the design. {@link EDIFTools#lockNetlist(EDIFNetlist)}.
*
*
* @param design The design of the netlist to lock.
*/
public static void lockNetlist(Design design) {
Expand All @@ -3651,7 +3651,7 @@ public static void lockNetlist(Design design) {
* property. This strives to be as close as possible to what Vivado's
* 'lock_design -unlock -level netlist' does to lock the
* design.{@link EDIFTools#unlockNetlist(EDIFNetlist)}.
*
*
* @param design The design of the netlist to unlock.
*/
public static void unlockNetlist(Design design) {
Expand All @@ -3663,7 +3663,7 @@ public static void unlockNetlist(Design design) {
* also lock or unlock the netlist of the design (see
* {@link #lockNetlist(Design)}). This strives to be as close as possible to
* what Vivado's 'lock_design -level placement' does to lock the design.
*
*
* @param design The design to lock
* @param lock Flag indicating to lock (true) or unlock (false) the design's
* placement and netlist.
Expand Down Expand Up @@ -3700,7 +3700,7 @@ public static void lockPlacement(Design design) {
* design (see {@link #unlockNetlist(Design)}). This strives to be as close as
* possible to what Vivado's 'lock_design -unlock -level placement' does to lock
* the design.
*
*
* @param design The design to unlock
*/
public static void unlockPlacement(Design design) {
Expand All @@ -3713,7 +3713,7 @@ public static void unlockPlacement(Design design) {
* the design (see {@link #lockPlacement(Design, boolean)}). This strives to be
* as close as possible to what Vivado's 'lock_design -level routing' does to
* lock the design.
*
*
* @param design The design to lock
* @param lock Flag indicating to lock (true) or unlock (false) the design's
* routing, placement and netlist.
Expand All @@ -3734,7 +3734,7 @@ public static void lockRouting(Design design, boolean lock) {
* Vivado. It will also lock the netlist and placement of the design. This
* strives to be as close as possible to what Vivado's 'lock_design -level
* routing' does to lock the design.
*
*
* @param design The design to lock
*/
public static void lockRouting(Design design) {
Expand All @@ -3745,7 +3745,7 @@ public static void lockRouting(Design design) {
* Unlocks any and all routing of a design. It will also unlock the netlist and
* placement of the design. This strives to be as close as possible to what
* Vivado's 'lock_design -unlock -level routing' does to lock the design.
*
*
* @param design The design to unlock
*/
public static void unlockRouting(Design design) {
Expand All @@ -3755,7 +3755,7 @@ public static void unlockRouting(Design design) {
/***
* Unroutes the GND net of a design and unroutes the site routing of any LUT GND
* sources while leaving other site routing inputs intact.
*
*
* @param design The design to modify.
*/
public static void unrouteGNDNetAndLUTSources(Design design) {
Expand Down Expand Up @@ -3786,7 +3786,7 @@ public static void unrouteGNDNetAndLUTSources(Design design) {
* when trying to preserve a partially implemented design that have additional
* logic placed and routed onto it later. The Vivado placer doesn't recognize
* the GND sources so this prevents the placer from using those BEL sites.
*
*
* @param design The design to which the PROHIBIT constraints are added.
*/
public static void prohibitGNDSources(Design design) {
Expand All @@ -3811,7 +3811,7 @@ public static void prohibitGNDSources(Design design) {
/**
* Checks the provided BEL's first letter to determine if it is in the top half
* of a SLICE or bottom half.
*
*
* @param bel The BEL of a SLICE to query
* @return True if the BEL resides in the top half of a SLICE (E6LUT, E5LUT,
* EFF, EFF2, ..). Returns false if it is in the bottom half and null if
Expand All @@ -3832,7 +3832,7 @@ public static Boolean isUltraScaleSliceTop(BEL bel) {
* routed implementation is desired to be preserved but to allow additional
* logic to be placed and routed on top of it without an area (pblock)
* constraint.
*
*
* @param design The design to which the constraints are added.
*/
public static void prohibitPartialHalfSlices(Design design) {
Expand Down Expand Up @@ -3870,7 +3870,7 @@ public static void prohibitPartialHalfSlices(Design design) {
/**
* Adds a PROHIBIT constraint to the specified BEL Locations (ex:
* "SLICE_X10Y10/AFF")
*
*
* @param design The design to which the constraint should be added
* @param belLocations A list of BEL locations using the syntax
* '<SITE-NAME>/<BEL-NAME>'.
Expand Down

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