DesignTools.makePhysNetNamesConsistent() to use hier name (#735)

* DesignTools.makePhysNetNamesConsisntent() to use hier name Signed-off-by: Eddie Hung <[email protected]> * Another case Signed-off-by: Eddie Hung <[email protected]> * Remove unused Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Jun 29, 2023 · 263cfe1 · 263cfe1
1 parent 83807c9
commit 263cfe1
Showing 1 changed file with 2 additions and 4 deletions.
diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java
@@ -2814,13 +2814,11 @@ public static void makePhysNetNamesConsistent(Design design) {
                 Net parentPhysNet;
                 // Assume that a net named <const1> or <const0> is always a VCC or GND net
                 if (parentNetName.equals(EDIFTools.LOGICAL_VCC_NET_NAME)) {
-                    parentNetName = Net.VCC_NET;
                     parentPhysNet = design.getVccNet();
                 } else if (parentNetName.equals(EDIFTools.LOGICAL_GND_NET_NAME)) {
-                    parentNetName = Net.GND_NET;
                     parentPhysNet = design.getGndNet();
                 } else {
-                    parentPhysNet = design.getNet(parentNetName);
+                    parentPhysNet = design.getNet(parentHierNet.getHierarchicalNetName());
                 }
                 if (parentPhysNet != null) {
                     // Merge both physical nets together
@@ -2833,7 +2831,7 @@ public static void makePhysNetNamesConsistent(Design design) {
                         }
                     }
                     design.movePinsToNewNetDeleteOldNet(net, parentPhysNet, true);
-                } else if (!net.rename(parentNetName)) {
+                } else if (!net.rename(parentHierNet.getHierarchicalNetName())) {
                     System.out.println("WARNING: Failed to adjust physical net name " + net.getName());
                 }
             }