[RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM…

… device (#1026) * Do not assume Y = 0 has Laguna tiles, since it could be HBM device Signed-off-by: Eddie Hung <[email protected]> * Add test for xcu50 Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Jul 11, 2024 · a311c73 · a311c73
1 parent 1979e17
commit a311c73
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Showing 2 changed files with 11 additions and 6 deletions.
diff --git a/src/com/xilinx/rapidwright/rwroute/RouteNodeGraph.java b/src/com/xilinx/rapidwright/rwroute/RouteNodeGraph.java
@@ -267,7 +267,8 @@ public RouteNodeGraph(RuntimeTracker setChildrenTimer, Design design, RWRouteCon
                 for (int x = 0; x < lagunaTilesAtY.length; x++) {
                     Tile tile = lagunaTilesAtY[x];
                     if (tile != null) {
-                        if (y == 0) {
+                        // For LAGUNA tiles on the first SLR boundary
+                        if (nextLagunaColumn[x] == Integer.MAX_VALUE) {
                             assert(x == tile.getTileXCoordinate());
                             // Looks like (on US+) LAGUNA tiles are always on the left side of an INT tile,
                             // with tile X coordinate one smaller

diff --git a/test/src/com/xilinx/rapidwright/rwroute/TestRWRoute.java b/test/src/com/xilinx/rapidwright/rwroute/TestRWRoute.java
@@ -383,16 +383,20 @@ public void testTimingAndWirelengthReport() {
     @ParameterizedTest
     @CsvSource({
             // Dedicated connections, hence no nodes popped
-            "GTYE4_CHANNEL_X0Y12,TXOUTCLK_INT,BUFG_GT_SYNC_X0Y46,CLK_IN,0",
-            "GTYE4_CHANNEL_X0Y12,TXOUTCLK_INT,BUFG_GT_X0Y78,CLK_IN,0", // (dst pin can be projected to INT but not src pin)
+            "xcvu3p,GTYE4_CHANNEL_X0Y12,TXOUTCLK_INT,BUFG_GT_SYNC_X0Y46,CLK_IN,0",
+            "xcvu3p,GTYE4_CHANNEL_X0Y12,TXOUTCLK_INT,BUFG_GT_X0Y78,CLK_IN,0", // (dst pin can be projected to INT but not src pin)
 
             // Non-dedicated connections
-            "IOB_X0Y47,I,SLICE_X77Y122,FX,600",
+            "xcvu3p,IOB_X0Y47,I,SLICE_X77Y122,FX,600",
+
+            // 240 CLB height SLR, no LAG tiles on Y0 (since HBM on bottom edge)
+            "xcu50,SLICE_X38Y239,AQ,SLICE_X38Y240,A1,500"
     })
-    public void testSingleConnection(String srcSiteName, String srcPinName,
+    public void testSingleConnection(String partName,
+                                     String srcSiteName, String srcPinName,
                                      String dstSiteName, String dstPinName,
                                      int nodesPoppedLimit) {
-        testSingleConnectionHelper("xcvu3p",
+        testSingleConnectionHelper(partName,
                 srcSiteName, srcPinName,
                 dstSiteName, dstPinName,
                 nodesPoppedLimit);