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[YosysTools] Add synthXilinx() wrapper for Yosys #1086

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merged 20 commits into from
Oct 29, 2024
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@eddieh-xlnx eddieh-xlnx commented Oct 22, 2024

Add YosysTools convenience class to use Yosys for synthesizing Verilog files into RapidWright EDIFNetlist objects. Requires that the yosys binary be available on PATH.

Currently, only a number of synthXilinx overloads are available, corresponding to Yosys' synth_xilinx command, with the following flags:

  • -family xcup (target UltraScale+ devices)
  • -edif <file> (write the result into an EDIF file)
  • -flatten (flatten the design into one module to benefit from cross-module optimizations)
  • -noclkbuf -noiopad (disable BUFG and IBUF/OBUF insertion, simulating Vivado's out-of-context mode)

Signed-off-by: Eddie Hung <[email protected]>
- FileTools.runCommand(String[] command, ...) is an array overload of
  FileTools.runCommand(String command, ...) for arguments with spaces
  in
- FileTools.getPath(String) is the generalized guts of
  FileTools.getVivadoPath()

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
This reverts commit 5482bfb.

Signed-off-by: Eddie Hung <[email protected]>
@eddieh-xlnx eddieh-xlnx force-pushed the filetools_runCommand_array branch from 425df83 to 3cc2065 Compare October 22, 2024 00:32
Base automatically changed from filetools_runCommand_array to master October 22, 2024 16:49
@eddieh-xlnx eddieh-xlnx marked this pull request as ready for review October 22, 2024 21:41
Signed-off-by: Eddie Hung <[email protected]>
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TestYosysTools passes with vanilla Yosys-0.46.

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
@eddieh-xlnx eddieh-xlnx merged commit 7d74c70 into master Oct 29, 2024
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@eddieh-xlnx eddieh-xlnx deleted the yosys_tools branch October 29, 2024 00:29
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2 participants